From 8623efd24aa50d69b5e110e43d84318cb340d7d6 Mon Sep 17 00:00:00 2001 From: Marcelo Tosatti Date: Wed, 27 Jul 2005 11:44:08 -0700 Subject: [PATCH] --- yaml --- r: 5138 b: refs/heads/master c: 3a1ce8aa2d9611a779c308fbf332ae86217b0df6 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/ppc/kernel/head_8xx.S | 12 +++++------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index 62255b64af2f..06aa419939a8 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 13e886c3b435d14668aefaed449d8d7ca6dce3a8 +refs/heads/master: 3a1ce8aa2d9611a779c308fbf332ae86217b0df6 diff --git a/trunk/arch/ppc/kernel/head_8xx.S b/trunk/arch/ppc/kernel/head_8xx.S index 5a7a64e91fc5..eb18cadb3755 100644 --- a/trunk/arch/ppc/kernel/head_8xx.S +++ b/trunk/arch/ppc/kernel/head_8xx.S @@ -288,13 +288,11 @@ SystemCall: * For the MPC8xx, this is a software tablewalk to load the instruction * TLB. It is modelled after the example in the Motorola manual. The task * switch loads the M_TWB register with the pointer to the first level table. - * If we discover there is no second level table (the value is zero), the - * plan was to load that into the TLB, which causes another fault into the - * TLB Error interrupt where we can handle such problems. However, that did - * not work, so if we discover there is no second level table, we restore - * registers and branch to the error exception. We have to use the MD_xxx - * registers for the tablewalk because the equivalent MI_xxx registers - * only perform the attribute functions. + * If we discover there is no second level table (value is zero) or if there + * is an invalid pte, we load that into the TLB, which causes another fault + * into the TLB Error interrupt where we can handle such problems. + * We have to use the MD_xxx registers for the tablewalk because the + * equivalent MI_xxx registers only perform the attribute functions. */ InstructionTLBMiss: #ifdef CONFIG_8xx_CPU6