From 8625853fee3a5c0297c5cbbfe7a32d61f821b98a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 29 Mar 2012 20:21:32 +1000 Subject: [PATCH] --- yaml --- r: 298507 b: refs/heads/master c: acde2d8037f4502669af251e44b05579681e0dc1 h: refs/heads/master i: 298505: c5acd4c051efabffd7f52b01d83b0c5d8ea3fcfe 298503: d06271af9519f1ae0b87b0c1d8c1d688c6e8f13d v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nouveau_channel.c | 15 +++++++++++---- trunk/drivers/gpu/drm/nouveau/nouveau_dma.h | 4 ++-- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/[refs] b/[refs] index 5b54f33ed78b..48737e832879 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4a206ffc0bfe8e8c3fc0468a052f5b0bb625a57b +refs/heads/master: acde2d8037f4502669af251e44b05579681e0dc1 diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_channel.c b/trunk/drivers/gpu/drm/nouveau/nouveau_channel.c index 44e6416d4a33..337e228629ed 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_channel.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_channel.c @@ -436,11 +436,18 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, } if (dev_priv->card_type < NV_C0) { - init->subchan[0].handle = NvSw; - init->subchan[0].grclass = NV_SW; - init->nr_subchan = 1; + init->subchan[0].handle = NvM2MF; + if (dev_priv->card_type < NV_50) + init->subchan[0].grclass = 0x0039; + else + init->subchan[0].grclass = 0x5039; + init->subchan[1].handle = NvSw; + init->subchan[1].grclass = NV_SW; + init->nr_subchan = 2; } else { - init->nr_subchan = 0; + init->subchan[0].handle = 0x9039; + init->subchan[0].grclass = 0x9039; + init->nr_subchan = 1; } /* Named memory object area */ diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_dma.h b/trunk/drivers/gpu/drm/nouveau/nouveau_dma.h index bcf0fd9e313e..23d4edf992b7 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -48,8 +48,8 @@ void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *, /* Hardcoded object assignments to subchannels (subchannel id). */ enum { - NvSubSw = 0, - NvSubM2MF = 1, + NvSubM2MF = 0, + NvSubSw = 1, NvSub2D = 2, NvSubCtxSurf2D = 2, NvSubGdiRect = 3,