From 865d7d0c95248d187ba1f53e24f863c42cf4fbcc Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 7 Feb 2007 09:45:55 +0100
Subject: [PATCH] --- yaml --- r: 46894 b: refs/heads/master c:
 f31909c00332b3e8299209eaba6cec80756f802c h: refs/heads/master v: v3

---
 [refs]                                  |  2 +-
 trunk/drivers/char/watchdog/booke_wdt.c | 20 +++++++++++---------
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/[refs] b/[refs]
index 9e84da13d4b9..0afbd6e7c139 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 2366fb16abcd8dea96820d3cb4f1de3a868d268c
+refs/heads/master: f31909c00332b3e8299209eaba6cec80756f802c
diff --git a/trunk/drivers/char/watchdog/booke_wdt.c b/trunk/drivers/char/watchdog/booke_wdt.c
index 488902231cc2..0e23f29f71ab 100644
--- a/trunk/drivers/char/watchdog/booke_wdt.c
+++ b/trunk/drivers/char/watchdog/booke_wdt.c
@@ -35,7 +35,7 @@
 #ifdef	CONFIG_FSL_BOOKE
 #define WDT_PERIOD_DEFAULT 63	/* Ex. wdt_period=28 bus=333Mhz , reset=~40sec */
 #else
-#define WDT_PERIOD_DEFAULT 4	/* Refer to the PPC40x and PPC4xx manuals */
+#define WDT_PERIOD_DEFAULT 3	/* Refer to the PPC40x and PPC4xx manuals */
 #endif				/* for timing information */
 
 u32 booke_wdt_enabled = 0;
@@ -47,6 +47,14 @@ u32 booke_wdt_period = WDT_PERIOD_DEFAULT;
 #define WDTP(x)		(TCR_WP(x))
 #endif
 
+/*
+ * booke_wdt_ping:
+ */
+static __inline__ void booke_wdt_ping(void)
+{
+	mtspr(SPRN_TSR, TSR_ENW|TSR_WIS);
+}
+
 /*
  * booke_wdt_enable:
  */
@@ -54,20 +62,14 @@ static __inline__ void booke_wdt_enable(void)
 {
 	u32 val;
 
+	/* clear status before enabling watchdog */
+	booke_wdt_ping();
 	val = mfspr(SPRN_TCR);
 	val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(booke_wdt_period));
 
 	mtspr(SPRN_TCR, val);
 }
 
-/*
- * booke_wdt_ping:
- */
-static __inline__ void booke_wdt_ping(void)
-{
-	mtspr(SPRN_TSR, TSR_ENW|TSR_WIS);
-}
-
 /*
  * booke_wdt_write:
  */