diff --git a/[refs] b/[refs] index adc41cb980d6..27e4c53fbecf 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5e83f6fbdb020b70c0e413312801424d13c58d68 +refs/heads/master: 4b30fbca4f64bc70c59867ad5769c37efb587ff4 diff --git a/trunk/Documentation/DocBook/dvb/dvbapi.xml b/trunk/Documentation/DocBook/dvb/dvbapi.xml index e3a97fdd62a6..63c528fee624 100644 --- a/trunk/Documentation/DocBook/dvb/dvbapi.xml +++ b/trunk/Documentation/DocBook/dvb/dvbapi.xml @@ -12,12 +12,10 @@ O. C.
rjkm@metzlerbros.de
 - - Mauro -Carvalho Chehab +Carvalho
mchehab@redhat.com
 Ported document to Docbook XML. @@ -25,23 +23,12 @@ 2002 2003 + 2009 Convergence GmbH - - 2009-2010 - Mauro Carvalho Chehab - - - 2.0.3 - 2010-07-03 - mcc - - Add some frontend capabilities flags, present on kernel, but missing at the specs. - - 2.0.2 2009-10-25 @@ -76,7 +63,7 @@ Added ISDB-T test originally written by Patrick Boettcher LINUX DVB API -Version 5.2 +Version 3 &sub-intro; diff --git a/trunk/Documentation/DocBook/dvb/frontend.h.xml b/trunk/Documentation/DocBook/dvb/frontend.h.xml index d08e0d401418..b99644f5340a 100644 --- a/trunk/Documentation/DocBook/dvb/frontend.h.xml +++ b/trunk/Documentation/DocBook/dvb/frontend.h.xml @@ -63,7 +63,6 @@ typedef enum fe_caps { FE_CAN_8VSB = 0x200000, FE_CAN_16VSB = 0x400000, FE_HAS_EXTENDED_CAPS = 0x800000, /* We need more bitspace for newer APIs, indicate this. */ - FE_CAN_TURBO_FEC = 0x8000000, /* frontend supports "turbo fec modulation" */ FE_CAN_2G_MODULATION = 0x10000000, /* frontend supports "2nd generation modulation" (DVB-S2) */ FE_NEEDS_BENDING = 0x20000000, /* not supported anymore, don't use (frontend requires frequency bending) */ FE_CAN_RECOVER = 0x40000000, /* frontend can recover from a cable unplug automatically */ diff --git a/trunk/Documentation/DocBook/dvb/frontend.xml b/trunk/Documentation/DocBook/dvb/frontend.xml index 78d756de5906..300ba1f04177 100644 --- a/trunk/Documentation/DocBook/dvb/frontend.xml +++ b/trunk/Documentation/DocBook/dvb/frontend.xml @@ -64,14 +64,8 @@ a specific frontend type. FE_CAN_BANDWIDTH_AUTO = 0x40000, FE_CAN_GUARD_INTERVAL_AUTO = 0x80000, FE_CAN_HIERARCHY_AUTO = 0x100000, - FE_CAN_8VSB = 0x200000, - FE_CAN_16VSB = 0x400000, - FE_HAS_EXTENDED_CAPS = 0x800000, - FE_CAN_TURBO_FEC = 0x8000000, - FE_CAN_2G_MODULATION = 0x10000000, - FE_NEEDS_BENDING = 0x20000000, - FE_CAN_RECOVER = 0x40000000, - FE_CAN_MUTE_TS = 0x80000000 + FE_CAN_MUTE_TS = 0x80000000, + FE_CAN_CLEAN_SETUP = 0x40000000 } fe_caps_t; diff --git a/trunk/Documentation/DocBook/media-entities.tmpl b/trunk/Documentation/DocBook/media-entities.tmpl index 6ae97157b1c7..5d4d40f429a5 100644 --- a/trunk/Documentation/DocBook/media-entities.tmpl +++ b/trunk/Documentation/DocBook/media-entities.tmpl @@ -218,7 +218,6 @@ - diff --git a/trunk/Documentation/DocBook/media.tmpl b/trunk/Documentation/DocBook/media.tmpl index f11048d4053f..eea564bb12cb 100644 --- a/trunk/Documentation/DocBook/media.tmpl +++ b/trunk/Documentation/DocBook/media.tmpl @@ -28,7 +28,7 @@ LINUX MEDIA INFRASTRUCTURE API - 2009-2010 + 2009 LinuxTV Developers @@ -61,7 +61,7 @@ Foundation. A copy of the license is included in the chapter entitled in fact it covers several different video standards including DVB-T, DVB-S, DVB-C and ATSC. The API is currently being updated to documment support also for DVB-S2, ISDB-T and ISDB-S. - The third part covers Remote Controller API + The third part covers other API's used by all media infrastructure devices For additional information and for the latest development code, see: http://linuxtv.org. For discussing improvements, reporting troubles, sending new drivers, etc, please mail to: Linux Media Mailing List (LMML).. @@ -86,7 +86,7 @@ Foundation. A copy of the license is included in the chapter entitled - 2009-2010 + 2009 Mauro Carvalho Chehab @@ -101,7 +101,7 @@ Foundation. A copy of the license is included in the chapter entitled -Remote Controller API +Other API's used by media infrastructure drivers &sub-remote_controllers; diff --git a/trunk/Documentation/DocBook/v4l/lirc_device_interface.xml b/trunk/Documentation/DocBook/v4l/lirc_device_interface.xml deleted file mode 100644 index 0413234023d4..000000000000 --- a/trunk/Documentation/DocBook/v4l/lirc_device_interface.xml +++ /dev/null @@ -1,235 +0,0 @@ -
-LIRC Device Interface - - -
-Introduction - -The LIRC device interface is a bi-directional interface for -transporting raw IR data between userspace and kernelspace. Fundamentally, -it is just a chardev (/dev/lircX, for X = 0, 1, 2, ...), with a number -of standard struct file_operations defined on it. With respect to -transporting raw IR data to and fro, the essential fops are read, write -and ioctl. - -Example dmesg output upon a driver registering w/LIRC: -
- $ dmesg |grep lirc_dev - lirc_dev: IR Remote Control driver registered, major 248 - rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0 -
- -What you should see for a chardev: -
- $ ls -l /dev/lirc* - crw-rw---- 1 root root 248, 0 Jul 2 22:20 /dev/lirc0 -
-
- -
-LIRC read fop - -The lircd userspace daemon reads raw IR data from the LIRC chardev. The -exact format of the data depends on what modes a driver supports, and what -mode has been selected. lircd obtains supported modes and sets the active mode -via the ioctl interface, detailed at . The generally -preferred mode is LIRC_MODE_MODE2, in which packets containing an int value -describing an IR signal are read from the chardev. - -See also http://www.lirc.org/html/technical.html for more info. -
- -
-LIRC write fop - -The data written to the chardev is a pulse/space sequence of integer -values. Pulses and spaces are only marked implicitly by their position. The -data must start and end with a pulse, therefore, the data must always include -an unevent number of samples. The write function must block until the data has -been transmitted by the hardware. -
- -
-LIRC ioctl fop - -The LIRC device's ioctl definition is bound by the ioctl function -definition of struct file_operations, leaving us with an unsigned int -for the ioctl command and an unsigned long for the arg. For the purposes -of ioctl portability across 32-bit and 64-bit, these values are capped -to their 32-bit sizes. - -The following ioctls can be used to change specific hardware settings. -In general each driver should have a default set of settings. The driver -implementation is expected to re-apply the default settings when the device -is closed by user-space, so that every application opening the device can rely -on working with the default settings initially. - - - - LIRC_GET_FEATURES - - Obviously, get the underlying hardware device's features. If a driver - does not announce support of certain features, calling of the corresponding - ioctls is undefined. - - - - LIRC_GET_SEND_MODE - - Get supported transmit mode. Only LIRC_MODE_PULSE is supported by lircd. - - - - LIRC_GET_REC_MODE - - Get supported receive modes. Only LIRC_MODE_MODE2 and LIRC_MODE_LIRCCODE - are supported by lircd. - - - - LIRC_GET_SEND_CARRIER - - Get carrier frequency (in Hz) currently used for transmit. - - - - LIRC_GET_REC_CARRIER - - Get carrier frequency (in Hz) currently used for IR reception. - - - - LIRC_{G,S}ET_{SEND,REC}_DUTY_CYCLE - - Get/set the duty cycle (from 0 to 100) of the carrier signal. Currently, - no special meaning is defined for 0 or 100, but this could be used to switch - off carrier generation in the future, so these values should be reserved. - - - - LIRC_GET_REC_RESOLUTION - - Some receiver have maximum resolution which is defined by internal - sample rate or data format limitations. E.g. it's common that signals can - only be reported in 50 microsecond steps. This integer value is used by - lircd to automatically adjust the aeps tolerance value in the lircd - config file. - - - - LIRC_GET_M{IN,AX}_TIMEOUT - - Some devices have internal timers that can be used to detect when - there's no IR activity for a long time. This can help lircd in detecting - that a IR signal is finished and can speed up the decoding process. - Returns an integer value with the minimum/maximum timeout that can be - set. Some devices have a fixed timeout, in that case both ioctls will - return the same value even though the timeout cannot be changed. - - - - LIRC_GET_M{IN,AX}_FILTER_{PULSE,SPACE} - - Some devices are able to filter out spikes in the incoming signal - using given filter rules. These ioctls return the hardware capabilities - that describe the bounds of the possible filters. Filter settings depend - on the IR protocols that are expected. lircd derives the settings from - all protocols definitions found in its config file. - - - - LIRC_GET_LENGTH - - Retrieves the code length in bits (only for LIRC_MODE_LIRCCODE). - Reads on the device must be done in blocks matching the bit count. - The bit could should be rounded up so that it matches full bytes. - - - - LIRC_SET_{SEND,REC}_MODE - - Set send/receive mode. Largely obsolete for send, as only - LIRC_MODE_PULSE is supported. - - - - LIRC_SET_{SEND,REC}_CARRIER - - Set send/receive carrier (in Hz). - - - - LIRC_SET_TRANSMITTER_MASK - - This enables the given set of transmitters. The first transmitter - is encoded by the least significant bit, etc. When an invalid bit mask - is given, i.e. a bit is set, even though the device does not have so many - transitters, then this ioctl returns the number of available transitters - and does nothing otherwise. - - - - LIRC_SET_REC_TIMEOUT - - Sets the integer value for IR inactivity timeout (cf. - LIRC_GET_MIN_TIMEOUT and LIRC_GET_MAX_TIMEOUT). A value of 0 (if - supported by the hardware) disables all hardware timeouts and data should - be reported as soon as possible. If the exact value cannot be set, then - the next possible value _greater_ than the given value should be set. - - - - LIRC_SET_REC_TIMEOUT_REPORTS - - Enable (1) or disable (0) timeout reports in LIRC_MODE_MODE2. By - default, timeout reports should be turned off. - - - - LIRC_SET_REC_FILTER_{,PULSE,SPACE} - - Pulses/spaces shorter than this are filtered out by hardware. If - filters cannot be set independently for pulse/space, the corresponding - ioctls must return an error and LIRC_SET_REC_FILTER shall be used instead. - - - - LIRC_SET_MEASURE_CARRIER_MODE - - Enable (1)/disable (0) measure mode. If enabled, from the next key - press on, the driver will send LIRC_MODE2_FREQUENCY packets. By default - this should be turned off. - - - - LIRC_SET_REC_{DUTY_CYCLE,CARRIER}_RANGE - - To set a range use LIRC_SET_REC_DUTY_CYCLE_RANGE/LIRC_SET_REC_CARRIER_RANGE - with the lower bound first and later LIRC_SET_REC_DUTY_CYCLE/LIRC_SET_REC_CARRIER - with the upper bound. - - - - LIRC_NOTIFY_DECODE - - This ioctl is called by lircd whenever a successful decoding of an - incoming IR signal could be done. This can be used by supporting hardware - to give visual feedback to the user e.g. by flashing a LED. - - - - LIRC_SETUP_{START,END} - - Setting of several driver parameters can be optimized by encapsulating - the according ioctl calls with LIRC_SETUP_START/LIRC_SETUP_END. When a - driver receives a LIRC_SETUP_START ioctl it can choose to not commit - further setting changes to the hardware until a LIRC_SETUP_END is received. - But this is open to the driver implementation and every driver must also - handle parameter changes which are not encapsulated by LIRC_SETUP_START - and LIRC_SETUP_END. Drivers can also choose to ignore these ioctls. - - - - -
-
diff --git a/trunk/Documentation/DocBook/v4l/remote_controllers.xml b/trunk/Documentation/DocBook/v4l/remote_controllers.xml index 3c3b667b28e7..73f5eab091f4 100644 --- a/trunk/Documentation/DocBook/v4l/remote_controllers.xml +++ b/trunk/Documentation/DocBook/v4l/remote_controllers.xml @@ -173,5 +173,3 @@ keymapping. This program demonstrates how to replace the keymap tables. &sub-keytable-c; - -&sub-lirc_device_interface; diff --git a/trunk/Documentation/apparmor.txt b/trunk/Documentation/apparmor.txt deleted file mode 100644 index 93c1fd7d0635..000000000000 --- a/trunk/Documentation/apparmor.txt +++ /dev/null @@ -1,39 +0,0 @@ ---- What is AppArmor? --- - -AppArmor is MAC style security extension for the Linux kernel. It implements -a task centered policy, with task "profiles" being created and loaded -from user space. Tasks on the system that do not have a profile defined for -them run in an unconfined state which is equivalent to standard Linux DAC -permissions. - ---- How to enable/disable --- - -set CONFIG_SECURITY_APPARMOR=y - -If AppArmor should be selected as the default security module then - set CONFIG_DEFAULT_SECURITY="apparmor" - and CONFIG_SECURITY_APPARMOR_BOOTPARAM_VALUE=1 - -Build the kernel - -If AppArmor is not the default security module it can be enabled by passing -security=apparmor on the kernel's command line. - -If AppArmor is the default security module it can be disabled by passing -apparmor=0, security=XXXX (where XXX is valid security module), on the -kernel's command line - -For AppArmor to enforce any restrictions beyond standard Linux DAC permissions -policy must be loaded into the kernel from user space (see the Documentation -and tools links). - ---- Documentation --- - -Documentation can be found on the wiki. - ---- Links --- - -Mailing List - apparmor@lists.ubuntu.com -Wiki - http://apparmor.wiki.kernel.org/ -User space tools - https://launchpad.net/apparmor -Kernel module - git://git.kernel.org/pub/scm/linux/kernel/git/jj/apparmor-dev.git diff --git a/trunk/Documentation/arm/memory.txt b/trunk/Documentation/arm/memory.txt index 771d48d3b335..eb0fae18ffb1 100644 --- a/trunk/Documentation/arm/memory.txt +++ b/trunk/Documentation/arm/memory.txt @@ -33,13 +33,7 @@ ffff0000 ffff0fff CPU vector page. fffe0000 fffeffff XScale cache flush area. This is used in proc-xscale.S to flush the whole data - cache. (XScale does not have TCM.) - -fffe8000 fffeffff DTCM mapping area for platforms with - DTCM mounted inside the CPU. - -fffe0000 fffe7fff ITCM mapping area for platforms with - ITCM mounted inside the CPU. + cache. Free for other usage on non-XScale. fff00000 fffdffff Fixmap mapping region. Addresses provided by fix_to_virt() will be located here. diff --git a/trunk/Documentation/arm/tcm.txt b/trunk/Documentation/arm/tcm.txt index 7c15871c1885..77fd9376e6d7 100644 --- a/trunk/Documentation/arm/tcm.txt +++ b/trunk/Documentation/arm/tcm.txt @@ -19,8 +19,8 @@ defines a CPUID_TCM register that you can read out from the system control coprocessor. Documentation from ARM can be found at http://infocenter.arm.com, search for "TCM Status Register" to see documents for all CPUs. Reading this register you can -determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present -in the machine. +determine if ITCM (bit 0) and/or DTCM (bit 16) is present in the +machine. There is further a TCM region register (search for "TCM Region Registers" at the ARM site) that can report and modify the location @@ -35,15 +35,7 @@ The TCM memory can then be remapped to another address again using the MMU, but notice that the TCM if often used in situations where the MMU is turned off. To avoid confusion the current Linux implementation will map the TCM 1 to 1 from physical to virtual -memory in the location specified by the kernel. Currently Linux -will map ITCM to 0xfffe0000 and on, and DTCM to 0xfffe8000 and -on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM. - -Newer versions of the region registers also support dividing these -TCMs in two separate banks, so for example an 8KiB ITCM is divided -into two 4KiB banks with its own control registers. The idea is to -be able to lock and hide one of the banks for use by the secure -world (TrustZone). +memory in the location specified by the machine. TCM is used for a few things: @@ -73,18 +65,18 @@ in . Using this interface it is possible to: memory. Such a heap is great for things like saving device state when shutting off device power domains. -A machine that has TCM memory shall select HAVE_TCM from -arch/arm/Kconfig for itself. Code that needs to use TCM shall -#include +A machine that has TCM memory shall select HAVE_TCM in +arch/arm/Kconfig for itself, and then the +rest of the functionality will depend on the physical +location and size of ITCM and DTCM to be defined in +mach/memory.h for the machine. Code that needs to use +TCM shall #include If the TCM is not located +at the place given in memory.h it will be moved using +the TCM Region registers. Functions to go into itcm can be tagged like this: int __tcmfunc foo(int bar); -Since these are marked to become long_calls and you may want -to have functions called locally inside the TCM without -wasting space, there is also the __tcmlocalfunc prefix that -will make the call relative. - Variables to go into dtcm can be tagged like this: int __tcmdata foo; diff --git a/trunk/Documentation/dvb/get_dvb_firmware b/trunk/Documentation/dvb/get_dvb_firmware index 350959f4e41b..239cbdbf4d12 100644 --- a/trunk/Documentation/dvb/get_dvb_firmware +++ b/trunk/Documentation/dvb/get_dvb_firmware @@ -26,7 +26,7 @@ use IO::Handle; "dec3000s", "vp7041", "dibusb", "nxt2002", "nxt2004", "or51211", "or51132_qam", "or51132_vsb", "bluebird", "opera1", "cx231xx", "cx18", "cx23885", "pvrusb2", "mpc718", - "af9015", "ngene", "az6027"); + "af9015", "ngene"); # Check args syntax() if (scalar(@ARGV) != 1); @@ -518,11 +518,11 @@ sub bluebird { sub af9015 { my $sourcefile = "download.ashx?file=57"; my $url = "http://www.ite.com.tw/EN/Services/$sourcefile"; - my $hash = "e3f08935158038d385ad382442f4bb2d"; + my $hash = "ff5b096ed47c080870eacdab2de33ad6"; my $outfile = "dvb-usb-af9015.fw"; my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); - my $fwoffset = 0x25690; - my $fwlength = 18725; + my $fwoffset = 0x22708; + my $fwlength = 18225; my ($chunklength, $buf, $rcount); checkstandard(); @@ -567,23 +567,6 @@ sub ngene { "$file1, $file2"; } -sub az6027{ - my $file = "AZ6027_Linux_Driver.tar.gz"; - my $url = "http://linux.terratec.de/files/$file"; - my $firmware = "dvb-usb-az6027-03.fw"; - - wgetfile($file, $url); - - #untar - if( system("tar xzvf $file $firmware")){ - die "failed to untar firmware"; - } - if( system("rm $file")){ - die ("unable to remove unnecessary files"); - } - - $firmware; -} # --------------------------------------------------------------- # Utilities diff --git a/trunk/Documentation/feature-removal-schedule.txt b/trunk/Documentation/feature-removal-schedule.txt index b273d35039ed..1571c0c83dba 100644 --- a/trunk/Documentation/feature-removal-schedule.txt +++ b/trunk/Documentation/feature-removal-schedule.txt @@ -459,6 +459,57 @@ Who: Corentin Chary ---------------------------- +What: usbvideo quickcam_messenger driver +When: 2.6.35 +Files: drivers/media/video/usbvideo/quickcam_messenger.[ch] +Why: obsolete v4l1 driver replaced by gspca_stv06xx +Who: Hans de Goede + +---------------------------- + +What: ov511 v4l1 driver +When: 2.6.35 +Files: drivers/media/video/ov511.[ch] +Why: obsolete v4l1 driver replaced by gspca_ov519 +Who: Hans de Goede + +---------------------------- + +What: w9968cf v4l1 driver +When: 2.6.35 +Files: drivers/media/video/w9968cf*.[ch] +Why: obsolete v4l1 driver replaced by gspca_ov519 +Who: Hans de Goede + +---------------------------- + +What: ovcamchip sensor framework +When: 2.6.35 +Files: drivers/media/video/ovcamchip/* +Why: Only used by obsoleted v4l1 drivers +Who: Hans de Goede + +---------------------------- + +What: stv680 v4l1 driver +When: 2.6.35 +Files: drivers/media/video/stv680.[ch] +Why: obsolete v4l1 driver replaced by gspca_stv0680 +Who: Hans de Goede + +---------------------------- + +What: zc0301 v4l driver +When: 2.6.35 +Files: drivers/media/video/zc0301/* +Why: Duplicate functionality with the gspca_zc3xx driver, zc0301 only + supports 2 USB-ID's (because it only supports a limited set of + sensors) wich are also supported by the gspca_zc3xx driver + (which supports 53 USB-ID's in total) +Who: Hans de Goede + +---------------------------- + What: sysfs-class-rfkill state file When: Feb 2014 Files: net/rfkill/core.c @@ -487,6 +538,17 @@ Who: Jan Kiszka ---------------------------- +What: KVM memory aliases support +When: July 2010 +Why: Memory aliasing support is used for speeding up guest vga access + through the vga windows. + + Modern userspace no longer uses this feature, so it's just bitrotted + code and can be removed with no impact. +Who: Avi Kivity + +---------------------------- + What: xtime, wall_to_monotonic When: 2.6.36+ Files: kernel/time/timekeeping.c include/linux/time.h @@ -497,6 +559,16 @@ Who: John Stultz ---------------------------- +What: KVM kernel-allocated memory slots +When: July 2010 +Why: Since 2.6.25, kvm supports user-allocated memory slots, which are + much more flexible than kernel-allocated slots. All current userspace + supports the newer interface and this code can be removed with no + impact. +Who: Avi Kivity + +---------------------------- + What: KVM paravirt mmu host support When: January 2011 Why: The paravirt mmu host support is slower than non-paravirt mmu, both diff --git a/trunk/Documentation/filesystems/xfs.txt b/trunk/Documentation/filesystems/xfs.txt index 7bff3e4f35df..9878f50d6ed6 100644 --- a/trunk/Documentation/filesystems/xfs.txt +++ b/trunk/Documentation/filesystems/xfs.txt @@ -131,6 +131,17 @@ When mounting an XFS filesystem, the following options are accepted. Don't check for double mounted file systems using the file system uuid. This is useful to mount LVM snapshot volumes. + osyncisosync + Make O_SYNC writes implement true O_SYNC. WITHOUT this option, + Linux XFS behaves as if an "osyncisdsync" option is used, + which will make writes to files opened with the O_SYNC flag set + behave as if the O_DSYNC flag had been used instead. + This can result in better performance without compromising + data safety. + However if this option is not in effect, timestamp updates from + O_SYNC writes can be lost if the system crashes. + If timestamp updates are critical, use the osyncisosync option. + uquota/usrquota/uqnoenforce/quota User disk quota accounting enabled, and limits (optionally) enforced. Refer to xfs_quota(8) for further details. diff --git a/trunk/Documentation/input/multi-touch-protocol.txt b/trunk/Documentation/input/multi-touch-protocol.txt index bdcba154b83e..c0fc1c75fd88 100644 --- a/trunk/Documentation/input/multi-touch-protocol.txt +++ b/trunk/Documentation/input/multi-touch-protocol.txt @@ -6,149 +6,31 @@ Multi-touch (MT) Protocol Introduction ------------ -In order to utilize the full power of the new multi-touch and multi-user -devices, a way to report detailed data from multiple contacts, i.e., -objects in direct contact with the device surface, is needed. This -document describes the multi-touch (MT) protocol which allows kernel -drivers to report details for an arbitrary number of contacts. - -The protocol is divided into two types, depending on the capabilities of the -hardware. For devices handling anonymous contacts (type A), the protocol -describes how to send the raw data for all contacts to the receiver. For -devices capable of tracking identifiable contacts (type B), the protocol -describes how to send updates for individual contacts via event slots. - - -Protocol Usage --------------- - -Contact details are sent sequentially as separate packets of ABS_MT -events. Only the ABS_MT events are recognized as part of a contact -packet. Since these events are ignored by current single-touch (ST) -applications, the MT protocol can be implemented on top of the ST protocol -in an existing driver. - -Drivers for type A devices separate contact packets by calling -input_mt_sync() at the end of each packet. This generates a SYN_MT_REPORT -event, which instructs the receiver to accept the data for the current -contact and prepare to receive another. - -Drivers for type B devices separate contact packets by calling -input_mt_slot(), with a slot as argument, at the beginning of each packet. -This generates an ABS_MT_SLOT event, which instructs the receiver to -prepare for updates of the given slot. - -All drivers mark the end of a multi-touch transfer by calling the usual -input_sync() function. This instructs the receiver to act upon events -accumulated since last EV_SYN/SYN_REPORT and prepare to receive a new set -of events/packets. - -The main difference between the stateless type A protocol and the stateful -type B slot protocol lies in the usage of identifiable contacts to reduce -the amount of data sent to userspace. The slot protocol requires the use of -the ABS_MT_TRACKING_ID, either provided by the hardware or computed from -the raw data [5]. - -For type A devices, the kernel driver should generate an arbitrary -enumeration of the full set of anonymous contacts currently on the -surface. The order in which the packets appear in the event stream is not -important. Event filtering and finger tracking is left to user space [3]. - -For type B devices, the kernel driver should associate a slot with each -identified contact, and use that slot to propagate changes for the contact. -Creation, replacement and destruction of contacts is achieved by modifying -the ABS_MT_TRACKING_ID of the associated slot. A non-negative tracking id -is interpreted as a contact, and the value -1 denotes an unused slot. A -tracking id not previously present is considered new, and a tracking id no -longer present is considered removed. Since only changes are propagated, -the full state of each initiated contact has to reside in the receiving -end. Upon receiving an MT event, one simply updates the appropriate -attribute of the current slot. - - -Protocol Example A ------------------- - -Here is what a minimal event sequence for a two-contact touch would look -like for a type A device: - - ABS_MT_POSITION_X x[0] - ABS_MT_POSITION_Y y[0] - SYN_MT_REPORT - ABS_MT_POSITION_X x[1] - ABS_MT_POSITION_Y y[1] - SYN_MT_REPORT - SYN_REPORT - -The sequence after moving one of the contacts looks exactly the same; the -raw data for all present contacts are sent between every synchronization -with SYN_REPORT. - -Here is the sequence after lifting the first contact: - - ABS_MT_POSITION_X x[1] - ABS_MT_POSITION_Y y[1] - SYN_MT_REPORT - SYN_REPORT - -And here is the sequence after lifting the second contact: - - SYN_MT_REPORT - SYN_REPORT - -If the driver reports one of BTN_TOUCH or ABS_PRESSURE in addition to the -ABS_MT events, the last SYN_MT_REPORT event may be omitted. Otherwise, the -last SYN_REPORT will be dropped by the input core, resulting in no -zero-contact event reaching userland. +In order to utilize the full power of the new multi-touch devices, a way to +report detailed finger data to user space is needed. This document +describes the multi-touch (MT) protocol which allows kernel drivers to +report details for an arbitrary number of fingers. -Protocol Example B ------------------- - -Here is what a minimal event sequence for a two-contact touch would look -like for a type B device: - - ABS_MT_SLOT 0 - ABS_MT_TRACKING_ID 45 - ABS_MT_POSITION_X x[0] - ABS_MT_POSITION_Y y[0] - ABS_MT_SLOT 1 - ABS_MT_TRACKING_ID 46 - ABS_MT_POSITION_X x[1] - ABS_MT_POSITION_Y y[1] - SYN_REPORT - -Here is the sequence after moving contact 45 in the x direction: - - ABS_MT_SLOT 0 - ABS_MT_POSITION_X x[0] - SYN_REPORT - -Here is the sequence after lifting the contact in slot 0: - - ABS_MT_TRACKING_ID -1 - SYN_REPORT - -The slot being modified is already 0, so the ABS_MT_SLOT is omitted. The -message removes the association of slot 0 with contact 45, thereby -destroying contact 45 and freeing slot 0 to be reused for another contact. - -Finally, here is the sequence after lifting the second contact: - - ABS_MT_SLOT 1 - ABS_MT_TRACKING_ID -1 - SYN_REPORT - +Usage +----- -Event Usage ------------ +Anonymous finger details are sent sequentially as separate packets of ABS +events. Only the ABS_MT events are recognized as part of a finger +packet. The end of a packet is marked by calling the input_mt_sync() +function, which generates a SYN_MT_REPORT event. This instructs the +receiver to accept the data for the current finger and prepare to receive +another. The end of a multi-touch transfer is marked by calling the usual +input_sync() function. This instructs the receiver to act upon events +accumulated since last EV_SYN/SYN_REPORT and prepare to receive a new +set of events/packets. A set of ABS_MT events with the desired properties is defined. The events are divided into categories, to allow for partial implementation. The minimum set consists of ABS_MT_POSITION_X and ABS_MT_POSITION_Y, which -allows for multiple contacts to be tracked. If the device supports it, the +allows for multiple fingers to be tracked. If the device supports it, the ABS_MT_TOUCH_MAJOR and ABS_MT_WIDTH_MAJOR may be used to provide the size -of the contact area and approaching contact, respectively. +of the contact area and approaching finger, respectively. The TOUCH and WIDTH parameters have a geometrical interpretation; imagine looking through a window at someone gently holding a finger against the @@ -159,26 +41,56 @@ ABS_MT_TOUCH_MAJOR, the diameter of the outer region is ABS_MT_WIDTH_MAJOR. Now imagine the person pressing the finger harder against the glass. The inner region will increase, and in general, the ratio ABS_MT_TOUCH_MAJOR / ABS_MT_WIDTH_MAJOR, which is always smaller than -unity, is related to the contact pressure. For pressure-based devices, +unity, is related to the finger pressure. For pressure-based devices, ABS_MT_PRESSURE may be used to provide the pressure on the contact area instead. -In addition to the MAJOR parameters, the oval shape of the contact can be +In addition to the MAJOR parameters, the oval shape of the finger can be described by adding the MINOR parameters, such that MAJOR and MINOR are the major and minor axis of an ellipse. Finally, the orientation of the oval shape can be describe with the ORIENTATION parameter. The ABS_MT_TOOL_TYPE may be used to specify whether the touching tool is a -contact or a pen or something else. Devices with more granular information +finger or a pen or something else. Devices with more granular information may specify general shapes as blobs, i.e., as a sequence of rectangular shapes grouped together by an ABS_MT_BLOB_ID. Finally, for the few devices that currently support it, the ABS_MT_TRACKING_ID event may be used to -report contact tracking from hardware [5]. +report finger tracking from hardware [5]. +Here is what a minimal event sequence for a two-finger touch would look +like: + + ABS_MT_POSITION_X + ABS_MT_POSITION_Y + SYN_MT_REPORT + ABS_MT_POSITION_X + ABS_MT_POSITION_Y + SYN_MT_REPORT + SYN_REPORT + +Here is the sequence after lifting one of the fingers: + + ABS_MT_POSITION_X + ABS_MT_POSITION_Y + SYN_MT_REPORT + SYN_REPORT + +And here is the sequence after lifting the remaining finger: + + SYN_MT_REPORT + SYN_REPORT + +If the driver reports one of BTN_TOUCH or ABS_PRESSURE in addition to the +ABS_MT events, the last SYN_MT_REPORT event may be omitted. Otherwise, the +last SYN_REPORT will be dropped by the input core, resulting in no +zero-finger event reaching userland. Event Semantics --------------- +The word "contact" is used to describe a tool which is in direct contact +with the surface. A finger, a pen or a rubber all classify as contacts. + ABS_MT_TOUCH_MAJOR The length of the major axis of the contact. The length should be given in @@ -245,16 +157,15 @@ MT_TOOL_PEN [2]. ABS_MT_BLOB_ID The BLOB_ID groups several packets together into one arbitrarily shaped -contact. This is a low-level anonymous grouping for type A devices, and -should not be confused with the high-level trackingID [5]. Most type A -devices do not have blob capability, so drivers can safely omit this event. +contact. This is a low-level anonymous grouping, and should not be confused +with the high-level trackingID [5]. Most kernel drivers will not have blob +capability, and can safely omit the event. ABS_MT_TRACKING_ID The TRACKING_ID identifies an initiated contact throughout its life cycle -[5]. This event is mandatory for type B devices. The value range of the -TRACKING_ID should be large enough to ensure unique identification of a -contact maintained over an extended period of time. +[5]. There are currently only a few devices that support it, so this event +should normally be omitted. Event Computation @@ -281,11 +192,20 @@ finger along the X axis (1). Finger Tracking --------------- +The kernel driver should generate an arbitrary enumeration of the set of +anonymous contacts currently on the surface. The order in which the packets +appear in the event stream is not important. + The process of finger tracking, i.e., to assign a unique trackingID to each -initiated contact on the surface, is a Euclidian Bipartite Matching -problem. At each event synchronization, the set of actual contacts is -matched to the set of contacts from the previous synchronization. A full -implementation can be found in [3]. +initiated contact on the surface, is left to user space; preferably the +multi-touch X driver [3]. In that driver, the trackingID stays the same and +unique until the contact vanishes (when the finger leaves the surface). The +problem of assigning a set of anonymous fingers to a set of identified +fingers is a euclidian bipartite matching problem at each event update, and +relies on a sufficiently rapid update rate. + +There are a few devices that support trackingID in hardware. User space can +make use of these native identifiers to reduce bandwidth and cpu usage. Gestures diff --git a/trunk/Documentation/kernel-parameters.txt b/trunk/Documentation/kernel-parameters.txt index b61f89fa01c1..2b2407d9a6d0 100644 --- a/trunk/Documentation/kernel-parameters.txt +++ b/trunk/Documentation/kernel-parameters.txt @@ -93,7 +93,6 @@ parameter is applicable: Documentation/scsi/. SECURITY Different security models are enabled. SELINUX SELinux support is enabled. - APPARMOR AppArmor support is enabled. SERIAL Serial support is enabled. SH SuperH architecture is enabled. SMP The kernel is an SMP kernel. @@ -2313,13 +2312,6 @@ and is between 256 and 4096 characters. It is defined in the file If enabled at boot time, /selinux/disable can be used later to disable prior to initial policy load. - apparmor= [APPARMOR] Disable or enable AppArmor at boot time - Format: { "0" | "1" } - See security/apparmor/Kconfig help text - 0 -- disable. - 1 -- enable. - Default value is set via kernel config option. - serialnumber [BUGS=X86-32] shapers= [NET] diff --git a/trunk/Documentation/kvm/api.txt b/trunk/Documentation/kvm/api.txt index 5f5b64982b1a..a237518e51b9 100644 --- a/trunk/Documentation/kvm/api.txt +++ b/trunk/Documentation/kvm/api.txt @@ -126,10 +126,6 @@ user fills in the size of the indices array in nmsrs, and in return kvm adjusts nmsrs to reflect the actual number of msrs and fills in the indices array with their numbers. -Note: if kvm indicates supports MCE (KVM_CAP_MCE), then the MCE bank MSRs are -not returned in the MSR list, as different vcpus can have a different number -of banks, as set via the KVM_X86_SETUP_MCE ioctl. - 4.4 KVM_CHECK_EXTENSION Capability: basic @@ -164,7 +160,29 @@ Type: vm ioctl Parameters: struct kvm_memory_region (in) Returns: 0 on success, -1 on error -This ioctl is obsolete and has been removed. +struct kvm_memory_region { + __u32 slot; + __u32 flags; + __u64 guest_phys_addr; + __u64 memory_size; /* bytes */ +}; + +/* for kvm_memory_region::flags */ +#define KVM_MEM_LOG_DIRTY_PAGES 1UL + +This ioctl allows the user to create or modify a guest physical memory +slot. When changing an existing slot, it may be moved in the guest +physical memory space, or its flags may be modified. It may not be +resized. Slots may not overlap. + +The flags field supports just one flag, KVM_MEM_LOG_DIRTY_PAGES, which +instructs kvm to keep track of writes to memory within the slot. See +the KVM_GET_DIRTY_LOG ioctl. + +It is recommended to use the KVM_SET_USER_MEMORY_REGION ioctl instead +of this API, if available. This newer API allows placing guest memory +at specified locations in the host address space, yielding better +control and easy access. 4.6 KVM_CREATE_VCPU @@ -208,7 +226,17 @@ Type: vm ioctl Parameters: struct kvm_memory_alias (in) Returns: 0 (success), -1 (error) -This ioctl is obsolete and has been removed. +struct kvm_memory_alias { + __u32 slot; /* this has a different namespace than memory slots */ + __u32 flags; + __u64 guest_phys_addr; + __u64 memory_size; + __u64 target_phys_addr; +}; + +Defines a guest physical address space region as an alias to another +region. Useful for aliased address, for example the VGA low memory +window. Should not be used with userspace memory. 4.9 KVM_RUN @@ -864,174 +892,6 @@ arguments. This ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace. -4.39 KVM_SET_IDENTITY_MAP_ADDR - -Capability: KVM_CAP_SET_IDENTITY_MAP_ADDR -Architectures: x86 -Type: vm ioctl -Parameters: unsigned long identity (in) -Returns: 0 on success, -1 on error - -This ioctl defines the physical address of a one-page region in the guest -physical address space. The region must be within the first 4GB of the -guest physical address space and must not conflict with any memory slot -or any mmio address. The guest may malfunction if it accesses this memory -region. - -This ioctl is required on Intel-based hosts. This is needed on Intel hardware -because of a quirk in the virtualization implementation (see the internals -documentation when it pops into existence). - -4.40 KVM_SET_BOOT_CPU_ID - -Capability: KVM_CAP_SET_BOOT_CPU_ID -Architectures: x86, ia64 -Type: vm ioctl -Parameters: unsigned long vcpu_id -Returns: 0 on success, -1 on error - -Define which vcpu is the Bootstrap Processor (BSP). Values are the same -as the vcpu id in KVM_CREATE_VCPU. If this ioctl is not called, the default -is vcpu 0. - -4.41 KVM_GET_XSAVE - -Capability: KVM_CAP_XSAVE -Architectures: x86 -Type: vcpu ioctl -Parameters: struct kvm_xsave (out) -Returns: 0 on success, -1 on error - -struct kvm_xsave { - __u32 region[1024]; -}; - -This ioctl would copy current vcpu's xsave struct to the userspace. - -4.42 KVM_SET_XSAVE - -Capability: KVM_CAP_XSAVE -Architectures: x86 -Type: vcpu ioctl -Parameters: struct kvm_xsave (in) -Returns: 0 on success, -1 on error - -struct kvm_xsave { - __u32 region[1024]; -}; - -This ioctl would copy userspace's xsave struct to the kernel. - -4.43 KVM_GET_XCRS - -Capability: KVM_CAP_XCRS -Architectures: x86 -Type: vcpu ioctl -Parameters: struct kvm_xcrs (out) -Returns: 0 on success, -1 on error - -struct kvm_xcr { - __u32 xcr; - __u32 reserved; - __u64 value; -}; - -struct kvm_xcrs { - __u32 nr_xcrs; - __u32 flags; - struct kvm_xcr xcrs[KVM_MAX_XCRS]; - __u64 padding[16]; -}; - -This ioctl would copy current vcpu's xcrs to the userspace. - -4.44 KVM_SET_XCRS - -Capability: KVM_CAP_XCRS -Architectures: x86 -Type: vcpu ioctl -Parameters: struct kvm_xcrs (in) -Returns: 0 on success, -1 on error - -struct kvm_xcr { - __u32 xcr; - __u32 reserved; - __u64 value; -}; - -struct kvm_xcrs { - __u32 nr_xcrs; - __u32 flags; - struct kvm_xcr xcrs[KVM_MAX_XCRS]; - __u64 padding[16]; -}; - -This ioctl would set vcpu's xcr to the value userspace specified. - -4.45 KVM_GET_SUPPORTED_CPUID - -Capability: KVM_CAP_EXT_CPUID -Architectures: x86 -Type: system ioctl -Parameters: struct kvm_cpuid2 (in/out) -Returns: 0 on success, -1 on error - -struct kvm_cpuid2 { - __u32 nent; - __u32 padding; - struct kvm_cpuid_entry2 entries[0]; -}; - -#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1 -#define KVM_CPUID_FLAG_STATEFUL_FUNC 2 -#define KVM_CPUID_FLAG_STATE_READ_NEXT 4 - -struct kvm_cpuid_entry2 { - __u32 function; - __u32 index; - __u32 flags; - __u32 eax; - __u32 ebx; - __u32 ecx; - __u32 edx; - __u32 padding[3]; -}; - -This ioctl returns x86 cpuid features which are supported by both the hardware -and kvm. Userspace can use the information returned by this ioctl to -construct cpuid information (for KVM_SET_CPUID2) that is consistent with -hardware, kernel, and userspace capabilities, and with user requirements (for -example, the user may wish to constrain cpuid to emulate older hardware, -or for feature consistency across a cluster). - -Userspace invokes KVM_GET_SUPPORTED_CPUID by passing a kvm_cpuid2 structure -with the 'nent' field indicating the number of entries in the variable-size -array 'entries'. If the number of entries is too low to describe the cpu -capabilities, an error (E2BIG) is returned. If the number is too high, -the 'nent' field is adjusted and an error (ENOMEM) is returned. If the -number is just right, the 'nent' field is adjusted to the number of valid -entries in the 'entries' array, which is then filled. - -The entries returned are the host cpuid as returned by the cpuid instruction, -with unknown or unsupported features masked out. The fields in each entry -are defined as follows: - - function: the eax value used to obtain the entry - index: the ecx value used to obtain the entry (for entries that are - affected by ecx) - flags: an OR of zero or more of the following: - KVM_CPUID_FLAG_SIGNIFCANT_INDEX: - if the index field is valid - KVM_CPUID_FLAG_STATEFUL_FUNC: - if cpuid for this function returns different values for successive - invocations; there will be several entries with the same function, - all with this flag set - KVM_CPUID_FLAG_STATE_READ_NEXT: - for KVM_CPUID_FLAG_STATEFUL_FUNC entries, set if this entry is - the first entry to be read by a cpu - eax, ebx, ecx, edx: the values returned by the cpuid instruction for - this function/index combination - 5. The kvm_run structure Application code obtains a pointer to the kvm_run structure by diff --git a/trunk/Documentation/kvm/mmu.txt b/trunk/Documentation/kvm/mmu.txt index 142cc5136650..aaed6ab9d7ab 100644 --- a/trunk/Documentation/kvm/mmu.txt +++ b/trunk/Documentation/kvm/mmu.txt @@ -77,10 +77,10 @@ Memory Guest memory (gpa) is part of the user address space of the process that is using kvm. Userspace defines the translation between guest addresses and user -addresses (gpa->hva); note that two gpas may alias to the same hva, but not +addresses (gpa->hva); note that two gpas may alias to the same gva, but not vice versa. -These hvas may be backed using any method available to the host: anonymous +These gvas may be backed using any method available to the host: anonymous memory, file backed memory, and device memory. Memory might be paged by the host at any time. @@ -161,7 +161,7 @@ Shadow pages contain the following information: role.cr4_pae: Contains the value of cr4.pae for which the page is valid (e.g. whether 32-bit or 64-bit gptes are in use). - role.nxe: + role.cr4_nxe: Contains the value of efer.nxe for which the page is valid. role.cr0_wp: Contains the value of cr0.wp for which the page is valid. @@ -180,9 +180,7 @@ Shadow pages contain the following information: guest pages as leaves. gfns: An array of 512 guest frame numbers, one for each present pte. Used to - perform a reverse map from a pte to a gfn. When role.direct is set, any - element of this array can be calculated from the gfn field when used, in - this case, the array of gfns is not allocated. See role.direct and gfn. + perform a reverse map from a pte to a gfn. slot_bitmap: A bitmap containing one bit per memory slot. If the page contains a pte mapping a page from memory slot n, then bit n of slot_bitmap will be set @@ -298,48 +296,6 @@ Host translation updates: - look up affected sptes through reverse map - drop (or update) translations -Emulating cr0.wp -================ - -If tdp is not enabled, the host must keep cr0.wp=1 so page write protection -works for the guest kernel, not guest guest userspace. When the guest -cr0.wp=1, this does not present a problem. However when the guest cr0.wp=0, -we cannot map the permissions for gpte.u=1, gpte.w=0 to any spte (the -semantics require allowing any guest kernel access plus user read access). - -We handle this by mapping the permissions to two possible sptes, depending -on fault type: - -- kernel write fault: spte.u=0, spte.w=1 (allows full kernel access, - disallows user access) -- read fault: spte.u=1, spte.w=0 (allows full read access, disallows kernel - write access) - -(user write faults generate a #PF) - -Large pages -=========== - -The mmu supports all combinations of large and small guest and host pages. -Supported page sizes include 4k, 2M, 4M, and 1G. 4M pages are treated as -two separate 2M pages, on both guest and host, since the mmu always uses PAE -paging. - -To instantiate a large spte, four constraints must be satisfied: - -- the spte must point to a large host page -- the guest pte must be a large pte of at least equivalent size (if tdp is - enabled, there is no guest pte and this condition is satisified) -- if the spte will be writeable, the large page frame may not overlap any - write-protected pages -- the guest page must be wholly contained by a single memory slot - -To check the last two conditions, the mmu maintains a ->write_count set of -arrays for each memory slot and large page size. Every write protected page -causes its write_count to be incremented, thus preventing instantiation of -a large spte. The frames at the end of an unaligned memory slot have -artificically inflated ->write_counts so they can never be instantiated. - Further reading =============== diff --git a/trunk/Documentation/kvm/msr.txt b/trunk/Documentation/kvm/msr.txt deleted file mode 100644 index 8ddcfe84c09a..000000000000 --- a/trunk/Documentation/kvm/msr.txt +++ /dev/null @@ -1,153 +0,0 @@ -KVM-specific MSRs. -Glauber Costa , Red Hat Inc, 2010 -===================================================== - -KVM makes use of some custom MSRs to service some requests. -At present, this facility is only used by kvmclock. - -Custom MSRs have a range reserved for them, that goes from -0x4b564d00 to 0x4b564dff. There are MSRs outside this area, -but they are deprecated and their use is discouraged. - -Custom MSR list --------- - -The current supported Custom MSR list is: - -MSR_KVM_WALL_CLOCK_NEW: 0x4b564d00 - - data: 4-byte alignment physical address of a memory area which must be - in guest RAM. This memory is expected to hold a copy of the following - structure: - - struct pvclock_wall_clock { - u32 version; - u32 sec; - u32 nsec; - } __attribute__((__packed__)); - - whose data will be filled in by the hypervisor. The hypervisor is only - guaranteed to update this data at the moment of MSR write. - Users that want to reliably query this information more than once have - to write more than once to this MSR. Fields have the following meanings: - - version: guest has to check version before and after grabbing - time information and check that they are both equal and even. - An odd version indicates an in-progress update. - - sec: number of seconds for wallclock. - - nsec: number of nanoseconds for wallclock. - - Note that although MSRs are per-CPU entities, the effect of this - particular MSR is global. - - Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid - leaf prior to usage. - -MSR_KVM_SYSTEM_TIME_NEW: 0x4b564d01 - - data: 4-byte aligned physical address of a memory area which must be in - guest RAM, plus an enable bit in bit 0. This memory is expected to hold - a copy of the following structure: - - struct pvclock_vcpu_time_info { - u32 version; - u32 pad0; - u64 tsc_timestamp; - u64 system_time; - u32 tsc_to_system_mul; - s8 tsc_shift; - u8 flags; - u8 pad[2]; - } __attribute__((__packed__)); /* 32 bytes */ - - whose data will be filled in by the hypervisor periodically. Only one - write, or registration, is needed for each VCPU. The interval between - updates of this structure is arbitrary and implementation-dependent. - The hypervisor may update this structure at any time it sees fit until - anything with bit0 == 0 is written to it. - - Fields have the following meanings: - - version: guest has to check version before and after grabbing - time information and check that they are both equal and even. - An odd version indicates an in-progress update. - - tsc_timestamp: the tsc value at the current VCPU at the time - of the update of this structure. Guests can subtract this value - from current tsc to derive a notion of elapsed time since the - structure update. - - system_time: a host notion of monotonic time, including sleep - time at the time this structure was last updated. Unit is - nanoseconds. - - tsc_to_system_mul: a function of the tsc frequency. One has - to multiply any tsc-related quantity by this value to get - a value in nanoseconds, besides dividing by 2^tsc_shift - - tsc_shift: cycle to nanosecond divider, as a power of two, to - allow for shift rights. One has to shift right any tsc-related - quantity by this value to get a value in nanoseconds, besides - multiplying by tsc_to_system_mul. - - With this information, guests can derive per-CPU time by - doing: - - time = (current_tsc - tsc_timestamp) - time = (time * tsc_to_system_mul) >> tsc_shift - time = time + system_time - - flags: bits in this field indicate extended capabilities - coordinated between the guest and the hypervisor. Availability - of specific flags has to be checked in 0x40000001 cpuid leaf. - Current flags are: - - flag bit | cpuid bit | meaning - ------------------------------------------------------------- - | | time measures taken across - 0 | 24 | multiple cpus are guaranteed to - | | be monotonic - ------------------------------------------------------------- - - Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid - leaf prior to usage. - - -MSR_KVM_WALL_CLOCK: 0x11 - - data and functioning: same as MSR_KVM_WALL_CLOCK_NEW. Use that instead. - - This MSR falls outside the reserved KVM range and may be removed in the - future. Its usage is deprecated. - - Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid - leaf prior to usage. - -MSR_KVM_SYSTEM_TIME: 0x12 - - data and functioning: same as MSR_KVM_SYSTEM_TIME_NEW. Use that instead. - - This MSR falls outside the reserved KVM range and may be removed in the - future. Its usage is deprecated. - - Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid - leaf prior to usage. - - The suggested algorithm for detecting kvmclock presence is then: - - if (!kvm_para_available()) /* refer to cpuid.txt */ - return NON_PRESENT; - - flags = cpuid_eax(0x40000001); - if (flags & 3) { - msr_kvm_system_time = MSR_KVM_SYSTEM_TIME_NEW; - msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK_NEW; - return PRESENT; - } else if (flags & 0) { - msr_kvm_system_time = MSR_KVM_SYSTEM_TIME; - msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK; - return PRESENT; - } else - return NON_PRESENT; diff --git a/trunk/Documentation/kvm/review-checklist.txt b/trunk/Documentation/kvm/review-checklist.txt deleted file mode 100644 index 730475ae1b8d..000000000000 --- a/trunk/Documentation/kvm/review-checklist.txt +++ /dev/null @@ -1,38 +0,0 @@ -Review checklist for kvm patches -================================ - -1. The patch must follow Documentation/CodingStyle and - Documentation/SubmittingPatches. - -2. Patches should be against kvm.git master branch. - -3. If the patch introduces or modifies a new userspace API: - - the API must be documented in Documentation/kvm/api.txt - - the API must be discoverable using KVM_CHECK_EXTENSION - -4. New state must include support for save/restore. - -5. New features must default to off (userspace should explicitly request them). - Performance improvements can and should default to on. - -6. New cpu features should be exposed via KVM_GET_SUPPORTED_CPUID2 - -7. Emulator changes should be accompanied by unit tests for qemu-kvm.git - kvm/test directory. - -8. Changes should be vendor neutral when possible. Changes to common code - are better than duplicating changes to vendor code. - -9. Similarly, prefer changes to arch independent code than to arch dependent - code. - -10. User/kernel interfaces and guest/host interfaces must be 64-bit clean - (all variables and sizes naturally aligned on 64-bit; use specific types - only - u64 rather than ulong). - -11. New guest visible features must either be documented in a hardware manual - or be accompanied by documentation. - -12. Features must be robust against reset and kexec - for example, shared - host/guest memory must be unshared to prevent the host from writing to - guest memory that the guest has not reserved for this purpose. diff --git a/trunk/Documentation/tomoyo.txt b/trunk/Documentation/tomoyo.txt index 200a2d37cbc8..b3a232cae7f8 100644 --- a/trunk/Documentation/tomoyo.txt +++ b/trunk/Documentation/tomoyo.txt @@ -3,8 +3,8 @@ TOMOYO is a name-based MAC extension (LSM module) for the Linux kernel. LiveCD-based tutorials are available at -http://tomoyo.sourceforge.jp/1.7/1st-step/ubuntu10.04-live/ -http://tomoyo.sourceforge.jp/1.7/1st-step/centos5-live/ . +http://tomoyo.sourceforge.jp/en/1.6.x/1st-step/ubuntu8.04-live/ +http://tomoyo.sourceforge.jp/en/1.6.x/1st-step/centos5-live/ . Though these tutorials use non-LSM version of TOMOYO, they are useful for you to know what TOMOYO is. @@ -13,12 +13,12 @@ to know what TOMOYO is. Build the kernel with CONFIG_SECURITY_TOMOYO=y and pass "security=tomoyo" on kernel's command line. -Please see http://tomoyo.sourceforge.jp/2.3/ for details. +Please see http://tomoyo.sourceforge.jp/en/2.2.x/ for details. --- Where is documentation? --- User <-> Kernel interface documentation is available at -http://tomoyo.sourceforge.jp/2.3/policy-reference.html . +http://tomoyo.sourceforge.jp/en/2.2.x/policy-reference.html . Materials we prepared for seminars and symposiums are available at http://sourceforge.jp/projects/tomoyo/docs/?category_id=532&language_id=1 . @@ -50,6 +50,6 @@ multiple LSM modules at the same time. We feel sorry that you have to give up SELinux/SMACK/AppArmor etc. when you want to use TOMOYO. We hope that LSM becomes stackable in future. Meanwhile, you can use non-LSM -version of TOMOYO, available at http://tomoyo.sourceforge.jp/1.7/ . +version of TOMOYO, available at http://tomoyo.sourceforge.jp/en/1.6.x/ . LSM version of TOMOYO is a subset of non-LSM version of TOMOYO. We are planning to port non-LSM version's functionalities to LSM versions. diff --git a/trunk/Documentation/video4linux/CARDLIST.cx23885 b/trunk/Documentation/video4linux/CARDLIST.cx23885 index 87c46347bd63..16ca030e1185 100644 --- a/trunk/Documentation/video4linux/CARDLIST.cx23885 +++ b/trunk/Documentation/video4linux/CARDLIST.cx23885 @@ -17,9 +17,9 @@ 16 -> DVBWorld DVB-S2 2005 [0001:2005] 17 -> NetUP Dual DVB-S2 CI [1b55:2a2c] 18 -> Hauppauge WinTV-HVR1270 [0070:2211] - 19 -> Hauppauge WinTV-HVR1275 [0070:2215,0070:221d,0070:22f2] - 20 -> Hauppauge WinTV-HVR1255 [0070:2251,0070:2259,0070:22f1] - 21 -> Hauppauge WinTV-HVR1210 [0070:2291,0070:2295,0070:2299,0070:229d,0070:22f0,0070:22f3,0070:22f4,0070:22f5] + 19 -> Hauppauge WinTV-HVR1275 [0070:2215] + 20 -> Hauppauge WinTV-HVR1255 [0070:2251] + 21 -> Hauppauge WinTV-HVR1210 [0070:2291,0070:2295] 22 -> Mygica X8506 DMB-TH [14f1:8651] 23 -> Magic-Pro ProHDTV Extreme 2 [14f1:8657] 24 -> Hauppauge WinTV-HVR1850 [0070:8541] diff --git a/trunk/Documentation/video4linux/CARDLIST.em28xx b/trunk/Documentation/video4linux/CARDLIST.em28xx index 5c568757c301..3a623aaeae5f 100644 --- a/trunk/Documentation/video4linux/CARDLIST.em28xx +++ b/trunk/Documentation/video4linux/CARDLIST.em28xx @@ -72,4 +72,3 @@ 73 -> Reddo DVB-C USB TV Box (em2870) 74 -> Actionmaster/LinXcel/Digitus VC211A (em2800) 75 -> Dikom DK300 (em2882) - 76 -> KWorld PlusTV 340U or UB435-Q (ATSC) (em2870) [1b80:a340] diff --git a/trunk/Documentation/video4linux/CARDLIST.saa7134 b/trunk/Documentation/video4linux/CARDLIST.saa7134 index 4000c29fcfb6..1387a69ae3aa 100644 --- a/trunk/Documentation/video4linux/CARDLIST.saa7134 +++ b/trunk/Documentation/video4linux/CARDLIST.saa7134 @@ -178,5 +178,4 @@ 177 -> Hawell HW-404M7 178 -> Beholder BeholdTV H7 [5ace:7190] 179 -> Beholder BeholdTV A7 [5ace:7090] -180 -> Avermedia PCI M733A [1461:4155,1461:4255] -181 -> TechoTrend TT-budget T-3000 [13c2:2804] +180 -> Avermedia M733A [1461:4155,1461:4255] diff --git a/trunk/Documentation/video4linux/gspca.txt b/trunk/Documentation/video4linux/gspca.txt index 56ba7bba7168..f13eb036c439 100644 --- a/trunk/Documentation/video4linux/gspca.txt +++ b/trunk/Documentation/video4linux/gspca.txt @@ -29,12 +29,8 @@ zc3xx 041e:4029 Creative WebCam Vista Pro zc3xx 041e:4034 Creative Instant P0620 zc3xx 041e:4035 Creative Instant P0620D zc3xx 041e:4036 Creative Live ! -sq930x 041e:4038 Creative Joy-IT zc3xx 041e:403a Creative Nx Pro 2 spca561 041e:403b Creative Webcam Vista (VF0010) -sq930x 041e:403c Creative Live! Ultra -sq930x 041e:403d Creative Live! Ultra for Notebooks -sq930x 041e:4041 Creative Live! Motion zc3xx 041e:4051 Creative Live!Cam Notebook Pro (VF0250) ov519 041e:4052 Creative Live! VISTA IM zc3xx 041e:4053 Creative Live!Cam Video IM @@ -142,7 +138,6 @@ finepix 04cb:013d Fujifilm FinePix unknown model finepix 04cb:013f Fujifilm FinePix F420 sunplus 04f1:1001 JVC GC A50 spca561 04fc:0561 Flexcam 100 -spca1528 04fc:1528 Sunplus MD80 clone sunplus 04fc:500c Sunplus CA500C sunplus 04fc:504a Aiptek Mini PenCam 1.3 sunplus 04fc:504b Maxell MaxPocket LE 1.3 @@ -258,7 +253,6 @@ pac7302 093a:2620 Apollo AC-905 pac7302 093a:2621 PAC731x pac7302 093a:2622 Genius Eye 312 pac7302 093a:2624 PAC7302 -pac7302 093a:2625 Genius iSlim 310 pac7302 093a:2626 Labtec 2200 pac7302 093a:2628 Genius iLook 300 pac7302 093a:2629 Genious iSlim 300 @@ -368,8 +362,6 @@ sq905c 2770:9052 Disney pix micro 2 (VGA) sq905c 2770:905c All 11 known cameras with this ID sq905 2770:9120 All 24 known cameras with this ID sq905c 2770:913d All 4 known cameras with this ID -sq930x 2770:930b Sweex Motion Tracking / I-Tec iCam Tracer -sq930x 2770:930c Trust WB-3500T / NSG Robbie 2.0 spca500 2899:012c Toptro Industrial ov519 8020:ef04 ov519 spca508 8086:0110 Intel Easy PC Camera diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 33606bb91f1f..02f75fccac20 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -5061,14 +5061,6 @@ S: Supported F: include/linux/selinux* F: security/selinux/ -APPARMOR SECURITY MODULE -M: John Johansen -L: apparmor@lists.ubuntu.com (subscribers-only, general discussion) -W: apparmor.wiki.kernel.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/jj/apparmor-dev.git -S: Supported -F: security/apparmor/ - SENSABLE PHANTOM M: Jiri Slaby S: Maintained @@ -5613,7 +5605,7 @@ L: tomoyo-users-en@lists.sourceforge.jp (subscribers-only, for developers and us L: tomoyo-dev@lists.sourceforge.jp (subscribers-only, for developers in Japanese) L: tomoyo-users@lists.sourceforge.jp (subscribers-only, for users in Japanese) W: http://tomoyo.sourceforge.jp/ -T: quilt http://svn.sourceforge.jp/svnroot/tomoyo/trunk/2.3.x/tomoyo-lsm/patches/ +T: quilt http://svn.sourceforge.jp/svnroot/tomoyo/trunk/2.2.x/tomoyo-lsm/patches/ S: Maintained F: security/tomoyo/ diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index e39caa8b0c93..98922f7d2d12 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -10,7 +10,6 @@ config ARM default y select HAVE_AOUT select HAVE_IDE - select HAVE_MEMBLOCK select RTC_LIB select SYS_SUPPORTS_APM_EMULATION select GENERIC_ATOMIC64 if (!CPU_32v6K) @@ -25,7 +24,6 @@ config ARM select HAVE_KERNEL_LZMA select HAVE_PERF_EVENTS select PERF_USE_VMALLOC - select HAVE_REGS_AND_STACK_ACCESS_API help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -57,7 +55,7 @@ config GENERIC_CLOCKEVENTS config GENERIC_CLOCKEVENTS_BROADCAST bool depends on GENERIC_CLOCKEVENTS - default y if SMP + default y if SMP && !LOCAL_TIMERS config HAVE_TCM bool @@ -303,7 +301,6 @@ config ARCH_CNS3XXX select CPU_V6 select GENERIC_CLOCKEVENTS select ARM_GIC - select PCI_DOMAINS if PCI help Support for Cavium Networks CNS3XXX platform. @@ -442,6 +439,21 @@ config ARCH_IXP4XX help Support for Intel's IXP4XX (XScale) family of processors. +config ARCH_L7200 + bool "LinkUp-L7200" + select CPU_ARM720T + select FIQ + select ARCH_USES_GETTIMEOFFSET + help + Say Y here if you intend to run this kernel on a LinkUp Systems + L7200 Software Development Board which uses an ARM720T processor. + Information on this board can be obtained at: + + + + If you have any questions or comments about the Linux kernel port + to this board, send e-mail to . + config ARCH_DOVE bool "Marvell Dove" select PCI @@ -470,19 +482,6 @@ config ARCH_LOKI help Support for the Marvell Loki (88RC8480) SoC. -config ARCH_LPC32XX - bool "NXP LPC32XX" - select CPU_ARM926T - select ARCH_REQUIRE_GPIOLIB - select HAVE_IDE - select ARM_AMBA - select USB_ARCH_HAS_OHCI - select COMMON_CLKDEV - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - help - Support for the NXP LPC32XX family of processors - config ARCH_MV78XX0 bool "Marvell MV78xx0" select CPU_FEROCEON @@ -587,7 +586,6 @@ config ARCH_MSM bool "Qualcomm MSM" select HAVE_CLK select GENERIC_CLOCKEVENTS - select ARCH_REQUIRE_GPIOLIB help Support for Qualcomm MSM/QSD based systems. This runs on the apps processor of the MSM/QSD and depends on a shared memory @@ -721,6 +719,7 @@ config ARCH_SHARK config ARCH_LH7A40X bool "Sharp LH7A40X" select CPU_ARM922T + select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM select ARCH_USES_GETTIMEOFFSET help @@ -846,8 +845,6 @@ source "arch/arm/mach-lh7a40x/Kconfig" source "arch/arm/mach-loki/Kconfig" -source "arch/arm/mach-lpc32xx/Kconfig" - source "arch/arm/mach-msm/Kconfig" source "arch/arm/mach-mv78xx0/Kconfig" @@ -1034,6 +1031,11 @@ endmenu source "arch/arm/common/Kconfig" +config FORCE_MAX_ZONEORDER + int + depends on SA1111 + default "9" + menu "Bus support" config ARM_AMBA @@ -1058,7 +1060,7 @@ config ISA_DMA_API bool config PCI - bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX + bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@ -1170,10 +1172,9 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \ - REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ - ARCH_U8500 || ARCH_VEXPRESS_CA9X4) + REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500) default y - select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500) + select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500) help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system @@ -1184,10 +1185,10 @@ source kernel/Kconfig.preempt config HZ int + default 128 if ARCH_L7200 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default AT91_TIMER_HZ if ARCH_AT91 - default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE default 100 config THUMB2_KERNEL @@ -1240,6 +1241,10 @@ config OABI_COMPAT config ARCH_HAS_HOLES_MEMORYMODEL bool +# Discontigmem is deprecated +config ARCH_DISCONTIGMEM_ENABLE + bool + config ARCH_SPARSEMEM_ENABLE bool @@ -1247,7 +1252,13 @@ config ARCH_SPARSEMEM_DEFAULT def_bool ARCH_SPARSEMEM_ENABLE config ARCH_SELECT_MEMORY_MODEL - def_bool ARCH_SPARSEMEM_ENABLE + def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE + +config NODES_SHIFT + int + default "4" if ARCH_LH7A40X + default "2" + depends on NEED_MULTIPLE_NODES config HIGHMEM bool "High Memory Support (EXPERIMENTAL)" @@ -1279,33 +1290,8 @@ config HW_PERF_EVENTS Enable hardware performance counter support for perf events. If disabled, perf events will use software events only. -config SPARSE_IRQ - def_bool n - help - This enables support for sparse irqs. This is useful in general - as most CPUs have a fairly sparse array of IRQ vectors, which - the irq_desc then maps directly on to. Systems with a high - number of off-chip IRQs will want to treat this as - experimental until they have been independently verified. - source "mm/Kconfig" -config FORCE_MAX_ZONEORDER - int "Maximum zone order" if ARCH_SHMOBILE - range 11 64 if ARCH_SHMOBILE - default "9" if SA1111 - default "11" - help - The kernel memory allocator divides physically contiguous memory - blocks into "zones", where each zone is a power of two number of - pages. This option selects the largest power of two that the kernel - keeps in the memory allocator. If you need to allocate very large - blocks of physically contiguous memory, then you may need to - increase this value. - - This config option is actually maximum order plus one. For example, - a value of 11 means that the largest free memory block is 2^10 pages. - config LEDS bool "Timer and CPU usage LEDs" depends on ARCH_CDB89712 || ARCH_EBSA110 || \ @@ -1389,24 +1375,6 @@ config UACCESS_WITH_MEMCPY However, if the CPU data cache is using a write-allocate mode, this option is unlikely to provide any performance gain. -config CC_STACKPROTECTOR - bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" - help - This option turns on the -fstack-protector GCC feature. This - feature puts, at the beginning of functions, a canary value on - the stack just before the return address, and validates - the value just before actually returning. Stack based buffer - overflows (that need to overwrite this return address) now also - overwrite the canary, which gets detected and the attack is then - neutralized via a kernel panic. - This feature requires gcc version 4.2 or above. - -config DEPRECATED_PARAM_STRUCT - bool "Provide old way to pass kernel parameters" - help - This was deprecated in 2001 and announced to live on for 5 years. - Some old boot loaders still use this way. - endmenu menu "Boot options" @@ -1517,105 +1485,6 @@ config ATAGS_PROC Should the atags used to boot the kernel be exported in an "atags" file in procfs. Useful with kexec. -config AUTO_ZRELADDR - bool "Auto calculation of the decompressed kernel image address" - depends on !ZBOOT_ROM && !ARCH_U300 - help - ZRELADDR is the physical address where the decompressed kernel - image will be placed. If AUTO_ZRELADDR is selected, the address - will be determined at run-time by masking the current IP with - 0xf8000000. This assumes the zImage being placed in the first 128MB - from start of memory. - -config ZRELADDR - hex "Physical address of the decompressed kernel image" - depends on !AUTO_ZRELADDR - default 0x00008000 if ARCH_BCMRING ||\ - ARCH_CNS3XXX ||\ - ARCH_DOVE ||\ - ARCH_EBSA110 ||\ - ARCH_FOOTBRIDGE ||\ - ARCH_INTEGRATOR ||\ - ARCH_IOP13XX ||\ - ARCH_IOP33X ||\ - ARCH_IXP2000 ||\ - ARCH_IXP23XX ||\ - ARCH_IXP4XX ||\ - ARCH_KIRKWOOD ||\ - ARCH_KS8695 ||\ - ARCH_LOKI ||\ - ARCH_MMP ||\ - ARCH_MV78XX0 ||\ - ARCH_NOMADIK ||\ - ARCH_NUC93X ||\ - ARCH_NS9XXX ||\ - ARCH_ORION5X ||\ - ARCH_SPEAR3XX ||\ - ARCH_SPEAR6XX ||\ - ARCH_U8500 ||\ - ARCH_VERSATILE ||\ - ARCH_W90X900 - default 0x08008000 if ARCH_MX1 ||\ - ARCH_SHARK - default 0x10008000 if ARCH_MSM ||\ - ARCH_OMAP1 ||\ - ARCH_RPC - default 0x20008000 if ARCH_S5P6440 ||\ - ARCH_S5P6442 ||\ - ARCH_S5PC100 ||\ - ARCH_S5PV210 - default 0x30008000 if ARCH_S3C2410 ||\ - ARCH_S3C2400 ||\ - ARCH_S3C2412 ||\ - ARCH_S3C2416 ||\ - ARCH_S3C2440 ||\ - ARCH_S3C2443 - default 0x40008000 if ARCH_STMP378X ||\ - ARCH_STMP37XX ||\ - ARCH_SH7372 ||\ - ARCH_SH7377 - default 0x50008000 if ARCH_S3C64XX ||\ - ARCH_SH7367 - default 0x60008000 if ARCH_VEXPRESS - default 0x80008000 if ARCH_MX25 ||\ - ARCH_MX3 ||\ - ARCH_NETX ||\ - ARCH_OMAP2PLUS ||\ - ARCH_PNX4008 - default 0x90008000 if ARCH_MX5 ||\ - ARCH_MX91231 - default 0xa0008000 if ARCH_IOP32X ||\ - ARCH_PXA ||\ - MACH_MX27 - default 0xc0008000 if ARCH_LH7A40X ||\ - MACH_MX21 - default 0xf0008000 if ARCH_AAEC2000 ||\ - ARCH_L7200 - default 0xc0028000 if ARCH_CLPS711X - default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45) - default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45) - default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX - default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX - default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET - default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET - default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET - default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET - default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET - default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP - default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP - default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET - default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET - default 0xc0208000 if ARCH_SA1100 && SA1111 - default 0xc0008000 if ARCH_SA1100 && !SA1111 - default 0x30108000 if ARCH_S3C2410 && PM_H1940 - default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM - default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM - help - ZRELADDR is the physical address where the decompressed kernel - image will be placed. ZRELADDR has to be specified when the - assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is - selected. - endmenu menu "CPU Power Management" diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index 63d998e8c672..64ba313724d2 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -34,10 +34,6 @@ ifeq ($(CONFIG_FRAME_POINTER),y) KBUILD_CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog endif -ifeq ($(CONFIG_CC_STACKPROTECTOR),y) -KBUILD_CFLAGS +=-fstack-protector -endif - ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) KBUILD_CPPFLAGS += -mbig-endian AS += -EB @@ -143,14 +139,14 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood machine-$(CONFIG_ARCH_KS8695) := ks8695 +machine-$(CONFIG_ARCH_L7200) := l7200 machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x machine-$(CONFIG_ARCH_LOKI) := loki -machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx machine-$(CONFIG_ARCH_MMP) := mmp machine-$(CONFIG_ARCH_MSM) := msm machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 -machine-$(CONFIG_ARCH_MX1) := imx -machine-$(CONFIG_ARCH_MX2) := imx +machine-$(CONFIG_ARCH_MX1) := mx1 +machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX5) := mx5 diff --git a/trunk/arch/arm/boot/Makefile b/trunk/arch/arm/boot/Makefile index f705213caa88..4a590f4113e2 100644 --- a/trunk/arch/arm/boot/Makefile +++ b/trunk/arch/arm/boot/Makefile @@ -14,16 +14,18 @@ MKIMAGE := $(srctree)/scripts/mkuboot.sh ifneq ($(MACHINE),) --include $(srctree)/$(MACHINE)/Makefile.boot +include $(srctree)/$(MACHINE)/Makefile.boot endif # Note: the following conditions must always be true: +# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET) # PARAMS_PHYS must be within 4MB of ZRELADDR # INITRD_PHYS must be in RAM +ZRELADDR := $(zreladdr-y) PARAMS_PHYS := $(params_phys-y) INITRD_PHYS := $(initrd_phys-y) -export INITRD_PHYS PARAMS_PHYS +export ZRELADDR INITRD_PHYS PARAMS_PHYS targets := Image zImage xipImage bootpImage uImage @@ -65,7 +67,7 @@ quiet_cmd_uimage = UIMAGE $@ ifeq ($(CONFIG_ZBOOT_ROM),y) $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT) else -$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR) +$(obj)/uImage: LOADADDR=$(ZRELADDR) endif ifeq ($(CONFIG_THUMB2_KERNEL),y) diff --git a/trunk/arch/arm/boot/compressed/Makefile b/trunk/arch/arm/boot/compressed/Makefile index 7636c9b3f9a7..864a002137fe 100644 --- a/trunk/arch/arm/boot/compressed/Makefile +++ b/trunk/arch/arm/boot/compressed/Makefile @@ -4,7 +4,6 @@ # create a compressed vmlinuz image from the original vmlinux # -AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) HEAD = head.o OBJS = misc.o decompress.o FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c @@ -20,6 +19,10 @@ ifeq ($(CONFIG_ARCH_SHARK),y) OBJS += head-shark.o ofw-shark.o endif +ifeq ($(CONFIG_ARCH_L7200),y) +OBJS += head-l7200.o +endif + ifeq ($(CONFIG_ARCH_P720T),y) # Borrow this code from SA1100 OBJS += head-sa1100.o @@ -79,9 +82,19 @@ endif EXTRA_CFLAGS := -fpic -fno-builtin EXTRA_AFLAGS := -Wa,-march=all +# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via +# linker symbols. We only define initrd_phys and params_phys if the +# machine class defined the corresponding makefile variable. +LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR) ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) LDFLAGS_vmlinux += --be8 endif +ifneq ($(INITRD_PHYS),) +LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS) +endif +ifneq ($(PARAMS_PHYS),) +LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS) +endif # ? LDFLAGS_vmlinux += -p # Report unresolved symbol references diff --git a/trunk/arch/arm/boot/compressed/Makefile.debug b/trunk/arch/arm/boot/compressed/Makefile.debug new file mode 100644 index 000000000000..491a037b2973 --- /dev/null +++ b/trunk/arch/arm/boot/compressed/Makefile.debug @@ -0,0 +1,23 @@ +# +# linux/arch/arm/boot/compressed/Makefile +# +# create a compressed vmlinux image from the original vmlinux +# + +COMPRESSED_EXTRA=../../lib/ll_char_wr.o +OBJECTS=misc-debug.o ll_char_wr.aout.o + +CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c + +test-gzip: piggy.aout.o $(OBJECTS) + $(CC) -o $@ $(OBJECTS) piggy.aout.o + +misc-debug.o: misc.c + $(CC) $(CFLAGS) -o $@ misc.c + +piggy.aout.o: piggy.o + arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o + +ll_char_wr.aout.o: $(COMPRESSED_EXTRA) + arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o + diff --git a/trunk/arch/arm/boot/compressed/head-l7200.S b/trunk/arch/arm/boot/compressed/head-l7200.S new file mode 100644 index 000000000000..d0e3b20856cd --- /dev/null +++ b/trunk/arch/arm/boot/compressed/head-l7200.S @@ -0,0 +1,29 @@ +/* + * linux/arch/arm/boot/compressed/head-l7200.S + * + * Copyright (C) 2000 Steve Hill + * + * Some code borrowed from Nicolas Pitre's 'head-sa1100.S' file. This + * is merged with head.S by the linker. + */ + +#include + +#ifndef CONFIG_ARCH_L7200 +#error What am I doing here... +#endif + + .section ".start", "ax" + +__L7200_start: + mov r0, #0x00100000 @ FLASH address of initrd + mov r2, #0xf1000000 @ RAM address of initrd + add r3, r2, #0x00700000 @ Size of initrd +1: + ldmia r0!, {r4, r5, r6, r7} + stmia r2!, {r4, r5, r6, r7} + cmp r2, r3 + ble 1b + + mov r8, #0 @ Zero it out + mov r7, #MACH_TYPE_L7200 @ Set architecture ID diff --git a/trunk/arch/arm/boot/compressed/head.S b/trunk/arch/arm/boot/compressed/head.S index abf4d65acf62..c5191b1532e8 100644 --- a/trunk/arch/arm/boot/compressed/head.S +++ b/trunk/arch/arm/boot/compressed/head.S @@ -170,16 +170,9 @@ not_angel: .text adr r0, LC0 - ARM( ldmia r0, {r1, r2, r3, r5, r6, r11, ip, sp}) - THUMB( ldmia r0, {r1, r2, r3, r5, r6, r11, ip} ) + ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp}) + THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} ) THUMB( ldr sp, [r0, #32] ) -#ifdef CONFIG_AUTO_ZRELADDR - @ determine final kernel image address - and r4, pc, #0xf8000000 - add r4, r4, #TEXT_OFFSET -#else - ldr r4, =CONFIG_ZRELADDR -#endif subs r0, r0, r1 @ calculate the delta offset @ if delta is zero, we are @@ -317,17 +310,18 @@ wont_overwrite: mov r0, r4 LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 + .word zreladdr @ r4 .word _start @ r5 .word _image_size @ r6 .word _got_start @ r11 .word _got_end @ ip - .word user_stack_end @ sp + .word user_stack+4096 @ sp LC1: .word reloc_end - reloc_start .size LC0, . - LC0 #ifdef CONFIG_ARCH_RPC .globl params -params: ldr r0, =0x10000100 @ params_phys for RPC +params: ldr r0, =params_phys mov pc, lr .ltorg .align @@ -345,8 +339,9 @@ params: ldr r0, =0x10000100 @ params_phys for RPC * r4 = kernel execution address * r7 = architecture number * r8 = atags pointer + * r9 = run-time address of "start" (???) * On exit, - * r0, r1, r2, r3, r9, r10, r12 corrupted + * r1, r2, r3, r9, r10, r12 corrupted * This routine must preserve: * r4, r5, r6, r7, r8 */ @@ -401,18 +396,12 @@ __armv3_mpu_cache_on: mov r0, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 - /* - * ?? ARMv3 MMU does not allow reading the control register, - * does this really work on ARMv3 MPU? - */ mrc p15, 0, r0, c1, c0, 0 @ read control reg @ .... .... .... WC.M orr r0, r0, #0x000d @ .... .... .... 11.1 - /* ?? this overwrites the value constructed above? */ mov r0, #0 mcr p15, 0, r0, c1, c0, 0 @ write control reg - /* ?? invalidate for the second time? */ mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr @@ -782,10 +771,8 @@ proc_types: * Turn off the Cache and MMU. ARMv3 does not support * reading the control register, but ARMv4 does. * - * On exit, - * r0, r1, r2, r3, r9, r12 corrupted - * This routine must preserve: - * r4, r6, r7 + * On exit, r0, r1, r2, r3, r9, r12 corrupted + * This routine must preserve: r4, r6, r7 */ .align 5 cache_off: mov r3, #12 @ cache_off function @@ -858,7 +845,7 @@ __armv3_mmu_cache_off: * Clean and flush the cache to maintain consistency. * * On exit, - * r1, r2, r3, r9, r10, r11, r12 corrupted + * r1, r2, r3, r9, r11, r12 corrupted * This routine must preserve: * r0, r4, r5, r6, r7 */ @@ -1001,7 +988,7 @@ no_cache_id: __armv3_mmu_cache_flush: __armv3_mpu_cache_flush: mov r1, #0 - mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 + mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr /* @@ -1014,7 +1001,6 @@ __armv3_mpu_cache_flush: phexbuf: .space 12 .size phexbuf, . - phexbuf -@ phex corrupts {r0, r1, r2, r3} phex: adr r3, phexbuf mov r2, #0 strb r2, [r3, r1] @@ -1029,7 +1015,6 @@ phex: adr r3, phexbuf strb r2, [r3, r1] b 1b -@ puts corrupts {r0, r1, r2, r3} puts: loadsp r3, r1 1: ldrb r2, [r0], #1 teq r2, #0 @@ -1044,14 +1029,12 @@ puts: loadsp r3, r1 teq r0, #0 bne 1b mov pc, lr -@ putc corrupts {r0, r1, r2, r3} putc: mov r2, r0 mov r0, #0 loadsp r3, r1 b 2b -@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr} memdump: mov r12, r0 mov r10, lr mov r11, #0 @@ -1087,4 +1070,3 @@ reloc_end: .align .section ".stack", "w" user_stack: .space 4096 -user_stack_end: diff --git a/trunk/arch/arm/boot/compressed/misc.c b/trunk/arch/arm/boot/compressed/misc.c index e653a6d3c8d9..d2b2ef41cd4f 100644 --- a/trunk/arch/arm/boot/compressed/misc.c +++ b/trunk/arch/arm/boot/compressed/misc.c @@ -28,6 +28,9 @@ unsigned int __machine_arch_type; #include +#ifdef STANDALONE_DEBUG +#define putstr printf +#else static void putstr(const char *ptr); extern void error(char *x); @@ -113,6 +116,7 @@ static void putstr(const char *ptr) flush(); } +#endif void *memcpy(void *__dest, __const void *__src, size_t __n) { @@ -182,6 +186,7 @@ asmlinkage void __div0(void) extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); +#ifndef STANDALONE_DEBUG unsigned long decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, @@ -206,3 +211,18 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, putstr(" done, booting the kernel.\n"); return output_ptr; } +#else + +char output_buffer[1500*1024]; + +int main() +{ + output_data = output_buffer; + + putstr("Uncompressing Linux..."); + decompress(input_data, input_data_end - input_data, + NULL, NULL, output_data, NULL, error); + putstr("done.\n"); + return 0; +} +#endif diff --git a/trunk/arch/arm/common/gic.c b/trunk/arch/arm/common/gic.c index 7dfa9a85bc0c..337741f734ac 100644 --- a/trunk/arch/arm/common/gic.c +++ b/trunk/arch/arm/common/gic.c @@ -108,51 +108,6 @@ static void gic_unmask_irq(unsigned int irq) spin_unlock(&irq_controller_lock); } -static int gic_set_type(unsigned int irq, unsigned int type) -{ - void __iomem *base = gic_dist_base(irq); - unsigned int gicirq = gic_irq(irq); - u32 enablemask = 1 << (gicirq % 32); - u32 enableoff = (gicirq / 32) * 4; - u32 confmask = 0x2 << ((gicirq % 16) * 2); - u32 confoff = (gicirq / 16) * 4; - bool enabled = false; - u32 val; - - /* Interrupt configuration for SGIs can't be changed */ - if (gicirq < 16) - return -EINVAL; - - if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) - return -EINVAL; - - spin_lock(&irq_controller_lock); - - val = readl(base + GIC_DIST_CONFIG + confoff); - if (type == IRQ_TYPE_LEVEL_HIGH) - val &= ~confmask; - else if (type == IRQ_TYPE_EDGE_RISING) - val |= confmask; - - /* - * As recommended by the spec, disable the interrupt before changing - * the configuration - */ - if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { - writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); - enabled = true; - } - - writel(val, base + GIC_DIST_CONFIG + confoff); - - if (enabled) - writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); - - spin_unlock(&irq_controller_lock); - - return 0; -} - #ifdef CONFIG_SMP static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) { @@ -206,7 +161,6 @@ static struct irq_chip gic_chip = { .ack = gic_ack_irq, .mask = gic_mask_irq, .unmask = gic_unmask_irq, - .set_type = gic_set_type, #ifdef CONFIG_SMP .set_affinity = gic_set_cpu, #endif diff --git a/trunk/arch/arm/common/sa1111.c b/trunk/arch/arm/common/sa1111.c index 517d50ddbeb3..9eaf65f43642 100644 --- a/trunk/arch/arm/common/sa1111.c +++ b/trunk/arch/arm/common/sa1111.c @@ -185,10 +185,13 @@ static struct sa1111_dev_info sa1111_devices[] = { }, }; -void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes) +void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes) { unsigned int sz = SZ_1M >> PAGE_SHIFT; + if (node != 0) + sz = 0; + size[1] = size[0] - sz; size[0] = sz; } diff --git a/trunk/arch/arm/configs/kirkwood_defconfig b/trunk/arch/arm/configs/kirkwood_defconfig index ccc9c9959b82..f2e3a9088df6 100644 --- a/trunk/arch/arm/configs/kirkwood_defconfig +++ b/trunk/arch/arm/configs/kirkwood_defconfig @@ -13,19 +13,11 @@ CONFIG_MACH_RD88F6192_NAS=y CONFIG_MACH_RD88F6281=y CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y -CONFIG_MACH_ESATA_SHEEVAPLUG=y -CONFIG_MACH_GURUPLUG=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y CONFIG_MACH_OPENRD_BASE=y CONFIG_MACH_OPENRD_CLIENT=y -CONFIG_MACH_OPENRD_ULTIMATE=y CONFIG_MACH_NETSPACE_V2=y -CONFIG_MACH_INETSPACE_V2=y -CONFIG_MACH_NETSPACE_MAX_V2=y -CONFIG_MACH_NET2BIG_V2=y -CONFIG_MACH_NET5BIG_V2=y -CONFIG_MACH_T5325=y # CONFIG_CPU_FEROCEON_OLD_ID is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/trunk/arch/arm/configs/lusl7200_defconfig b/trunk/arch/arm/configs/lusl7200_defconfig new file mode 100644 index 000000000000..816fc42884c9 --- /dev/null +++ b/trunk/arch/arm/configs/lusl7200_defconfig @@ -0,0 +1,23 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +# CONFIG_HOTPLUG is not set +CONFIG_MODULES=y +CONFIG_ARCH_L7200=y +# CONFIG_ARM_THUMB is not set +CONFIG_ZBOOT_ROM_TEXT=0x00010000 +CONFIG_ZBOOT_ROM_BSS=0xf03e0000 +CONFIG_ZBOOT_ROM=y +CONFIG_CMDLINE="console=tty0 console=ttyLU1,115200 root=/dev/ram initrd=0xf1000000,0x005dac7b mem=32M" +CONFIG_BINFMT_AOUT=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_INPUT is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_EXT2_FS=y +CONFIG_DEBUG_USER=y +# CONFIG_CRC32 is not set diff --git a/trunk/arch/arm/include/asm/elf.h b/trunk/arch/arm/include/asm/elf.h index 6750b8e45a49..51662feb9f1d 100644 --- a/trunk/arch/arm/include/asm/elf.h +++ b/trunk/arch/arm/include/asm/elf.h @@ -121,8 +121,4 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); extern void elf_set_personality(const struct elf32_hdr *); #define SET_PERSONALITY(ex) elf_set_personality(&(ex)) -struct mm_struct; -extern unsigned long arch_randomize_brk(struct mm_struct *mm); -#define arch_randomize_brk arch_randomize_brk - #endif diff --git a/trunk/arch/arm/include/asm/hwcap.h b/trunk/arch/arm/include/asm/hwcap.h index c1062c317103..f7bd52b1c365 100644 --- a/trunk/arch/arm/include/asm/hwcap.h +++ b/trunk/arch/arm/include/asm/hwcap.h @@ -19,7 +19,6 @@ #define HWCAP_NEON 4096 #define HWCAP_VFPv3 8192 #define HWCAP_VFPv3D16 16384 -#define HWCAP_TLS 32768 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) /* diff --git a/trunk/arch/arm/include/asm/irq.h b/trunk/arch/arm/include/asm/irq.h index 2721a5814cb9..237282f7c762 100644 --- a/trunk/arch/arm/include/asm/irq.h +++ b/trunk/arch/arm/include/asm/irq.h @@ -7,8 +7,6 @@ #define irq_canonicalize(i) (i) #endif -#define NR_IRQS_LEGACY 16 - /* * Use this value to indicate lack of interrupt * capability diff --git a/trunk/arch/arm/include/asm/kexec.h b/trunk/arch/arm/include/asm/kexec.h index 8ec9ef5c3c7b..df15a0dc228e 100644 --- a/trunk/arch/arm/include/asm/kexec.h +++ b/trunk/arch/arm/include/asm/kexec.h @@ -19,26 +19,10 @@ #ifndef __ASSEMBLY__ -/** - * crash_setup_regs() - save registers for the panic kernel - * @newregs: registers are saved here - * @oldregs: registers to be saved (may be %NULL) - * - * Function copies machine registers from @oldregs to @newregs. If @oldregs is - * %NULL then current registers are stored there. - */ +struct kimage; +/* Provide a dummy definition to avoid build failures. */ static inline void crash_setup_regs(struct pt_regs *newregs, - struct pt_regs *oldregs) -{ - if (oldregs) { - memcpy(newregs, oldregs, sizeof(*newregs)); - } else { - __asm__ __volatile__ ("stmia %0, {r0 - r15}" - : : "r" (&newregs->ARM_r0)); - __asm__ __volatile__ ("mrs %0, cpsr" - : "=r" (newregs->ARM_cpsr)); - } -} + struct pt_regs *oldregs) { } #endif /* __ASSEMBLY__ */ diff --git a/trunk/arch/arm/include/asm/mach/arch.h b/trunk/arch/arm/include/asm/mach/arch.h index 8a0dd18ba642..c59842dc7cb8 100644 --- a/trunk/arch/arm/include/asm/mach/arch.h +++ b/trunk/arch/arm/include/asm/mach/arch.h @@ -20,7 +20,6 @@ struct machine_desc { * by assembler code in head.S, head-common.S */ unsigned int nr; /* architecture number */ - unsigned int nr_irqs; /* number of IRQs */ unsigned int phys_io; /* start of physical io */ unsigned int io_pg_offst; /* byte offset for io * page tabe entry */ @@ -38,7 +37,6 @@ struct machine_desc { void (*fixup)(struct machine_desc *, struct tag *, char **, struct meminfo *); - void (*reserve)(void);/* reserve mem blocks */ void (*map_io)(void);/* IO mapping function */ void (*init_irq)(void); struct sys_timer *timer; /* system tick timer */ diff --git a/trunk/arch/arm/include/asm/mach/irq.h b/trunk/arch/arm/include/asm/mach/irq.h index ce3eee9fe26c..8920b2d6e3b8 100644 --- a/trunk/arch/arm/include/asm/mach/irq.h +++ b/trunk/arch/arm/include/asm/mach/irq.h @@ -17,7 +17,6 @@ struct seq_file; /* * This is internal. Do not use it. */ -extern unsigned int arch_nr_irqs; extern void (*init_arch_irq)(void); extern void init_FIQ(void); extern int show_fiq_list(struct seq_file *, void *); diff --git a/trunk/arch/arm/include/asm/mach/map.h b/trunk/arch/arm/include/asm/mach/map.h index d2fedb5aeb1f..742c2aaeb020 100644 --- a/trunk/arch/arm/include/asm/mach/map.h +++ b/trunk/arch/arm/include/asm/mach/map.h @@ -27,8 +27,6 @@ struct map_desc { #define MT_MEMORY 9 #define MT_ROM 10 #define MT_MEMORY_NONCACHED 11 -#define MT_MEMORY_DTCM 12 -#define MT_MEMORY_ITCM 13 #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); diff --git a/trunk/arch/arm/include/asm/mach/pci.h b/trunk/arch/arm/include/asm/mach/pci.h index 16330bd0657c..52f0da1e97df 100644 --- a/trunk/arch/arm/include/asm/mach/pci.h +++ b/trunk/arch/arm/include/asm/mach/pci.h @@ -46,7 +46,6 @@ struct pci_sys_data { /* IRQ mapping */ int (*map_irq)(struct pci_dev *, u8, u8); struct hw_pci *hw; - void *private_data; /* platform controller private data */ }; /* diff --git a/trunk/arch/arm/include/asm/memblock.h b/trunk/arch/arm/include/asm/memblock.h deleted file mode 100644 index fdbc43b2e6c0..000000000000 --- a/trunk/arch/arm/include/asm/memblock.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _ASM_ARM_MEMBLOCK_H -#define _ASM_ARM_MEMBLOCK_H - -#ifdef CONFIG_MMU -extern phys_addr_t lowmem_end_addr; -#define MEMBLOCK_REAL_LIMIT lowmem_end_addr -#else -#define MEMBLOCK_REAL_LIMIT 0 -#endif - -struct meminfo; -struct machine_desc; - -extern void arm_memblock_init(struct meminfo *, struct machine_desc *); - -#endif diff --git a/trunk/arch/arm/include/asm/memory.h b/trunk/arch/arm/include/asm/memory.h index 23c2e8e5c0fa..4312ee5e3d0b 100644 --- a/trunk/arch/arm/include/asm/memory.h +++ b/trunk/arch/arm/include/asm/memory.h @@ -123,15 +123,6 @@ #endif /* !CONFIG_MMU */ -/* - * We fix the TCM memories max 32 KiB ITCM resp DTCM at these - * locations - */ -#ifdef CONFIG_HAVE_TCM -#define ITCM_OFFSET UL(0xfffe0000) -#define DTCM_OFFSET UL(0xfffe8000) -#endif - /* * Physical vs virtual RAM address space conversion. These are * private definitions which should NOT be used outside memory.h @@ -167,7 +158,7 @@ #endif #ifndef arch_adjust_zones -#define arch_adjust_zones(size,holes) do { } while (0) +#define arch_adjust_zones(node,size,holes) do { } while (0) #elif !defined(CONFIG_ZONE_DMA) #error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA" #endif @@ -243,11 +234,76 @@ static inline __deprecated void *bus_to_virt(unsigned long x) * virt_to_page(k) convert a _valid_ virtual address to struct page * * virt_addr_valid(k) indicates whether a virtual address is valid */ +#ifndef CONFIG_DISCONTIGMEM + #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) +#define PHYS_TO_NID(addr) (0) + +#else /* CONFIG_DISCONTIGMEM */ + +/* + * This is more complex. We have a set of mem_map arrays spread + * around in memory. + */ +#include + +#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn) +#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT) + +#define virt_to_page(kaddr) \ + (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) + +#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < MAX_NUMNODES) + +/* + * Common discontigmem stuff. + * PHYS_TO_NID is used by the ARM kernel/setup.c + */ +#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) + +/* + * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory + * and returns the mem_map of that node. + */ +#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) + +/* + * Given a page frame number, find the owning node of the memory + * and returns the mem_map of that node. + */ +#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) + +#ifdef NODE_MEM_SIZE_BITS +#define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1) + +/* + * Given a kernel address, find the home node of the underlying memory. + */ +#define KVADDR_TO_NID(addr) \ + (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS) + +/* + * Given a page frame number, convert it to a node id. + */ +#define PFN_TO_NID(pfn) \ + (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT)) + +/* + * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory + * and returns the index corresponding to the appropriate page in the + * node's mem_map. + */ +#define LOCAL_MAP_NR(addr) \ + (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT) + +#endif /* NODE_MEM_SIZE_BITS */ + +#endif /* !CONFIG_DISCONTIGMEM */ + /* * Optional coherency support. Currently used only by selected * Intel XSC3-based systems. diff --git a/trunk/arch/arm/include/asm/mmzone.h b/trunk/arch/arm/include/asm/mmzone.h new file mode 100644 index 000000000000..ae63a4fd28c8 --- /dev/null +++ b/trunk/arch/arm/include/asm/mmzone.h @@ -0,0 +1,30 @@ +/* + * arch/arm/include/asm/mmzone.h + * + * 1999-12-29 Nicolas Pitre Created + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_MMZONE_H +#define __ASM_MMZONE_H + +/* + * Currently defined in arch/arm/mm/discontig.c + */ +extern pg_data_t discontig_node_data[]; + +/* + * Return a pointer to the node data for node n. + */ +#define NODE_DATA(nid) (&discontig_node_data[nid]) + +/* + * NODE_MEM_MAP gives the kaddr for the mem_map of the node. + */ +#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map) + +#include + +#endif diff --git a/trunk/arch/arm/include/asm/ptrace.h b/trunk/arch/arm/include/asm/ptrace.h index c974be8913a7..9dcb11e59026 100644 --- a/trunk/arch/arm/include/asm/ptrace.h +++ b/trunk/arch/arm/include/asm/ptrace.h @@ -184,42 +184,6 @@ extern unsigned long profile_pc(struct pt_regs *regs); #define predicate(x) ((x) & 0xf0000000) #define PREDICATE_ALWAYS 0xe0000000 -/* - * kprobe-based event tracer support - */ -#include -#include -#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0)) - -extern int regs_query_register_offset(const char *name); -extern const char *regs_query_register_name(unsigned int offset); -extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr); -extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, - unsigned int n); - -/** - * regs_get_register() - get register value from its offset - * @regs: pt_regs from which register value is gotten - * @offset: offset number of the register. - * - * regs_get_register returns the value of a register whose offset from @regs. - * The @offset is the offset of the register in struct pt_regs. - * If @offset is bigger than MAX_REG_OFFSET, this returns 0. - */ -static inline unsigned long regs_get_register(struct pt_regs *regs, - unsigned int offset) -{ - if (unlikely(offset > MAX_REG_OFFSET)) - return 0; - return *(unsigned long *)((unsigned long)regs + offset); -} - -/* Valid only for Kernel mode traps. */ -static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) -{ - return regs->ARM_sp; -} - #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/trunk/arch/arm/include/asm/setup.h b/trunk/arch/arm/include/asm/setup.h index f1e5a9bca249..f392fb4437af 100644 --- a/trunk/arch/arm/include/asm/setup.h +++ b/trunk/arch/arm/include/asm/setup.h @@ -201,7 +201,8 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn } struct membank { unsigned long start; unsigned long size; - unsigned int highmem; + unsigned short node; + unsigned short highmem; }; struct meminfo { @@ -211,8 +212,9 @@ struct meminfo { extern struct meminfo meminfo; -#define for_each_bank(iter,mi) \ - for (iter = 0; iter < (mi)->nr_banks; iter++) +#define for_each_nodebank(iter,mi,no) \ + for (iter = 0; iter < (mi)->nr_banks; iter++) \ + if ((mi)->bank[iter].node == no) #define bank_pfn_start(bank) __phys_to_pfn((bank)->start) #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) diff --git a/trunk/arch/arm/include/asm/stackprotector.h b/trunk/arch/arm/include/asm/stackprotector.h deleted file mode 100644 index de003327be97..000000000000 --- a/trunk/arch/arm/include/asm/stackprotector.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * GCC stack protector support. - * - * Stack protector works by putting predefined pattern at the start of - * the stack frame and verifying that it hasn't been overwritten when - * returning from the function. The pattern is called stack canary - * and gcc expects it to be defined by a global variable called - * "__stack_chk_guard" on ARM. This unfortunately means that on SMP - * we cannot have a different canary value per task. - */ - -#ifndef _ASM_STACKPROTECTOR_H -#define _ASM_STACKPROTECTOR_H 1 - -#include -#include - -extern unsigned long __stack_chk_guard; - -/* - * Initialize the stackprotector canary value. - * - * NOTE: this must only be called from functions that never return, - * and it must always be inlined. - */ -static __always_inline void boot_init_stack_canary(void) -{ - unsigned long canary; - - /* Try to get a semi random initial value. */ - get_random_bytes(&canary, sizeof(canary)); - canary ^= LINUX_VERSION_CODE; - - current->stack_canary = canary; - __stack_chk_guard = current->stack_canary; -} - -#endif /* _ASM_STACKPROTECTOR_H */ diff --git a/trunk/arch/arm/include/asm/system.h b/trunk/arch/arm/include/asm/system.h index 8ba1ccf82a02..5f4f48002734 100644 --- a/trunk/arch/arm/include/asm/system.h +++ b/trunk/arch/arm/include/asm/system.h @@ -83,7 +83,7 @@ void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), - int sig, int code, const char *name); + int sig, const char *name); #define xchg(ptr,x) \ ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) diff --git a/trunk/arch/arm/include/asm/tls.h b/trunk/arch/arm/include/asm/tls.h deleted file mode 100644 index e71d6ff8d104..000000000000 --- a/trunk/arch/arm/include/asm/tls.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __ASMARM_TLS_H -#define __ASMARM_TLS_H - -#ifdef __ASSEMBLY__ - .macro set_tls_none, tp, tmp1, tmp2 - .endm - - .macro set_tls_v6k, tp, tmp1, tmp2 - mcr p15, 0, \tp, c13, c0, 3 @ set TLS register - .endm - - .macro set_tls_v6, tp, tmp1, tmp2 - ldr \tmp1, =elf_hwcap - ldr \tmp1, [\tmp1, #0] - mov \tmp2, #0xffff0fff - tst \tmp1, #HWCAP_TLS @ hardware TLS available? - mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register - streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 - .endm - - .macro set_tls_software, tp, tmp1, tmp2 - mov \tmp1, #0xffff0fff - str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0 - .endm -#endif - -#ifdef CONFIG_TLS_REG_EMUL -#define tls_emu 1 -#define has_tls_reg 1 -#define set_tls set_tls_none -#elif __LINUX_ARM_ARCH__ >= 7 || \ - (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K)) -#define tls_emu 0 -#define has_tls_reg 1 -#define set_tls set_tls_v6k -#elif __LINUX_ARM_ARCH__ == 6 -#define tls_emu 0 -#define has_tls_reg (elf_hwcap & HWCAP_TLS) -#define set_tls set_tls_v6 -#else -#define tls_emu 0 -#define has_tls_reg 0 -#define set_tls set_tls_software -#endif - -#endif /* __ASMARM_TLS_H */ diff --git a/trunk/arch/arm/include/asm/vfpmacros.h b/trunk/arch/arm/include/asm/vfpmacros.h index 3d5fc41ae8d3..422f3cc204a2 100644 --- a/trunk/arch/arm/include/asm/vfpmacros.h +++ b/trunk/arch/arm/include/asm/vfpmacros.h @@ -3,8 +3,6 @@ * * Assembler-only file containing VFP macros and register definitions. */ -#include - #include "vfp.h" @ Macros to allow building with old toolkits (with no VFP support) @@ -24,19 +22,11 @@ LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} #endif #ifdef CONFIG_VFPv3 -#if __LINUX_ARM_ARCH__ <= 6 - ldr \tmp, =elf_hwcap @ may not have MVFR regs - ldr \tmp, [\tmp, #0] - tst \tmp, #HWCAP_VFPv3D16 - ldceq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} - addne \base, \base, #32*4 @ step over unused register space -#else VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field cmp \tmp, #2 @ 32 x 64bit registers? ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} addne \base, \base, #32*4 @ step over unused register space -#endif #endif .endm @@ -48,18 +38,10 @@ STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15} #endif #ifdef CONFIG_VFPv3 -#if __LINUX_ARM_ARCH__ <= 6 - ldr \tmp, =elf_hwcap @ may not have MVFR regs - ldr \tmp, [\tmp, #0] - tst \tmp, #HWCAP_VFPv3D16 - stceq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} - addne \base, \base, #32*4 @ step over unused register space -#else VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field cmp \tmp, #2 @ 32 x 64bit registers? stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} addne \base, \base, #32*4 @ step over unused register space -#endif #endif .endm diff --git a/trunk/arch/arm/kernel/Makefile b/trunk/arch/arm/kernel/Makefile index 980b78e31328..26d302c28e13 100644 --- a/trunk/arch/arm/kernel/Makefile +++ b/trunk/arch/arm/kernel/Makefile @@ -13,12 +13,10 @@ CFLAGS_REMOVE_return_address.o = -pg # Object file lists. -obj-y := elf.o entry-armv.o entry-common.o irq.o \ +obj-y := compat.o elf.o entry-armv.o entry-common.o irq.o \ process.o ptrace.o return_address.o setup.o signal.o \ sys_arm.o stacktrace.o time.o traps.o -obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o - obj-$(CONFIG_LEDS) += leds.o obj-$(CONFIG_OC_ETM) += etm.o @@ -41,7 +39,6 @@ obj-$(CONFIG_ARM_THUMBEE) += thumbee.o obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_ARM_UNWIND) += unwind.o obj-$(CONFIG_HAVE_TCM) += tcm.o -obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 diff --git a/trunk/arch/arm/kernel/asm-offsets.c b/trunk/arch/arm/kernel/asm-offsets.c index 85f2a019f77b..883511522fca 100644 --- a/trunk/arch/arm/kernel/asm-offsets.c +++ b/trunk/arch/arm/kernel/asm-offsets.c @@ -40,9 +40,6 @@ int main(void) { DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); -#ifdef CONFIG_CC_STACKPROTECTOR - DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary)); -#endif BLANK(); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); diff --git a/trunk/arch/arm/kernel/compat.c b/trunk/arch/arm/kernel/compat.c index 925652318b8b..0a1385442f43 100644 --- a/trunk/arch/arm/kernel/compat.c +++ b/trunk/arch/arm/kernel/compat.c @@ -217,3 +217,10 @@ void __init convert_to_tag_list(struct tag *tags) struct param_struct *params = (struct param_struct *)tags; build_tag_list(params, ¶ms->u2); } + +void __init squash_mem_tags(struct tag *tag) +{ + for (; tag->hdr.size; tag = tag_next(tag)) + if (tag->hdr.tag == ATAG_MEM) + tag->hdr.tag = ATAG_NONE; +} diff --git a/trunk/arch/arm/kernel/compat.h b/trunk/arch/arm/kernel/compat.h index 39264ab1b9c6..27e61a68bd1c 100644 --- a/trunk/arch/arm/kernel/compat.h +++ b/trunk/arch/arm/kernel/compat.h @@ -9,3 +9,5 @@ */ extern void convert_to_tag_list(struct tag *tags); + +extern void squash_mem_tags(struct tag *tag); diff --git a/trunk/arch/arm/kernel/crash_dump.c b/trunk/arch/arm/kernel/crash_dump.c deleted file mode 100644 index cd3b853a8a6d..000000000000 --- a/trunk/arch/arm/kernel/crash_dump.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/arm/kernel/crash_dump.c - * - * Copyright (C) 2010 Nokia Corporation. - * Author: Mika Westerberg - * - * This code is taken from arch/x86/kernel/crash_dump_64.c - * Created by: Hariprasad Nellitheertha (hari@in.ibm.com) - * Copyright (C) IBM Corporation, 2004. All rights reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -/* stores the physical address of elf header of crash image */ -unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; - -/** - * copy_oldmem_page() - copy one page from old kernel memory - * @pfn: page frame number to be copied - * @buf: buffer where the copied page is placed - * @csize: number of bytes to copy - * @offset: offset in bytes into the page - * @userbuf: if set, @buf is int he user address space - * - * This function copies one page from old kernel memory into buffer pointed by - * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes - * copied or negative error in case of failure. - */ -ssize_t copy_oldmem_page(unsigned long pfn, char *buf, - size_t csize, unsigned long offset, - int userbuf) -{ - void *vaddr; - - if (!csize) - return 0; - - vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE); - if (!vaddr) - return -ENOMEM; - - if (userbuf) { - if (copy_to_user(buf, vaddr + offset, csize)) { - iounmap(vaddr); - return -EFAULT; - } - } else { - memcpy(buf, vaddr + offset, csize); - } - - iounmap(vaddr); - return csize; -} diff --git a/trunk/arch/arm/kernel/entry-armv.S b/trunk/arch/arm/kernel/entry-armv.S index bb8e93a76407..3fd7861de4d1 100644 --- a/trunk/arch/arm/kernel/entry-armv.S +++ b/trunk/arch/arm/kernel/entry-armv.S @@ -22,7 +22,6 @@ #include #include #include -#include #include "entry-header.S" @@ -736,11 +735,11 @@ ENTRY(__switch_to) #ifdef CONFIG_MMU ldr r6, [r2, #TI_CPU_DOMAIN] #endif - set_tls r3, r4, r5 -#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) - ldr r7, [r2, #TI_TASK] - ldr r8, =__stack_chk_guard - ldr r7, [r7, #TSK_STACK_CANARY] +#if defined(CONFIG_HAS_TLS_REG) + mcr p15, 0, r3, c13, c0, 3 @ set TLS register +#elif !defined(CONFIG_TLS_REG_EMUL) + mov r4, #0xffff0fff + str r3, [r4, #-15] @ TLS val at 0xffff0ff0 #endif #ifdef CONFIG_MMU mcr p15, 0, r6, c3, c0, 0 @ Set domain register @@ -750,9 +749,6 @@ ENTRY(__switch_to) ldr r0, =thread_notify_head mov r1, #THREAD_NOTIFY_SWITCH bl atomic_notifier_call_chain -#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) - str r7, [r8] -#endif THUMB( mov ip, r4 ) mov r0, r5 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously @@ -1009,12 +1005,17 @@ kuser_cmpxchg_fixup: */ __kuser_get_tls: @ 0xffff0fe0 - ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init + +#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) + ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 +#else + mrc p15, 0, r0, c13, c0, 3 @ read TLS register +#endif usr_ret lr - mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code - .rep 4 - .word 0 @ 0xffff0ff0 software TLS value, then - .endr @ pad up to __kuser_helper_version + + .rep 5 + .word 0 @ pad up to __kuser_helper_version + .endr /* * Reference declaration: diff --git a/trunk/arch/arm/kernel/irq.c b/trunk/arch/arm/kernel/irq.c index c0d5c3b3a760..3b3d2c80509c 100644 --- a/trunk/arch/arm/kernel/irq.c +++ b/trunk/arch/arm/kernel/irq.c @@ -47,14 +47,12 @@ #define irq_finish(irq) do { } while (0) #endif -unsigned int arch_nr_irqs; void (*init_arch_irq)(void) __initdata = NULL; unsigned long irq_err_count; int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, cpu; - struct irq_desc *desc; struct irqaction * action; unsigned long flags; @@ -69,25 +67,24 @@ int show_interrupts(struct seq_file *p, void *v) seq_putc(p, '\n'); } - if (i < nr_irqs) { - desc = irq_to_desc(i); - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; + if (i < NR_IRQS) { + raw_spin_lock_irqsave(&irq_desc[i].lock, flags); + action = irq_desc[i].action; if (!action) goto unlock; seq_printf(p, "%3d: ", i); for_each_present_cpu(cpu) seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %10s", desc->chip->name ? : "-"); + seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-"); seq_printf(p, " %s", action->name); for (action = action->next; action; action = action->next) seq_printf(p, ", %s", action->name); seq_putc(p, '\n'); unlock: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } else if (i == nr_irqs) { + raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + } else if (i == NR_IRQS) { #ifdef CONFIG_FIQ show_fiq_list(p, v); #endif @@ -115,7 +112,7 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs) * Some hardware gives randomly wrong interrupts. Rather * than crashing, do something sensible. */ - if (unlikely(irq >= nr_irqs)) { + if (unlikely(irq >= NR_IRQS)) { if (printk_ratelimit()) printk(KERN_WARNING "Bad IRQ%u\n", irq); ack_bad_irq(irq); @@ -135,12 +132,12 @@ void set_irq_flags(unsigned int irq, unsigned int iflags) struct irq_desc *desc; unsigned long flags; - if (irq >= nr_irqs) { + if (irq >= NR_IRQS) { printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); return; } - desc = irq_to_desc(irq); + desc = irq_desc + irq; raw_spin_lock_irqsave(&desc->lock, flags); desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; if (iflags & IRQF_VALID) @@ -154,25 +151,14 @@ void set_irq_flags(unsigned int irq, unsigned int iflags) void __init init_IRQ(void) { - struct irq_desc *desc; int irq; - for (irq = 0; irq < nr_irqs; irq++) { - desc = irq_to_desc_alloc_node(irq, 0); - desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; - } + for (irq = 0; irq < NR_IRQS; irq++) + irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE; init_arch_irq(); } -#ifdef CONFIG_SPARSE_IRQ -int __init arch_probe_nr_irqs(void) -{ - nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS; - return 0; -} -#endif - #ifdef CONFIG_HOTPLUG_CPU static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) @@ -192,9 +178,10 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) void migrate_irqs(void) { unsigned int i, cpu = smp_processor_id(); - struct irq_desc *desc; - for_each_irq_desc(i, desc) { + for (i = 0; i < NR_IRQS; i++) { + struct irq_desc *desc = irq_desc + i; + if (desc->node == cpu) { unsigned int newcpu = cpumask_any_and(desc->affinity, cpu_online_mask); diff --git a/trunk/arch/arm/kernel/machine_kexec.c b/trunk/arch/arm/kernel/machine_kexec.c index 1fc74cbd1a19..598ca61e7bca 100644 --- a/trunk/arch/arm/kernel/machine_kexec.c +++ b/trunk/arch/arm/kernel/machine_kexec.c @@ -37,12 +37,12 @@ void machine_kexec_cleanup(struct kimage *image) { } -void machine_crash_shutdown(struct pt_regs *regs) +void machine_shutdown(void) { - local_irq_disable(); - crash_save_cpu(regs, smp_processor_id()); +} - printk(KERN_INFO "Loading crashdump kernel...\n"); +void machine_crash_shutdown(struct pt_regs *regs) +{ } void machine_kexec(struct kimage *image) @@ -74,11 +74,7 @@ void machine_kexec(struct kimage *image) (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); printk(KERN_INFO "Bye!\n"); - local_irq_disable(); - local_fiq_disable(); - setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ - flush_cache_all(); cpu_proc_fin(); - flush_cache_all(); + setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ cpu_reset(reboot_code_buffer_phys); } diff --git a/trunk/arch/arm/kernel/process.c b/trunk/arch/arm/kernel/process.c index 401e38be1f78..a4a9cc88bec7 100644 --- a/trunk/arch/arm/kernel/process.c +++ b/trunk/arch/arm/kernel/process.c @@ -28,9 +28,7 @@ #include #include #include -#include -#include #include #include #include @@ -38,12 +36,6 @@ #include #include -#ifdef CONFIG_CC_STACKPROTECTOR -#include -unsigned long __stack_chk_guard __read_mostly; -EXPORT_SYMBOL(__stack_chk_guard); -#endif - static const char *processor_modes[] = { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", @@ -92,9 +84,10 @@ __setup("hlt", hlt_setup); void arm_machine_restart(char mode, const char *cmd) { - /* Disable interrupts first */ - local_irq_disable(); - local_fiq_disable(); + /* + * Clean and disable cache, and turn off interrupts + */ + cpu_proc_fin(); /* * Tell the mm system that we are going to reboot - @@ -103,15 +96,6 @@ void arm_machine_restart(char mode, const char *cmd) */ setup_mm_for_reboot(mode); - /* Clean and invalidate caches */ - flush_cache_all(); - - /* Turn off caching */ - cpu_proc_fin(); - - /* Push out any further dirty data, and ensure cache is empty */ - flush_cache_all(); - /* * Now call the architecture specific reboot code. */ @@ -205,29 +189,19 @@ int __init reboot_setup(char *str) __setup("reboot=", reboot_setup); -void machine_shutdown(void) -{ -#ifdef CONFIG_SMP - smp_send_stop(); -#endif -} - void machine_halt(void) { - machine_shutdown(); - while (1); } + void machine_power_off(void) { - machine_shutdown(); if (pm_power_off) pm_power_off(); } void machine_restart(char *cmd) { - machine_shutdown(); arm_pm_restart(reboot_mode, cmd); } @@ -452,9 +426,3 @@ unsigned long get_wchan(struct task_struct *p) } while (count ++ < 16); return 0; } - -unsigned long arch_randomize_brk(struct mm_struct *mm) -{ - unsigned long range_end = mm->brk + 0x02000000; - return randomize_range(mm->brk, range_end, 0) ? : mm->brk; -} diff --git a/trunk/arch/arm/kernel/ptrace.c b/trunk/arch/arm/kernel/ptrace.c index f99d489822d5..3f562a7c0a99 100644 --- a/trunk/arch/arm/kernel/ptrace.c +++ b/trunk/arch/arm/kernel/ptrace.c @@ -52,102 +52,6 @@ #define BREAKINST_THUMB 0xde01 #endif -struct pt_regs_offset { - const char *name; - int offset; -}; - -#define REG_OFFSET_NAME(r) \ - {.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)} -#define REG_OFFSET_END {.name = NULL, .offset = 0} - -static const struct pt_regs_offset regoffset_table[] = { - REG_OFFSET_NAME(r0), - REG_OFFSET_NAME(r1), - REG_OFFSET_NAME(r2), - REG_OFFSET_NAME(r3), - REG_OFFSET_NAME(r4), - REG_OFFSET_NAME(r5), - REG_OFFSET_NAME(r6), - REG_OFFSET_NAME(r7), - REG_OFFSET_NAME(r8), - REG_OFFSET_NAME(r9), - REG_OFFSET_NAME(r10), - REG_OFFSET_NAME(fp), - REG_OFFSET_NAME(ip), - REG_OFFSET_NAME(sp), - REG_OFFSET_NAME(lr), - REG_OFFSET_NAME(pc), - REG_OFFSET_NAME(cpsr), - REG_OFFSET_NAME(ORIG_r0), - REG_OFFSET_END, -}; - -/** - * regs_query_register_offset() - query register offset from its name - * @name: the name of a register - * - * regs_query_register_offset() returns the offset of a register in struct - * pt_regs from its name. If the name is invalid, this returns -EINVAL; - */ -int regs_query_register_offset(const char *name) -{ - const struct pt_regs_offset *roff; - for (roff = regoffset_table; roff->name != NULL; roff++) - if (!strcmp(roff->name, name)) - return roff->offset; - return -EINVAL; -} - -/** - * regs_query_register_name() - query register name from its offset - * @offset: the offset of a register in struct pt_regs. - * - * regs_query_register_name() returns the name of a register from its - * offset in struct pt_regs. If the @offset is invalid, this returns NULL; - */ -const char *regs_query_register_name(unsigned int offset) -{ - const struct pt_regs_offset *roff; - for (roff = regoffset_table; roff->name != NULL; roff++) - if (roff->offset == offset) - return roff->name; - return NULL; -} - -/** - * regs_within_kernel_stack() - check the address in the stack - * @regs: pt_regs which contains kernel stack pointer. - * @addr: address which is checked. - * - * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). - * If @addr is within the kernel stack, it returns true. If not, returns false. - */ -bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) -{ - return ((addr & ~(THREAD_SIZE - 1)) == - (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); -} - -/** - * regs_get_kernel_stack_nth() - get Nth entry of the stack - * @regs: pt_regs which contains kernel stack pointer. - * @n: stack entry number. - * - * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which - * is specified by @regs. If the @n th entry is NOT in the kernel stack, - * this returns 0. - */ -unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) -{ - unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); - addr += n; - if (regs_within_kernel_stack(regs, (unsigned long)addr)) - return *addr; - else - return 0; -} - /* * this routine will get a word off of the processes privileged stack. * the offset is how far from the base addr as stored in the THREAD. diff --git a/trunk/arch/arm/kernel/relocate_kernel.S b/trunk/arch/arm/kernel/relocate_kernel.S index fd26f8d65151..61930eb09029 100644 --- a/trunk/arch/arm/kernel/relocate_kernel.S +++ b/trunk/arch/arm/kernel/relocate_kernel.S @@ -10,12 +10,6 @@ relocate_new_kernel: ldr r0,kexec_indirection_page ldr r1,kexec_start_address - /* - * If there is no indirection page (we are doing crashdumps) - * skip any relocation. - */ - cmp r0, #0 - beq 2f 0: /* top, read another word for the indirection page */ ldr r3, [r0],#4 diff --git a/trunk/arch/arm/kernel/setup.c b/trunk/arch/arm/kernel/setup.c index d5231ae7355a..122d999bdc7c 100644 --- a/trunk/arch/arm/kernel/setup.c +++ b/trunk/arch/arm/kernel/setup.c @@ -19,15 +19,12 @@ #include #include #include -#include -#include #include #include #include #include #include #include -#include #include #include @@ -47,9 +44,7 @@ #include #include -#if defined(CONFIG_DEPRECATED_PARAM_STRUCT) #include "compat.h" -#endif #include "atags.h" #include "tcm.h" @@ -274,21 +269,6 @@ static void __init cacheid_init(void) extern struct proc_info_list *lookup_processor_type(unsigned int); extern struct machine_desc *lookup_machine_type(unsigned int); -static void __init feat_v6_fixup(void) -{ - int id = read_cpuid_id(); - - if ((id & 0xff0f0000) != 0x41070000) - return; - - /* - * HWCAP_TLS is available only on 1136 r1p0 and later, - * see also kuser_get_tls_init. - */ - if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0)) - elf_hwcap &= ~HWCAP_TLS; -} - static void __init setup_processor(void) { struct proc_info_list *list; @@ -331,8 +311,6 @@ static void __init setup_processor(void) elf_hwcap &= ~HWCAP_THUMB; #endif - feat_v6_fixup(); - cacheid_init(); cpu_proc_init(); } @@ -424,12 +402,13 @@ static int __init arm_add_memory(unsigned long start, unsigned long size) size -= start & ~PAGE_MASK; bank->start = PAGE_ALIGN(start); bank->size = size & PAGE_MASK; + bank->node = PHYS_TO_NID(start); /* * Check whether this memory region has non-zero size or * invalid node number. */ - if (bank->size == 0) + if (bank->size == 0 || bank->node >= MAX_NUMNODES) return -EINVAL; meminfo.nr_banks++; @@ -684,86 +663,6 @@ static int __init customize_machine(void) } arch_initcall(customize_machine); -#ifdef CONFIG_KEXEC -static inline unsigned long long get_total_mem(void) -{ - unsigned long total; - - total = max_low_pfn - min_low_pfn; - return total << PAGE_SHIFT; -} - -/** - * reserve_crashkernel() - reserves memory are for crash kernel - * - * This function reserves memory area given in "crashkernel=" kernel command - * line parameter. The memory reserved is used by a dump capture kernel when - * primary kernel is crashing. - */ -static void __init reserve_crashkernel(void) -{ - unsigned long long crash_size, crash_base; - unsigned long long total_mem; - int ret; - - total_mem = get_total_mem(); - ret = parse_crashkernel(boot_command_line, total_mem, - &crash_size, &crash_base); - if (ret) - return; - - ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE); - if (ret < 0) { - printk(KERN_WARNING "crashkernel reservation failed - " - "memory is in use (0x%lx)\n", (unsigned long)crash_base); - return; - } - - printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " - "for crashkernel (System RAM: %ldMB)\n", - (unsigned long)(crash_size >> 20), - (unsigned long)(crash_base >> 20), - (unsigned long)(total_mem >> 20)); - - crashk_res.start = crash_base; - crashk_res.end = crash_base + crash_size - 1; - insert_resource(&iomem_resource, &crashk_res); -} -#else -static inline void reserve_crashkernel(void) {} -#endif /* CONFIG_KEXEC */ - -/* - * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by - * is_kdump_kernel() to determine if we are booting after a panic. Hence - * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. - */ - -#ifdef CONFIG_CRASH_DUMP -/* - * elfcorehdr= specifies the location of elf core header stored by the crashed - * kernel. This option will be passed by kexec loader to the capture kernel. - */ -static int __init setup_elfcorehdr(char *arg) -{ - char *end; - - if (!arg) - return -EINVAL; - - elfcorehdr_addr = memparse(arg, &end); - return end > arg ? 0 : -EINVAL; -} -early_param("elfcorehdr", setup_elfcorehdr); -#endif /* CONFIG_CRASH_DUMP */ - -static void __init squash_mem_tags(struct tag *tag) -{ - for (; tag->hdr.size; tag = tag_next(tag)) - if (tag->hdr.tag == ATAG_MEM) - tag->hdr.tag = ATAG_NONE; -} - void __init setup_arch(char **cmdline_p) { struct tag *tags = (struct tag *)&init_tags; @@ -784,14 +683,12 @@ void __init setup_arch(char **cmdline_p) else if (mdesc->boot_params) tags = phys_to_virt(mdesc->boot_params); -#if defined(CONFIG_DEPRECATED_PARAM_STRUCT) /* * If we have the old style parameters, convert them to * a tag list. */ if (tags->hdr.tag != ATAG_CORE) convert_to_tag_list(tags); -#endif if (tags->hdr.tag != ATAG_CORE) tags = (struct tag *)&init_tags; @@ -819,15 +716,12 @@ void __init setup_arch(char **cmdline_p) parse_early_param(); - arm_memblock_init(&meminfo, mdesc); - paging_init(mdesc); request_standard_resources(&meminfo, mdesc); #ifdef CONFIG_SMP smp_init_cpus(); #endif - reserve_crashkernel(); cpu_init(); tcm_init(); @@ -835,7 +729,6 @@ void __init setup_arch(char **cmdline_p) /* * Set up various architecture-specific pointers */ - arch_nr_irqs = mdesc->nr_irqs; init_arch_irq = mdesc->init_irq; system_timer = mdesc->timer; init_machine = mdesc->init_machine; diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c index 40dc74f2b27f..b8c3d0f689d9 100644 --- a/trunk/arch/arm/kernel/smp.c +++ b/trunk/arch/arm/kernel/smp.c @@ -429,11 +429,7 @@ static void smp_timer_broadcast(const struct cpumask *mask) { send_ipi_message(mask, IPI_TIMER); } -#else -#define smp_timer_broadcast NULL -#endif -#ifndef CONFIG_LOCAL_TIMERS static void broadcast_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { @@ -448,6 +444,7 @@ static void local_timer_setup(struct clock_event_device *evt) evt->rating = 400; evt->mult = 1; evt->set_mode = broadcast_timer_set_mode; + evt->broadcast = smp_timer_broadcast; clockevents_register_device(evt); } @@ -459,7 +456,6 @@ void __cpuinit percpu_timer_setup(void) struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); evt->cpumask = cpumask_of(cpu); - evt->broadcast = smp_timer_broadcast; local_timer_setup(evt); } @@ -471,13 +467,10 @@ static DEFINE_SPINLOCK(stop_lock); */ static void ipi_cpu_stop(unsigned int cpu) { - if (system_state == SYSTEM_BOOTING || - system_state == SYSTEM_RUNNING) { - spin_lock(&stop_lock); - printk(KERN_CRIT "CPU%u: stopping\n", cpu); - dump_stack(); - spin_unlock(&stop_lock); - } + spin_lock(&stop_lock); + printk(KERN_CRIT "CPU%u: stopping\n", cpu); + dump_stack(); + spin_unlock(&stop_lock); set_cpu_online(cpu, false); diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c index 35882fbf37f9..7c5f0c024db7 100644 --- a/trunk/arch/arm/kernel/smp_twd.c +++ b/trunk/arch/arm/kernel/smp_twd.c @@ -132,8 +132,7 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) twd_calibrate_rate(); clk->name = "local_timer"; - clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_C3STOP; + clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; clk->rating = 350; clk->set_mode = twd_set_mode; clk->set_next_event = twd_set_next_event; diff --git a/trunk/arch/arm/kernel/tcm.c b/trunk/arch/arm/kernel/tcm.c index 26685c2f7a49..e50303868f1b 100644 --- a/trunk/arch/arm/kernel/tcm.c +++ b/trunk/arch/arm/kernel/tcm.c @@ -13,35 +13,38 @@ #include #include #include /* memcpy */ +#include /* PAGE_SHIFT */ #include #include #include #include "tcm.h" +/* Scream and warn about misuse */ +#if !defined(ITCM_OFFSET) || !defined(ITCM_END) || \ + !defined(DTCM_OFFSET) || !defined(DTCM_END) +#error "TCM support selected but offsets not defined!" +#endif + static struct gen_pool *tcm_pool; /* TCM section definitions from the linker */ extern char __itcm_start, __sitcm_text, __eitcm_text; extern char __dtcm_start, __sdtcm_data, __edtcm_data; -/* These will be increased as we run */ -u32 dtcm_end = DTCM_OFFSET; -u32 itcm_end = ITCM_OFFSET; - /* * TCM memory resources */ static struct resource dtcm_res = { .name = "DTCM RAM", .start = DTCM_OFFSET, - .end = DTCM_OFFSET, + .end = DTCM_END, .flags = IORESOURCE_MEM }; static struct resource itcm_res = { .name = "ITCM RAM", .start = ITCM_OFFSET, - .end = ITCM_OFFSET, + .end = ITCM_END, .flags = IORESOURCE_MEM }; @@ -49,8 +52,8 @@ static struct map_desc dtcm_iomap[] __initdata = { { .virtual = DTCM_OFFSET, .pfn = __phys_to_pfn(DTCM_OFFSET), - .length = 0, - .type = MT_MEMORY_DTCM + .length = (DTCM_END - DTCM_OFFSET + 1), + .type = MT_UNCACHED } }; @@ -58,8 +61,8 @@ static struct map_desc itcm_iomap[] __initdata = { { .virtual = ITCM_OFFSET, .pfn = __phys_to_pfn(ITCM_OFFSET), - .length = 0, - .type = MT_MEMORY_ITCM + .length = (ITCM_END - ITCM_OFFSET + 1), + .type = MT_UNCACHED } }; @@ -90,24 +93,14 @@ void tcm_free(void *addr, size_t len) } EXPORT_SYMBOL(tcm_free); -static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks, - u32 *offset) + +static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size) { const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128, 256, 512, 1024, -1, -1, -1, -1 }; u32 tcm_region; int tcm_size; - /* - * If there are more than one TCM bank of this type, - * select the TCM bank to operate on in the TCM selection - * register. - */ - if (banks > 1) - asm("mcr p15, 0, %0, c9, c2, 0" - : /* No output operands */ - : "r" (bank)); - /* Read the special TCM region register c9, 0 */ if (!type) asm("mrc p15, 0, %0, c9, c1, 0" @@ -118,24 +111,26 @@ static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks, tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f]; if (tcm_size < 0) { - pr_err("CPU: %sTCM%d of unknown size\n", - type ? "I" : "D", bank); - return -EINVAL; - } else if (tcm_size > 32) { - pr_err("CPU: %sTCM%d larger than 32k found\n", - type ? "I" : "D", bank); - return -EINVAL; + pr_err("CPU: %sTCM of unknown size!\n", + type ? "I" : "D"); } else { - pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n", + pr_info("CPU: found %sTCM %dk @ %08x, %senabled\n", type ? "I" : "D", - bank, tcm_size, (tcm_region & 0xfffff000U), (tcm_region & 1) ? "" : "not "); } + if (tcm_size != expected_size) { + pr_crit("CPU: %sTCM was detected %dk but expected %dk!\n", + type ? "I" : "D", + tcm_size, + expected_size); + /* Adjust to the expected size? what can we do... */ + } + /* Force move the TCM bank to where we want it, enable */ - tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1; + tcm_region = offset | (tcm_region & 0x00000ffeU) | 1; if (!type) asm("mcr p15, 0, %0, c9, c1, 0" @@ -146,15 +141,10 @@ static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks, : /* No output operands */ : "r" (tcm_region)); - /* Increase offset */ - *offset += (tcm_size << 10); - - pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n", - type ? "I" : "D", - bank, - tcm_size, - (tcm_region & 0xfffff000U)); - return 0; + pr_debug("CPU: moved %sTCM %dk to %08x, enabled\n", + type ? "I" : "D", + tcm_size, + (tcm_region & 0xfffff000U)); } /* @@ -163,52 +153,34 @@ static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks, void __init tcm_init(void) { u32 tcm_status = read_cpuid_tcmstatus(); - u8 dtcm_banks = (tcm_status >> 16) & 0x03; - u8 itcm_banks = (tcm_status & 0x03); char *start; char *end; char *ram; - int ret; - int i; /* Setup DTCM if present */ - if (dtcm_banks > 0) { - for (i = 0; i < dtcm_banks; i++) { - ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end); - if (ret) - return; - } - dtcm_res.end = dtcm_end - 1; + if (tcm_status & (1 << 16)) { + setup_tcm_bank(0, DTCM_OFFSET, + (DTCM_END - DTCM_OFFSET + 1) >> 10); request_resource(&iomem_resource, &dtcm_res); - dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET; iotable_init(dtcm_iomap, 1); /* Copy data from RAM to DTCM */ start = &__sdtcm_data; end = &__edtcm_data; ram = &__dtcm_start; - /* This means you compiled more code than fits into DTCM */ - BUG_ON((end - start) > (dtcm_end - DTCM_OFFSET)); memcpy(start, ram, (end-start)); pr_debug("CPU DTCM: copied data from %p - %p\n", start, end); } /* Setup ITCM if present */ - if (itcm_banks > 0) { - for (i = 0; i < itcm_banks; i++) { - ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end); - if (ret) - return; - } - itcm_res.end = itcm_end - 1; + if (tcm_status & 1) { + setup_tcm_bank(1, ITCM_OFFSET, + (ITCM_END - ITCM_OFFSET + 1) >> 10); request_resource(&iomem_resource, &itcm_res); - itcm_iomap[0].length = itcm_end - ITCM_OFFSET; iotable_init(itcm_iomap, 1); /* Copy code from RAM to ITCM */ start = &__sitcm_text; end = &__eitcm_text; ram = &__itcm_start; - /* This means you compiled more code than fits into ITCM */ - BUG_ON((end - start) > (itcm_end - ITCM_OFFSET)); memcpy(start, ram, (end-start)); pr_debug("CPU ITCM: copied code from %p - %p\n", start, end); } @@ -236,10 +208,10 @@ static int __init setup_tcm_pool(void) pr_debug("Setting up TCM memory pool\n"); /* Add the rest of DTCM to the TCM pool */ - if (tcm_status & (0x03 << 16)) { - if (dtcm_pool_start < dtcm_end) { + if (tcm_status & (1 << 16)) { + if (dtcm_pool_start < DTCM_END) { ret = gen_pool_add(tcm_pool, dtcm_pool_start, - dtcm_end - dtcm_pool_start, -1); + DTCM_END - dtcm_pool_start + 1, -1); if (ret) { pr_err("CPU DTCM: could not add DTCM " \ "remainder to pool!\n"); @@ -247,16 +219,16 @@ static int __init setup_tcm_pool(void) } pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \ "the TCM memory pool\n", - dtcm_end - dtcm_pool_start, + DTCM_END - dtcm_pool_start + 1, dtcm_pool_start); } } /* Add the rest of ITCM to the TCM pool */ - if (tcm_status & 0x03) { - if (itcm_pool_start < itcm_end) { + if (tcm_status & 1) { + if (itcm_pool_start < ITCM_END) { ret = gen_pool_add(tcm_pool, itcm_pool_start, - itcm_end - itcm_pool_start, -1); + ITCM_END - itcm_pool_start + 1, -1); if (ret) { pr_err("CPU ITCM: could not add ITCM " \ "remainder to pool!\n"); @@ -264,7 +236,7 @@ static int __init setup_tcm_pool(void) } pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \ "the TCM memory pool\n", - itcm_end - itcm_pool_start, + ITCM_END - itcm_pool_start + 1, itcm_pool_start); } } diff --git a/trunk/arch/arm/kernel/traps.c b/trunk/arch/arm/kernel/traps.c index cda78d59aa31..1621e5327b2a 100644 --- a/trunk/arch/arm/kernel/traps.c +++ b/trunk/arch/arm/kernel/traps.c @@ -30,7 +30,6 @@ #include #include #include -#include #include "ptrace.h" #include "signal.h" @@ -519,20 +518,17 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) case NR(set_tls): thread->tp_value = regs->ARM_r0; - if (tls_emu) - return 0; - if (has_tls_reg) { - asm ("mcr p15, 0, %0, c13, c0, 3" - : : "r" (regs->ARM_r0)); - } else { - /* - * User space must never try to access this directly. - * Expect your app to break eventually if you do so. - * The user helper at 0xffff0fe0 must be used instead. - * (see entry-armv.S for details) - */ - *((unsigned int *)0xffff0ff0) = regs->ARM_r0; - } +#if defined(CONFIG_HAS_TLS_REG) + asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) ); +#elif !defined(CONFIG_TLS_REG_EMUL) + /* + * User space must never try to access this directly. + * Expect your app to break eventually if you do so. + * The user helper at 0xffff0fe0 must be used instead. + * (see entry-armv.S for details) + */ + *((unsigned int *)0xffff0ff0) = regs->ARM_r0; +#endif return 0; #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG @@ -747,16 +743,6 @@ void __init trap_init(void) return; } -static void __init kuser_get_tls_init(unsigned long vectors) -{ - /* - * vectors + 0xfe0 = __kuser_get_tls - * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8 - */ - if (tls_emu || has_tls_reg) - memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4); -} - void __init early_trap_init(void) { unsigned long vectors = CONFIG_VECTORS_BASE; @@ -774,11 +760,6 @@ void __init early_trap_init(void) memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start); memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz); - /* - * Do processor specific fixups for the kuser helpers - */ - kuser_get_tls_init(vectors); - /* * Copy signal return handlers into the vector page, and * set sigreturn to be a pointer to these. diff --git a/trunk/arch/arm/lib/Makefile b/trunk/arch/arm/lib/Makefile index 59ff42ddf0ae..030ba7219f48 100644 --- a/trunk/arch/arm/lib/Makefile +++ b/trunk/arch/arm/lib/Makefile @@ -41,6 +41,7 @@ else endif lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o +lib-$(CONFIG_ARCH_L7200) += io-acorn.o lib-$(CONFIG_ARCH_SHARK) += io-shark.o $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S diff --git a/trunk/arch/arm/mach-aaec2000/include/mach/memory.h b/trunk/arch/arm/mach-aaec2000/include/mach/memory.h index 4f93c567a35a..c00822543d9f 100644 --- a/trunk/arch/arm/mach-aaec2000/include/mach/memory.h +++ b/trunk/arch/arm/mach-aaec2000/include/mach/memory.h @@ -14,4 +14,14 @@ #define PHYS_OFFSET UL(0xf0000000) +/* + * The nodes are the followings: + * + * node 0: 0xf000.0000 - 0xf3ff.ffff + * node 1: 0xf400.0000 - 0xf7ff.ffff + * node 2: 0xf800.0000 - 0xfbff.ffff + * node 3: 0xfc00.0000 - 0xffff.ffff + */ +#define NODE_MEM_SIZE_BITS 26 + #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/trunk/arch/arm/mach-at91/Kconfig b/trunk/arch/arm/mach-at91/Kconfig index 939bccd70569..841eaf8f27e2 100644 --- a/trunk/arch/arm/mach-at91/Kconfig +++ b/trunk/arch/arm/mach-at91/Kconfig @@ -366,17 +366,6 @@ config MACH_STAMP9G20 endif -if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) -comment "AT91SAM9260/AT91SAM9G20 boards" - -config MACH_SNAPPER_9260 - bool "Bluewater Systems Snapper 9260/9G20 module" - help - Select this if you are using the Bluewater Systems Snapper 9260 or - Snapper 9G20 modules. - -endif - # ---------------------------------------------------------- if ARCH_AT91SAM9G45 diff --git a/trunk/arch/arm/mach-at91/Makefile b/trunk/arch/arm/mach-at91/Makefile index ca2ac003f41f..c1f821e58222 100644 --- a/trunk/arch/arm/mach-at91/Makefile +++ b/trunk/arch/arm/mach-at91/Makefile @@ -66,9 +66,6 @@ obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o -# AT91SAM9260/AT91SAM9G20 board-specific support -obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o - # AT91SAM9G45 board-specific support obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o diff --git a/trunk/arch/arm/mach-at91/at91sam9g45.c b/trunk/arch/arm/mach-at91/at91sam9g45.c index 753c0d31a3d3..85166b7e69a1 100644 --- a/trunk/arch/arm/mach-at91/at91sam9g45.c +++ b/trunk/arch/arm/mach-at91/at91sam9g45.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "generic.h" #include "clock.h" @@ -177,13 +176,6 @@ static struct clk mmc1_clk = { .type = CLK_TYPE_PERIPHERAL, }; -/* Video decoder clock - Only for sam9m10/sam9m11 */ -static struct clk vdec_clk = { - .name = "vdec_clk", - .pmc_mask = 1 << AT91SAM9G45_ID_VDEC, - .type = CLK_TYPE_PERIPHERAL, -}; - /* One additional fake clock for ohci */ static struct clk ohci_clk = { .name = "ohci_clk", @@ -247,9 +239,6 @@ static void __init at91sam9g45_register_clocks(void) for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) clk_register(periph_clocks[i]); - if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) - clk_register(&vdec_clk); - clk_register(&pck0); clk_register(&pck1); } diff --git a/trunk/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/trunk/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c index c49f5c003ee1..a4102d72cc9b 100644 --- a/trunk/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c +++ b/trunk/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c @@ -26,9 +26,6 @@ #include #include #include -#include -#include -#include #include #include @@ -238,46 +235,6 @@ static struct gpio_led ek_leds[] = { } }; -#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) -static struct regulator_consumer_supply ek_audio_consumer_supplies[] = { - REGULATOR_SUPPLY("AVDD", "0-001b"), - REGULATOR_SUPPLY("HPVDD", "0-001b"), - REGULATOR_SUPPLY("DBVDD", "0-001b"), - REGULATOR_SUPPLY("DCVDD", "0-001b"), -}; - -static struct regulator_init_data ek_avdd_reg_init_data = { - .constraints = { - .name = "3V3", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .consumer_supplies = ek_audio_consumer_supplies, - .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies), -}; - -static struct fixed_voltage_config ek_vdd_pdata = { - .supply_name = "board-3V3", - .microvolts = 3300000, - .gpio = -EINVAL, - .enabled_at_boot = 0, - .init_data = &ek_avdd_reg_init_data, -}; -static struct platform_device ek_voltage_regulator = { - .name = "reg-fixed-voltage", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ek_vdd_pdata, - }, -}; -static void __init ek_add_regulators(void) -{ - platform_device_register(&ek_voltage_regulator); -} -#else -static void __init ek_add_regulators(void) {} -#endif - static struct i2c_board_info __initdata ek_i2c_devices[] = { { I2C_BOARD_INFO("24c512", 0x50), @@ -299,8 +256,6 @@ static void __init ek_board_init(void) ek_add_device_nand(); /* Ethernet */ at91_add_device_eth(&ek_macb_data); - /* Regulators */ - ek_add_regulators(); /* MMC */ #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) at91_add_device_mci(0, &ek_mmc_data); diff --git a/trunk/arch/arm/mach-at91/board-sam9g20ek.c b/trunk/arch/arm/mach-at91/board-sam9g20ek.c index 6ea9808b8868..c11fd47aec5d 100644 --- a/trunk/arch/arm/mach-at91/board-sam9g20ek.c +++ b/trunk/arch/arm/mach-at91/board-sam9g20ek.c @@ -27,9 +27,6 @@ #include #include #include -#include -#include -#include #include #include @@ -272,46 +269,6 @@ static void __init ek_add_device_buttons(void) static void __init ek_add_device_buttons(void) {} #endif -#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) -static struct regulator_consumer_supply ek_audio_consumer_supplies[] = { - REGULATOR_SUPPLY("AVDD", "0-001b"), - REGULATOR_SUPPLY("HPVDD", "0-001b"), - REGULATOR_SUPPLY("DBVDD", "0-001b"), - REGULATOR_SUPPLY("DCVDD", "0-001b"), -}; - -static struct regulator_init_data ek_avdd_reg_init_data = { - .constraints = { - .name = "3V3", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .consumer_supplies = ek_audio_consumer_supplies, - .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies), -}; - -static struct fixed_voltage_config ek_vdd_pdata = { - .supply_name = "board-3V3", - .microvolts = 3300000, - .gpio = -EINVAL, - .enabled_at_boot = 0, - .init_data = &ek_avdd_reg_init_data, -}; -static struct platform_device ek_voltage_regulator = { - .name = "reg-fixed-voltage", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ek_vdd_pdata, - }, -}; -static void __init ek_add_regulators(void) -{ - platform_device_register(&ek_voltage_regulator); -} -#else -static void __init ek_add_regulators(void) {} -#endif - static struct i2c_board_info __initdata ek_i2c_devices[] = { { @@ -337,8 +294,6 @@ static void __init ek_board_init(void) ek_add_device_nand(); /* Ethernet */ at91_add_device_eth(&ek_macb_data); - /* Regulators */ - ek_add_regulators(); /* MMC */ at91_add_device_mmc(0, &ek_mmc_data); /* I2C */ diff --git a/trunk/arch/arm/mach-at91/board-snapper9260.c b/trunk/arch/arm/mach-at91/board-snapper9260.c deleted file mode 100644 index 2c08ae4ad3a1..000000000000 --- a/trunk/arch/arm/mach-at91/board-snapper9260.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * linux/arch/arm/mach-at91/board-snapper9260.c - * - * Copyright (C) 2010 Bluewater System Ltd - * - * Author: Andre Renaud - * Author: Ryan Mallon - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "sam9_smc.h" -#include "generic.h" - -#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x)) - -static void __init snapper9260_map_io(void) -{ - at91sam9260_initialize(18432000); - - /* Debug on ttyS0 */ - at91_register_uart(0, 0, 0); - at91_set_serial_console(0); - - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_register_uart(AT91SAM9260_ID_US2, 3, 0); -} - -static void __init snapper9260_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - -static struct at91_usbh_data __initdata snapper9260_usbh_data = { - .ports = 2, -}; - -static struct at91_udc_data __initdata snapper9260_udc_data = { - .vbus_pin = SNAPPER9260_IO_EXP_GPIO(5), - .vbus_active_low = 1, - .vbus_polled = 1, -}; - -static struct at91_eth_data snapper9260_macb_data = { - .is_rmii = 1, -}; - -static struct mtd_partition __initdata snapper9260_nand_partitions[] = { - { - .name = "Preboot", - .offset = 0, - .size = SZ_128K, - }, - { - .name = "Bootloader", - .offset = MTDPART_OFS_APPEND, - .size = SZ_256K, - }, - { - .name = "Environment", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - }, - { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - }, - { - .name = "Filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct mtd_partition * __init -snapper9260_nand_partition_info(int size, int *num_partitions) -{ - *num_partitions = ARRAY_SIZE(snapper9260_nand_partitions); - return snapper9260_nand_partitions; -} - -static struct atmel_nand_data __initdata snapper9260_nand_data = { - .ale = 21, - .cle = 22, - .rdy_pin = AT91_PIN_PC13, - .partition_info = snapper9260_nand_partition_info, - .bus_width_16 = 0, -}; - -static struct sam9_smc_config __initdata snapper9260_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 0, - .ncs_write_setup = 0, - .nwe_setup = 0, - - .ncs_read_pulse = 5, - .nrd_pulse = 2, - .ncs_write_pulse = 5, - .nwe_pulse = 2, - - .read_cycle = 7, - .write_cycle = 7, - - .mode = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE), - .tdf_cycles = 1, -}; - -static struct pca953x_platform_data snapper9260_io_expander_data = { - .gpio_base = SNAPPER9260_IO_EXP_GPIO(0), -}; - -static struct i2c_board_info __initdata snapper9260_i2c_devices[] = { - { - /* IO expander */ - I2C_BOARD_INFO("max7312", 0x28), - .platform_data = &snapper9260_io_expander_data, - }, - { - /* Audio codec */ - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, - { - /* RTC */ - I2C_BOARD_INFO("isl1208", 0x6f), - }, -}; - -static void __init snapper9260_add_device_nand(void) -{ - at91_set_A_periph(AT91_PIN_PC14, 0); - sam9_smc_configure(3, &snapper9260_nand_smc_config); - at91_add_device_nand(&snapper9260_nand_data); -} - -static void __init snapper9260_board_init(void) -{ - at91_add_device_i2c(snapper9260_i2c_devices, - ARRAY_SIZE(snapper9260_i2c_devices)); - at91_add_device_serial(); - at91_add_device_usbh(&snapper9260_usbh_data); - at91_add_device_udc(&snapper9260_udc_data); - at91_add_device_eth(&snapper9260_macb_data); - at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK | - ATMEL_SSC_TD | ATMEL_SSC_RD)); - snapper9260_add_device_nand(); -} - -MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, - .map_io = snapper9260_map_io, - .init_irq = snapper9260_init_irq, - .init_machine = snapper9260_board_init, -MACHINE_END - - diff --git a/trunk/arch/arm/mach-at91/include/mach/at91cap9.h b/trunk/arch/arm/mach-at91/include/mach/at91cap9.h index 9c6af9737485..d8c1ededaa75 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91cap9.h @@ -84,7 +84,7 @@ */ #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) +#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) diff --git a/trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h index 976f4a6c3353..1499b1cbffdd 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h @@ -15,7 +15,7 @@ #ifndef AT91CAP9_DDRSDR_H #define AT91CAP9_DDRSDR_H -#define AT91_DDRSDRC_MR 0x00 /* Mode Register */ +#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ #define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ #define AT91_DDRSDRC_MODE_NORMAL 0 #define AT91_DDRSDRC_MODE_NOP 1 @@ -25,10 +25,10 @@ #define AT91_DDRSDRC_MODE_EXT_LMR 5 #define AT91_DDRSDRC_MODE_DEEP 6 -#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ +#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ -#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ +#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ #define AT91_DDRSDRC_NC_SDR8 (0 << 0) #define AT91_DDRSDRC_NC_SDR9 (1 << 0) @@ -49,7 +49,7 @@ #define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ -#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ +#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ @@ -59,13 +59,13 @@ #define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ -#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ +#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ -#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */ +#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ #define AT91_DDRSDRC_LPCB_DISABLE 0 #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 @@ -80,14 +80,14 @@ #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */ +#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ #define AT91_DDRSDRC_MD_SDR 0 #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 #define AT91_DDRSDRC_MD_DDR 2 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 -#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ +#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ @@ -98,11 +98,5 @@ #define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ #define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ -/* Register access macros */ -#define at91_ramc_read(num, reg) \ - at91_sys_read(AT91_DDRSDRC##num + reg) -#define at91_ramc_write(num, reg, value) \ - at91_sys_write(AT91_DDRSDRC##num + reg, value) - #endif diff --git a/trunk/arch/arm/mach-at91/include/mach/at91sam9260.h b/trunk/arch/arm/mach-at91/include/mach/at91sam9260.h index 4e79036d3b80..43c396b9b4cb 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -84,7 +84,7 @@ * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) diff --git a/trunk/arch/arm/mach-at91/include/mach/at91sam9261.h b/trunk/arch/arm/mach-at91/include/mach/at91sam9261.h index 2b5618518129..87de8be17484 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -68,7 +68,7 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) diff --git a/trunk/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/trunk/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h deleted file mode 100644 index d27b15ba8ebf..000000000000 --- a/trunk/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Header file for the Atmel DDR/SDR SDRAM Controller - * - * Copyright (C) 2010 Atmel Corporation - * Nicolas Ferre - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#ifndef AT91SAM9_DDRSDR_H -#define AT91SAM9_DDRSDR_H - -#define AT91_DDRSDRC_MR 0x00 /* Mode Register */ -#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ -#define AT91_DDRSDRC_MODE_NORMAL 0 -#define AT91_DDRSDRC_MODE_NOP 1 -#define AT91_DDRSDRC_MODE_PRECHARGE 2 -#define AT91_DDRSDRC_MODE_LMR 3 -#define AT91_DDRSDRC_MODE_REFRESH 4 -#define AT91_DDRSDRC_MODE_EXT_LMR 5 -#define AT91_DDRSDRC_MODE_DEEP 6 - -#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ -#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ -#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_DDRSDRC_NC_SDR8 (0 << 0) -#define AT91_DDRSDRC_NC_SDR9 (1 << 0) -#define AT91_DDRSDRC_NC_SDR10 (2 << 0) -#define AT91_DDRSDRC_NC_SDR11 (3 << 0) -#define AT91_DDRSDRC_NC_DDR9 (0 << 0) -#define AT91_DDRSDRC_NC_DDR10 (1 << 0) -#define AT91_DDRSDRC_NC_DDR11 (2 << 0) -#define AT91_DDRSDRC_NC_DDR12 (3 << 0) -#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_DDRSDRC_NR_11 (0 << 2) -#define AT91_DDRSDRC_NR_12 (1 << 2) -#define AT91_DDRSDRC_NR_13 (2 << 2) -#define AT91_DDRSDRC_NR_14 (3 << 2) -#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ -#define AT91_DDRSDRC_CAS_2 (2 << 4) -#define AT91_DDRSDRC_CAS_3 (3 << 4) -#define AT91_DDRSDRC_CAS_25 (6 << 4) -#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ -#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ -#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */ -#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */ -#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */ -#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */ - -#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ -#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ -#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ -#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ -#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ -#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ -#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ -#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ -#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */ -#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ - -#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ -#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ -#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ -#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ -#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ - -#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */ -#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ -#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ -#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ -#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ - -#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ -#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_DDRSDRC_LPCB_DISABLE 0 -#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 -#define AT91_DDRSDRC_LPCB_POWER_DOWN 2 -#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ -#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ -#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */ -#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ - -#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ -#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ -#define AT91_DDRSDRC_MD_SDR 0 -#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 -#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 -#define AT91_DDRSDRC_MD_DDR2 6 -#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ -#define AT91_DDRSDRC_DBW_32BITS (0 << 4) -#define AT91_DDRSDRC_DBW_16BITS (1 << 4) - -#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ -#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ -#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ -#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ -#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ - -#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */ -#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ - -#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ - -#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */ -#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ -#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ -#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ - -#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */ -#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ -#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ - -/* Register access macros */ -#define at91_ramc_read(num, reg) \ - at91_sys_read(AT91_DDRSDRC##num + reg) -#define at91_ramc_write(num, reg, value) \ - at91_sys_write(AT91_DDRSDRC##num + reg, value) - -#endif diff --git a/trunk/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/trunk/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h index 100f5a592926..b7260389f7ca 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h @@ -17,7 +17,7 @@ #define AT91SAM9_SDRAMC_H /* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */ +#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ #define AT91_SDRAMC_MODE_NORMAL 0 #define AT91_SDRAMC_MODE_NOP 1 @@ -27,10 +27,10 @@ #define AT91_SDRAMC_MODE_EXT_LMR 5 #define AT91_SDRAMC_MODE_DEEP 6 -#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */ +#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ -#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */ +#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ #define AT91_SDRAMC_NC_8 (0 << 0) #define AT91_SDRAMC_NC_9 (1 << 0) @@ -57,7 +57,7 @@ #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ -#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */ +#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ #define AT91_SDRAMC_LPCB_DISABLE 0 #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 @@ -71,21 +71,16 @@ #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */ +#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ -#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */ +#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 -/* Register access macros */ -#define at91_ramc_read(num, reg) \ - at91_sys_read(AT91_SDRAMC##num + reg) -#define at91_ramc_write(num, reg, value) \ - at91_sys_write(AT91_SDRAMC##num + reg, value) #endif diff --git a/trunk/arch/arm/mach-at91/include/mach/at91sam9rl.h b/trunk/arch/arm/mach-at91/include/mach/at91sam9rl.h index 87ba8517ad98..fc2de6c09c86 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -74,7 +74,7 @@ */ #define AT91_DMA (0xffffe600 - AT91_BASE_SYS) #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) diff --git a/trunk/arch/arm/mach-at91/include/mach/board.h b/trunk/arch/arm/mach-at91/include/mach/board.h index 58528aa9c8a8..df2ed848c9f8 100644 --- a/trunk/arch/arm/mach-at91/include/mach/board.h +++ b/trunk/arch/arm/mach-at91/include/mach/board.h @@ -44,8 +44,6 @@ /* USB Device */ struct at91_udc_data { u8 vbus_pin; /* high == host powering us */ - u8 vbus_active_low; /* vbus polarity */ - u8 vbus_polled; /* Use polling, not interrupt */ u8 pullup_pin; /* active == D+ pulled up */ u8 pullup_active_low; /* true == pullup_pin is active low */ }; diff --git a/trunk/arch/arm/mach-at91/include/mach/cpu.h b/trunk/arch/arm/mach-at91/include/mach/cpu.h index 3bef931d0b1c..833659d1200a 100644 --- a/trunk/arch/arm/mach-at91/include/mach/cpu.h +++ b/trunk/arch/arm/mach-at91/include/mach/cpu.h @@ -52,7 +52,6 @@ static inline unsigned long at91_cpu_fully_identify(void) #define ARCH_EXID_AT91SAM9M11 0x00000001 #define ARCH_EXID_AT91SAM9M10 0x00000002 -#define ARCH_EXID_AT91SAM9G46 0x00000003 #define ARCH_EXID_AT91SAM9G45 0x00000004 static inline unsigned long at91_exid_identify(void) @@ -129,18 +128,9 @@ static inline unsigned long at91cap9_rev_identify(void) #ifdef CONFIG_ARCH_AT91SAM9G45 #define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) #define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES) -#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9M10)) -#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G46)) -#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9M11)) #else #define cpu_is_at91sam9g45() (0) #define cpu_is_at91sam9g45es() (0) -#define cpu_is_at91sam9m10() (0) -#define cpu_is_at91sam9g46() (0) -#define cpu_is_at91sam9m11() (0) #endif #ifdef CONFIG_ARCH_AT91CAP9 diff --git a/trunk/arch/arm/mach-at91/include/mach/gpio.h b/trunk/arch/arm/mach-at91/include/mach/gpio.h index bfdd8ab26dc8..04c91e31c9c5 100644 --- a/trunk/arch/arm/mach-at91/include/mach/gpio.h +++ b/trunk/arch/arm/mach-at91/include/mach/gpio.h @@ -19,7 +19,6 @@ #define PIN_BASE NR_AIC_IRQS #define MAX_GPIO_BANKS 5 -#define NR_BUILTIN_GPIO (PIN_BASE + (MAX_GPIO_BANKS * 32)) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ diff --git a/trunk/arch/arm/mach-at91/pm.h b/trunk/arch/arm/mach-at91/pm.h index 8c87d0c1b8f8..08322c44df1a 100644 --- a/trunk/arch/arm/mach-at91/pm.h +++ b/trunk/arch/arm/mach-at91/pm.h @@ -30,50 +30,14 @@ static inline u32 sdram_selfrefresh_enable(void) { u32 saved_lpr, lpr; - saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); + saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR); lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; - at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); + at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) - -#elif defined(CONFIG_ARCH_AT91SAM9G45) -#include - -/* We manage both DDRAM/SDRAM controllers, we need more than one value to - * remember. - */ -static u32 saved_lpr1; - -static inline u32 sdram_selfrefresh_enable(void) -{ - /* Those tow values allow us to delay self-refresh activation - * to the maximum. */ - u32 lpr0, lpr1; - u32 saved_lpr0; - - saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); - lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; - lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - - saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); - lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; - lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - - /* self-refresh mode now */ - at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); - at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); - - return saved_lpr0; -} - -#define sdram_selfrefresh_disable(saved_lpr0) \ - do { \ - at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ - at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ - } while (0) +#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr) #else #include @@ -83,6 +47,7 @@ static inline u32 sdram_selfrefresh_enable(void) * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; * handle those cases both here and in the Suspend-To-RAM support. */ +#define AT91_SDRAMC AT91_SDRAMC0 #warning Assuming EB1 SDRAM controller is *NOT* used #endif @@ -90,13 +55,13 @@ static inline u32 sdram_selfrefresh_enable(void) { u32 saved_lpr, lpr; - saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR); + saved_lpr = at91_sys_read(AT91_SDRAMC_LPR); lpr = saved_lpr & ~AT91_SDRAMC_LPCB; - at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); + at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) +#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) #endif diff --git a/trunk/arch/arm/mach-at91/pm_slowclock.S b/trunk/arch/arm/mach-at91/pm_slowclock.S index b6b00a1f6125..9c5b48e68a71 100644 --- a/trunk/arch/arm/mach-at91/pm_slowclock.S +++ b/trunk/arch/arm/mach-at91/pm_slowclock.S @@ -16,12 +16,10 @@ #include #include -#if defined(CONFIG_ARCH_AT91RM9200) +#ifdef CONFIG_ARCH_AT91RM9200 #include #elif defined(CONFIG_ARCH_AT91CAP9) #include -#elif defined(CONFIG_ARCH_AT91SAM9G45) -#include #else #include #endif @@ -32,6 +30,7 @@ * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; * handle those cases both here and in the Suspend-To-RAM support. */ +#define AT91_SDRAMC AT91_SDRAMC0 #warning Assuming EB1 SDRAM controller is *NOT* used #endif @@ -114,14 +113,12 @@ ENTRY(at91_slow_clock) /* * Register usage: * R1 = Base address of AT91_PMC - * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) + * R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200) * R3 = temporary register * R4 = temporary register - * R5 = Base address of second RAM Controller or 0 if not present */ ldr r1, .at91_va_base_pmc ldr r2, .at91_va_base_sdramc - ldr r5, .at91_va_base_ramc1 /* Drain write buffer */ mcr p15, 0, r0, c7, c10, 4 @@ -130,33 +127,20 @@ ENTRY(at91_slow_clock) /* Put SDRAM in self-refresh mode */ mov r3, #1 str r3, [r2, #AT91_SDRAMC_SRR] -#elif defined(CONFIG_ARCH_AT91CAP9) \ - || defined(CONFIG_ARCH_AT91SAM9G45) - - /* prepare for DDRAM self-refresh mode */ - ldr r3, [r2, #AT91_DDRSDRC_LPR] +#elif defined(CONFIG_ARCH_AT91CAP9) + /* Enable SDRAM self-refresh mode */ + ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] str r3, .saved_sam9_lpr - bic r3, #AT91_DDRSDRC_LPCB - orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH - - /* figure out if we use the second ram controller */ - cmp r5, #0 - ldrne r4, [r5, #AT91_DDRSDRC_LPR] - strne r4, .saved_sam9_lpr1 - bicne r4, #AT91_DDRSDRC_LPCB - orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH - - /* Enable DDRAM self-refresh mode */ - str r3, [r2, #AT91_DDRSDRC_LPR] - strne r4, [r5, #AT91_DDRSDRC_LPR] + + mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH + str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] #else /* Enable SDRAM self-refresh mode */ - ldr r3, [r2, #AT91_SDRAMC_LPR] + ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] str r3, .saved_sam9_lpr - bic r3, #AT91_SDRAMC_LPCB - orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH - str r3, [r2, #AT91_SDRAMC_LPR] + mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH + str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] #endif /* Save Master clock setting */ @@ -263,21 +247,14 @@ ENTRY(at91_slow_clock) #ifdef CONFIG_ARCH_AT91RM9200 /* Do nothing - self-refresh is automatically disabled. */ -#elif defined(CONFIG_ARCH_AT91CAP9) \ - || defined(CONFIG_ARCH_AT91SAM9G45) - /* Restore LPR on AT91 with DDRAM */ +#elif defined(CONFIG_ARCH_AT91CAP9) + /* Restore LPR on AT91CAP9 */ ldr r3, .saved_sam9_lpr - str r3, [r2, #AT91_DDRSDRC_LPR] - - /* if we use the second ram controller */ - cmp r5, #0 - ldrne r4, .saved_sam9_lpr1 - strne r4, [r5, #AT91_DDRSDRC_LPR] - + str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] #else - /* Restore LPR on AT91 with SDRAM */ + /* Restore LPR on AT91SAM9 */ ldr r3, .saved_sam9_lpr - str r3, [r2, #AT91_SDRAMC_LPR] + str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] #endif /* Restore registers, and return */ @@ -296,29 +273,18 @@ ENTRY(at91_slow_clock) .saved_sam9_lpr: .word 0 -.saved_sam9_lpr1: - .word 0 - .at91_va_base_pmc: .word AT91_VA_BASE_SYS + AT91_PMC #ifdef CONFIG_ARCH_AT91RM9200 .at91_va_base_sdramc: .word AT91_VA_BASE_SYS -#elif defined(CONFIG_ARCH_AT91CAP9) \ - || defined(CONFIG_ARCH_AT91SAM9G45) +#elif defined(CONFIG_ARCH_AT91CAP9) .at91_va_base_sdramc: - .word AT91_VA_BASE_SYS + AT91_DDRSDRC0 + .word AT91_VA_BASE_SYS + AT91_DDRSDRC #else .at91_va_base_sdramc: - .word AT91_VA_BASE_SYS + AT91_SDRAMC0 -#endif - -.at91_va_base_ramc1: -#if defined(CONFIG_ARCH_AT91SAM9G45) - .word AT91_VA_BASE_SYS + AT91_DDRSDRC1 -#else - .word 0 + .word AT91_VA_BASE_SYS + AT91_SDRAMC #endif ENTRY(at91_slow_clock_sz) diff --git a/trunk/arch/arm/mach-bcmring/core.c b/trunk/arch/arm/mach-bcmring/core.c index d3f959e92b2d..72e405df0fb0 100644 --- a/trunk/arch/arm/mach-bcmring/core.c +++ b/trunk/arch/arm/mach-bcmring/core.c @@ -91,23 +91,14 @@ static struct clk uart_clk = { .parent = &pll1_clk, }; -static struct clk dummy_apb_pclk = { - .name = "BUSCLK", - .type = CLK_TYPE_PRIMARY, - .mode = CLK_MODE_XTAL, -}; - static struct clk_lookup lookups[] = { - { /* Bus clock */ - .con_id = "apb_pclk", - .clk = &dummy_apb_pclk, - }, { /* UART0 */ - .dev_id = "uarta", - .clk = &uart_clk, - }, { /* UART1 */ - .dev_id = "uartb", - .clk = &uart_clk, - } + { /* UART0 */ + .dev_id = "uarta", + .clk = &uart_clk, + }, { /* UART1 */ + .dev_id = "uartb", + .clk = &uart_clk, + } }; static struct amba_device *amba_devs[] __initdata = { diff --git a/trunk/arch/arm/mach-clps711x/Kconfig b/trunk/arch/arm/mach-clps711x/Kconfig index eb34bd1251d4..dbaae5f746a1 100644 --- a/trunk/arch/arm/mach-clps711x/Kconfig +++ b/trunk/arch/arm/mach-clps711x/Kconfig @@ -30,6 +30,7 @@ config ARCH_CLEP7312 config ARCH_EDB7211 bool "EDB7211" select ISA + select ARCH_DISCONTIGMEM_ENABLE select ARCH_SPARSEMEM_ENABLE select ARCH_SELECT_MEMORY_MODEL help diff --git a/trunk/arch/arm/mach-clps711x/clep7312.c b/trunk/arch/arm/mach-clps711x/clep7312.c index 3c3bf45039ff..09fb57e45213 100644 --- a/trunk/arch/arm/mach-clps711x/clep7312.c +++ b/trunk/arch/arm/mach-clps711x/clep7312.c @@ -32,6 +32,7 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags, mi->nr_banks=1; mi->bank[0].start = 0xc0000000; mi->bank[0].size = 0x01000000; + mi->bank[0].node = 0; } diff --git a/trunk/arch/arm/mach-clps711x/edb7211-arch.c b/trunk/arch/arm/mach-clps711x/edb7211-arch.c index 4a7a2322979a..dc81cc68595d 100644 --- a/trunk/arch/arm/mach-clps711x/edb7211-arch.c +++ b/trunk/arch/arm/mach-clps711x/edb7211-arch.c @@ -18,7 +18,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include -#include #include #include @@ -30,12 +29,6 @@ extern void edb7211_map_io(void); -/* Reserve screen memory region at the start of main system memory. */ -static void __init edb7211_reserve(void) -{ - memblock_reserve(PHYS_OFFSET, 0x00020000); -} - static void __init fixup_edb7211(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) @@ -50,8 +43,10 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags, */ mi->bank[0].start = 0xc0000000; mi->bank[0].size = 8*1024*1024; + mi->bank[0].node = 0; mi->bank[1].start = 0xc1000000; mi->bank[1].size = 8*1024*1024; + mi->bank[1].node = 1; mi->nr_banks = 2; } @@ -62,7 +57,6 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") .boot_params = 0xc0020100, /* 0xc0000000 - 0xc001ffff can be video RAM */ .fixup = fixup_edb7211, .map_io = edb7211_map_io, - .reserve = edb7211_reserve, .init_irq = clps711x_init_irq, .timer = &clps711x_timer, MACHINE_END diff --git a/trunk/arch/arm/mach-clps711x/fortunet.c b/trunk/arch/arm/mach-clps711x/fortunet.c index a696099aa4f8..7430e4049d87 100644 --- a/trunk/arch/arm/mach-clps711x/fortunet.c +++ b/trunk/arch/arm/mach-clps711x/fortunet.c @@ -39,6 +39,7 @@ struct meminfo memmap = { { .start = 0xC0000000, .size = 0x01000000, + .node = 0 }, }, }; diff --git a/trunk/arch/arm/mach-clps711x/include/mach/memory.h b/trunk/arch/arm/mach-clps711x/include/mach/memory.h index f45c8e892cb5..f70d52be48a2 100644 --- a/trunk/arch/arm/mach-clps711x/include/mach/memory.h +++ b/trunk/arch/arm/mach-clps711x/include/mach/memory.h @@ -20,6 +20,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H + /* * Physical DRAM offset. */ @@ -71,6 +72,7 @@ * node 2: 0xd0000000 - 0xd7ffffff * node 3: 0xd8000000 - 0xdfffffff */ +#define NODE_MEM_SIZE_BITS 24 #define SECTION_SIZE_BITS 24 #define MAX_PHYSMEM_BITS 32 diff --git a/trunk/arch/arm/mach-cns3xxx/Makefile b/trunk/arch/arm/mach-cns3xxx/Makefile index 11033f1c2e23..427507a2d696 100644 --- a/trunk/arch/arm/mach-cns3xxx/Makefile +++ b/trunk/arch/arm/mach-cns3xxx/Makefile @@ -1,3 +1,2 @@ -obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o -obj-$(CONFIG_PCI) += pcie.o +obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/trunk/arch/arm/mach-cns3xxx/cns3420vb.c b/trunk/arch/arm/mach-cns3xxx/cns3420vb.c index 9df8391fd78a..2e30c8288740 100644 --- a/trunk/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/trunk/arch/arm/mach-cns3xxx/cns3420vb.c @@ -32,7 +32,6 @@ #include #include #include "core.h" -#include "devices.h" /* * NOR Flash @@ -118,9 +117,6 @@ static void __init cns3420_init(void) { platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); - cns3xxx_ahci_init(); - cns3xxx_sdhci_init(); - pm_power_off = cns3xxx_power_off; } diff --git a/trunk/arch/arm/mach-cns3xxx/devices.c b/trunk/arch/arm/mach-cns3xxx/devices.c deleted file mode 100644 index 50b4d31c27c0..000000000000 --- a/trunk/arch/arm/mach-cns3xxx/devices.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * CNS3xxx common devices - * - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "core.h" -#include "devices.h" - -/* - * AHCI - */ -static struct resource cns3xxx_ahci_resource[] = { - [0] = { - .start = CNS3XXX_SATA2_BASE, - .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_SATA, - .end = IRQ_CNS3XXX_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device cns3xxx_ahci_pdev = { - .name = "ahci", - .id = 0, - .resource = cns3xxx_ahci_resource, - .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource), - .dev = { - .dma_mask = &cns3xxx_ahci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init cns3xxx_ahci_init(void) -{ - u32 tmp; - - tmp = __raw_readl(MISC_SATA_POWER_MODE); - tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ - tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ - __raw_writel(tmp, MISC_SATA_POWER_MODE); - - /* Enable SATA PHY */ - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); - - /* Enable SATA Clock */ - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); - - /* De-Asscer SATA Reset */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); - - platform_device_register(&cns3xxx_ahci_pdev); -} - -/* - * SDHCI - */ -static struct resource cns3xxx_sdhci_resources[] = { - [0] = { - .start = CNS3XXX_SDIO_BASE, - .end = CNS3XXX_SDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_SDIO, - .end = IRQ_CNS3XXX_SDIO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device cns3xxx_sdhci_pdev = { - .name = "sdhci-cns3xxx", - .id = 0, - .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources), - .resource = cns3xxx_sdhci_resources, -}; - -void __init cns3xxx_sdhci_init(void) -{ - u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014); - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ - gpioa_pins |= 0x1fff0004; - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); - - platform_device_register(&cns3xxx_sdhci_pdev); -} diff --git a/trunk/arch/arm/mach-cns3xxx/devices.h b/trunk/arch/arm/mach-cns3xxx/devices.h deleted file mode 100644 index 27e15a10aa85..000000000000 --- a/trunk/arch/arm/mach-cns3xxx/devices.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * CNS3xxx common devices - * - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#ifndef __CNS3XXX_DEVICES_H_ -#define __CNS3XXX_DEVICES_H_ - -void __init cns3xxx_ahci_init(void); -void __init cns3xxx_sdhci_init(void); - -#endif /* __CNS3XXX_DEVICES_H_ */ diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 6dbce13771ca..8a2f5a21d4ee 100644 --- a/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h @@ -247,36 +247,37 @@ * Misc block */ #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) - -#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) -#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) -#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) -#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) -#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) -#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) -#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) -#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) -#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) -#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) -#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) -#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) -#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) -#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) -#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) -#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) -#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) -#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) - -#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) - -#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) -#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) -#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) -#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) -#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) -#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) +#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset)))) + +#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00) +#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04) +#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08) +#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C) +#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10) +#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14) +#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20) +#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24) +#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28) +#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C) +#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30) +#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34) +#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40) +#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44) +#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48) +#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C) +#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50) +#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54) + +#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310) + +#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800) +#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804) +#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808) +#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c) +#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810) +#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814) #define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) #define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) @@ -299,21 +300,21 @@ /* * Power management and clock control */ -#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) - -#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) -#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) -#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) -#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) -#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) -#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) -#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) -#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) -#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) -#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) -#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) -#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) -#define PM_CSR_REG PMU_MEM_MAP(0x030) +#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset)))) + +#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000) +#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004) +#define PM_HS_CFG_REG PMU_REG_VALUE(0x008) +#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C) +#define PM_PWR_STA_REG PMU_REG_VALUE(0x010) +#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014) +#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018) +#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C) +#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020) +#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024) +#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028) +#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C) +#define PM_CSR_REG PMU_REG_VALUE(0x030) /* PM_CLK_GATE_REG */ #define PM_CLK_GATE_REG_OFFSET_SDIO (25) diff --git a/trunk/arch/arm/mach-cns3xxx/pcie.c b/trunk/arch/arm/mach-cns3xxx/pcie.c deleted file mode 100644 index 38088c36936c..000000000000 --- a/trunk/arch/arm/mach-cns3xxx/pcie.c +++ /dev/null @@ -1,389 +0,0 @@ -/* - * PCI-E support for CNS3xxx - * - * Copyright 2008 Cavium Networks - * Richard Liu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "core.h" - -enum cns3xxx_access_type { - CNS3XXX_HOST_TYPE = 0, - CNS3XXX_CFG0_TYPE, - CNS3XXX_CFG1_TYPE, - CNS3XXX_NUM_ACCESS_TYPES, -}; - -struct cns3xxx_pcie { - struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES]; - unsigned int irqs[2]; - struct resource res_io; - struct resource res_mem; - struct hw_pci hw_pci; - - bool linked; -}; - -static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */ - -static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata) -{ - struct pci_sys_data *root = sysdata; - - return &cns3xxx_pcie[root->domain]; -} - -static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev) -{ - return sysdata_to_cnspci(dev->sysdata); -} - -static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus) -{ - return sysdata_to_cnspci(bus->sysdata); -} - -static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus, - unsigned int devfn, int where) -{ - struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); - int busno = bus->number; - int slot = PCI_SLOT(devfn); - int offset; - enum cns3xxx_access_type type; - void __iomem *base; - - /* If there is no link, just show the CNS PCI bridge. */ - if (!cnspci->linked && (busno > 0 || slot > 0)) - return NULL; - - /* - * The CNS PCI bridge doesn't fit into the PCI hierarchy, though - * we still want to access it. For this to work, we must place - * the first device on the same bus as the CNS PCI bridge. - */ - if (busno == 0) { - if (slot > 1) - return NULL; - type = slot; - } else { - type = CNS3XXX_CFG1_TYPE; - } - - base = (void __iomem *)cnspci->cfg_bases[type].virtual; - offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc); - - return base + offset; -} - -static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 v; - void __iomem *base; - u32 mask = (0x1ull << (size * 8)) - 1; - int shift = (where % 4) * 8; - - base = cns3xxx_pci_cfg_base(bus, devfn, where); - if (!base) { - *val = 0xffffffff; - return PCIBIOS_SUCCESSFUL; - } - - v = __raw_readl(base); - - if (bus->number == 0 && devfn == 0 && - (where & 0xffc) == PCI_CLASS_REVISION) { - /* - * RC's class is 0xb, but Linux PCI driver needs 0x604 - * for a PCIe bridge. So we must fixup the class code - * to 0x604 here. - */ - v &= 0xff; - v |= 0x604 << 16; - } - - *val = (v >> shift) & mask; - - return PCIBIOS_SUCCESSFUL; -} - -static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 v; - void __iomem *base; - u32 mask = (0x1ull << (size * 8)) - 1; - int shift = (where % 4) * 8; - - base = cns3xxx_pci_cfg_base(bus, devfn, where); - if (!base) - return PCIBIOS_SUCCESSFUL; - - v = __raw_readl(base); - - v &= ~(mask << shift); - v |= (val & mask) << shift; - - __raw_writel(v, base); - - return PCIBIOS_SUCCESSFUL; -} - -static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys) -{ - struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys); - struct resource *res_io = &cnspci->res_io; - struct resource *res_mem = &cnspci->res_mem; - struct resource **sysres = sys->resource; - - BUG_ON(request_resource(&iomem_resource, res_io) || - request_resource(&iomem_resource, res_mem)); - - sysres[0] = res_io; - sysres[1] = res_mem; - - return 1; -} - -static struct pci_ops cns3xxx_pcie_ops = { - .read = cns3xxx_pci_read_config, - .write = cns3xxx_pci_write_config, -}; - -static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys); -} - -static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); - int irq = cnspci->irqs[slot]; - - pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", - pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), slot, pin, irq); - - return irq; -} - -static struct cns3xxx_pcie cns3xxx_pcie[] = { - [0] = { - .cfg_bases = { - [CNS3XXX_HOST_TYPE] = { - .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - [CNS3XXX_CFG0_TYPE] = { - .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - [CNS3XXX_CFG1_TYPE] = { - .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - }, - .res_io = { - .name = "PCIe0 I/O space", - .start = CNS3XXX_PCIE0_IO_BASE, - .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1, - .flags = IORESOURCE_IO, - }, - .res_mem = { - .name = "PCIe0 non-prefetchable", - .start = CNS3XXX_PCIE0_MEM_BASE, - .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, - .hw_pci = { - .domain = 0, - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = cns3xxx_pci_setup, - .scan = cns3xxx_pci_scan_bus, - .map_irq = cns3xxx_pcie_map_irq, - }, - }, - [1] = { - .cfg_bases = { - [CNS3XXX_HOST_TYPE] = { - .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - [CNS3XXX_CFG0_TYPE] = { - .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - [CNS3XXX_CFG1_TYPE] = { - .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - }, - .res_io = { - .name = "PCIe1 I/O space", - .start = CNS3XXX_PCIE1_IO_BASE, - .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1, - .flags = IORESOURCE_IO, - }, - .res_mem = { - .name = "PCIe1 non-prefetchable", - .start = CNS3XXX_PCIE1_MEM_BASE, - .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, - .hw_pci = { - .domain = 1, - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = cns3xxx_pci_setup, - .scan = cns3xxx_pci_scan_bus, - .map_irq = cns3xxx_pcie_map_irq, - }, - }, -}; - -static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci) -{ - int port = cnspci->hw_pci.domain; - u32 reg; - unsigned long time; - - reg = __raw_readl(MISC_PCIE_CTRL(port)); - /* - * Enable Application Request to 1, it will exit L1 automatically, - * but when chip back, it will use another clock, still can use 0x1. - */ - reg |= 0x3; - __raw_writel(reg, MISC_PCIE_CTRL(port)); - - pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port); - pr_info("PCIe: Port[%d] Check data link layer...", port); - - time = jiffies; - while (1) { - reg = __raw_readl(MISC_PCIE_PM_DEBUG(port)); - if (reg & 0x1) { - pr_info("Link up.\n"); - cnspci->linked = 1; - break; - } else if (time_after(jiffies, time + 50)) { - pr_info("Device not found.\n"); - break; - } - } -} - -static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) -{ - int port = cnspci->hw_pci.domain; - struct pci_sys_data sd = { - .domain = port, - }; - struct pci_bus bus = { - .number = 0, - .ops = &cns3xxx_pcie_ops, - .sysdata = &sd, - }; - u32 io_base = cnspci->res_io.start >> 16; - u32 mem_base = cnspci->res_mem.start >> 16; - u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn; - u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn; - u32 devfn = 0; - u8 tmp8; - u16 pos; - u16 dc; - - host_base = (__pfn_to_phys(host_base) - 1) >> 16; - cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16; - - pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0); - pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1); - pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1); - - pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8); - pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8); - pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8); - - pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base); - pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base); - pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base); - pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base); - - if (!cnspci->linked) - return; - - /* Set Device Max_Read_Request_Size to 128 byte */ - devfn = PCI_DEVFN(1, 0); - pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP); - pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); - dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */ - pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc); - pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); - if (!(dc & (0x3 << 12))) - pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n"); - - /* Disable PCIe0 Interrupt Mask INTA to INTD */ - __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port)); -} - -static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, - struct pt_regs *regs) -{ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - return 0; -} - -static int __init cns3xxx_pcie_init(void) -{ - int i; - - hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, - "imprecise external abort"); - - for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { - iotable_init(cns3xxx_pcie[i].cfg_bases, - ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); - cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); - cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); - cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); - pci_common_init(&cns3xxx_pcie[i].hw_pci); - } - - pci_assign_unassigned_resources(); - - return 0; -} -device_initcall(cns3xxx_pcie_init); diff --git a/trunk/arch/arm/mach-cns3xxx/pm.c b/trunk/arch/arm/mach-cns3xxx/pm.c index 38e44706feab..725e1a4fc231 100644 --- a/trunk/arch/arm/mach-cns3xxx/pm.c +++ b/trunk/arch/arm/mach-cns3xxx/pm.c @@ -6,25 +6,18 @@ * published by the Free Software Foundation. */ -#include #include #include #include void cns3xxx_pwr_clk_en(unsigned int block) { - u32 reg = __raw_readl(PM_CLK_GATE_REG); - - reg |= (block & PM_CLK_GATE_REG_MASK); - __raw_writel(reg, PM_CLK_GATE_REG); + PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK); } void cns3xxx_pwr_power_up(unsigned int block) { - u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); - - reg &= ~(block & CNS3XXX_PWR_PLL_ALL); - __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); + PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL); /* Wait for 300us for the PLL output clock locked. */ udelay(300); @@ -32,29 +25,22 @@ void cns3xxx_pwr_power_up(unsigned int block) void cns3xxx_pwr_power_down(unsigned int block) { - u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); - /* write '1' to power down */ - reg |= (block & CNS3XXX_PWR_PLL_ALL); - __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); + PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL); }; static void cns3xxx_pwr_soft_rst_force(unsigned int block) { - u32 reg = __raw_readl(PM_SOFT_RST_REG); - /* * bit 0, 28, 29 => program low to reset, * the other else program low and then high */ if (block & 0x30000001) { - reg &= ~(block & PM_SOFT_RST_REG_MASK); + PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); } else { - reg &= ~(block & PM_SOFT_RST_REG_MASK); - reg |= (block & PM_SOFT_RST_REG_MASK); + PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); + PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK); } - - __raw_writel(reg, PM_SOFT_RST_REG); } void cns3xxx_pwr_soft_rst(unsigned int block) @@ -87,13 +73,12 @@ void arch_reset(char mode, const char *cmd) */ int cns3xxx_cpu_clock(void) { - u32 reg = __raw_readl(PM_CLK_CTRL_REG); int cpu; int cpu_sel; int div_sel; - cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; - div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; + cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; + div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel; diff --git a/trunk/arch/arm/mach-davinci/include/mach/memory.h b/trunk/arch/arm/mach-davinci/include/mach/memory.h index 22eb97c1c30b..a91edfb8beea 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/memory.h +++ b/trunk/arch/arm/mach-davinci/include/mach/memory.h @@ -48,16 +48,19 @@ * below 128M */ static inline void -__arch_adjust_zones(unsigned long *size, unsigned long *holes) +__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) { unsigned int sz = (128<<20) >> PAGE_SHIFT; + if (node != 0) + sz = 0; + size[1] = size[0] - sz; size[0] = sz; } -#define arch_adjust_zones(zone_size, holes) \ - if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes) +#define arch_adjust_zones(node, zone_size, holes) \ + if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) #define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20)) diff --git a/trunk/arch/arm/mach-dove/common.c b/trunk/arch/arm/mach-dove/common.c index f7a12586a1f5..5da2cf402c81 100644 --- a/trunk/arch/arm/mach-dove/common.c +++ b/trunk/arch/arm/mach-dove/common.c @@ -752,67 +752,6 @@ void __init dove_xor1_init(void) platform_device_register(&dove_xor11_channel); } -/***************************************************************************** - * SDIO - ****************************************************************************/ -static u64 sdio_dmamask = DMA_BIT_MASK(32); - -static struct resource dove_sdio0_resources[] = { - { - .start = DOVE_SDIO0_PHYS_BASE, - .end = DOVE_SDIO0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_SDIO0, - .end = IRQ_DOVE_SDIO0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_sdio0 = { - .name = "sdhci-mv", - .id = 0, - .dev = { - .dma_mask = &sdio_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = dove_sdio0_resources, - .num_resources = ARRAY_SIZE(dove_sdio0_resources), -}; - -void __init dove_sdio0_init(void) -{ - platform_device_register(&dove_sdio0); -} - -static struct resource dove_sdio1_resources[] = { - { - .start = DOVE_SDIO1_PHYS_BASE, - .end = DOVE_SDIO1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_SDIO1, - .end = IRQ_DOVE_SDIO1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_sdio1 = { - .name = "sdhci-mv", - .id = 1, - .dev = { - .dma_mask = &sdio_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = dove_sdio1_resources, - .num_resources = ARRAY_SIZE(dove_sdio1_resources), -}; - -void __init dove_sdio1_init(void) -{ - platform_device_register(&dove_sdio1); -} - void __init dove_init(void) { int tclk; diff --git a/trunk/arch/arm/mach-dove/common.h b/trunk/arch/arm/mach-dove/common.h index a51517c3fe76..b29e8937de4f 100644 --- a/trunk/arch/arm/mach-dove/common.h +++ b/trunk/arch/arm/mach-dove/common.h @@ -36,7 +36,5 @@ void dove_uart3_init(void); void dove_spi0_init(void); void dove_spi1_init(void); void dove_i2c_init(void); -void dove_sdio0_init(void); -void dove_sdio1_init(void); #endif diff --git a/trunk/arch/arm/mach-dove/dove-db-setup.c b/trunk/arch/arm/mach-dove/dove-db-setup.c index bef70460fbc6..f2971b745224 100644 --- a/trunk/arch/arm/mach-dove/dove-db-setup.c +++ b/trunk/arch/arm/mach-dove/dove-db-setup.c @@ -82,8 +82,6 @@ static void __init dove_db_init(void) dove_ehci0_init(); dove_ehci1_init(); dove_sata_init(&dove_db_sata_data); - dove_sdio0_init(); - dove_sdio1_init(); dove_spi0_init(); dove_spi1_init(); dove_uart0_init(); diff --git a/trunk/arch/arm/mach-ep93xx/adssphere.c b/trunk/arch/arm/mach-ep93xx/adssphere.c index f744f676783f..3a1a855bfdca 100644 --- a/trunk/arch/arm/mach-ep93xx/adssphere.c +++ b/trunk/arch/arm/mach-ep93xx/adssphere.c @@ -13,6 +13,7 @@ #include #include #include +#include #include @@ -20,6 +21,26 @@ #include +static struct physmap_flash_data adssphere_flash_data = { + .width = 4, +}; + +static struct resource adssphere_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device adssphere_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &adssphere_flash_data, + }, + .num_resources = 1, + .resource = &adssphere_flash_resource, +}; + static struct ep93xx_eth_data __initdata adssphere_eth_data = { .phy_id = 1, }; @@ -27,7 +48,8 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = { static void __init adssphere_init_machine(void) { ep93xx_init_devices(); - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); + platform_device_register(&adssphere_flash); + ep93xx_register_eth(&adssphere_eth_data, 1); } diff --git a/trunk/arch/arm/mach-ep93xx/clock.c b/trunk/arch/arm/mach-ep93xx/clock.c index 7f3039761d91..e29bdef9b2e2 100644 --- a/trunk/arch/arm/mach-ep93xx/clock.c +++ b/trunk/arch/arm/mach-ep93xx/clock.c @@ -185,7 +185,7 @@ static struct clk_lookup clocks[] = { INIT_CK(NULL, "pll1", &clk_pll1), INIT_CK(NULL, "fclk", &clk_f), INIT_CK(NULL, "hclk", &clk_h), - INIT_CK(NULL, "apb_pclk", &clk_p), + INIT_CK(NULL, "pclk", &clk_p), INIT_CK(NULL, "pll2", &clk_pll2), INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), INIT_CK("ep93xx-keypad", NULL, &clk_keypad), diff --git a/trunk/arch/arm/mach-ep93xx/core.c b/trunk/arch/arm/mach-ep93xx/core.c index 8e37a045188c..9092677f63eb 100644 --- a/trunk/arch/arm/mach-ep93xx/core.c +++ b/trunk/arch/arm/mach-ep93xx/core.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -216,8 +215,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) spin_lock_irqsave(&syscon_swlock, flags); val = __raw_readl(EP93XX_SYSCON_DEVCFG); - val &= ~clear_bits; val |= set_bits; + val &= ~clear_bits; __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); __raw_writel(val, EP93XX_SYSCON_DEVCFG); @@ -348,43 +347,6 @@ static struct platform_device ep93xx_ohci_device = { }; -/************************************************************************* - * EP93xx physmap'ed flash - *************************************************************************/ -static struct physmap_flash_data ep93xx_flash_data; - -static struct resource ep93xx_flash_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ep93xx_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ep93xx_flash_data, - }, - .num_resources = 1, - .resource = &ep93xx_flash_resource, -}; - -/** - * ep93xx_register_flash() - Register the external flash device. - * @width: bank width in octets - * @start: resource start address - * @size: resource size - */ -void __init ep93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size) -{ - ep93xx_flash_data.width = width; - - ep93xx_flash_resource.start = start; - ep93xx_flash_resource.end = start + size - 1; - - platform_device_register(&ep93xx_flash); -} - - /************************************************************************* * EP93xx ethernet peripheral handling *************************************************************************/ @@ -658,11 +620,6 @@ static struct platform_device ep93xx_fb_device = { .resource = ep93xx_fb_resource, }; -static struct platform_device ep93xx_bl_device = { - .name = "ep93xx-bl", - .id = -1, -}; - /** * ep93xx_register_fb - Register the framebuffer platform device. * @data: platform specific framebuffer configuration (__initdata) @@ -671,7 +628,6 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) { ep93xxfb_data = *data; platform_device_register(&ep93xx_fb_device); - platform_device_register(&ep93xx_bl_device); } diff --git a/trunk/arch/arm/mach-ep93xx/edb93xx.c b/trunk/arch/arm/mach-ep93xx/edb93xx.c index c2ce9034ba87..3884182cd362 100644 --- a/trunk/arch/arm/mach-ep93xx/edb93xx.c +++ b/trunk/arch/arm/mach-ep93xx/edb93xx.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -37,13 +38,39 @@ #include +static struct physmap_flash_data edb93xx_flash_data; + +static struct resource edb93xx_flash_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb93xx_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb93xx_flash_data, + }, + .num_resources = 1, + .resource = &edb93xx_flash_resource, +}; + +static void __init __edb93xx_register_flash(unsigned int width, + resource_size_t start, resource_size_t size) +{ + edb93xx_flash_data.width = width; + edb93xx_flash_resource.start = start; + edb93xx_flash_resource.end = start + size - 1; + + platform_device_register(&edb93xx_flash); +} + static void __init edb93xx_register_flash(void) { if (machine_is_edb9307() || machine_is_edb9312() || machine_is_edb9315()) { - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); + __edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); } else { - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); + __edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); } } diff --git a/trunk/arch/arm/mach-ep93xx/gesbc9312.c b/trunk/arch/arm/mach-ep93xx/gesbc9312.c index d97168c0ba33..a809618e9f05 100644 --- a/trunk/arch/arm/mach-ep93xx/gesbc9312.c +++ b/trunk/arch/arm/mach-ep93xx/gesbc9312.c @@ -13,6 +13,7 @@ #include #include #include +#include #include @@ -20,6 +21,26 @@ #include +static struct physmap_flash_data gesbc9312_flash_data = { + .width = 4, +}; + +static struct resource gesbc9312_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gesbc9312_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &gesbc9312_flash_data, + }, + .num_resources = 1, + .resource = &gesbc9312_flash_resource, +}; + static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { .phy_id = 1, }; @@ -27,7 +48,8 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { static void __init gesbc9312_init_machine(void) { ep93xx_init_devices(); - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M); + platform_device_register(&gesbc9312_flash); + ep93xx_register_eth(&gesbc9312_eth_data, 0); } diff --git a/trunk/arch/arm/mach-ep93xx/include/mach/platform.h b/trunk/arch/arm/mach-ep93xx/include/mach/platform.h index a6c09176334c..9a4413dd44bb 100644 --- a/trunk/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/trunk/arch/arm/mach-ep93xx/include/mach/platform.h @@ -43,9 +43,6 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits) unsigned int ep93xx_chip_revision(void); -void ep93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size); - void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); void ep93xx_register_i2c(struct i2c_gpio_platform_data *data, struct i2c_board_info *devices, int num); diff --git a/trunk/arch/arm/mach-ep93xx/micro9.c b/trunk/arch/arm/mach-ep93xx/micro9.c index 2ba776320a82..1cc911b4efa6 100644 --- a/trunk/arch/arm/mach-ep93xx/micro9.c +++ b/trunk/arch/arm/mach-ep93xx/micro9.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -30,6 +31,31 @@ * Micro9-Lite uses a separate MTD map driver for flash support * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1 *************************************************************************/ +static struct physmap_flash_data micro9_flash_data; + +static struct resource micro9_flash_resource = { + .start = EP93XX_CS1_PHYS_BASE, + .end = EP93XX_CS1_PHYS_BASE + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device micro9_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = µ9_flash_data, + }, + .num_resources = 1, + .resource = µ9_flash_resource, +}; + +static void __init __micro9_register_flash(unsigned int width) +{ + micro9_flash_data.width = width; + + platform_device_register(µ9_flash); +} + static unsigned int __init micro9_detect_bootwidth(void) { u32 v; @@ -44,17 +70,10 @@ static unsigned int __init micro9_detect_bootwidth(void) static void __init micro9_register_flash(void) { - unsigned int width; - if (machine_is_micro9()) - width = 4; + __micro9_register_flash(4); else if (machine_is_micro9m() || machine_is_micro9s()) - width = micro9_detect_bootwidth(); - else - width = 0; - - if (width) - ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M); + __micro9_register_flash(micro9_detect_bootwidth()); } diff --git a/trunk/arch/arm/mach-ep93xx/simone.c b/trunk/arch/arm/mach-ep93xx/simone.c index 5dded5884133..388aec95f60e 100644 --- a/trunk/arch/arm/mach-ep93xx/simone.c +++ b/trunk/arch/arm/mach-ep93xx/simone.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,26 @@ #include #include +static struct physmap_flash_data simone_flash_data = { + .width = 2, +}; + +static struct resource simone_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device simone_flash = { + .name = "physmap-flash", + .id = 0, + .num_resources = 1, + .resource = &simone_flash_resource, + .dev = { + .platform_data = &simone_flash_data, + }, +}; + static struct ep93xx_eth_data __initdata simone_eth_data = { .phy_id = 1, }; @@ -56,7 +77,8 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = { static void __init simone_init_machine(void) { ep93xx_init_devices(); - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M); + + platform_device_register(&simone_flash); ep93xx_register_eth(&simone_eth_data, 1); ep93xx_register_fb(&simone_fb_info); ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info, diff --git a/trunk/arch/arm/mach-ep93xx/ts72xx.c b/trunk/arch/arm/mach-ep93xx/ts72xx.c index 93aeab8af705..ae7319e588c7 100644 --- a/trunk/arch/arm/mach-ep93xx/ts72xx.c +++ b/trunk/arch/arm/mach-ep93xx/ts72xx.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -172,13 +173,31 @@ static struct platform_device ts72xx_nand_flash = { }; +/************************************************************************* + * NOR flash (TS-7200 only) + *************************************************************************/ +static struct physmap_flash_data ts72xx_nor_data = { + .width = 2, +}; + +static struct resource ts72xx_nor_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ts72xx_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev.platform_data = &ts72xx_nor_data, + .resource = &ts72xx_nor_resource, + .num_resources = 1, +}; + static void __init ts72xx_register_flash(void) { - /* - * TS7200 has NOR flash all other TS72xx board have NAND flash. - */ if (board_is_ts7200()) { - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); + platform_device_register(&ts72xx_nor_flash); } else { resource_size_t start; diff --git a/trunk/arch/arm/mach-imx/devices-imx1.h b/trunk/arch/arm/mach-imx/devices-imx1.h deleted file mode 100644 index a8d94f078196..000000000000 --- a/trunk/arch/arm/mach-imx/devices-imx1.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include - -#define imx1_add_i2c_imx(pdata) \ - imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata) - -#define imx1_add_imx_uart0(pdata) \ - imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata) -#define imx1_add_imx_uart1(pdata) \ - imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata) diff --git a/trunk/arch/arm/mach-imx/devices-imx21.h b/trunk/arch/arm/mach-imx/devices-imx21.h deleted file mode 100644 index 42788e99d127..000000000000 --- a/trunk/arch/arm/mach-imx/devices-imx21.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include - -#define imx21_add_i2c_imx(pdata) \ - imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata) - -#define imx21_add_imx_uart0(pdata) \ - imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata) -#define imx21_add_imx_uart1(pdata) \ - imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata) -#define imx21_add_imx_uart2(pdata) \ - imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata) -#define imx21_add_imx_uart3(pdata) \ - imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata) - -#define imx21_add_mxc_nand(pdata) \ - imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata) - -#define imx21_add_spi_imx0(pdata) \ - imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata) -#define imx21_add_spi_imx1(pdata) \ - imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata) diff --git a/trunk/arch/arm/mach-imx/devices-imx27.h b/trunk/arch/arm/mach-imx/devices-imx27.h deleted file mode 100644 index 65e7bb7ec2e8..000000000000 --- a/trunk/arch/arm/mach-imx/devices-imx27.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include - -#define imx27_add_i2c_imx0(pdata) \ - imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata) -#define imx27_add_i2c_imx1(pdata) \ - imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata) - -#define imx27_add_imx_uart0(pdata) \ - imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata) -#define imx27_add_imx_uart1(pdata) \ - imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata) -#define imx27_add_imx_uart2(pdata) \ - imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata) -#define imx27_add_imx_uart3(pdata) \ - imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata) -#define imx27_add_imx_uart4(pdata) \ - imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata) -#define imx27_add_imx_uart5(pdata) \ - imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata) - -#define imx27_add_mxc_nand(pdata) \ - imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata) - -#define imx27_add_spi_imx0(pdata) \ - imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata) -#define imx27_add_spi_imx1(pdata) \ - imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata) -#define imx27_add_spi_imx2(pdata) \ - imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata) diff --git a/trunk/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/trunk/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h deleted file mode 100644 index df5f522da6b3..000000000000 --- a/trunk/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __MACH_DMA_MX1_MX2_H__ -#define __MACH_DMA_MX1_MX2_H__ -/* - * Don't use this header in new code, it will go away when all users are - * converted to mach/dma-v1.h - */ - -#include - -#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */ diff --git a/trunk/arch/arm/mach-imx/pm-imx27.c b/trunk/arch/arm/mach-imx/pm-imx27.c deleted file mode 100644 index afc17ce0bb54..000000000000 --- a/trunk/arch/arm/mach-imx/pm-imx27.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * i.MX27 Power Management Routines - * - * Based on Freescale's BSP - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License. - */ - -#include -#include -#include -#include -#include - -static int mx27_suspend_enter(suspend_state_t state) -{ - u32 cscr; - switch (state) { - case PM_SUSPEND_MEM: - /* Clear MPEN and SPEN to disable MPLL/SPLL */ - cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); - cscr &= 0xFFFFFFFC; - __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); - /* Executes WFI */ - arch_idle(); - break; - - default: - return -EINVAL; - } - return 0; -} - -static struct platform_suspend_ops mx27_suspend_ops = { - .enter = mx27_suspend_enter, - .valid = suspend_valid_only_mem, -}; - -static int __init mx27_pm_init(void) -{ - suspend_set_ops(&mx27_suspend_ops); - return 0; -} - -device_initcall(mx27_pm_init); diff --git a/trunk/arch/arm/mach-integrator/common.h b/trunk/arch/arm/mach-integrator/common.h deleted file mode 100644 index 5f96e1518aa9..000000000000 --- a/trunk/arch/arm/mach-integrator/common.h +++ /dev/null @@ -1 +0,0 @@ -void integrator_reserve(void); diff --git a/trunk/arch/arm/mach-integrator/core.c b/trunk/arch/arm/mach-integrator/core.c index 8f4fb6d638f7..b02cfc06e0ae 100644 --- a/trunk/arch/arm/mach-integrator/core.c +++ b/trunk/arch/arm/mach-integrator/core.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -31,7 +30,6 @@ #include #include #include -#include static struct amba_pl010_data integrator_uart_data; @@ -121,13 +119,8 @@ static struct clk uartclk = { .rate = 14745600, }; -static struct clk dummy_apb_pclk; - static struct clk_lookup lookups[] = { - { /* Bus clock */ - .con_id = "apb_pclk", - .clk = &dummy_apb_pclk, - }, { /* UART0 */ + { /* UART0 */ .dev_id = "mb:16", .clk = &uartclk, }, { /* UART1 */ @@ -222,13 +215,3 @@ void cm_control(u32 mask, u32 set) } EXPORT_SYMBOL(cm_control); - -/* - * We need to stop things allocating the low memory; ideally we need a - * better implementation of GFP_DMA which does not assume that DMA-able - * memory starts at zero. - */ -void __init integrator_reserve(void) -{ - memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); -} diff --git a/trunk/arch/arm/mach-integrator/integrator_ap.c b/trunk/arch/arm/mach-integrator/integrator_ap.c index 6ab5a03ab9d8..227cf4d05088 100644 --- a/trunk/arch/arm/mach-integrator/integrator_ap.c +++ b/trunk/arch/arm/mach-integrator/integrator_ap.c @@ -48,8 +48,6 @@ #include #include -#include "common.h" - /* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx * is the (PA >> 12). @@ -504,7 +502,6 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator") .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, .boot_params = 0x00000100, .map_io = ap_map_io, - .reserve = integrator_reserve, .init_irq = ap_init_irq, .timer = &ap_timer, .init_machine = ap_init, diff --git a/trunk/arch/arm/mach-integrator/integrator_cp.c b/trunk/arch/arm/mach-integrator/integrator_cp.c index 05db40e3c4f7..cde57b2b83b5 100644 --- a/trunk/arch/arm/mach-integrator/integrator_cp.c +++ b/trunk/arch/arm/mach-integrator/integrator_cp.c @@ -43,8 +43,6 @@ #include -#include "common.h" - #define INTCP_PA_FLASH_BASE 0x24000000 #define INTCP_FLASH_SIZE SZ_32M @@ -603,7 +601,6 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, .boot_params = 0x00000100, .map_io = intcp_map_io, - .reserve = integrator_reserve, .init_irq = intcp_init_irq, .timer = &cp_timer, .init_machine = intcp_init, diff --git a/trunk/arch/arm/mach-integrator/pci_v3.c b/trunk/arch/arm/mach-integrator/pci_v3.c index 6467d99fa2ee..9cef0590d5aa 100644 --- a/trunk/arch/arm/mach-integrator/pci_v3.c +++ b/trunk/arch/arm/mach-integrator/pci_v3.c @@ -505,10 +505,10 @@ void __init pci_v3_preinit(void) /* * Hook in our fault handler for PCI errors */ - hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); - hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); - hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); - hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); + hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch"); + hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch"); + hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch"); + hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch"); spin_lock_irqsave(&v3_lock, flags); diff --git a/trunk/arch/arm/mach-iop13xx/include/mach/memory.h b/trunk/arch/arm/mach-iop13xx/include/mach/memory.h index 7415e4338651..25b1da9a5035 100644 --- a/trunk/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/trunk/arch/arm/mach-iop13xx/include/mach/memory.h @@ -69,4 +69,6 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) #endif /* CONFIG_ARCH_IOP13XX */ #endif /* !ASSEMBLY */ +#define PFN_TO_NID(addr) (0) + #endif diff --git a/trunk/arch/arm/mach-iop13xx/pci.c b/trunk/arch/arm/mach-iop13xx/pci.c index 773ea0c95b9f..6d5a90813d31 100644 --- a/trunk/arch/arm/mach-iop13xx/pci.c +++ b/trunk/arch/arm/mach-iop13xx/pci.c @@ -987,7 +987,7 @@ void __init iop13xx_pci_init(void) iop13xx_atux_setup(); } - hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0, + hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, "imprecise external abort"); } diff --git a/trunk/arch/arm/mach-ixp2000/pci.c b/trunk/arch/arm/mach-ixp2000/pci.c index f797c5f538b0..90771cad06f8 100644 --- a/trunk/arch/arm/mach-ixp2000/pci.c +++ b/trunk/arch/arm/mach-ixp2000/pci.c @@ -209,7 +209,7 @@ ixp2000_pci_preinit(void) "the needed workaround has not been configured in"); #endif - hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0, + hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, "PCI config cycle to non-existent device"); } diff --git a/trunk/arch/arm/mach-ixp23xx/pci.c b/trunk/arch/arm/mach-ixp23xx/pci.c index 563819a83292..4b0e598a91c9 100644 --- a/trunk/arch/arm/mach-ixp23xx/pci.c +++ b/trunk/arch/arm/mach-ixp23xx/pci.c @@ -229,7 +229,7 @@ void __init ixp23xx_pci_preinit(void) { ixp23xx_pci_common_init(); - hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0, + hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, "PCI config cycle to non-existent device"); *IXP23XX_PCI_ADDR_EXT = 0x0000e000; diff --git a/trunk/arch/arm/mach-ixp4xx/common-pci.c b/trunk/arch/arm/mach-ixp4xx/common-pci.c index 61cd4d64b985..e3181534c7f9 100644 --- a/trunk/arch/arm/mach-ixp4xx/common-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/common-pci.c @@ -348,7 +348,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) * This is really ugly and we need a better way of specifying * DMA-capable regions of memory. */ -void __init ixp4xx_adjust_zones(unsigned long *zone_size, +void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) { unsigned int sz = SZ_64M >> PAGE_SHIFT; @@ -356,7 +356,7 @@ void __init ixp4xx_adjust_zones(unsigned long *zone_size, /* * Only adjust if > 64M on current system */ - if (zone_size[0] <= sz) + if (node || (zone_size[0] <= sz)) return; zone_size[1] = zone_size[0] - sz; @@ -382,8 +382,7 @@ void __init ixp4xx_pci_preinit(void) /* hook in our fault handler for PCI errors */ - hook_fault_code(16+6, abort_handler, SIGBUS, 0, - "imprecise external abort"); + hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort"); pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/memory.h b/trunk/arch/arm/mach-ixp4xx/include/mach/memory.h index 0136eaa29224..98f5e5e20980 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -16,10 +16,10 @@ #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) -void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes); +void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes); -#define arch_adjust_zones(size, holes) \ - ixp4xx_adjust_zones(size, holes) +#define arch_adjust_zones(node, size, holes) \ + ixp4xx_adjust_zones(node, size, holes) #define ISA_DMA_THRESHOLD (SZ_64M - 1) #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) diff --git a/trunk/arch/arm/mach-kirkwood/Kconfig b/trunk/arch/arm/mach-kirkwood/Kconfig index cc25501b57fa..29b2163b1fe3 100644 --- a/trunk/arch/arm/mach-kirkwood/Kconfig +++ b/trunk/arch/arm/mach-kirkwood/Kconfig @@ -75,13 +75,6 @@ config MACH_OPENRD_CLIENT Say 'Y' here if you want your kernel to support the Marvell OpenRD Client Board. -config MACH_OPENRD_ULTIMATE - bool "Marvell OpenRD Ultimate Board" - select MACH_OPENRD - help - Say 'Y' here if you want your kernel to support the - Marvell OpenRD Ultimate Board. - config MACH_NETSPACE_V2 bool "LaCie Network Space v2 NAS Board" help @@ -94,12 +87,6 @@ config MACH_INETSPACE_V2 Say 'Y' here if you want your kernel to support the LaCie Internet Space v2 NAS. -config MACH_NETSPACE_MAX_V2 - bool "LaCie Network Space Max v2 NAS Board" - help - Say 'Y' here if you want your kernel to support the - LaCie Network Space Max v2 NAS. - config MACH_NET2BIG_V2 bool "LaCie 2Big Network v2 NAS Board" help @@ -112,12 +99,6 @@ config MACH_NET5BIG_V2 Say 'Y' here if you want your kernel to support the LaCie 5Big Network v2 NAS. -config MACH_T5325 - bool "HP t5325 Thin Client" - help - Say 'Y' here if you want your kernel to support the - HP t5325 Thin Client. - endmenu endif diff --git a/trunk/arch/arm/mach-kirkwood/Makefile b/trunk/arch/arm/mach-kirkwood/Makefile index 295d7baa6ae1..c0cd5d362002 100644 --- a/trunk/arch/arm/mach-kirkwood/Makefile +++ b/trunk/arch/arm/mach-kirkwood/Makefile @@ -12,9 +12,7 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o -obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o -obj-$(CONFIG_MACH_T5325) += t5325-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/trunk/arch/arm/mach-kirkwood/addr-map.c b/trunk/arch/arm/mach-kirkwood/addr-map.c index 8d03bcef5182..2e69168fc699 100644 --- a/trunk/arch/arm/mach-kirkwood/addr-map.c +++ b/trunk/arch/arm/mach-kirkwood/addr-map.c @@ -31,8 +31,6 @@ #define ATTR_DEV_CS0 0x3e #define ATTR_PCIE_IO 0xe0 #define ATTR_PCIE_MEM 0xe8 -#define ATTR_PCIE1_IO 0xd0 -#define ATTR_PCIE1_MEM 0xd8 #define ATTR_SRAM 0x01 /* @@ -108,21 +106,17 @@ void __init kirkwood_setup_cpu_mbus(void) TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); - setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, - TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE); - setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE); /* * Setup window for NAND controller. */ - setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, + setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, TARGET_DEV_BUS, ATTR_DEV_NAND, -1); /* * Setup window for SRAM. */ - setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, + setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); /* diff --git a/trunk/arch/arm/mach-kirkwood/common.c b/trunk/arch/arm/mach-kirkwood/common.c index 9dd67c7b4459..6072eaa5e66a 100644 --- a/trunk/arch/arm/mach-kirkwood/common.c +++ b/trunk/arch/arm/mach-kirkwood/common.c @@ -43,11 +43,6 @@ static struct map_desc kirkwood_io_desc[] __initdata = { .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), .length = KIRKWOOD_PCIE_IO_SIZE, .type = MT_DEVICE, - }, { - .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, - .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), - .length = KIRKWOOD_PCIE1_IO_SIZE, - .type = MT_DEVICE, }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), @@ -407,7 +402,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) u32 dev, rev; kirkwood_pcie_id(&dev, &rev); - if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */ + if (rev == 0) /* catch all Kirkwood Z0's */ mvsdio_data->clock = 100000000; else mvsdio_data->clock = 200000000; @@ -852,10 +847,8 @@ int __init kirkwood_find_tclk(void) u32 dev, rev; kirkwood_pcie_id(&dev, &rev); - - if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 || - rev == MV88F6281_REV_A1)) || - (dev == MV88F6282_DEV_ID)) + if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 || + rev == MV88F6281_REV_A1)) return 200000000; return 166666667; @@ -898,22 +891,13 @@ static char * __init kirkwood_id(void) return "MV88F6192-Z0"; else if (rev == MV88F6192_REV_A0) return "MV88F6192-A0"; - else if (rev == MV88F6192_REV_A1) - return "MV88F6192-A1"; else return "MV88F6192-Rev-Unsupported"; } else if (dev == MV88F6180_DEV_ID) { if (rev == MV88F6180_REV_A0) return "MV88F6180-Rev-A0"; - else if (rev == MV88F6180_REV_A1) - return "MV88F6180-Rev-A1"; else return "MV88F6180-Rev-Unsupported"; - } else if (dev == MV88F6282_DEV_ID) { - if (rev == MV88F6282_REV_A0) - return "MV88F6282-Rev-A0"; - else - return "MV88F6282-Rev-Unsupported"; } else { return "Device-Unknown"; } @@ -965,14 +949,12 @@ void __init kirkwood_init(void) static int __init kirkwood_clock_gate(void) { unsigned int curr = readl(CLOCK_GATING_CTRL); - u32 dev, rev; - kirkwood_pcie_id(&dev, &rev); printk(KERN_DEBUG "Gating clock of unused units\n"); printk(KERN_DEBUG "before: 0x%08x\n", curr); /* Make sure those units are accessible */ - writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL); + writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL); /* For SATA: first shutdown the phy */ if (!(kirkwood_clk_ctrl & CGC_SATA0)) { @@ -997,18 +979,6 @@ static int __init kirkwood_clock_gate(void) writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); } - /* For PCIe 1: first shutdown the phy */ - if (dev == MV88F6282_DEV_ID) { - if (!(kirkwood_clk_ctrl & CGC_PEX1)) { - writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL); - while (1) - if (readl(PCIE1_STATUS) & 0x1) - break; - writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL); - } - } else /* keep this bit set for devices that don't have PCIe1 */ - kirkwood_clk_ctrl |= CGC_PEX1; - /* Now gate clock the required units */ writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); diff --git a/trunk/arch/arm/mach-kirkwood/common.h b/trunk/arch/arm/mach-kirkwood/common.h index 5b2c1c18d641..05e8a8a5692e 100644 --- a/trunk/arch/arm/mach-kirkwood/common.h +++ b/trunk/arch/arm/mach-kirkwood/common.h @@ -18,9 +18,6 @@ struct mvsdio_platform_data; struct mtd_partition; struct mtd_info; -#define KW_PCIE0 (1 << 0) -#define KW_PCIE1 (1 << 1) - /* * Basic Kirkwood init functions used early by machine-setup. */ @@ -37,7 +34,7 @@ void kirkwood_ehci_init(void); void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); -void kirkwood_pcie_init(unsigned int portmask); +void kirkwood_pcie_init(void); void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data); void kirkwood_spi_init(void); diff --git a/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index 16f6691e7c68..39bdf4bcace9 100644 --- a/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -51,14 +51,6 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = { }; static unsigned int db88f6281_mpp_config[] __initdata = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP18_NF_IO0, - MPP19_NF_IO1, MPP37_GPIO, MPP38_GPIO, 0 @@ -82,15 +74,9 @@ static void __init db88f6281_init(void) static int __init db88f6281_pci_init(void) { - if (machine_is_db88f6281_bp()) { - u32 dev, rev; + if (machine_is_db88f6281_bp()) + kirkwood_pcie_init(); - kirkwood_pcie_id(&dev, &rev); - if (dev == MV88F6282_DEV_ID) - kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0); - else - kirkwood_pcie_init(KW_PCIE0); - } return 0; } subsys_initcall(db88f6281_pci_init); diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/trunk/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index aff0e1327e38..418f5017c50e 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -59,9 +59,8 @@ #define CGC_SATA1 (1 << 15) #define CGC_XOR1 (1 << 16) #define CGC_CRYPTO (1 << 17) -#define CGC_PEX1 (1 << 18) #define CGC_GE1 (1 << 19) #define CGC_TDM (1 << 20) -#define CGC_RESERVED (0x6 << 21) +#define CGC_RESERVED ((1 << 18) | (0x6 << 21)) #endif diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/irqs.h b/trunk/arch/arm/mach-kirkwood/include/mach/irqs.h index 9da2eb59180b..f00a0a45a67e 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/irqs.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/irqs.h @@ -23,7 +23,6 @@ #define IRQ_KIRKWOOD_XOR_10 7 #define IRQ_KIRKWOOD_XOR_11 8 #define IRQ_KIRKWOOD_PCIE 9 -#define IRQ_KIRKWOOD_PCIE1 10 #define IRQ_KIRKWOOD_GE00_SUM 11 #define IRQ_KIRKWOOD_GE01_SUM 15 #define IRQ_KIRKWOOD_USB 19 diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h index d141af4c2744..a15cf0ee22bd 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -16,48 +16,36 @@ * Marvell Kirkwood address maps. * * phys - * e0000000 PCIe #0 Memory space - * e8000000 PCIe #1 Memory space + * e0000000 PCIe Memory space * f1000000 on-chip peripheral registers - * f2000000 PCIe #0 I/O space - * f3000000 PCIe #1 I/O space - * f4000000 NAND controller address window - * f5000000 Security Accelerator SRAM + * f2000000 PCIe I/O space + * f3000000 NAND controller address window + * f4000000 Security Accelerator SRAM * * virt phys size - * fed00000 f1000000 1M on-chip peripheral registers - * fee00000 f2000000 1M PCIe #0 I/O space - * fef00000 f3000000 1M PCIe #1 I/O space + * fee00000 f1000000 1M on-chip peripheral registers + * fef00000 f2000000 1M PCIe I/O space */ -#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000 +#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 #define KIRKWOOD_SRAM_SIZE SZ_2K -#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000 +#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 #define KIRKWOOD_NAND_MEM_SIZE SZ_1K -#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 -#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 -#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000 -#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M - #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 +#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 #define KIRKWOOD_PCIE_IO_SIZE SZ_1M #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 -#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 +#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 #define KIRKWOOD_REGS_SIZE SZ_1M #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 #define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000 #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M -#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000 -#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000 -#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M - /* * Register Map */ @@ -84,9 +72,6 @@ #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) #define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) #define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) -#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) -#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) -#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04) #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) @@ -122,12 +107,8 @@ #define MV88F6192_DEV_ID 0x6192 #define MV88F6192_REV_Z0 0 #define MV88F6192_REV_A0 2 -#define MV88F6192_REV_A1 3 #define MV88F6180_DEV_ID 0x6180 #define MV88F6180_REV_A0 2 -#define MV88F6180_REV_A1 3 -#define MV88F6282_DEV_ID 0x6282 -#define MV88F6282_REV_A0 0 #endif diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/trunk/arch/arm/mach-kirkwood/include/mach/leds-ns2.h deleted file mode 100644 index e21272e5f668..000000000000 --- a/trunk/arch/arm/mach-kirkwood/include/mach/leds-ns2.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-kirkwood/include/mach/leds-ns2.h - * - * Platform data structure for Network Space v2 LED driver - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_LEDS_NS2_H -#define __MACH_LEDS_NS2_H - -struct ns2_led { - const char *name; - const char *default_trigger; - unsigned cmd; - unsigned slow; -}; - -struct ns2_led_platform_data { - int num_leds; - struct ns2_led *leds; -}; - -#endif /* __MACH_LEDS_NS2_H */ diff --git a/trunk/arch/arm/mach-kirkwood/mpp.c b/trunk/arch/arm/mach-kirkwood/mpp.c index 065187d177c6..a5900f64e38c 100644 --- a/trunk/arch/arm/mach-kirkwood/mpp.c +++ b/trunk/arch/arm/mach-kirkwood/mpp.c @@ -23,8 +23,7 @@ static unsigned int __init kirkwood_variant(void) kirkwood_pcie_id(&dev, &rev); - if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) || - (dev == MV88F6282_DEV_ID)) + if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) return MPP_F6281_MASK; if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) return MPP_F6192_MASK; diff --git a/trunk/arch/arm/mach-kirkwood/mpp.h b/trunk/arch/arm/mach-kirkwood/mpp.h index 9b0a94d85c3e..bc74278ed311 100644 --- a/trunk/arch/arm/mach-kirkwood/mpp.h +++ b/trunk/arch/arm/mach-kirkwood/mpp.h @@ -11,7 +11,7 @@ #ifndef __KIRKWOOD_MPP_H #define __KIRKWOOD_MPP_H -#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \ +#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ /* MPP number */ ((_num) & 0xff) | \ /* MPP select value */ (((_sel) & 0xf) << 8) | \ /* may be input signal */ ((!!(_in)) << 12) | \ @@ -19,332 +19,282 @@ /* available on F6180 */ ((!!(_F6180)) << 14) | \ /* available on F6190 */ ((!!(_F6190)) << 15) | \ /* available on F6192 */ ((!!(_F6192)) << 16) | \ - /* available on F6281 */ ((!!(_F6281)) << 17) | \ - /* available on F6282 */ ((!!(_F6282)) << 18)) + /* available on F6281 */ ((!!(_F6281)) << 17)) #define MPP_NUM(x) ((x) & 0xff) #define MPP_SEL(x) (((x) >> 8) & 0xf) - /* num sel i o 6180 6190 6192 6281 6282 */ - -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 ) -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 ) - -#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 ) -#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 ) -#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 ) -#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1, 0 ) -#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) - -#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) - -#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) - -#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) - -#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) - -#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) - -#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) -#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) - -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) - -#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) - -#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) - -#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) - -#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) - -#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) - -#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) -#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) - -#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) - -#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) - -#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) - -#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) - -#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) - -#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) -#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) -#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) -#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) -#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) -#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) - -#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) -#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) - -#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) -#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) - -#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) -#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) -#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) -#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) -#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) -#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) -#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) -#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) -#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) -#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) - -#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) -#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) -#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + /* num sel i o 6180 6190 6192 6281 */ + +#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) +#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) + +#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) +#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) +#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) +#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) + +#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) + +#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) +#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) +#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) +#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) + +#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) +#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) + +#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) + +#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) + +#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) + +#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) + +#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) + +#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) + +#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) + +#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) +#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) + +#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) +#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) +#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) +#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) +#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) + +#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) +#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) +#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) +#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) + +#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) + +#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) + +#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) + +#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) #define MPP_MAX 49 diff --git a/trunk/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/trunk/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c index c6b92b42eb4e..5e6f711b1c67 100644 --- a/trunk/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c +++ b/trunk/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c @@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void) static int __init mv88f6281gtw_ge_pci_init(void) { if (machine_is_mv88f6281gtw_ge()) - kirkwood_pcie_init(KW_PCIE0); + kirkwood_pcie_init(); return 0; } diff --git a/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c b/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c index d26bf324738b..3ae158d72681 100644 --- a/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -39,7 +39,6 @@ #include #include #include -#include #include #include "common.h" #include "mpp.h" @@ -127,18 +126,6 @@ static void __init netspace_v2_sata_power_init(void) } if (err) pr_err("netspace_v2: failed to setup SATA0 power\n"); - - if (machine_is_netspace_max_v2()) { - err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power"); - if (err == 0) { - err = gpio_direction_output( - NETSPACE_V2_GPIO_SATA1_POWER, 1); - if (err) - gpio_free(NETSPACE_V2_GPIO_SATA1_POWER); - } - if (err) - pr_err("netspace_v2: failed to setup SATA1 power\n"); - } } /***************************************************************************** @@ -173,12 +160,36 @@ static struct platform_device netspace_v2_gpio_buttons = { * GPIO LEDs ****************************************************************************/ +/* + * The blue front LED is wired to a CPLD and can blink in relation with the + * SATA activity. + * + * The following array detail the different LED registers and the combination + * of their possible values: + * + * cmd_led | slow_led | /SATA active | LED state + * | | | + * 1 | 0 | x | off + * - | 1 | x | on + * 0 | 0 | 1 | on + * 0 | 0 | 0 | blink (rate 300ms) + */ + #define NETSPACE_V2_GPIO_RED_LED 12 +#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29 +#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30 + static struct gpio_led netspace_v2_gpio_led_pins[] = { { - .name = "ns_v2:red:fail", - .gpio = NETSPACE_V2_GPIO_RED_LED, + .name = "ns_v2:blue:sata", + .default_trigger = "default-on", + .gpio = NETSPACE_V2_GPIO_BLUE_LED_CMD, + .active_low = 1, + }, + { + .name = "ns_v2:red:fail", + .gpio = NETSPACE_V2_GPIO_RED_LED, }, }; @@ -195,33 +206,22 @@ static struct platform_device netspace_v2_gpio_leds = { }, }; -/***************************************************************************** - * Dual-GPIO CPLD LEDs - ****************************************************************************/ - -#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29 -#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30 - -static struct ns2_led netspace_v2_led_pins[] = { - { - .name = "ns_v2:blue:sata", - .cmd = NETSPACE_V2_GPIO_BLUE_LED_CMD, - .slow = NETSPACE_V2_GPIO_BLUE_LED_SLOW, - }, -}; +static void __init netspace_v2_gpio_leds_init(void) +{ + int err; -static struct ns2_led_platform_data netspace_v2_leds_data = { - .num_leds = ARRAY_SIZE(netspace_v2_led_pins), - .leds = netspace_v2_led_pins, -}; + /* Configure register slow_led to allow SATA activity LED blinking */ + err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow"); + if (err == 0) { + err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0); + if (err) + gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW); + } + if (err) + pr_err("netspace_v2: failed to configure blue LED slow GPIO\n"); -static struct platform_device netspace_v2_leds = { - .name = "leds-ns2", - .id = -1, - .dev = { - .platform_data = &netspace_v2_leds_data, - }, -}; + platform_device_register(&netspace_v2_gpio_leds); +} /***************************************************************************** * Timer @@ -249,21 +249,17 @@ static unsigned int netspace_v2_mpp_config[] __initdata = { MPP4_NF_IO6, MPP5_NF_IO7, MPP6_SYSRST_OUTn, - MPP7_GPO, /* Fan speed (bit 1) */ - MPP8_TW0_SDA, - MPP9_TW0_SCK, + MPP8_TW_SDA, + MPP9_TW_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP12_GPO, /* Red led */ MPP14_GPIO, /* USB fuse */ MPP16_GPIO, /* SATA 0 power */ - MPP17_GPIO, /* SATA 1 power */ MPP18_NF_IO0, MPP19_NF_IO1, MPP20_SATA1_ACTn, MPP21_SATA0_ACTn, - MPP22_GPIO, /* Fan speed (bit 0) */ - MPP23_GPIO, /* Fan power */ MPP24_GPIO, /* USB mode select */ MPP25_GPIO, /* Fan rotation fail */ MPP26_GPIO, /* USB device vbus */ @@ -272,7 +268,6 @@ static unsigned int netspace_v2_mpp_config[] __initdata = { MPP30_GPIO, /* Blue led (command register) */ MPP31_GPIO, /* Board power off */ MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ - MPP33_GPO, /* Fan speed (bit 2) */ 0 }; @@ -304,8 +299,7 @@ static void __init netspace_v2_init(void) i2c_register_board_info(0, netspace_v2_i2c_info, ARRAY_SIZE(netspace_v2_i2c_info)); - platform_device_register(&netspace_v2_leds); - platform_device_register(&netspace_v2_gpio_leds); + netspace_v2_gpio_leds_init(); platform_device_register(&netspace_v2_gpio_buttons); if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 && @@ -338,15 +332,3 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") .timer = &netspace_v2_timer, MACHINE_END #endif - -#ifdef CONFIG_MACH_NETSPACE_MAX_V2 -MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2") - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = netspace_v2_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &netspace_v2_timer, -MACHINE_END -#endif diff --git a/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c index 2bd14c5079de..8a2bb0228e4f 100644 --- a/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c +++ b/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c @@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = { MPP3_SPI_MISO, MPP6_SYSRST_OUTn, MPP7_GPO, /* Request power-off */ - MPP8_TW0_SDA, - MPP9_TW0_SCK, + MPP8_TW_SDA, + MPP9_TW_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP13_GPIO, /* Rear power switch (on|auto) */ @@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = { MPP3_SPI_MISO, MPP6_SYSRST_OUTn, MPP7_GPO, /* Request power-off */ - MPP8_TW0_SDA, - MPP9_TW0_SCK, + MPP8_TW_SDA, + MPP9_TW_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP13_GPIO, /* Rear power switch (on|auto) */ @@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = { MPP15_GPIO, /* Rear power switch (auto|off) */ MPP16_GPIO, /* SATA HDD1 power */ MPP17_GPIO, /* SATA HDD2 power */ - MPP20_GE1_TXD0, - MPP21_GE1_TXD1, - MPP22_GE1_TXD2, - MPP23_GE1_TXD3, - MPP24_GE1_RXD0, - MPP25_GE1_RXD1, - MPP26_GE1_RXD2, - MPP27_GE1_RXD3, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, MPP28_GPIO, /* USB enable host vbus */ MPP29_GPIO, /* CPLD extension ALE */ - MPP30_GE1_RXCTL, - MPP31_GE1_RXCLK, - MPP32_GE1_TCLKOUT, - MPP33_GE1_TXCTL, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, MPP34_GPIO, /* Rear Push button */ MPP35_GPIO, /* Inhibit switch power-off */ MPP36_GPIO, /* SATA HDD1 presence */ diff --git a/trunk/arch/arm/mach-kirkwood/openrd-setup.c b/trunk/arch/arm/mach-kirkwood/openrd-setup.c index fd64cd2b4e0a..ad3f1ec33796 100644 --- a/trunk/arch/arm/mach-kirkwood/openrd-setup.c +++ b/trunk/arch/arm/mach-kirkwood/openrd-setup.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-kirkwood/openrd-setup.c * - * Marvell OpenRD (Base|Client|Ultimate) Board Setup + * Marvell OpenRD (Base|Client) Board Setup * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -73,15 +73,9 @@ static void __init openrd_init(void) kirkwood_ehci_init(); - if (machine_is_openrd_ultimate()) { - openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); - openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1); - } - kirkwood_ge00_init(&openrd_ge00_data); - if (!machine_is_openrd_base()) + if (machine_is_openrd_client()) kirkwood_ge01_init(&openrd_ge01_data); - kirkwood_sata_init(&openrd_sata_data); kirkwood_sdio_init(&openrd_mvsdio_data); @@ -90,10 +84,8 @@ static void __init openrd_init(void) static int __init openrd_pci_init(void) { - if (machine_is_openrd_base() || - machine_is_openrd_client() || - machine_is_openrd_ultimate()) - kirkwood_pcie_init(KW_PCIE0); + if (machine_is_openrd_base() || machine_is_openrd_client()) + kirkwood_pcie_init(); return 0; } @@ -124,16 +116,3 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board") .timer = &kirkwood_timer, MACHINE_END #endif - -#ifdef CONFIG_MACH_OPENRD_ULTIMATE -MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board") - /* Maintainer: Dhaval Vasa */ - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = openrd_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, -MACHINE_END -#endif diff --git a/trunk/arch/arm/mach-kirkwood/pcie.c b/trunk/arch/arm/mach-kirkwood/pcie.c index 55e7f00836b7..dee1eff50d39 100644 --- a/trunk/arch/arm/mach-kirkwood/pcie.c +++ b/trunk/arch/arm/mach-kirkwood/pcie.c @@ -18,43 +18,29 @@ #include #include "common.h" -void __init kirkwood_pcie_id(u32 *dev, u32 *rev) -{ - *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); - *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE); -} - -struct pcie_port { - u8 root_bus_nr; - void __iomem *base; - spinlock_t conf_lock; - int irq; - struct resource res[2]; -}; -static int pcie_port_map[2]; -static int num_pcie_ports; +#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE) -static inline struct pcie_port *bus_to_port(struct pci_bus *bus) +void __init kirkwood_pcie_id(u32 *dev, u32 *rev) { - struct pci_sys_data *sys = bus->sysdata; - return sys->private_data; + *dev = orion_pcie_dev_id(PCIE_BASE); + *rev = orion_pcie_rev(PCIE_BASE); } -static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) +static int pcie_valid_config(int bus, int dev) { /* * Don't go out when trying to access -- * 1. nonexisting device on local bus * 2. where there's no device connected (no link) */ - if (bus == pp->root_bus_nr && dev == 0) + if (bus == 0 && dev == 0) return 1; - if (!orion_pcie_link_up(pp->base)) + if (!orion_pcie_link_up(PCIE_BASE)) return 0; - if (bus == pp->root_bus_nr && dev != 1) + if (bus == 0 && dev != 1) return 0; return 1; @@ -66,22 +52,22 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) * and then reading the PCIE_CONF_DATA register. Need to make sure these * transactions are atomic. */ +static DEFINE_SPINLOCK(kirkwood_pcie_lock); static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus_to_port(bus); unsigned long flags; int ret; - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } - spin_lock_irqsave(&pp->conf_lock, flags); - ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); - spin_unlock_irqrestore(&pp->conf_lock, flags); + spin_lock_irqsave(&kirkwood_pcie_lock, flags); + ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); return ret; } @@ -89,16 +75,15 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus_to_port(bus); unsigned long flags; int ret; - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) return PCIBIOS_DEVICE_NOT_FOUND; - spin_lock_irqsave(&pp->conf_lock, flags); - ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); - spin_unlock_irqrestore(&pp->conf_lock, flags); + spin_lock_irqsave(&kirkwood_pcie_lock, flags); + ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); return ret; } @@ -108,98 +93,50 @@ static struct pci_ops pcie_ops = { .write = pcie_wr_conf, }; -static void __init pcie0_ioresources_init(struct pcie_port *pp) + +static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) { - pp->base = (void __iomem *)PCIE_VIRT_BASE; - pp->irq = IRQ_KIRKWOOD_PCIE; + struct resource *res; + extern unsigned int kirkwood_clk_ctrl; /* - * IORESOURCE_IO + * Generic PCIe unit setup. */ - pp->res[0].name = "PCIe 0 I/O Space"; - pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE; - pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; + orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info); /* - * IORESOURCE_MEM + * Request resources. */ - pp->res[1].name = "PCIe 0 MEM"; - pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; - pp->res[1].flags = IORESOURCE_MEM; -} - -static void __init pcie1_ioresources_init(struct pcie_port *pp) -{ - pp->base = (void __iomem *)PCIE1_VIRT_BASE; - pp->irq = IRQ_KIRKWOOD_PCIE1; + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("pcie_setup unable to alloc resources"); /* * IORESOURCE_IO */ - pp->res[0].name = "PCIe 1 I/O Space"; - pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE; - pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; + res[0].name = "PCIe I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; + res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCIe IO resource failed\n"); + sys->resource[0] = &res[0]; /* * IORESOURCE_MEM */ - pp->res[1].name = "PCIe 1 MEM"; - pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; - pp->res[1].flags = IORESOURCE_MEM; -} - -static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) -{ - extern unsigned int kirkwood_clk_ctrl; - struct pcie_port *pp; - int index; + res[1].name = "PCIe Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE; + res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCIe Memory resource failed\n"); + sys->resource[1] = &res[1]; - if (nr >= num_pcie_ports) - return 0; - - index = pcie_port_map[nr]; - printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index); - - pp = kzalloc(sizeof(*pp), GFP_KERNEL); - if (!pp) - panic("PCIe: failed to allocate pcie_port data"); - sys->private_data = pp; - pp->root_bus_nr = sys->busnr; - spin_lock_init(&pp->conf_lock); - - switch (index) { - case 0: - kirkwood_clk_ctrl |= CGC_PEX0; - pcie0_ioresources_init(pp); - break; - case 1: - kirkwood_clk_ctrl |= CGC_PEX1; - pcie1_ioresources_init(pp); - break; - default: - panic("PCIe setup: invalid controller %d", index); - } - - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe%d IO resource failed\n", index); - if (request_resource(&iomem_resource, &pp->res[1])) - panic("Request PCIe%d Memory resource failed\n", index); - - sys->resource[0] = &pp->res[0]; - sys->resource[1] = &pp->res[1]; sys->resource[2] = NULL; sys->io_offset = 0; - /* - * Generic PCIe unit setup. - */ - orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - - orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); + kirkwood_clk_ctrl |= CGC_PEX0; return 1; } @@ -226,7 +163,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; - if (nr < num_pcie_ports) { + if (nr == 0) { bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); } else { bus = NULL; @@ -238,37 +175,18 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - struct pcie_port *pp = bus_to_port(dev->bus); - - return pp->irq; + return IRQ_KIRKWOOD_PCIE; } static struct hw_pci kirkwood_pci __initdata = { + .nr_controllers = 1, .swizzle = pci_std_swizzle, .setup = kirkwood_pcie_setup, .scan = kirkwood_pcie_scan_bus, .map_irq = kirkwood_pcie_map_irq, }; -static void __init add_pcie_port(int index, unsigned long base) +void __init kirkwood_pcie_init(void) { - printk(KERN_INFO "Kirkwood PCIe port %d: ", index); - - if (orion_pcie_link_up((void __iomem *)base)) { - printk(KERN_INFO "link up\n"); - pcie_port_map[num_pcie_ports++] = index; - } else - printk(KERN_INFO "link down, ignoring\n"); -} - -void __init kirkwood_pcie_init(unsigned int portmask) -{ - if (portmask & KW_PCIE0) - add_pcie_port(0, PCIE_VIRT_BASE); - - if (portmask & KW_PCIE1) - add_pcie_port(1, PCIE1_VIRT_BASE); - - kirkwood_pci.nr_controllers = num_pcie_ports; pci_common_init(&kirkwood_pci); } diff --git a/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c index c34718c2cfe5..3bf6304158f6 100644 --- a/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +++ b/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c @@ -71,7 +71,7 @@ static void __init rd88f6192_init(void) static int __init rd88f6192_pci_init(void) { if (machine_is_rd88f6192_nas()) - kirkwood_pcie_init(KW_PCIE0); + kirkwood_pcie_init(); return 0; } diff --git a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c index 3d1477135e12..31708ddbc83e 100644 --- a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -107,7 +107,7 @@ static void __init rd88f6281_init(void) static int __init rd88f6281_pci_init(void) { if (machine_is_rd88f6281()) - kirkwood_pcie_init(KW_PCIE0); + kirkwood_pcie_init(); return 0; } diff --git a/trunk/arch/arm/mach-kirkwood/t5325-setup.c b/trunk/arch/arm/mach-kirkwood/t5325-setup.c deleted file mode 100644 index d01bf89cedbe..000000000000 --- a/trunk/arch/arm/mach-kirkwood/t5325-setup.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * - * HP t5325 Thin Client setup - * - * Copyright (C) 2010 Martin Michlmayr - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" - -struct mtd_partition hp_t5325_partitions[] = { - { - .name = "u-boot env", - .size = SZ_64K, - .offset = SZ_512K + SZ_256K, - }, - { - .name = "permanent u-boot env", - .size = SZ_64K, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "HP env", - .size = SZ_64K, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "u-boot", - .size = SZ_512K, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "SSD firmware", - .size = SZ_256K, - .offset = SZ_512K, - }, -}; - -const struct flash_platform_data hp_t5325_flash = { - .type = "mx25l8005", - .name = "spi_flash", - .parts = hp_t5325_partitions, - .nr_parts = ARRAY_SIZE(hp_t5325_partitions), -}; - -struct spi_board_info __initdata hp_t5325_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &hp_t5325_flash, - .irq = -1, - }, -}; - -static struct mv643xx_eth_platform_data hp_t5325_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv_sata_platform_data hp_t5325_sata_data = { - .n_ports = 2, -}; - -static struct gpio_keys_button hp_t5325_buttons[] = { - { - .code = KEY_POWER, - .gpio = 45, - .desc = "Power", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data hp_t5325_button_data = { - .buttons = hp_t5325_buttons, - .nbuttons = ARRAY_SIZE(hp_t5325_buttons), -}; - -static struct platform_device hp_t5325_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &hp_t5325_button_data, - } -}; - -static unsigned int hp_t5325_mpp_config[] __initdata = { - MPP0_NF_IO2, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_SPI_SCn, - MPP8_TW0_SDA, - MPP9_TW0_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_GPIO, - MPP14_GPIO, - MPP15_GPIO, - MPP16_GPIO, - MPP17_GPIO, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GPIO, - MPP21_GPIO, - MPP22_GPIO, - MPP23_GPIO, - MPP32_GPIO, - MPP33_GE1_TXCTL, - MPP39_AU_I2SBCLK, - MPP40_AU_I2SDO, - MPP41_AU_I2SLRCLK, - MPP42_AU_I2SMCLK, - MPP45_GPIO, /* Power button */ - MPP48_GPIO, /* Board power off */ - 0 -}; - -#define HP_T5325_GPIO_POWER_OFF 48 - -static void hp_t5325_power_off(void) -{ - gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1); -} - -static void __init hp_t5325_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(hp_t5325_mpp_config); - - kirkwood_uart0_init(); - spi_register_board_info(hp_t5325_spi_slave_info, - ARRAY_SIZE(hp_t5325_spi_slave_info)); - kirkwood_spi_init(); - kirkwood_i2c_init(); - kirkwood_ge00_init(&hp_t5325_ge00_data); - kirkwood_sata_init(&hp_t5325_sata_data); - kirkwood_ehci_init(); - platform_device_register(&hp_t5325_button_device); - - if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 && - gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0) - pm_power_off = hp_t5325_power_off; - else - pr_err("t5325: failed to configure power-off GPIO\n"); -} - -static int __init hp_t5325_pci_init(void) -{ - if (machine_is_t5325()) - kirkwood_pcie_init(KW_PCIE0); - - return 0; -} -subsys_initcall(hp_t5325_pci_init); - -MACHINE_START(T5325, "HP t5325 Thin Client") - /* Maintainer: Martin Michlmayr */ - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = hp_t5325_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-kirkwood/ts219-setup.c b/trunk/arch/arm/mach-kirkwood/ts219-setup.c index a5bd7fde04a9..2830f0fe80e0 100644 --- a/trunk/arch/arm/mach-kirkwood/ts219-setup.c +++ b/trunk/arch/arm/mach-kirkwood/ts219-setup.c @@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP3_SPI_MISO, MPP4_SATA1_ACTn, MPP5_SATA0_ACTn, - MPP8_TW0_SDA, - MPP9_TW0_SCK, + MPP8_TW_SDA, + MPP9_TW_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP13_UART1_TXD, /* PIC controller */ @@ -83,7 +83,6 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP15_GPIO, /* USB Copy button */ MPP16_GPIO, /* Reset button */ MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ - MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */ 0 }; @@ -111,10 +110,10 @@ static void __init qnap_ts219_init(void) static int __init ts219_pci_init(void) { - if (machine_is_ts219()) - kirkwood_pcie_init(KW_PCIE0); + if (machine_is_ts219()) + kirkwood_pcie_init(); - return 0; + return 0; } subsys_initcall(ts219_pci_init); diff --git a/trunk/arch/arm/mach-kirkwood/ts41x-setup.c b/trunk/arch/arm/mach-kirkwood/ts41x-setup.c index 2e14afef07a2..de49c2d9e74b 100644 --- a/trunk/arch/arm/mach-kirkwood/ts41x-setup.c +++ b/trunk/arch/arm/mach-kirkwood/ts41x-setup.c @@ -2,7 +2,7 @@ * * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup * - * Copyright (C) 2009-2010 Martin Michlmayr + * Copyright (C) 2009 Martin Michlmayr * Copyright (C) 2008 Byron Bradley * * This program is free software; you can redistribute it and/or @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -27,8 +26,6 @@ #include "mpp.h" #include "tsx1x-common.h" -#define QNAP_TS41X_JUMPER_JP1 45 - static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { I2C_BOARD_INFO("s35390a", 0x30), }; @@ -81,31 +78,31 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = { MPP3_SPI_MISO, MPP6_SYSRST_OUTn, MPP7_PEX_RST_OUTn, - MPP8_TW0_SDA, - MPP9_TW0_SCK, + MPP8_TW_SDA, + MPP9_TW_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP13_UART1_TXD, /* PIC controller */ MPP14_UART1_RXD, /* PIC controller */ MPP15_SATA0_ACTn, MPP16_SATA1_ACTn, - MPP20_GE1_TXD0, - MPP21_GE1_TXD1, - MPP22_GE1_TXD2, - MPP23_GE1_TXD3, - MPP24_GE1_RXD0, - MPP25_GE1_RXD1, - MPP26_GE1_RXD2, - MPP27_GE1_RXD3, - MPP30_GE1_RXCTL, - MPP31_GE1_RXCLK, - MPP32_GE1_TCLKOUT, - MPP33_GE1_TXCTL, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ MPP37_GPIO, /* Reset button */ MPP43_GPIO, /* USB Copy button */ MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */ - MPP45_GPIO, /* JP1: 0: LCD, 1: serial console */ + MPP45_GPIO, /* JP1: 0: console, 1: LCD */ MPP46_GPIO, /* External SATA HDD1 error indicator */ MPP47_GPIO, /* External SATA HDD2 error indicator */ MPP48_GPIO, /* External SATA HDD3 error indicator */ @@ -134,14 +131,12 @@ static void __init qnap_ts41x_init(void) pm_power_off = qnap_tsx1x_power_off; - if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0) - gpio_export(QNAP_TS41X_JUMPER_JP1, 0); } static int __init ts41x_pci_init(void) { if (machine_is_ts41x()) - kirkwood_pcie_init(KW_PCIE0); + kirkwood_pcie_init(); return 0; } diff --git a/trunk/arch/arm/mach-ks8695/pci.c b/trunk/arch/arm/mach-ks8695/pci.c index 5fcd082a17f9..78499667eb7b 100644 --- a/trunk/arch/arm/mach-ks8695/pci.c +++ b/trunk/arch/arm/mach-ks8695/pci.c @@ -268,8 +268,8 @@ static void __init ks8695_pci_preinit(void) __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC); /* hook in fault handlers */ - hook_fault_code(8, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); - hook_fault_code(10, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); + hook_fault_code(8, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); + hook_fault_code(10, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); } static void ks8695_show_pciregs(void) diff --git a/trunk/arch/arm/mach-l7200/Makefile b/trunk/arch/arm/mach-l7200/Makefile new file mode 100644 index 000000000000..4bd8ebd70e7b --- /dev/null +++ b/trunk/arch/arm/mach-l7200/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := core.o +obj-m := +obj-n := +obj- := + diff --git a/trunk/arch/arm/mach-l7200/Makefile.boot b/trunk/arch/arm/mach-l7200/Makefile.boot new file mode 100644 index 000000000000..6c72ecbe6b64 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y := 0xf0008000 + diff --git a/trunk/arch/arm/mach-l7200/core.c b/trunk/arch/arm/mach-l7200/core.c new file mode 100644 index 000000000000..50d23246d4f0 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/core.c @@ -0,0 +1,100 @@ +/* + * linux/arch/arm/mm/mm-lusl7200.c + * + * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) + * + * Extra MM routines for L7200 architecture + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +/* + * IRQ base register + */ +#define IRQ_BASE (IO_BASE_2 + 0x1000) + +/* + * Normal IRQ registers + */ +#define IRQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x000)) +#define IRQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x004)) +#define IRQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x008)) +#define IRQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x00c)) +#define IRQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x010)) +#define IRQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x018)) + +/* + * Fast IRQ registers + */ +#define FIQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x100)) +#define FIQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x104)) +#define FIQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x108)) +#define FIQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x10c)) +#define FIQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x110)) +#define FIQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x118)) + +static void l7200_mask_irq(unsigned int irq) +{ + IRQ_ENABLECLEAR = 1 << irq; +} + +static void l7200_unmask_irq(unsigned int irq) +{ + IRQ_ENABLE = 1 << irq; +} + +static struct irq_chip l7200_irq_chip = { + .ack = l7200_mask_irq, + .mask = l7200_mask_irq, + .unmask = l7200_unmask_irq +}; + +static void __init l7200_init_irq(void) +{ + int irq; + + IRQ_ENABLECLEAR = 0xffffffff; /* clear all interrupt enables */ + FIQ_ENABLECLEAR = 0xffffffff; /* clear all fast interrupt enables */ + + for (irq = 0; irq < NR_IRQS; irq++) { + set_irq_chip(irq, &l7200_irq_chip); + set_irq_flags(irq, IRQF_VALID); + set_irq_handler(irq, handle_level_irq); + } + + init_FIQ(); +} + +static struct map_desc l7200_io_desc[] __initdata = { + { IO_BASE, IO_START, IO_SIZE, MT_DEVICE }, + { IO_BASE_2, IO_START_2, IO_SIZE_2, MT_DEVICE }, + { AUX_BASE, AUX_START, AUX_SIZE, MT_DEVICE }, + { FLASH1_BASE, FLASH1_START, FLASH1_SIZE, MT_DEVICE }, + { FLASH2_BASE, FLASH2_START, FLASH2_SIZE, MT_DEVICE } +}; + +static void __init l7200_map_io(void) +{ + iotable_init(l7200_io_desc, ARRAY_SIZE(l7200_io_desc)); +} + +MACHINE_START(L7200, "LinkUp Systems L7200") + /* Maintainer: Steve Hill / Scott McConnell */ + .phys_io = 0x80040000, + .io_pg_offst = ((0xd0000000) >> 18) & 0xfffc, + .map_io = l7200_map_io, + .init_irq = l7200_init_irq, +MACHINE_END + diff --git a/trunk/arch/arm/mach-l7200/include/mach/aux_reg.h b/trunk/arch/arm/mach-l7200/include/mach/aux_reg.h new file mode 100644 index 000000000000..4671558cdd51 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/aux_reg.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-l7200/include/mach/aux_reg.h + * + * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) + * + * Changelog: + * 08-02-2000 SJH Created file + */ +#ifndef _ASM_ARCH_AUXREG_H +#define _ASM_ARCH_AUXREG_H + +#include + +#define l7200aux_reg *((volatile unsigned int *) (AUX_BASE)) + +/* + * Auxillary register values + */ +#define AUX_CLEAR 0x00000000 +#define AUX_DIAG_LED_ON 0x00000002 +#define AUX_RTS_UART1 0x00000004 +#define AUX_DTR_UART1 0x00000008 +#define AUX_KBD_COLUMN_12_HIGH 0x00000010 +#define AUX_KBD_COLUMN_12_OFF 0x00000020 +#define AUX_KBD_COLUMN_13_HIGH 0x00000040 +#define AUX_KBD_COLUMN_13_OFF 0x00000080 + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/debug-macro.S b/trunk/arch/arm/mach-l7200/include/mach/debug-macro.S new file mode 100644 index 000000000000..b69ed344c7c9 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/debug-macro.S @@ -0,0 +1,40 @@ +/* arch/arm/mach-l7200/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .equ io_virt, IO_BASE + .equ io_phys, IO_START + + .macro addruart, rx, tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #io_phys @ physical base address + movne \rx, #io_virt @ virtual address + add \rx, \rx, #0x00044000 @ UART1 +@ add \rx, \rx, #0x00045000 @ UART2 + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #0x0] @ UARTDR + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full + bne 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy + bne 1001b + .endm diff --git a/trunk/arch/arm/mach-l7200/include/mach/entry-macro.S b/trunk/arch/arm/mach-l7200/include/mach/entry-macro.S new file mode 100644 index 000000000000..1726d91fc1d3 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/entry-macro.S @@ -0,0 +1,35 @@ +/* + * arch/arm/mach-l7200/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for L7200-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include + + .equ irq_base_addr, IO_BASE_2 + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \irqstat, #irq_base_addr @ Virt addr IRQ regs + add \irqstat, \irqstat, #0x00001000 @ Status reg + ldr \irqstat, [\irqstat, #0] @ get interrupts + mov \irqnr, #0 +1001: tst \irqstat, #1 + addeq \irqnr, \irqnr, #1 + moveq \irqstat, \irqstat, lsr #1 + tsteq \irqnr, #32 + beq 1001b + teq \irqnr, #32 + .endm + diff --git a/trunk/arch/arm/mach-l7200/include/mach/gp_timers.h b/trunk/arch/arm/mach-l7200/include/mach/gp_timers.h new file mode 100644 index 000000000000..2b7086a26b81 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/gp_timers.h @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-l7200/include/mach/gp_timers.h + * + * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) + * + * Changelog: + * 07-28-2000 SJH Created file + * 08-02-2000 SJH Used structure for registers + */ +#ifndef _ASM_ARCH_GPTIMERS_H +#define _ASM_ARCH_GPTIMERS_H + +#include + +/* + * Layout of L7200 general purpose timer registers + */ +struct GPT_Regs { + unsigned int TIMERLOAD; + unsigned int TIMERVALUE; + unsigned int TIMERCONTROL; + unsigned int TIMERCLEAR; +}; + +#define GPT_BASE (IO_BASE_2 + 0x3000) +#define l7200_timer1_regs ((volatile struct GPT_Regs *) (GPT_BASE)) +#define l7200_timer2_regs ((volatile struct GPT_Regs *) (GPT_BASE + 0x20)) + +/* + * General register values + */ +#define GPT_PRESCALE_1 0x00000000 +#define GPT_PRESCALE_16 0x00000004 +#define GPT_PRESCALE_256 0x00000008 +#define GPT_MODE_FREERUN 0x00000000 +#define GPT_MODE_PERIODIC 0x00000040 +#define GPT_ENABLE 0x00000080 +#define GPT_BZTOG 0x00000100 +#define GPT_BZMOD 0x00000200 +#define GPT_LOAD_MASK 0x0000ffff + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/gpio.h b/trunk/arch/arm/mach-l7200/include/mach/gpio.h new file mode 100644 index 000000000000..c7b0a5d7b8bb --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/gpio.h @@ -0,0 +1,105 @@ +/****************************************************************************/ +/* + * arch/arm/mach-l7200/include/mach/gpio.h + * + * Registers and helper functions for the L7200 Link-Up Systems + * GPIO. + * + * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +/****************************************************************************/ + +#define GPIO_OFF 0x00005000 /* Offset from IO_START to the GPIO reg's. */ + +/* IO_START and IO_BASE are defined in hardware.h */ + +#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */ +#define GPIO_BASE (IO_BASE_2 + GPIO_OFF) /* Virtual addr of the GPIO reg. */ + +/* Offsets from the start of the GPIO for all the registers. */ +#define PADR_OFF 0x000 +#define PADDR_OFF 0x004 +#define PASBSR_OFF 0x008 +#define PAEENR_OFF 0x00c +#define PAESNR_OFF 0x010 +#define PAESTR_OFF 0x014 +#define PAIMR_OFF 0x018 +#define PAINT_OFF 0x01c + +#define PBDR_OFF 0x020 +#define PBDDR_OFF 0x024 +#define PBSBSR_OFF 0x028 +#define PBIMR_OFF 0x038 +#define PBINT_OFF 0x03c + +#define PCDR_OFF 0x040 +#define PCDDR_OFF 0x044 +#define PCSBSR_OFF 0x048 +#define PCIMR_OFF 0x058 +#define PCINT_OFF 0x05c + +#define PDDR_OFF 0x060 +#define PDDDR_OFF 0x064 +#define PDSBSR_OFF 0x068 +#define PDEENR_OFF 0x06c +#define PDESNR_OFF 0x070 +#define PDESTR_OFF 0x074 +#define PDIMR_OFF 0x078 +#define PDINT_OFF 0x07c + +#define PEDR_OFF 0x080 +#define PEDDR_OFF 0x084 +#define PESBSR_OFF 0x088 +#define PEEENR_OFF 0x08c +#define PEESNR_OFF 0x090 +#define PEESTR_OFF 0x094 +#define PEIMR_OFF 0x098 +#define PEINT_OFF 0x09c + +/* Define the GPIO registers for use by device drivers and the kernel. */ +#define PADR (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF)) +#define PADDR (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF)) +#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF)) +#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF)) +#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF)) +#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF)) +#define PAIMR (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF)) +#define PAINT (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF)) + +#define PBDR (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF)) +#define PBDDR (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF)) +#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF)) +#define PBIMR (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF)) +#define PBINT (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF)) + +#define PCDR (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF)) +#define PCDDR (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF)) +#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF)) +#define PCIMR (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF)) +#define PCINT (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF)) + +#define PDDR (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF)) +#define PDDDR (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF)) +#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF)) +#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF)) +#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF)) +#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF)) +#define PDIMR (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF)) +#define PDINT (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF)) + +#define PEDR (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF)) +#define PEDDR (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF)) +#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF)) +#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF)) +#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF)) +#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF)) +#define PEIMR (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF)) +#define PEINT (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF)) + +#define VEE_EN 0x02 +#define BACKLIGHT_EN 0x04 diff --git a/trunk/arch/arm/mach-l7200/include/mach/hardware.h b/trunk/arch/arm/mach-l7200/include/mach/hardware.h new file mode 100644 index 000000000000..c31909cfc254 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/hardware.h @@ -0,0 +1,57 @@ +/* + * arch/arm/mach-l7200/include/mach/hardware.h + * + * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) + * Steve Hill (sjhill@cotw.com) + * + * This file contains the hardware definitions for the + * LinkUp Systems L7200 SOC development board. + * + * Changelog: + * 02-01-2000 RS Created L7200 version, derived from rpc code + * 03-21-2000 SJH Cleaned up file + * 04-21-2000 RS Changed mapping of I/O in virtual space + * 04-25-2000 SJH Removed unused symbols and such + * 05-05-2000 SJH Complete rewrite + * 07-31-2000 SJH Added undocumented debug auxillary port to + * get at last two columns for keyboard driver + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* Hardware addresses of major areas. + * *_START is the physical address + * *_SIZE is the size of the region + * *_BASE is the virtual address + */ +#define RAM_START 0xf0000000 +#define RAM_SIZE 0x02000000 +#define RAM_BASE 0xc0000000 + +#define IO_START 0x80000000 /* I/O */ +#define IO_SIZE 0x01000000 +#define IO_BASE 0xd0000000 + +#define IO_START_2 0x90000000 /* I/O */ +#define IO_SIZE_2 0x01000000 +#define IO_BASE_2 0xd1000000 + +#define AUX_START 0x1a000000 /* AUX PORT */ +#define AUX_SIZE 0x01000000 +#define AUX_BASE 0xd2000000 + +#define FLASH1_START 0x00000000 /* FLASH BANK 1 */ +#define FLASH1_SIZE 0x01000000 +#define FLASH1_BASE 0xd3000000 + +#define FLASH2_START 0x10000000 /* FLASH BANK 2 */ +#define FLASH2_SIZE 0x01000000 +#define FLASH2_BASE 0xd4000000 + +#define ISA_START 0x20000000 /* ISA */ +#define ISA_SIZE 0x20000000 +#define ISA_BASE 0xe0000000 + +#define PCIO_BASE IO_BASE + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/io.h b/trunk/arch/arm/mach-l7200/include/mach/io.h new file mode 100644 index 000000000000..a770a89fb708 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/io.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-l7200/include/mach/io.h + * + * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) + * + * Changelog: + * 03-21-2000 SJH Created from arch/arm/mach-nexuspci/include/mach/io.h + * 08-31-2000 SJH Added in IO functions necessary for new drivers + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * There are not real ISA nor PCI buses, so we fake it. + */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/irqs.h b/trunk/arch/arm/mach-l7200/include/mach/irqs.h new file mode 100644 index 000000000000..7edffd713c5b --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/irqs.h @@ -0,0 +1,56 @@ +/* + * arch/arm/mach-l7200/include/mach/irqs.h + * + * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) + * Steve Hill (sjhill@cotw.com) + * + * Changelog: + * 01-02-2000 RS Create l7200 version + * 03-28-2000 SJH Removed unused interrupt + * 07-28-2000 SJH Added pseudo-keyboard interrupt + */ + +/* + * NOTE: The second timer (Timer 2) is used as the keyboard + * interrupt when the keyboard driver is enabled. + */ + +#define NR_IRQS 32 + +#define IRQ_STWDOG 0 /* Watchdog timer */ +#define IRQ_PROG 1 /* Programmable interrupt */ +#define IRQ_DEBUG_RX 2 /* Comm Rx debug */ +#define IRQ_DEBUG_TX 3 /* Comm Tx debug */ +#define IRQ_GCTC1 4 /* Timer 1 */ +#define IRQ_GCTC2 5 /* Timer 2 / Keyboard */ +#define IRQ_DMA 6 /* DMA controller */ +#define IRQ_CLCD 7 /* Color LCD controller */ +#define IRQ_SM_RX 8 /* Smart card */ +#define IRQ_SM_TX 9 /* Smart cart */ +#define IRQ_SM_RST 10 /* Smart card */ +#define IRQ_SIB 11 /* Serial Interface Bus */ +#define IRQ_MMC 12 /* MultiMediaCard */ +#define IRQ_SSP1 13 /* Synchronous Serial Port 1 */ +#define IRQ_SSP2 14 /* Synchronous Serial Port 1 */ +#define IRQ_SPI 15 /* SPI slave */ +#define IRQ_UART_1 16 /* UART 1 */ +#define IRQ_UART_2 17 /* UART 2 */ +#define IRQ_IRDA 18 /* IRDA */ +#define IRQ_RTC_TICK 19 /* Real Time Clock tick */ +#define IRQ_RTC_ALARM 20 /* Real Time Clock alarm */ +#define IRQ_GPIO 21 /* General Purpose IO */ +#define IRQ_GPIO_DMA 22 /* General Purpose IO, DMA */ +#define IRQ_M2M 23 /* Memory to memory DMA */ +#define IRQ_RESERVED 24 /* RESERVED, don't use */ +#define IRQ_INTF 25 /* External active low interrupt */ +#define IRQ_INT0 26 /* External active low interrupt */ +#define IRQ_INT1 27 /* External active low interrupt */ +#define IRQ_INT2 28 /* External active low interrupt */ +#define IRQ_UCB1200 29 /* Interrupt generated by UCB1200*/ +#define IRQ_BAT_LO 30 /* Low batery or external power */ +#define IRQ_MEDIA_CHG 31 /* Media change interrupt */ + +/* + * This is the offset of the FIQ "IRQ" numbers + */ +#define FIQ_START 64 diff --git a/trunk/arch/arm/mach-l7200/include/mach/memory.h b/trunk/arch/arm/mach-l7200/include/mach/memory.h new file mode 100644 index 000000000000..9fb40ed2f03b --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/memory.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-l7200/include/mach/memory.h + * + * Copyright (c) 2000 Steve Hill (sjhill@cotw.com) + * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net) + * + * Changelog: + * 03-13-2000 SJH Created + * 04-13-2000 RS Changed bus macros for new addr + * 05-03-2000 SJH Removed bus macros and fixed virt_to_phys macro + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset on the L7200 SDB. + */ +#define PHYS_OFFSET UL(0xf0000000) + +/* + * Cache flushing area - ROM + */ +#define FLUSH_BASE_PHYS 0x40000000 +#define FLUSH_BASE 0xdf000000 + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/pmpcon.h b/trunk/arch/arm/mach-l7200/include/mach/pmpcon.h new file mode 100644 index 000000000000..3959871e8361 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/pmpcon.h @@ -0,0 +1,46 @@ +/****************************************************************************/ +/* + * arch/arm/mach-l7200/include/mach/pmpcon.h + * + * Registers and helper functions for the L7200 Link-Up Systems + * DC/DC converter register. + * + * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +/****************************************************************************/ + +#define PMPCON_OFF 0x00006000 /* Offset from IO_START_2. */ + +/* IO_START_2 and IO_BASE_2 are defined in hardware.h */ + +#define PMPCON_START (IO_START_2 + PMPCON_OFF) /* Physical address of reg. */ +#define PMPCON_BASE (IO_BASE_2 + PMPCON_OFF) /* Virtual address of reg. */ + + +#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE)) + +#define PWM2_50CYCLE 0x800 +#define CONTRAST 0x9 + +#define PWM1H (CONTRAST) +#define PWM1L (CONTRAST << 4) + +#define PMPCON_VALUE (PWM2_50CYCLE | PWM1L | PWM1H) + +/* PMPCON = 0x811; // too light and fuzzy + * PMPCON = 0x844; + * PMPCON = 0x866; // better color poor depth + * PMPCON = 0x888; // Darker but better depth + * PMPCON = 0x899; // Darker even better depth + * PMPCON = 0x8aa; // too dark even better depth + * PMPCON = 0X8cc; // Way too dark + */ + +/* As CONTRAST value increases the greater the depth perception and + * the darker the colors. + */ diff --git a/trunk/arch/arm/mach-l7200/include/mach/pmu.h b/trunk/arch/arm/mach-l7200/include/mach/pmu.h new file mode 100644 index 000000000000..a2da7aedf208 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/pmu.h @@ -0,0 +1,125 @@ +/****************************************************************************/ +/* + * arch/arm/mach-l7200/include/mach/pmu.h + * + * Registers and helper functions for the L7200 Link-Up Systems + * Power Management Unit (PMU). + * + * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +/****************************************************************************/ + +#define PMU_OFF 0x00050000 /* Offset from IO_START to the PMU registers. */ + +/* IO_START and IO_BASE are defined in hardware.h */ + +#define PMU_START (IO_START + PMU_OFF) /* Physical addr. of the PMU reg. */ +#define PMU_BASE (IO_BASE + PMU_OFF) /* Virtual addr. of the PMU reg. */ + + +/* Define the PMU registers for use by device drivers and the kernel. */ + +typedef struct { + unsigned int CURRENT; /* Current configuration register */ + unsigned int NEXT; /* Next configuration register */ + unsigned int reserved; + unsigned int RUN; /* Run configuration register */ + unsigned int COMM; /* Configuration command register */ + unsigned int SDRAM; /* SDRAM configuration bypass register */ +} pmu_interface; + +#define PMU ((volatile pmu_interface *)(PMU_BASE)) + + +/* Macro's for reading the common register fields. */ + +#define GET_TRANSOP(reg) ((reg >> 25) & 0x03) /* Bits 26-25 */ +#define GET_OSCEN(reg) ((reg >> 16) & 0x01) +#define GET_OSCMUX(reg) ((reg >> 15) & 0x01) +#define GET_PLLMUL(reg) ((reg >> 9) & 0x3f) /* Bits 14-9 */ +#define GET_PLLEN(reg) ((reg >> 8) & 0x01) +#define GET_PLLMUX(reg) ((reg >> 7) & 0x01) +#define GET_BCLK_DIV(reg) ((reg >> 3) & 0x03) /* Bits 4-3 */ +#define GET_SDRB_SEL(reg) ((reg >> 2) & 0x01) +#define GET_SDRF_SEL(reg) ((reg >> 1) & 0x01) +#define GET_FASTBUS(reg) (reg & 0x1) + +/* CFG_NEXT register */ + +#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f) /* Bits 24-18 */ +#define CFG_NEXT_INTRET ((PMU->NEXT >> 17) & 0x01) +#define CFG_NEXT_SDR_STOP ((PMU->NEXT >> 6) & 0x01) +#define CFG_NEXT_SYSCLKEN ((PMU->NEXT >> 5) & 0x01) + +/* Useful field values that can be used to construct the + * CFG_NEXT and CFG_RUN registers. + */ + +#define TRANSOP_NOP 0<<25 /* NOCHANGE_NOSTALL */ +#define NOCHANGE_STALL 1<<25 +#define CHANGE_NOSTALL 2<<25 +#define CHANGE_STALL 3<<25 + +#define INTRET 1<<17 +#define OSCEN 1<<16 +#define OSCMUX 1<<15 + +/* PLL frequencies */ + +#define PLLMUL_0 0<<9 /* 3.6864 MHz */ +#define PLLMUL_1 1<<9 /* ?????? MHz */ +#define PLLMUL_5 5<<9 /* 18.432 MHz */ +#define PLLMUL_10 10<<9 /* 36.864 MHz */ +#define PLLMUL_18 18<<9 /* ?????? MHz */ +#define PLLMUL_20 20<<9 /* 73.728 MHz */ +#define PLLMUL_32 32<<9 /* ?????? MHz */ +#define PLLMUL_35 35<<9 /* 129.024 MHz */ +#define PLLMUL_36 36<<9 /* ?????? MHz */ +#define PLLMUL_39 39<<9 /* ?????? MHz */ +#define PLLMUL_40 40<<9 /* 147.456 MHz */ + +/* Clock recovery times */ + +#define CRCLOCK_1 1<<18 +#define CRCLOCK_2 2<<18 +#define CRCLOCK_4 4<<18 +#define CRCLOCK_8 8<<18 +#define CRCLOCK_16 16<<18 +#define CRCLOCK_32 32<<18 +#define CRCLOCK_63 63<<18 +#define CRCLOCK_127 127<<18 + +#define PLLEN 1<<8 +#define PLLMUX 1<<7 +#define SDR_STOP 1<<6 +#define SYSCLKEN 1<<5 + +#define BCLK_DIV_4 2<<3 +#define BCLK_DIV_2 1<<3 +#define BCLK_DIV_1 0<<3 + +#define SDRB_SEL 1<<2 +#define SDRF_SEL 1<<1 +#define FASTBUS 1<<0 + + +/* CFG_SDRAM */ + +#define SDRREFFQ 1<<0 /* Only if SDRSTOPRQ is not set. */ +#define SDRREFACK 1<<1 /* Read-only */ +#define SDRSTOPRQ 1<<2 /* Only if SDRREFFQ is not set. */ +#define SDRSTOPACK 1<<3 /* Read-only */ +#define PICEN 1<<4 /* Enable Co-procesor */ +#define PICTEST 1<<5 + +#define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01) +#define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */ +#define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01) +#define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */ +#define GET_PICEN ((PMU->SDRAM >> 4) & 0x01) +#define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01) diff --git a/trunk/arch/arm/mach-l7200/include/mach/serial.h b/trunk/arch/arm/mach-l7200/include/mach/serial.h new file mode 100644 index 000000000000..adc05e5f8378 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/serial.h @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-l7200/include/mach/serial.h + * + * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net) + * Steve Hill (sjhill@cotw.com) + * + * Changelog: + * 03-20-2000 SJH Created + * 03-26-2000 SJH Added flags for serial ports + * 03-27-2000 SJH Corrected BASE_BAUD value + * 04-14-2000 RS Made register addr dependent on IO_BASE + * 05-03-2000 SJH Complete rewrite + * 05-09-2000 SJH Stripped out architecture specific serial stuff + * and placed it in a separate file + * 07-28-2000 SJH Moved base baud rate variable + */ +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +/* + * This assumes you have a 3.6864 MHz clock for your UART. + */ +#define BASE_BAUD 3686400 + +/* + * Standard COM flags + */ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + +#define STD_SERIAL_PORT_DEFNS \ + /* MAGIC UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS }, /* ttyLU0 */ \ + { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS }, /* ttyLU1 */ \ + +#define EXTRA_SERIAL_PORT_DEFNS + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/serial_l7200.h b/trunk/arch/arm/mach-l7200/include/mach/serial_l7200.h new file mode 100644 index 000000000000..645f1c5e568d --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/serial_l7200.h @@ -0,0 +1,101 @@ +/* + * arch/arm/mach-l7200/include/mach/serial_l7200.h + * + * Copyright (c) 2000 Steven Hill (sjhill@cotw.com) + * + * Changelog: + * 05-09-2000 SJH Created + */ +#ifndef __ASM_ARCH_SERIAL_L7200_H +#define __ASM_ARCH_SERIAL_L7200_H + +#include + +/* + * This assumes you have a 3.6864 MHz clock for your UART. + */ +#define BASE_BAUD 3686400 + +/* + * UART base register addresses + */ +#define UART1_BASE (IO_BASE + 0x00044000) +#define UART2_BASE (IO_BASE + 0x00045000) + +/* + * UART register offsets + */ +#define UARTDR 0x00 /* Tx/Rx data */ +#define RXSTAT 0x04 /* Rx status */ +#define H_UBRLCR 0x08 /* mode register high */ +#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/ +#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/ +#define UARTCON 0x14 /* control register */ +#define UARTFLG 0x18 /* flag register */ +#define UARTINTSTAT 0x1C /* FIFO IRQ status register */ +#define UARTINTMASK 0x20 /* FIFO IRQ mask register */ + +/* + * UART baud rate register values + */ +#define BR_110 0x827 +#define BR_1200 0x06e +#define BR_2400 0x05f +#define BR_4800 0x02f +#define BR_9600 0x017 +#define BR_14400 0x00f +#define BR_19200 0x00b +#define BR_38400 0x005 +#define BR_57600 0x003 +#define BR_76800 0x002 +#define BR_115200 0x001 + +/* + * Receiver status register (RXSTAT) mask values + */ +#define RXSTAT_NO_ERR 0x00 /* No error */ +#define RXSTAT_FRM_ERR 0x01 /* Framing error */ +#define RXSTAT_PAR_ERR 0x02 /* Parity error */ +#define RXSTAT_OVR_ERR 0x04 /* Overrun error */ + +/* + * High byte of UART bit rate and line control register (H_UBRLCR) values + */ +#define UBRLCR_BRK 0x01 /* generate break on tx */ +#define UBRLCR_PEN 0x02 /* enable parity */ +#define UBRLCR_PDIS 0x00 /* disable parity */ +#define UBRLCR_EVEN 0x04 /* 1= even parity,0 = odd parity */ +#define UBRLCR_STP2 0x08 /* transmit 2 stop bits */ +#define UBRLCR_FIFO 0x10 /* enable FIFO */ +#define UBRLCR_LEN5 0x60 /* word length5 */ +#define UBRLCR_LEN6 0x40 /* word length6 */ +#define UBRLCR_LEN7 0x20 /* word length7 */ +#define UBRLCR_LEN8 0x00 /* word length8 */ + +/* + * UART control register (UARTCON) values + */ +#define UARTCON_UARTEN 0x01 /* Enable UART */ +#define UARTCON_DMAONERR 0x08 /* Mask RxDmaRq when errors occur */ + +/* + * UART flag register (UARTFLG) mask values + */ +#define UARTFLG_UTXFF 0x20 /* Transmit FIFO full */ +#define UARTFLG_URXFE 0x10 /* Receiver FIFO empty */ +#define UARTFLG_UBUSY 0x08 /* Transmitter busy */ +#define UARTFLG_DCD 0x04 /* Data carrier detect */ +#define UARTFLG_DSR 0x02 /* Data set ready */ +#define UARTFLG_CTS 0x01 /* Clear to send */ + +/* + * UART interrupt status/clear registers (UARTINTSTAT/CLR) values + */ +#define UART_TXINT 0x01 /* TX interrupt */ +#define UART_RXINT 0x02 /* RX interrupt */ +#define UART_RXERRINT 0x04 /* RX error interrupt */ +#define UART_MSINT 0x08 /* Modem Status interrupt */ +#define UART_UDINT 0x10 /* UART Disabled interrupt */ +#define UART_ALLIRQS 0x1f /* All interrupts */ + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/sib.h b/trunk/arch/arm/mach-l7200/include/mach/sib.h new file mode 100644 index 000000000000..965728712cf3 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/sib.h @@ -0,0 +1,119 @@ +/****************************************************************************/ +/* + * arch/arm/mach-l7200/include/mach/sib.h + * + * Registers and helper functions for the Serial Interface Bus. + * + * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +/****************************************************************************/ + +#define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */ + +/* IO_START and IO_BASE are defined in hardware.h */ + +#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */ +#define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */ + +/* Offsets from the start of the SIB for all the registers. */ + +/* Define the SIB registers for use by device drivers and the kernel. */ + +typedef struct +{ + unsigned int MCCR; /* SIB Control Register Offset: 0x00 */ + unsigned int RES1; /* Reserved Offset: 0x04 */ + unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */ + unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */ + unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */ + unsigned int RES2; /* Reserved Offset: 0x14 */ + unsigned int MCSR; /* SIB Status Register Offset: 0x18 */ +} SIB_Interface; + +#define SIB ((volatile SIB_Interface *) (SIB_BASE)) + +/* MCCR */ + +#define INTERNAL_FREQ 9216000 /* Hertz */ +#define AUDIO_FREQ 5000 /* Hertz */ +#define TELECOM_FREQ 5000 /* Hertz */ + +#define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ)) +#define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ)) + +#define MCCR_ASD57 AUDIO_DIVIDE +#define MCCR_TSD57 (TELECOM_DIVIDE << 8) +#define MCCR_MCE (1 << 16) /* SIB enable */ +#define MCCR_ECS (1 << 17) /* External Clock Select */ +#define MCCR_ADM (1 << 18) /* A/D Data Sampling */ +#define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */ + + +#define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */ +#define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */ +#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */ +#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */ +#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */ +#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ +#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */ +#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ +#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */ +#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */ +#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */ +#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */ +#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */ +#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */ + +/* MCDR0 */ + +#define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff) +#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4)) + +/* MCDR1 */ + +#define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff) +#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2)) + + +/* MCSR */ + +#define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */ +#define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */ +#define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */ +#define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */ + +#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO) + + +#define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/ +#define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/ +#define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */ +#define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */ +#define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */ +#define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */ +#define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */ +#define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */ +#define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */ +#define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */ +#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */ +#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */ +#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */ +#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */ +#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */ +#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */ + +/* MCDR2 */ + +#define MCDR2_rW (1 << 16) + +#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff))) +#define MCDR2_WRITE_COMPLETE GET_CWC + +#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17)) +#define MCDR2_READ_COMPLETE GET_CRC +#define MCDR2_READ (SIB->MCDR2 & 0xffff) diff --git a/trunk/arch/arm/mach-l7200/include/mach/sys-clock.h b/trunk/arch/arm/mach-l7200/include/mach/sys-clock.h new file mode 100644 index 000000000000..e9729a35751d --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/sys-clock.h @@ -0,0 +1,67 @@ +/****************************************************************************/ +/* + * arch/arm/mach-l7200/include/mach/sys-clock.h + * + * Registers and helper functions for the L7200 Link-Up Systems + * System clocks. + * + * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +/****************************************************************************/ + +#define SYS_CLOCK_OFF 0x00050030 /* Offset from IO_START. */ + +/* IO_START and IO_BASE are defined in hardware.h */ + +#define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF) /* Physical address */ +#define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */ + +/* Define the interface to the SYS_CLOCK */ + +typedef struct +{ + unsigned int ENABLE; + unsigned int ESYNC; + unsigned int SELECT; +} sys_clock_interface; + +#define SYS_CLOCK ((volatile sys_clock_interface *)(SYS_CLOCK_BASE)) + +//#define CLOCK_EN (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF)) +//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF)) +//#define CLOCK_SEL (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF)) + +/* SYS_CLOCK -> ENABLE */ + +#define SYN_EN 1<<0 +#define B18M_EN 1<<1 +#define CLK3M6_EN 1<<2 +#define BUART_EN 1<<3 +#define CLK18MU_EN 1<<4 +#define FIR_EN 1<<5 +#define MIRN_EN 1<<6 +#define UARTM_EN 1<<7 +#define SIBADC_EN 1<<8 +#define ALTD_EN 1<<9 +#define CLCLK_EN 1<<10 + +/* SYS_CLOCK -> SELECT */ + +#define CLK18M_DIV 1<<0 +#define MIR_SEL 1<<1 +#define SSP_SEL 1<<4 +#define MM_DIV 1<<5 +#define MM_SEL 1<<6 +#define ADC_SEL_2 0<<7 +#define ADC_SEL_4 1<<7 +#define ADC_SEL_8 3<<7 +#define ADC_SEL_16 7<<7 +#define ADC_SEL_32 0x0f<<7 +#define ADC_SEL_64 0x1f<<7 +#define ADC_SEL_128 0x3f<<7 +#define ALTD_SEL 1<<13 diff --git a/trunk/arch/arm/mach-l7200/include/mach/system.h b/trunk/arch/arm/mach-l7200/include/mach/system.h new file mode 100644 index 000000000000..e0dd3b6ae4aa --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/system.h @@ -0,0 +1,29 @@ +/* + * arch/arm/mach-l7200/include/mach/system.h + * + * Copyright (c) 2000 Steve Hill (sjhill@cotw.com) + * + * Changelog + * 03-21-2000 SJH Created + * 04-26-2000 SJH Fixed functions + * 05-03-2000 SJH Removed usage of obsolete 'iomd.h' + * 05-31-2000 SJH Properly implemented 'arch_idle' + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include + +static inline void arch_idle(void) +{ + *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */ +} + +static inline void arch_reset(char mode, const char *cmd) +{ + if (mode == 's') { + cpu_reset(0); + } +} + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/time.h b/trunk/arch/arm/mach-l7200/include/mach/time.h new file mode 100644 index 000000000000..061771c2c2bd --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/time.h @@ -0,0 +1,73 @@ +/* + * arch/arm/mach-l7200/include/mach/time.h + * + * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) + * Steve Hill (sjhill@cotw.com) + * + * Changelog: + * 01-02-2000 RS Created l7200 version, derived from rpc code + * 05-03-2000 SJH Complete rewrite + */ +#ifndef _ASM_ARCH_TIME_H +#define _ASM_ARCH_TIME_H + +#include + +/* + * RTC base register address + */ +#define RTC_BASE (IO_BASE_2 + 0x2000) + +/* + * RTC registers + */ +#define RTC_RTCDR (*(volatile unsigned char *) (RTC_BASE + 0x000)) +#define RTC_RTCMR (*(volatile unsigned char *) (RTC_BASE + 0x004)) +#define RTC_RTCS (*(volatile unsigned char *) (RTC_BASE + 0x008)) +#define RTC_RTCC (*(volatile unsigned char *) (RTC_BASE + 0x008)) +#define RTC_RTCDV (*(volatile unsigned char *) (RTC_BASE + 0x00c)) +#define RTC_RTCCR (*(volatile unsigned char *) (RTC_BASE + 0x010)) + +/* + * RTCCR register values + */ +#define RTC_RATE_32 0x00 /* 32 Hz tick */ +#define RTC_RATE_64 0x10 /* 64 Hz tick */ +#define RTC_RATE_128 0x20 /* 128 Hz tick */ +#define RTC_RATE_256 0x30 /* 256 Hz tick */ +#define RTC_EN_ALARM 0x01 /* Enable alarm */ +#define RTC_EN_TIC 0x04 /* Enable counter */ +#define RTC_EN_STWDOG 0x08 /* Enable watchdog */ + +/* + * Handler for RTC timer interrupt + */ +static irqreturn_t +timer_interrupt(int irq, void *dev_id) +{ + struct pt_regs *regs = get_irq_regs(); + do_timer(1); +#ifndef CONFIG_SMP + update_process_times(user_mode(regs)); +#endif + do_profile(regs); + RTC_RTCC = 0; /* Clear interrupt */ + + return IRQ_HANDLED; +} + +/* + * Set up RTC timer interrupt, and return the current time in seconds. + */ +void __init time_init(void) +{ + RTC_RTCC = 0; /* Clear interrupt */ + + timer_irq.handler = timer_interrupt; + + setup_irq(IRQ_RTC_TICK, &timer_irq); + + RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC; /* Set rate and enable timer */ +} + +#endif diff --git a/trunk/arch/arm/mach-l7200/include/mach/timex.h b/trunk/arch/arm/mach-l7200/include/mach/timex.h new file mode 100644 index 000000000000..ffc96a63b5a2 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/timex.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-l7200/include/mach/timex.h + * + * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) + * Steve Hill (sjhill@cotw.com) + * + * 04-21-2000 RS Created file + * 05-03-2000 SJH Tick rate was wrong + * + */ + +/* + * On the ARM720T, clock ticks are set to 128 Hz. + * + * NOTE: The actual RTC value is set in 'time.h' which + * must be changed when choosing a different tick + * rate. The value of HZ in 'param.h' must also + * be changed to match below. + */ +#define CLOCK_TICK_RATE 128 diff --git a/trunk/arch/arm/mach-l7200/include/mach/uncompress.h b/trunk/arch/arm/mach-l7200/include/mach/uncompress.h new file mode 100644 index 000000000000..591c962bb315 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/uncompress.h @@ -0,0 +1,39 @@ +/* + * arch/arm/mach-l7200/include/mach/uncompress.h + * + * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) + * + * Changelog: + * 05-01-2000 SJH Created + * 05-13-2000 SJH Filled in function bodies + * 07-26-2000 SJH Removed hard coded baud rate + */ + +#include + +#define IO_UART IO_START + 0x00044000 + +#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v)) +#define __raw_readb(p) (*(volatile unsigned char *)(p)) + +static inline void putc(int c) +{ + while(__raw_readb(IO_UART + 0x18) & 0x20 || + __raw_readb(IO_UART + 0x18) & 0x08) + barrier(); + + __raw_writeb(c, IO_UART + 0x00); +} + +static inline void flush(void) +{ +} + +static __inline__ void arch_decomp_setup(void) +{ + __raw_writeb(0x00, IO_UART + 0x08); /* Set HSB */ + __raw_writeb(0x00, IO_UART + 0x20); /* Disable IRQs */ + __raw_writeb(0x01, IO_UART + 0x14); /* Enable UART */ +} + +#define arch_decomp_wdog() diff --git a/trunk/arch/arm/mach-l7200/include/mach/vmalloc.h b/trunk/arch/arm/mach-l7200/include/mach/vmalloc.h new file mode 100644 index 000000000000..85f0abbf15f1 --- /dev/null +++ b/trunk/arch/arm/mach-l7200/include/mach/vmalloc.h @@ -0,0 +1,4 @@ +/* + * arch/arm/mach-l7200/include/mach/vmalloc.h + */ +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/trunk/arch/arm/mach-lh7a40x/include/mach/memory.h b/trunk/arch/arm/mach-lh7a40x/include/mach/memory.h index edb8f5faf5d5..189d20e543e7 100644 --- a/trunk/arch/arm/mach-lh7a40x/include/mach/memory.h +++ b/trunk/arch/arm/mach-lh7a40x/include/mach/memory.h @@ -19,6 +19,50 @@ */ #define PHYS_OFFSET UL(0xc0000000) +#ifdef CONFIG_DISCONTIGMEM + +/* + * Given a kernel address, find the home node of the underlying memory. + */ + +# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE +# define KVADDR_TO_NID(addr) \ + ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\ + | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1)) +# else /* 2 banks per node */ +# define KVADDR_TO_NID(addr) \ + (((unsigned long) (addr) - PAGE_OFFSET) >> 26) +# endif + +/* + * Given a page frame number, convert it to a node id. + */ + +# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE +# define PFN_TO_NID(pfn) \ + (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\ + | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1)) +# else /* 2 banks per node */ +# define PFN_TO_NID(pfn) \ + (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT)) +#endif + +/* + * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory + * and returns the index corresponding to the appropriate page in the + * node's mem_map. + */ + +# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE +# define LOCAL_MAP_NR(addr) \ + (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT) +# else /* 2 banks per node */ +# define LOCAL_MAP_NR(addr) \ + (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT) +# endif + +#endif + /* * Sparsemem version of the above */ diff --git a/trunk/arch/arm/mach-lpc32xx/Kconfig b/trunk/arch/arm/mach-lpc32xx/Kconfig deleted file mode 100644 index fde663508696..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/Kconfig +++ /dev/null @@ -1,33 +0,0 @@ -if ARCH_LPC32XX - -menu "Individual UART enable selections" - -config ARCH_LPC32XX_UART3_SELECT - bool "Add support for standard UART3" - help - Adds support for standard UART 3 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART4_SELECT - bool "Add support for standard UART4" - help - Adds support for standard UART 4 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART5_SELECT - bool "Add support for standard UART5" - default y - help - Adds support for standard UART 5 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART6_SELECT - bool "Add support for standard UART6" - help - Adds support for standard UART 6 when the 8250 serial support - is enabled. - -endmenu - -endif - diff --git a/trunk/arch/arm/mach-lpc32xx/Makefile b/trunk/arch/arm/mach-lpc32xx/Makefile deleted file mode 100644 index a5fc5d0eeaeb..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-y := timer.o irq.o common.o serial.o clock.o -obj-y += gpiolib.o pm.o suspend.o -obj-y += phy3250.o - diff --git a/trunk/arch/arm/mach-lpc32xx/Makefile.boot b/trunk/arch/arm/mach-lpc32xx/Makefile.boot deleted file mode 100644 index b796b41ebf8f..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ - zreladdr-y := 0x80008000 -params_phys-y := 0x80000100 -initrd_phys-y := 0x82000000 - diff --git a/trunk/arch/arm/mach-lpc32xx/clock.c b/trunk/arch/arm/mach-lpc32xx/clock.c deleted file mode 100644 index 32d63796430a..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/clock.c +++ /dev/null @@ -1,1137 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/clock.c - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * LPC32xx clock management driver overview - * - * The LPC32XX contains a number of high level system clocks that can be - * generated from different sources. These system clocks are used to - * generate the CPU and bus rates and the individual peripheral clocks in - * the system. When Linux is started by the boot loader, the system - * clocks are already running. Stopping a system clock during normal - * Linux operation should never be attempted, as peripherals that require - * those clocks will quit working (ie, DRAM). - * - * The LPC32xx high level clock tree looks as follows. Clocks marked with - * an asterisk are always on and cannot be disabled. Clocks marked with - * an ampersand can only be disabled in CPU suspend mode. Clocks marked - * with a caret are always on if it is the selected clock for the SYSCLK - * source. The clock that isn't used for SYSCLK can be enabled and - * disabled normally. - * 32KHz oscillator* - * / | \ - * RTC* PLL397^ TOUCH - * / - * Main oscillator^ / - * | \ / - * | SYSCLK& - * | \ - * | \ - * USB_PLL HCLK_PLL& - * | | | - * USB host/device PCLK& | - * | | - * Peripherals - * - * The CPU and chip bus rates are derived from the HCLK PLL, which can - * generate various clock rates up to 266MHz and beyond. The internal bus - * rates (PCLK and HCLK) are generated from dividers based on the HCLK - * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate, - * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high - * level clocks are based on either HCLK or PCLK, but have their own - * dividers as part of the IP itself. Because of this, the system clock - * rates should not be changed. - * - * The HCLK PLL is clocked from SYSCLK, which can be derived from the - * main oscillator or PLL397. PLL397 generates a rate that is 397 times - * the 32KHz oscillator rate. The main oscillator runs at the selected - * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate - * is normally 13MHz, but depends on the selection of external crystals - * or oscillators. If USB operation is required, the main oscillator must - * be used in the system. - * - * Switching SYSCLK between sources during normal Linux operation is not - * supported. SYSCLK is preset in the bootloader. Because of the - * complexities of clock management during clock frequency changes, - * there are some limitations to the clock driver explained below: - * - The PLL397 and main oscillator can be enabled and disabled by the - * clk_enable() and clk_disable() functions unless SYSCLK is based - * on that clock. This allows the other oscillator that isn't driving - * the HCLK PLL to be used as another system clock that can be routed - * to an external pin. - * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with - * this driver. - * - HCLK and PCLK rates cannot be changed as part of this driver. - * - Most peripherals have their own dividers are part of the peripheral - * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates - * will also impact the individual peripheral rates. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include "clock.h" -#include "common.h" - -static struct clk clk_armpll; -static struct clk clk_usbpll; -static DEFINE_MUTEX(clkm_lock); - -/* - * Post divider values for PLLs based on selected register value - */ -static const u32 pll_postdivs[4] = {1, 2, 4, 8}; - -static unsigned long local_return_parent_rate(struct clk *clk) -{ - /* - * If a clock has a rate of 0, then it inherits it's parent - * clock rate - */ - while (clk->rate == 0) - clk = clk->parent; - - return clk->rate; -} - -/* 32KHz clock has a fixed rate and is not stoppable */ -static struct clk osc_32KHz = { - .rate = LPC32XX_CLOCK_OSC_FREQ, - .get_rate = local_return_parent_rate, -}; - -static int local_pll397_enable(struct clk *clk, int enable) -{ - u32 reg; - unsigned long timeout = 1 + msecs_to_jiffies(10); - - reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL); - - if (enable == 0) { - reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS; - __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL); - } else { - /* Enable PLL397 */ - reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS; - __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL); - - /* Wait for PLL397 lock */ - while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & - LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) && - (timeout > jiffies)) - cpu_relax(); - - if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & - LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) - return -ENODEV; - } - - return 0; -} - -static int local_oscmain_enable(struct clk *clk, int enable) -{ - u32 reg; - unsigned long timeout = 1 + msecs_to_jiffies(10); - - reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL); - - if (enable == 0) { - reg |= LPC32XX_CLKPWR_MOSC_DISABLE; - __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL); - } else { - /* Enable main oscillator */ - reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE; - __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL); - - /* Wait for main oscillator to start */ - while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & - LPC32XX_CLKPWR_MOSC_DISABLE) != 0) && - (timeout > jiffies)) - cpu_relax(); - - if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & - LPC32XX_CLKPWR_MOSC_DISABLE) != 0) - return -ENODEV; - } - - return 0; -} - -static struct clk osc_pll397 = { - .parent = &osc_32KHz, - .enable = local_pll397_enable, - .rate = LPC32XX_CLOCK_OSC_FREQ * 397, - .get_rate = local_return_parent_rate, -}; - -static struct clk osc_main = { - .enable = local_oscmain_enable, - .rate = LPC32XX_MAIN_OSC_FREQ, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_sys; - -/* - * Convert a PLL register value to a PLL output frequency - */ -u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval) -{ - struct clk_pll_setup pllcfg; - - pllcfg.cco_bypass_b15 = 0; - pllcfg.direct_output_b14 = 0; - pllcfg.fdbk_div_ctrl_b13 = 0; - if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0) - pllcfg.cco_bypass_b15 = 1; - if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0) - pllcfg.direct_output_b14 = 1; - if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0) - pllcfg.fdbk_div_ctrl_b13 = 1; - pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF); - pllcfg.pll_n = 1 + ((regval >> 9) & 0x3); - pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)]; - - return clk_check_pll_setup(inputclk, &pllcfg); -} - -/* - * Setup the HCLK PLL with a PLL structure - */ -static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup) -{ - u32 tv, tmp = 0; - - if (PllSetup->analog_on != 0) - tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP; - if (PllSetup->cco_bypass_b15 != 0) - tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS; - if (PllSetup->direct_output_b14 != 0) - tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS; - if (PllSetup->fdbk_div_ctrl_b13 != 0) - tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK; - - tv = ffs(PllSetup->pll_p) - 1; - if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3)) - return 0; - - tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv); - tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1); - tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1); - - return tmp; -} - -/* - * Update the ARM core PLL frequency rate variable from the actual PLL setting - */ -static void local_update_armpll_rate(void) -{ - u32 clkin, pllreg; - - clkin = clk_armpll.parent->rate; - pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF; - - clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg); -} - -/* - * Find a PLL configuration for the selected input frequency - */ -static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq, - struct clk_pll_setup *pllsetup) -{ - u32 ifreq, freqtol, m, n, p, fclkout; - - /* Determine frequency tolerance limits */ - freqtol = target_freq / 250; - ifreq = pllin_freq; - - /* Is direct bypass mode possible? */ - if (abs(pllin_freq - target_freq) <= freqtol) { - pllsetup->analog_on = 0; - pllsetup->cco_bypass_b15 = 1; - pllsetup->direct_output_b14 = 1; - pllsetup->fdbk_div_ctrl_b13 = 1; - pllsetup->pll_p = pll_postdivs[0]; - pllsetup->pll_n = 1; - pllsetup->pll_m = 1; - return clk_check_pll_setup(ifreq, pllsetup); - } else if (target_freq <= ifreq) { - pllsetup->analog_on = 0; - pllsetup->cco_bypass_b15 = 1; - pllsetup->direct_output_b14 = 0; - pllsetup->fdbk_div_ctrl_b13 = 1; - pllsetup->pll_n = 1; - pllsetup->pll_m = 1; - for (p = 0; p <= 3; p++) { - pllsetup->pll_p = pll_postdivs[p]; - fclkout = clk_check_pll_setup(ifreq, pllsetup); - if (abs(target_freq - fclkout) <= freqtol) - return fclkout; - } - } - - /* Is direct mode possible? */ - pllsetup->analog_on = 1; - pllsetup->cco_bypass_b15 = 0; - pllsetup->direct_output_b14 = 1; - pllsetup->fdbk_div_ctrl_b13 = 0; - pllsetup->pll_p = pll_postdivs[0]; - for (m = 1; m <= 256; m++) { - for (n = 1; n <= 4; n++) { - /* Compute output frequency for this value */ - pllsetup->pll_n = n; - pllsetup->pll_m = m; - fclkout = clk_check_pll_setup(ifreq, - pllsetup); - if (abs(target_freq - fclkout) <= - freqtol) - return fclkout; - } - } - - /* Is integer mode possible? */ - pllsetup->analog_on = 1; - pllsetup->cco_bypass_b15 = 0; - pllsetup->direct_output_b14 = 0; - pllsetup->fdbk_div_ctrl_b13 = 1; - for (m = 1; m <= 256; m++) { - for (n = 1; n <= 4; n++) { - for (p = 0; p < 4; p++) { - /* Compute output frequency */ - pllsetup->pll_p = pll_postdivs[p]; - pllsetup->pll_n = n; - pllsetup->pll_m = m; - fclkout = clk_check_pll_setup( - ifreq, pllsetup); - if (abs(target_freq - fclkout) <= freqtol) - return fclkout; - } - } - } - - /* Try non-integer mode */ - pllsetup->analog_on = 1; - pllsetup->cco_bypass_b15 = 0; - pllsetup->direct_output_b14 = 0; - pllsetup->fdbk_div_ctrl_b13 = 0; - for (m = 1; m <= 256; m++) { - for (n = 1; n <= 4; n++) { - for (p = 0; p < 4; p++) { - /* Compute output frequency */ - pllsetup->pll_p = pll_postdivs[p]; - pllsetup->pll_n = n; - pllsetup->pll_m = m; - fclkout = clk_check_pll_setup( - ifreq, pllsetup); - if (abs(target_freq - fclkout) <= freqtol) - return fclkout; - } - } - } - - return 0; -} - -static struct clk clk_armpll = { - .parent = &clk_sys, - .get_rate = local_return_parent_rate, -}; - -/* - * Setup the USB PLL with a PLL structure - */ -static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup) -{ - u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup); - - reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF; - reg |= tmp; - __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); - - return clk_check_pll_setup(clk_usbpll.parent->rate, - pHCLKPllSetup); -} - -static int local_usbpll_enable(struct clk *clk, int enable) -{ - u32 reg; - int ret = -ENODEV; - unsigned long timeout = 1 + msecs_to_jiffies(10); - - reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); - - if (enable == 0) { - reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 | - LPC32XX_CLKPWR_USBCTRL_CLK_EN2); - __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); - } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) { - reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1; - __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); - - /* Wait for PLL lock */ - while ((timeout > jiffies) & (ret == -ENODEV)) { - reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); - if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS) - ret = 0; - } - - if (ret == 0) { - reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2; - __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); - } - } - - return ret; -} - -static unsigned long local_usbpll_round_rate(struct clk *clk, - unsigned long rate) -{ - u32 clkin, usbdiv; - struct clk_pll_setup pllsetup; - - /* - * Unlike other clocks, this clock has a KHz input rate, so bump - * it up to work with the PLL function - */ - rate = rate * 1000; - - clkin = clk->parent->rate; - usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) & - LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1; - clkin = clkin / usbdiv; - - /* Try to find a good rate setup */ - if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0) - return 0; - - return clk_check_pll_setup(clkin, &pllsetup); -} - -static int local_usbpll_set_rate(struct clk *clk, unsigned long rate) -{ - u32 clkin, reg, usbdiv; - struct clk_pll_setup pllsetup; - - /* - * Unlike other clocks, this clock has a KHz input rate, so bump - * it up to work with the PLL function - */ - rate = rate * 1000; - - clkin = clk->get_rate(clk); - usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) & - LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1; - clkin = clkin / usbdiv; - - /* Try to find a good rate setup */ - if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0) - return -EINVAL; - - local_usbpll_enable(clk, 0); - - reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); - reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1; - __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); - - pllsetup.analog_on = 1; - local_clk_usbpll_setup(&pllsetup); - - clk->rate = clk_check_pll_setup(clkin, &pllsetup); - - reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); - reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2; - __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); - - return 0; -} - -static struct clk clk_usbpll = { - .parent = &osc_main, - .set_rate = local_usbpll_set_rate, - .enable = local_usbpll_enable, - .rate = 48000, /* In KHz */ - .get_rate = local_return_parent_rate, - .round_rate = local_usbpll_round_rate, -}; - -static u32 clk_get_hclk_div(void) -{ - static const u32 hclkdivs[4] = {1, 2, 4, 4}; - return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW( - __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))]; -} - -static struct clk clk_hclk = { - .parent = &clk_armpll, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_pclk = { - .parent = &clk_armpll, - .get_rate = local_return_parent_rate, -}; - -static int local_onoff_enable(struct clk *clk, int enable) -{ - u32 tmp; - - tmp = __raw_readl(clk->enable_reg); - - if (enable == 0) - tmp &= ~clk->enable_mask; - else - tmp |= clk->enable_mask; - - __raw_writel(tmp, clk->enable_reg); - - return 0; -} - -/* Peripheral clock sources */ -static struct clk clk_timer0 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, - .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN, - .get_rate = local_return_parent_rate, -}; -static struct clk clk_timer1 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, - .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN, - .get_rate = local_return_parent_rate, -}; -static struct clk clk_timer2 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, - .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN, - .get_rate = local_return_parent_rate, -}; -static struct clk clk_timer3 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, - .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN, - .get_rate = local_return_parent_rate, -}; -static struct clk clk_wdt = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN, - .get_rate = local_return_parent_rate, -}; -static struct clk clk_vfp9 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL, - .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT, - .get_rate = local_return_parent_rate, -}; -static struct clk clk_dma = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_uart3 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_uart4 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_uart5 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_uart6 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_i2c0 = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_i2c1 = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_i2c2 = { - .parent = &clk_pclk, - .enable = local_onoff_enable, - .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4), - .enable_mask = 0x4, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_ssp0 = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_ssp1 = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_kscan = { - .parent = &osc_32KHz, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_nand = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_i2s0 = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_i2s1 = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_net = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL, - .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN | - LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN | - LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN), - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_rtc = { - .parent = &osc_32KHz, - .rate = 1, /* 1 Hz */ - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_usbd = { - .parent = &clk_usbpll, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_USB_CTRL, - .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, - .get_rate = local_return_parent_rate, -}; - -static int tsc_onoff_enable(struct clk *clk, int enable) -{ - u32 tmp; - - /* Make sure 32KHz clock is the selected clock */ - tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1); - tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL; - __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1); - - if (enable == 0) - __raw_writel(0, clk->enable_reg); - else - __raw_writel(clk->enable_mask, clk->enable_reg); - - return 0; -} - -static struct clk clk_tsc = { - .parent = &osc_32KHz, - .enable = tsc_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN, - .get_rate = local_return_parent_rate, -}; - -static int mmc_onoff_enable(struct clk *clk, int enable) -{ - u32 tmp; - - tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & - ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; - - /* If rate is 0, disable clock */ - if (enable != 0) - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; - - __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); - - return 0; -} - -static unsigned long mmc_get_rate(struct clk *clk) -{ - u32 div, rate, oldclk; - - /* The MMC clock must be on when accessing an MMC register */ - oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); - __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, - LPC32XX_CLKPWR_MS_CTRL); - div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); - __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); - - /* Get the parent clock rate */ - rate = clk->parent->get_rate(clk->parent); - - /* Get the MMC controller clock divider value */ - div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); - - if (!div) - div = 1; - - return rate / div; -} - -static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long div, prate; - - /* Get the parent clock rate */ - prate = clk->parent->get_rate(clk->parent); - - if (rate >= prate) - return prate; - - div = prate / rate; - if (div > 0xf) - div = 0xf; - - return prate / div; -} - -static int mmc_set_rate(struct clk *clk, unsigned long rate) -{ - u32 oldclk, tmp; - unsigned long prate, div, crate = mmc_round_rate(clk, rate); - - prate = clk->parent->get_rate(clk->parent); - - div = prate / crate; - - /* The MMC clock must be on when accessing an MMC register */ - oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); - __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, - LPC32XX_CLKPWR_MS_CTRL); - tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & - ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div); - __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); - - __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); - - return 0; -} - -static struct clk clk_mmc = { - .parent = &clk_armpll, - .set_rate = mmc_set_rate, - .get_rate = mmc_get_rate, - .round_rate = mmc_round_rate, - .enable = mmc_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_MS_CTRL, - .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN, -}; - -static unsigned long clcd_get_rate(struct clk *clk) -{ - u32 tmp, div, rate, oldclk; - - /* The LCD clock must be on when accessing an LCD register */ - oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); - __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN, - LPC32XX_CLKPWR_LCDCLK_CTRL); - tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)); - __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL); - - rate = clk->parent->get_rate(clk->parent); - - /* Only supports internal clocking */ - if (tmp & TIM2_BCD) - return rate; - - div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22); - tmp = rate / (2 + div); - - return tmp; -} - -static int clcd_set_rate(struct clk *clk, unsigned long rate) -{ - u32 tmp, prate, div, oldclk; - - /* The LCD clock must be on when accessing an LCD register */ - oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); - __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN, - LPC32XX_CLKPWR_LCDCLK_CTRL); - - tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD; - prate = clk->parent->get_rate(clk->parent); - - if (rate < prate) { - /* Find closest divider */ - div = prate / rate; - if (div >= 2) { - div -= 2; - tmp &= ~TIM2_BCD; - } - - tmp &= ~(0xF800001F); - tmp |= (div & 0x1F); - tmp |= (((div >> 5) & 0x1F) << 27); - } - - __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)); - __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL); - - return 0; -} - -static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate) -{ - u32 prate, div; - - prate = clk->parent->get_rate(clk->parent); - - if (rate >= prate) - rate = prate; - else { - div = prate / rate; - if (div > 0x3ff) - div = 0x3ff; - - rate = prate / div; - } - - return rate; -} - -static struct clk clk_lcd = { - .parent = &clk_hclk, - .set_rate = clcd_set_rate, - .get_rate = clcd_get_rate, - .round_rate = clcd_round_rate, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN, -}; - -static inline void clk_lock(void) -{ - mutex_lock(&clkm_lock); -} - -static inline void clk_unlock(void) -{ - mutex_unlock(&clkm_lock); -} - -static void local_clk_disable(struct clk *clk) -{ - WARN_ON(clk->usecount == 0); - - /* Don't attempt to disable clock if it has no users */ - if (clk->usecount > 0) { - clk->usecount--; - - /* Only disable clock when it has no more users */ - if ((clk->usecount == 0) && (clk->enable)) - clk->enable(clk, 0); - - /* Check parent clocks, they may need to be disabled too */ - if (clk->parent) - local_clk_disable(clk->parent); - } -} - -static int local_clk_enable(struct clk *clk) -{ - int ret = 0; - - /* Enable parent clocks first and update use counts */ - if (clk->parent) - ret = local_clk_enable(clk->parent); - - if (!ret) { - /* Only enable clock if it's currently disabled */ - if ((clk->usecount == 0) && (clk->enable)) - ret = clk->enable(clk, 1); - - if (!ret) - clk->usecount++; - else if (clk->parent) - local_clk_disable(clk->parent); - } - - return ret; -} - -/* - * clk_enable - inform the system when the clock source should be running. - */ -int clk_enable(struct clk *clk) -{ - int ret; - - clk_lock(); - ret = local_clk_enable(clk); - clk_unlock(); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -/* - * clk_disable - inform the system when the clock source is no longer required - */ -void clk_disable(struct clk *clk) -{ - clk_lock(); - local_clk_disable(clk); - clk_unlock(); -} -EXPORT_SYMBOL(clk_disable); - -/* - * clk_get_rate - obtain the current clock rate (in Hz) for a clock source - */ -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long rate; - - clk_lock(); - rate = clk->get_rate(clk); - clk_unlock(); - - return rate; -} -EXPORT_SYMBOL(clk_get_rate); - -/* - * clk_set_rate - set the clock rate for a clock source - */ -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - /* - * Most system clocks can only be enabled or disabled, with - * the actual rate set as part of the peripheral dividers - * instead of high level clock control - */ - if (clk->set_rate) { - clk_lock(); - ret = clk->set_rate(clk, rate); - clk_unlock(); - } - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -/* - * clk_round_rate - adjust a rate to the exact rate a clock can provide - */ -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - clk_lock(); - - if (clk->round_rate) - rate = clk->round_rate(clk, rate); - else - rate = clk->get_rate(clk); - - clk_unlock(); - - return rate; -} -EXPORT_SYMBOL(clk_round_rate); - -/* - * clk_set_parent - set the parent clock source for this clock - */ -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - /* Clock re-parenting is not supported */ - return -EINVAL; -} -EXPORT_SYMBOL(clk_set_parent); - -/* - * clk_get_parent - get the parent clock source for this clock - */ -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = (d), \ - .con_id = (n), \ - .clk = &(c), \ - }, - -static struct clk_lookup lookups[] = { - _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz) - _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397) - _REGISTER_CLOCK(NULL, "osc_main", osc_main) - _REGISTER_CLOCK(NULL, "sys_ck", clk_sys) - _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll) - _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll) - _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk) - _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk) - _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0) - _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1) - _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2) - _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3) - _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9) - _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma) - _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt) - _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3) - _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4) - _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5) - _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6) - _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0) - _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1) - _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2) - _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0) - _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1) - _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan) - _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) - _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0) - _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1) - _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc) - _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc) - _REGISTER_CLOCK("lpc-net.0", NULL, clk_net) - _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd) - _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd) - _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc) -}; - -static int __init clk_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(lookups); i++) - clkdev_add(&lookups[i]); - - /* - * Setup muxed SYSCLK for HCLK PLL base -this selects the - * parent clock used for the ARM PLL and is used to derive - * the many system clock rates in the device. - */ - if (clk_is_sysclk_mainosc() != 0) - clk_sys.parent = &osc_main; - else - clk_sys.parent = &osc_pll397; - - clk_sys.rate = clk_sys.parent->rate; - - /* Compute the current ARM PLL and USB PLL frequencies */ - local_update_armpll_rate(); - - /* Compute HCLK and PCLK bus rates */ - clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div(); - clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div(); - - /* - * Enable system clocks - this step is somewhat formal, as the - * clocks are already running, but it does get the clock data - * inline with the actual system state. Never disable these - * clocks as they will only stop if the system is going to sleep. - * In that case, the chip/system power management functions will - * handle clock gating. - */ - if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk)) - printk(KERN_ERR "Error enabling system HCLK and PCLK\n"); - - /* - * Timers 0 and 1 were enabled and are being used by the high - * resolution tick function prior to this driver being initialized. - * Tag them now as used. - */ - if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1)) - printk(KERN_ERR "Error enabling timer tick clocks\n"); - - return 0; -} -core_initcall(clk_init); - diff --git a/trunk/arch/arm/mach-lpc32xx/clock.h b/trunk/arch/arm/mach-lpc32xx/clock.h deleted file mode 100644 index c0a8434307f7..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/clock.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/clock.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __LPC32XX_CLOCK_H -#define __LPC32XX_CLOCK_H - -struct clk { - struct list_head node; - struct clk *parent; - u32 rate; - u32 usecount; - - int (*set_rate) (struct clk *, unsigned long); - unsigned long (*round_rate) (struct clk *, unsigned long); - unsigned long (*get_rate) (struct clk *clk); - int (*enable) (struct clk *, int); - - /* Register address and bit mask for simple clocks */ - void __iomem *enable_reg; - u32 enable_mask; -}; - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/common.c b/trunk/arch/arm/mach-lpc32xx/common.c deleted file mode 100644 index ee24dc28e93e..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/common.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/common.c - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include "common.h" - -/* - * Watchdog timer - */ -static struct resource watchdog_resources[] = { - [0] = { - .start = LPC32XX_WDTIM_BASE, - .end = LPC32XX_WDTIM_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device lpc32xx_watchdog_device = { - .name = "pnx4008-watchdog", - .id = -1, - .num_resources = ARRAY_SIZE(watchdog_resources), - .resource = watchdog_resources, -}; - -/* - * I2C busses - */ -static struct i2c_pnx_data i2c0_data = { - .name = I2C_CHIP_NAME "1", - .base = LPC32XX_I2C1_BASE, - .irq = IRQ_LPC32XX_I2C_1, -}; - -static struct i2c_pnx_data i2c1_data = { - .name = I2C_CHIP_NAME "2", - .base = LPC32XX_I2C2_BASE, - .irq = IRQ_LPC32XX_I2C_2, -}; - -static struct i2c_pnx_data i2c2_data = { - .name = "USB-I2C", - .base = LPC32XX_OTG_I2C_BASE, - .irq = IRQ_LPC32XX_USB_I2C, -}; - -struct platform_device lpc32xx_i2c0_device = { - .name = "pnx-i2c", - .id = 0, - .dev = { - .platform_data = &i2c0_data, - }, -}; - -struct platform_device lpc32xx_i2c1_device = { - .name = "pnx-i2c", - .id = 1, - .dev = { - .platform_data = &i2c1_data, - }, -}; - -struct platform_device lpc32xx_i2c2_device = { - .name = "pnx-i2c", - .id = 2, - .dev = { - .platform_data = &i2c2_data, - }, -}; - -/* - * Returns the unique ID for the device - */ -void lpc32xx_get_uid(u32 devid[4]) -{ - int i; - - for (i = 0; i < 4; i++) - devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2)); -} - -/* - * Returns SYSCLK source - * 0 = PLL397, 1 = main oscillator - */ -int clk_is_sysclk_mainosc(void) -{ - if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) & - LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0) - return 1; - - return 0; -} - -/* - * System reset via the watchdog timer - */ -void lpc32xx_watchdog_reset(void) -{ - /* Make sure WDT clocks are enabled */ - __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN, - LPC32XX_CLKPWR_TIMER_CLK_CTRL); - - /* Instant assert of RESETOUT_N with pulse length 1mS */ - __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18)); - __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC)); -} - -/* - * Detects and returns IRAM size for the device variation - */ -#define LPC32XX_IRAM_BANK_SIZE SZ_128K -static u32 iram_size; -u32 lpc32xx_return_iram_size(void) -{ - if (iram_size == 0) { - u32 savedval1, savedval2; - void __iomem *iramptr1, *iramptr2; - - iramptr1 = io_p2v(LPC32XX_IRAM_BASE); - iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE); - savedval1 = __raw_readl(iramptr1); - savedval2 = __raw_readl(iramptr2); - - if (savedval1 == savedval2) { - __raw_writel(savedval2 + 1, iramptr2); - if (__raw_readl(iramptr1) == savedval2 + 1) - iram_size = LPC32XX_IRAM_BANK_SIZE; - else - iram_size = LPC32XX_IRAM_BANK_SIZE * 2; - __raw_writel(savedval2, iramptr2); - } else - iram_size = LPC32XX_IRAM_BANK_SIZE * 2; - } - - return iram_size; -} - -/* - * Computes PLL rate from PLL register and input clock - */ -u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup) -{ - u32 ilfreq, p, m, n, fcco, fref, cfreq; - int mode; - - /* - * PLL requirements - * ifreq must be >= 1MHz and <= 20MHz - * FCCO must be >= 156MHz and <= 320MHz - * FREF must be >= 1MHz and <= 27MHz - * Assume the passed input data is not valid - */ - - ilfreq = ifreq; - m = pllsetup->pll_m; - n = pllsetup->pll_n; - p = pllsetup->pll_p; - - mode = (pllsetup->cco_bypass_b15 << 2) | - (pllsetup->direct_output_b14 << 1) | - pllsetup->fdbk_div_ctrl_b13; - - switch (mode) { - case 0x0: /* Non-integer mode */ - cfreq = (m * ilfreq) / (2 * p * n); - fcco = (m * ilfreq) / n; - fref = ilfreq / n; - break; - - case 0x1: /* integer mode */ - cfreq = (m * ilfreq) / n; - fcco = (m * ilfreq) / (n * 2 * p); - fref = ilfreq / n; - break; - - case 0x2: - case 0x3: /* Direct mode */ - cfreq = (m * ilfreq) / n; - fcco = cfreq; - fref = ilfreq / n; - break; - - case 0x4: - case 0x5: /* Bypass mode */ - cfreq = ilfreq / (2 * p); - fcco = 156000000; - fref = 1000000; - break; - - case 0x6: - case 0x7: /* Direct bypass mode */ - default: - cfreq = ilfreq; - fcco = 156000000; - fref = 1000000; - break; - } - - if (fcco < 156000000 || fcco > 320000000) - cfreq = 0; - - if (fref < 1000000 || fref > 27000000) - cfreq = 0; - - return (u32) cfreq; -} - -u32 clk_get_pclk_div(void) -{ - return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F); -} - -static struct map_desc lpc32xx_io_desc[] __initdata = { - { - .virtual = IO_ADDRESS(LPC32XX_AHB0_START), - .pfn = __phys_to_pfn(LPC32XX_AHB0_START), - .length = LPC32XX_AHB0_SIZE, - .type = MT_DEVICE - }, - { - .virtual = IO_ADDRESS(LPC32XX_AHB1_START), - .pfn = __phys_to_pfn(LPC32XX_AHB1_START), - .length = LPC32XX_AHB1_SIZE, - .type = MT_DEVICE - }, - { - .virtual = IO_ADDRESS(LPC32XX_FABAPB_START), - .pfn = __phys_to_pfn(LPC32XX_FABAPB_START), - .length = LPC32XX_FABAPB_SIZE, - .type = MT_DEVICE - }, - { - .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE), - .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE), - .length = (LPC32XX_IRAM_BANK_SIZE * 2), - .type = MT_DEVICE - }, -}; - -void __init lpc32xx_map_io(void) -{ - iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc)); -} diff --git a/trunk/arch/arm/mach-lpc32xx/common.h b/trunk/arch/arm/mach-lpc32xx/common.h deleted file mode 100644 index f82211fd80c1..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/common.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/common.h - * - * Author: Kevin Wells - * - * Copyright (C) 2009-2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __LPC32XX_COMMON_H -#define __LPC32XX_COMMON_H - -#include - -/* - * Arch specific platform device structures - */ -extern struct platform_device lpc32xx_watchdog_device; -extern struct platform_device lpc32xx_i2c0_device; -extern struct platform_device lpc32xx_i2c1_device; -extern struct platform_device lpc32xx_i2c2_device; - -/* - * Other arch specific structures and functions - */ -extern struct sys_timer lpc32xx_timer; -extern void __init lpc32xx_init_irq(void); -extern void __init lpc32xx_map_io(void); -extern void __init lpc32xx_serial_init(void); -extern void __init lpc32xx_gpio_init(void); - -/* - * Structure used for setting up and querying the PLLS - */ -struct clk_pll_setup { - int analog_on; - int cco_bypass_b15; - int direct_output_b14; - int fdbk_div_ctrl_b13; - int pll_p; - int pll_n; - u32 pll_m; -}; - -extern int clk_is_sysclk_mainosc(void); -extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup); -extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval); -extern u32 clk_get_pclk_div(void); - -/* - * Returns the LPC32xx unique 128-bit chip ID - */ -extern void lpc32xx_get_uid(u32 devid[4]); - -extern void lpc32xx_watchdog_reset(void); -extern u32 lpc32xx_return_iram_size(void); - -/* - * Pointers used for sizing and copying suspend function data - */ -extern int lpc32xx_sys_suspend(void); -extern int lpc32xx_sys_suspend_sz; - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/gpiolib.c b/trunk/arch/arm/mach-lpc32xx/gpiolib.c deleted file mode 100644 index 69061ea8997a..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/gpiolib.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/gpiolib.c - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include "common.h" - -#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) -#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) -#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) -#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) -#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) -#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) -#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) -#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) -#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) -#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) -#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) -#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) -#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) -#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) -#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) -#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) -#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) -#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) -#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) -#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) -#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) -#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) -#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) -#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) -#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) -#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) -#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) - -#define GPIO012_PIN_TO_BIT(x) (1 << (x)) -#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) -#define GPO3_PIN_TO_BIT(x) (1 << (x)) -#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) -#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) -#define GPIO3_PIN_IN_SEL(x, y) ((x) >> GPIO3_PIN_IN_SHIFT(y)) -#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) -#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) - -struct gpio_regs { - void __iomem *inp_state; - void __iomem *outp_set; - void __iomem *outp_clr; - void __iomem *dir_set; - void __iomem *dir_clr; -}; - -/* - * GPIO names - */ -static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { - "p0.0", "p0.1", "p0.2", "p0.3", - "p0.4", "p0.5", "p0.6", "p0.7" -}; - -static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { - "p1.0", "p1.1", "p1.2", "p1.3", - "p1.4", "p1.5", "p1.6", "p1.7", - "p1.8", "p1.9", "p1.10", "p1.11", - "p1.12", "p1.13", "p1.14", "p1.15", - "p1.16", "p1.17", "p1.18", "p1.19", - "p1.20", "p1.21", "p1.22", "p1.23", -}; - -static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { - "p2.0", "p2.1", "p2.2", "p2.3", - "p2.4", "p2.5", "p2.6", "p2.7", - "p2.8", "p2.9", "p2.10", "p2.11", - "p2.12" -}; - -static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { - "gpi000", "gpio01", "gpio02", "gpio03", - "gpio04", "gpio05" -}; - -static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { - "gpi00", "gpi01", "gpi02", "gpi03", - "gpi04", "gpi05", "gpi06", "gpi07", - "gpi08", "gpi09", NULL, NULL, - NULL, NULL, NULL, "gpi15", - "gpi16", "gpi17", "gpi18", "gpi19", - "gpi20", "gpi21", "gpi22", "gpi23", - "gpi24", "gpi25", "gpi26", "gpi27" -}; - -static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { - "gpo00", "gpo01", "gpo02", "gpo03", - "gpo04", "gpo05", "gpo06", "gpo07", - "gpo08", "gpo09", "gpo10", "gpo11", - "gpo12", "gpo13", "gpo14", "gpo15", - "gpo16", "gpo17", "gpo18", "gpo19", - "gpo20", "gpo21", "gpo22", "gpo23" -}; - -static struct gpio_regs gpio_grp_regs_p0 = { - .inp_state = LPC32XX_GPIO_P0_INP_STATE, - .outp_set = LPC32XX_GPIO_P0_OUTP_SET, - .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, - .dir_set = LPC32XX_GPIO_P0_DIR_SET, - .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, -}; - -static struct gpio_regs gpio_grp_regs_p1 = { - .inp_state = LPC32XX_GPIO_P1_INP_STATE, - .outp_set = LPC32XX_GPIO_P1_OUTP_SET, - .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, - .dir_set = LPC32XX_GPIO_P1_DIR_SET, - .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, -}; - -static struct gpio_regs gpio_grp_regs_p2 = { - .inp_state = LPC32XX_GPIO_P2_INP_STATE, - .outp_set = LPC32XX_GPIO_P2_OUTP_SET, - .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, - .dir_set = LPC32XX_GPIO_P2_DIR_SET, - .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, -}; - -static struct gpio_regs gpio_grp_regs_p3 = { - .inp_state = LPC32XX_GPIO_P3_INP_STATE, - .outp_set = LPC32XX_GPIO_P3_OUTP_SET, - .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, - .dir_set = LPC32XX_GPIO_P2_DIR_SET, - .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, -}; - -struct lpc32xx_gpio_chip { - struct gpio_chip chip; - struct gpio_regs *gpio_grp; -}; - -static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio( - struct gpio_chip *gpc) -{ - return container_of(gpc, struct lpc32xx_gpio_chip, chip); -} - -static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, - unsigned pin, int input) -{ - if (input) - __raw_writel(GPIO012_PIN_TO_BIT(pin), - group->gpio_grp->dir_clr); - else - __raw_writel(GPIO012_PIN_TO_BIT(pin), - group->gpio_grp->dir_set); -} - -static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, - unsigned pin, int input) -{ - u32 u = GPIO3_PIN_TO_BIT(pin); - - if (input) - __raw_writel(u, group->gpio_grp->dir_clr); - else - __raw_writel(u, group->gpio_grp->dir_set); -} - -static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, - unsigned pin, int high) -{ - if (high) - __raw_writel(GPIO012_PIN_TO_BIT(pin), - group->gpio_grp->outp_set); - else - __raw_writel(GPIO012_PIN_TO_BIT(pin), - group->gpio_grp->outp_clr); -} - -static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, - unsigned pin, int high) -{ - u32 u = GPIO3_PIN_TO_BIT(pin); - - if (high) - __raw_writel(u, group->gpio_grp->outp_set); - else - __raw_writel(u, group->gpio_grp->outp_clr); -} - -static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, - unsigned pin, int high) -{ - if (high) - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); - else - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); -} - -static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, - unsigned pin) -{ - return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), - pin); -} - -static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, - unsigned pin) -{ - int state = __raw_readl(group->gpio_grp->inp_state); - - /* - * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped - * to bits 10..14, while GPIOP3-5 is mapped to bit 24. - */ - return GPIO3_PIN_IN_SEL(state, pin); -} - -static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, - unsigned pin) -{ - return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); -} - -/* - * GENERIC_GPIO primitives. - */ -static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, - unsigned pin) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - __set_gpio_dir_p012(group, pin, 1); - - return 0; -} - -static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, - unsigned pin) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - __set_gpio_dir_p3(group, pin, 1); - - return 0; -} - -static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, - unsigned pin) -{ - return 0; -} - -static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - return __get_gpio_state_p012(group, pin); -} - -static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - return __get_gpio_state_p3(group, pin); -} - -static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - return __get_gpi_state_p3(group, pin); -} - -static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, - int value) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - __set_gpio_dir_p012(group, pin, 0); - - return 0; -} - -static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, - int value) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - __set_gpio_dir_p3(group, pin, 0); - - return 0; -} - -static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, - int value) -{ - return 0; -} - -static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, - int value) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - __set_gpio_level_p012(group, pin, value); -} - -static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, - int value) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - __set_gpio_level_p3(group, pin, value); -} - -static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, - int value) -{ - struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); - - __set_gpo_level_p3(group, pin, value); -} - -static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) -{ - if (pin < chip->ngpio) - return 0; - - return -EINVAL; -} - -static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { - { - .chip = { - .label = "gpio_p0", - .direction_input = lpc32xx_gpio_dir_input_p012, - .get = lpc32xx_gpio_get_value_p012, - .direction_output = lpc32xx_gpio_dir_output_p012, - .set = lpc32xx_gpio_set_value_p012, - .request = lpc32xx_gpio_request, - .base = LPC32XX_GPIO_P0_GRP, - .ngpio = LPC32XX_GPIO_P0_MAX, - .names = gpio_p0_names, - .can_sleep = 0, - }, - .gpio_grp = &gpio_grp_regs_p0, - }, - { - .chip = { - .label = "gpio_p1", - .direction_input = lpc32xx_gpio_dir_input_p012, - .get = lpc32xx_gpio_get_value_p012, - .direction_output = lpc32xx_gpio_dir_output_p012, - .set = lpc32xx_gpio_set_value_p012, - .request = lpc32xx_gpio_request, - .base = LPC32XX_GPIO_P1_GRP, - .ngpio = LPC32XX_GPIO_P1_MAX, - .names = gpio_p1_names, - .can_sleep = 0, - }, - .gpio_grp = &gpio_grp_regs_p1, - }, - { - .chip = { - .label = "gpio_p2", - .direction_input = lpc32xx_gpio_dir_input_p012, - .get = lpc32xx_gpio_get_value_p012, - .direction_output = lpc32xx_gpio_dir_output_p012, - .set = lpc32xx_gpio_set_value_p012, - .request = lpc32xx_gpio_request, - .base = LPC32XX_GPIO_P2_GRP, - .ngpio = LPC32XX_GPIO_P2_MAX, - .names = gpio_p2_names, - .can_sleep = 0, - }, - .gpio_grp = &gpio_grp_regs_p2, - }, - { - .chip = { - .label = "gpio_p3", - .direction_input = lpc32xx_gpio_dir_input_p3, - .get = lpc32xx_gpio_get_value_p3, - .direction_output = lpc32xx_gpio_dir_output_p3, - .set = lpc32xx_gpio_set_value_p3, - .request = lpc32xx_gpio_request, - .base = LPC32XX_GPIO_P3_GRP, - .ngpio = LPC32XX_GPIO_P3_MAX, - .names = gpio_p3_names, - .can_sleep = 0, - }, - .gpio_grp = &gpio_grp_regs_p3, - }, - { - .chip = { - .label = "gpi_p3", - .direction_input = lpc32xx_gpio_dir_in_always, - .get = lpc32xx_gpi_get_value, - .request = lpc32xx_gpio_request, - .base = LPC32XX_GPI_P3_GRP, - .ngpio = LPC32XX_GPI_P3_MAX, - .names = gpi_p3_names, - .can_sleep = 0, - }, - .gpio_grp = &gpio_grp_regs_p3, - }, - { - .chip = { - .label = "gpo_p3", - .direction_output = lpc32xx_gpio_dir_out_always, - .set = lpc32xx_gpo_set_value, - .request = lpc32xx_gpio_request, - .base = LPC32XX_GPO_P3_GRP, - .ngpio = LPC32XX_GPO_P3_MAX, - .names = gpo_p3_names, - .can_sleep = 0, - }, - .gpio_grp = &gpio_grp_regs_p3, - }, -}; - -void __init lpc32xx_gpio_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) - gpiochip_add(&lpc32xx_gpiochip[i].chip); -} diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/trunk/arch/arm/mach-lpc32xx/include/mach/debug-macro.S deleted file mode 100644 index 621744d6b152..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/debug-macro.S +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/debug-macro.S - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Debug output is hardcoded to standard UART 5 -*/ - - .macro addruart,rx, tmp - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - ldreq \rx, =0x40090000 - ldrne \rx, =0xF4090000 - .endm - -#define UART_SHIFT 2 -#include diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/trunk/arch/arm/mach-lpc32xx/include/mach/entry-macro.S deleted file mode 100644 index 870227c96602..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/entry-macro.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/entry-macro.S - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - -/* - * Return IRQ number in irqnr. Also return processor Z flag status in CPSR - * as set if an interrupt is pending. - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS] - clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #31 - teq \irqstat, #0 - .endm - - .macro irq_prio_table - .endm - diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/gpio.h b/trunk/arch/arm/mach-lpc32xx/include/mach/gpio.h deleted file mode 100644 index 67d03da1eee9..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/gpio.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/gpio.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#include - -/* - * Note! - * Muxed GP pins need to be setup to the GP state in the board level - * code prior to using this driver. - * GPI pins : 28xP3 group - * GPO pins : 24xP3 group - * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group - */ - -#define LPC32XX_GPIO_P0_MAX 8 -#define LPC32XX_GPIO_P1_MAX 24 -#define LPC32XX_GPIO_P2_MAX 13 -#define LPC32XX_GPIO_P3_MAX 6 -#define LPC32XX_GPI_P3_MAX 28 -#define LPC32XX_GPO_P3_MAX 24 - -#define LPC32XX_GPIO_P0_GRP 0 -#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX) -#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX) -#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX) -#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX) -#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) - -/* - * A specific GPIO can be selected with this macro - * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) - * See the LPC32x0 User's guide for GPIO group numbers - */ -#define LPC32XX_GPIO(x, y) ((x) + (y)) - -static inline int gpio_get_value(unsigned gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return __gpio_to_irq(gpio); -} - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h b/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h deleted file mode 100644 index 33e1dde37bd9..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/hardware.h - * - * Copyright (c) 2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Start of virtual addresses for IO devices - */ -#define IO_BASE 0xF0000000 - -/* - * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 - */ -#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ - IO_BASE) - -#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) -#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/i2c.h b/trunk/arch/arm/mach-lpc32xx/include/mach/i2c.h deleted file mode 100644 index 034dc9286bcc..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/i2c.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * PNX4008-specific tweaks for I2C IP3204 block - * - * Author: Vitaly Wool - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __ASM_ARCH_I2C_H -#define __ASM_ARCH_I2C_H - -enum { - mstatus_tdi = 0x00000001, - mstatus_afi = 0x00000002, - mstatus_nai = 0x00000004, - mstatus_drmi = 0x00000008, - mstatus_active = 0x00000020, - mstatus_scl = 0x00000040, - mstatus_sda = 0x00000080, - mstatus_rff = 0x00000100, - mstatus_rfe = 0x00000200, - mstatus_tff = 0x00000400, - mstatus_tfe = 0x00000800, -}; - -enum { - mcntrl_tdie = 0x00000001, - mcntrl_afie = 0x00000002, - mcntrl_naie = 0x00000004, - mcntrl_drmie = 0x00000008, - mcntrl_daie = 0x00000020, - mcntrl_rffie = 0x00000040, - mcntrl_tffie = 0x00000080, - mcntrl_reset = 0x00000100, - mcntrl_cdbmode = 0x00000400, -}; - -enum { - rw_bit = 1 << 0, - start_bit = 1 << 8, - stop_bit = 1 << 9, -}; - -#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */ -#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */ -#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */ -#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */ -#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */ -#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */ -#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */ -#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */ -#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */ -#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */ -#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */ -#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */ -#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */ - -#define I2C_CHIP_NAME "PNX4008-I2C" - -#endif /* __ASM_ARCH_I2C_H */ diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/irqs.h b/trunk/arch/arm/mach-lpc32xx/include/mach/irqs.h deleted file mode 100644 index 2667f52e3b04..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/irqs.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/irqs.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARM_ARCH_IRQS_H -#define __ASM_ARM_ARCH_IRQS_H - -#define LPC32XX_SIC1_IRQ(n) (32 + (n)) -#define LPC32XX_SIC2_IRQ(n) (64 + (n)) - -/* - * MIC interrupts - */ -#define IRQ_LPC32XX_SUB1IRQ 0 -#define IRQ_LPC32XX_SUB2IRQ 1 -#define IRQ_LPC32XX_PWM3 3 -#define IRQ_LPC32XX_PWM4 4 -#define IRQ_LPC32XX_HSTIMER 5 -#define IRQ_LPC32XX_WATCH 6 -#define IRQ_LPC32XX_UART_IIR3 7 -#define IRQ_LPC32XX_UART_IIR4 8 -#define IRQ_LPC32XX_UART_IIR5 9 -#define IRQ_LPC32XX_UART_IIR6 10 -#define IRQ_LPC32XX_FLASH 11 -#define IRQ_LPC32XX_SD1 13 -#define IRQ_LPC32XX_LCD 14 -#define IRQ_LPC32XX_SD0 15 -#define IRQ_LPC32XX_TIMER0 16 -#define IRQ_LPC32XX_TIMER1 17 -#define IRQ_LPC32XX_TIMER2 18 -#define IRQ_LPC32XX_TIMER3 19 -#define IRQ_LPC32XX_SSP0 20 -#define IRQ_LPC32XX_SSP1 21 -#define IRQ_LPC32XX_I2S0 22 -#define IRQ_LPC32XX_I2S1 23 -#define IRQ_LPC32XX_UART_IIR7 24 -#define IRQ_LPC32XX_UART_IIR2 25 -#define IRQ_LPC32XX_UART_IIR1 26 -#define IRQ_LPC32XX_MSTIMER 27 -#define IRQ_LPC32XX_DMA 28 -#define IRQ_LPC32XX_ETHERNET 29 -#define IRQ_LPC32XX_SUB1FIQ 30 -#define IRQ_LPC32XX_SUB2FIQ 31 - -/* - * SIC1 interrupts start at offset 32 - */ -#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) -#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) -#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4) -#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) -#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) -#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) -#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12) -#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13) -#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14) -#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17) -#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18) -#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19) -#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20) -#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22) -#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23) -#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24) -#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25) -#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26) -#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27) -#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28) -#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29) -#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30) -#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31) - -/* - * SIC2 interrupts start at offset 64 - */ -#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0) -#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1) -#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2) -#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3) -#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4) -#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5) -#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6) -#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7) -#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8) -#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9) -#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10) -#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11) -#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12) -#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15) -#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18) -#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19) -#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20) -#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22) -#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23) -#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24) -#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25) -#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26) -#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27) -#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28) -#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31) - -#define NR_IRQS 96 - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/platform.h b/trunk/arch/arm/mach-lpc32xx/include/mach/platform.h deleted file mode 100644 index 14ea8d1aadb5..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/platform.h +++ /dev/null @@ -1,694 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/platform.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_PLATFORM_H -#define __ASM_ARCH_PLATFORM_H - -#define _SBF(f, v) ((v) << (f)) -#define _BIT(n) _SBF(n, 1) - -/* - * AHB 0 physical base addresses - */ -#define LPC32XX_SLC_BASE 0x20020000 -#define LPC32XX_SSP0_BASE 0x20084000 -#define LPC32XX_SPI1_BASE 0x20088000 -#define LPC32XX_SSP1_BASE 0x2008C000 -#define LPC32XX_SPI2_BASE 0x20090000 -#define LPC32XX_I2S0_BASE 0x20094000 -#define LPC32XX_SD_BASE 0x20098000 -#define LPC32XX_I2S1_BASE 0x2009C000 -#define LPC32XX_MLC_BASE 0x200A8000 -#define LPC32XX_AHB0_START LPC32XX_SLC_BASE -#define LPC32XX_AHB0_SIZE 0x00089000 - -/* - * AHB 1 physical base addresses - */ -#define LPC32XX_DMA_BASE 0x31000000 -#define LPC32XX_USB_BASE 0x31020000 -#define LPC32XX_USBH_BASE 0x31020000 -#define LPC32XX_USB_OTG_BASE 0x31020000 -#define LPC32XX_OTG_I2C_BASE 0x31020300 -#define LPC32XX_LCD_BASE 0x31040000 -#define LPC32XX_ETHERNET_BASE 0x31060000 -#define LPC32XX_EMC_BASE 0x31080000 -#define LPC32XX_ETB_CFG_BASE 0x310C0000 -#define LPC32XX_ETB_DATA_BASE 0x310E0000 -#define LPC32XX_AHB1_START LPC32XX_DMA_BASE -#define LPC32XX_AHB1_SIZE 0x000E1000 - -/* - * FAB physical base addresses - */ -#define LPC32XX_CLK_PM_BASE 0x40004000 -#define LPC32XX_MIC_BASE 0x40008000 -#define LPC32XX_SIC1_BASE 0x4000C000 -#define LPC32XX_SIC2_BASE 0x40010000 -#define LPC32XX_HS_UART1_BASE 0x40014000 -#define LPC32XX_HS_UART2_BASE 0x40018000 -#define LPC32XX_HS_UART7_BASE 0x4001C000 -#define LPC32XX_RTC_BASE 0x40024000 -#define LPC32XX_RTC_RAM_BASE 0x40024080 -#define LPC32XX_GPIO_BASE 0x40028000 -#define LPC32XX_PWM3_BASE 0x4002C000 -#define LPC32XX_PWM4_BASE 0x40030000 -#define LPC32XX_MSTIM_BASE 0x40034000 -#define LPC32XX_HSTIM_BASE 0x40038000 -#define LPC32XX_WDTIM_BASE 0x4003C000 -#define LPC32XX_DEBUG_CTRL_BASE 0x40040000 -#define LPC32XX_TIMER0_BASE 0x40044000 -#define LPC32XX_ADC_BASE 0x40048000 -#define LPC32XX_TIMER1_BASE 0x4004C000 -#define LPC32XX_KSCAN_BASE 0x40050000 -#define LPC32XX_UART_CTRL_BASE 0x40054000 -#define LPC32XX_TIMER2_BASE 0x40058000 -#define LPC32XX_PWM1_BASE 0x4005C000 -#define LPC32XX_PWM2_BASE 0x4005C004 -#define LPC32XX_TIMER3_BASE 0x40060000 - -/* - * APB physical base addresses - */ -#define LPC32XX_UART3_BASE 0x40080000 -#define LPC32XX_UART4_BASE 0x40088000 -#define LPC32XX_UART5_BASE 0x40090000 -#define LPC32XX_UART6_BASE 0x40098000 -#define LPC32XX_I2C1_BASE 0x400A0000 -#define LPC32XX_I2C2_BASE 0x400A8000 - -/* - * FAB and APB base and sizing - */ -#define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE -#define LPC32XX_FABAPB_SIZE 0x000A5000 - -/* - * Internal memory bases and sizes - */ -#define LPC32XX_IRAM_BASE 0x08000000 -#define LPC32XX_IROM_BASE 0x0C000000 - -/* - * External Static Memory Bank Address Space Bases - */ -#define LPC32XX_EMC_CS0_BASE 0xE0000000 -#define LPC32XX_EMC_CS1_BASE 0xE1000000 -#define LPC32XX_EMC_CS2_BASE 0xE2000000 -#define LPC32XX_EMC_CS3_BASE 0xE3000000 - -/* - * External SDRAM Memory Bank Address Space Bases - */ -#define LPC32XX_EMC_DYCS0_BASE 0x80000000 -#define LPC32XX_EMC_DYCS1_BASE 0xA0000000 - -/* - * Clock and crystal information - */ -#define LPC32XX_MAIN_OSC_FREQ 13000000 -#define LPC32XX_CLOCK_OSC_FREQ 32768 - -/* - * Clock and Power control register offsets - */ -#define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ - (x)) -#define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000) -#define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014) -#define LPC32XX_CLKPWR_P01_ER _PMREG(0x018) -#define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C) -#define LPC32XX_CLKPWR_INT_ER _PMREG(0x020) -#define LPC32XX_CLKPWR_INT_RS _PMREG(0x024) -#define LPC32XX_CLKPWR_INT_SR _PMREG(0x028) -#define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C) -#define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030) -#define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034) -#define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038) -#define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C) -#define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040) -#define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044) -#define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048) -#define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C) -#define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050) -#define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054) -#define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058) -#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060) -#define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064) -#define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068) -#define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C) -#define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070) -#define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074) -#define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078) -#define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C) -#define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080) -#define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090) -#define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4) -#define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8) -#define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC) -#define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0) -#define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4) -#define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8) -#define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC) -#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0) -#define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4) -#define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8) -#define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0) -#define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4) -#define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8) -#define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC) -#define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0) -#define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4) -#define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8) -#define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC) -#define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x)) - -/* - * clkpwr_debug_ctrl register definitions -*/ -#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4) - -/* - * clkpwr_bootmap register definitions - */ -#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1) - -/* - * clkpwr_start_gpio register bit definitions - */ -#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0) - -/* - * clkpwr_usbclk_pdiv register definitions - */ -#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF - -/* - * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int, - * clkpwr_start_pol_int, register bit definitions - */ -#define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31) -#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30) -#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29) -#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26) -#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25) -#define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24) -#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23) -#define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22) -#define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21) -#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20) -#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19) -#define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16) -#define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7) -#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6) -#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5) -#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4) -#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3) -#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2) -#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1) -#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0) - -/* - * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin, - * clkpwr_start_pol_pin register bit definitions - */ -#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31) -#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30) -#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28) -#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26) -#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25) -#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24) -#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23) -#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22) -#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21) -#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18) -#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17) -#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16) -#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15) -#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14) -#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13) -#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12) -#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11) -#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10) -#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9) -#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8) -#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7) -#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6) -#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5) -#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4) -#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3) - -/* - * clkpwr_hclk_div register definitions - */ -#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7) -#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7) -#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7) -#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2) -#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3) - -/* - * clkpwr_pwr_ctrl register definitions - */ -#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10) -#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9) -#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8) -#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7) -#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5) -#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4) -#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3) -#define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2) -#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1) -#define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0) - -/* - * clkpwr_pll397_ctrl register definitions - */ -#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10) -#define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9) -#define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000 -#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040 -#define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080 -#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0 -#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100 -#define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140 -#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180 -#define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0 -#define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0 -#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1) -#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0) - -/* - * clkpwr_main_osc_ctrl register definitions - */ -#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2) -#define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2) -#define LPC32XX_CLKPWR_TEST_MODE _BIT(1) -#define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0) - -/* - * clkpwr_sysclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2) -#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2) -#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1) -#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0) - -/* - * clkpwr_lcdclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0 -#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020 -#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F) -#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F - -/* - * clkpwr_hclkpll_ctrl register definitions - */ -#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16) -#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15) -#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14) -#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13) -#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11) -#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) -#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1) -#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0) - -/* - * clkpwr_adc_clk_ctrl_1 register definitions - */ -#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0) -#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8) - -/* - * clkpwr_usb_ctrl register definitions - */ -#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24) -#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23) -#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22) -#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21) -#define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19) -#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19) -#define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19) -#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18) -#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17) -#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16) -#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15) -#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14) -#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13) -#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) -#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) -#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) -#define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0) - -/* - * clkpwr_sdramclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22) -#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21) -#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20) -#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19) -#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14) -#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13) -#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10) -#define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9) -#define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8) -#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7) -#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2) -#define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1) -#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0) - -/* - * clkpwr_ssp_blk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5) -#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4) -#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3) -#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2) -#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1) -#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0) - -/* - * clkpwr_i2s_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6) -#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5) -#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4) -#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3) -#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2) -#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1) -#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0) - -/* - * clkpwr_ms_ctrl register definitions - */ -#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10) -#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9) -#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8) -#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7) -#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6) -#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5) -#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF) - -/* - * clkpwr_macclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00 -#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08 -#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18 -#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18 -#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2) -#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1) -#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0) - -/* - * clkpwr_test_clk_sel register definitions - */ -#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5) -#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5) -#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5) -#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5) -#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1) -#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0) - -/* - * clkpwr_sw_int register definitions - */ -#define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1)) -#define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1) - -/* - * clkpwr_i2c_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4) -#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3) -#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2) -#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1) -#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0) - -/* - * clkpwr_key_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1 - -/* - * clkpwr_adc_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1 - -/* - * clkpwr_pwm_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8) -#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4) -#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8 -#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4 -#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2 -#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1 - -/* - * clkpwr_timer_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2 -#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1 - -/* - * clkpwr_timers_pwms_clk_ctrl_1 register definitions - */ -#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 -#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 -#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 -#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04 -#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02 -#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01 - -/* - * clkpwr_spi_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80 -#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40 -#define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20 -#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10 -#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08 -#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04 -#define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02 -#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01 - -/* - * clkpwr_nand_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20 -#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10 -#define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08 -#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04 -#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02 -#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01 - -/* - * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl - * and clkpwr_uart6_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF) -#define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8) -#define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16) - -/* - * clkpwr_irda_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF) -#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8) - -/* - * clkpwr_uart_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3) -#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2) -#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1) -#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0) - -/* - * clkpwr_dmaclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1 - -/* - * clkpwr_autoclock register definitions - */ -#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40 -#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02 -#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01 - -/* - * Interrupt controller register offsets - */ -#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00) -#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04) -#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08) -#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C) -#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10) -#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14) - -/* - * Timer/counter register offsets - */ -#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00) -#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04) -#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08) -#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C) -#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10) -#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14) -#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18) -#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) -#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20) -#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24) -#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28) -#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) -#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30) -#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34) -#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38) -#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) -#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) - -/* - * ir register definitions - */ -#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) -#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) - -/* - * tcr register definitions - */ -#define LCP32XX_TIMER_CNTR_TCR_EN 0x1 -#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2 - -/* - * mcr register definitions - */ -#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) -#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) -#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) - -/* - * Standard UART register offsets - */ -#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00) -#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04) -#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08) -#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C) -#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10) -#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14) -#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18) -#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C) - -/* - * UART control structure offsets - */ -#define _UCREG(x) io_p2v(\ - LPC32XX_UART_CTRL_BASE + (x)) -#define LPC32XX_UARTCTL_CTRL _UCREG(0x00) -#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04) -#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08) - -/* - * ctrl register definitions - */ -#define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11) -#define LPC32XX_UART_IRRX6_INV_EN _BIT(10) -#define LPC32XX_UART_HDPX_EN _BIT(9) -#define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5) -#define LPC32XX_RT_IRTX6_INV_EN _BIT(4) -#define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3) -#define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2) -#define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1) -#define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0) - -/* - * clkmode register definitions - */ -#define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F) -#define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1) -#define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14) -#define LPC32XX_UART_CLKMODE_OFF 0x0 -#define LPC32XX_UART_CLKMODE_ON 0x1 -#define LPC32XX_UART_CLKMODE_AUTO 0x2 -#define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4)) -#define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4)) - -/* - * GPIO Module Register offsets - */ -#define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x)) -#define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100) -#define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104) -#define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108) -#define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110) -#define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114) -#define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118) -#define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120) -#define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124) -#define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128) -#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) -#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) -#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/system.h b/trunk/arch/arm/mach-lpc32xx/include/mach/system.h deleted file mode 100644 index df3b0dea4d7b..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/system.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/system.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -static void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - extern void lpc32xx_watchdog_reset(void); - - switch (mode) { - case 's': - case 'h': - printk(KERN_CRIT "RESET: Rebooting system\n"); - - /* Disable interrupts */ - local_irq_disable(); - - lpc32xx_watchdog_reset(); - break; - - default: - /* Do nothing */ - break; - } - - /* Wait for watchdog to reset system */ - while (1) - ; -} - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/timex.h b/trunk/arch/arm/mach-lpc32xx/include/mach/timex.h deleted file mode 100644 index 8d4066b16b3f..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/timex.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/timex.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* - * Rate in Hz of the main system oscillator. This value should match - * the value 'MAIN_OSC_FREQ' in platform.h - */ -#define CLOCK_TICK_RATE 13000000 - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/trunk/arch/arm/mach-lpc32xx/include/mach/uncompress.h deleted file mode 100644 index c142487d299a..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/uncompress.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/uncompress.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H -#define __ASM_ARM_ARCH_UNCOMPRESS_H - -#include - -#include -#include - -/* - * Uncompress output is hardcoded to standard UART 5 - */ - -#define UART_FIFO_CTL_TX_RESET (1 << 2) -#define UART_STATUS_TX_MT (1 << 6) - -#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x)) - -#define LPC32XX_UART_DLLFIFO_O 0x00 -#define LPC32XX_UART_IIRFCR_O 0x08 -#define LPC32XX_UART_LSR_O 0x14 - -static inline void putc(int ch) -{ - /* Wait for transmit FIFO to empty */ - while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) & - UART_STATUS_TX_MT) == 0) - ; - - __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O)); -} - -static inline void flush(void) -{ - __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) | - UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O)); -} - -/* NULL functions; we don't presently need them */ -#define arch_decomp_setup() -#define arch_decomp_wdog() - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/trunk/arch/arm/mach-lpc32xx/include/mach/vmalloc.h deleted file mode 100644 index d1d936c7236d..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/vmalloc.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/vmalloc.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END 0xF0000000 - -#endif diff --git a/trunk/arch/arm/mach-lpc32xx/irq.c b/trunk/arch/arm/mach-lpc32xx/irq.c deleted file mode 100644 index bd0df26c415b..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/irq.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/irq.c - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include "common.h" - -/* - * Default value representing the Activation polarity of all internal - * interrupt sources - */ -#define MIC_APR_DEFAULT 0x3FF0EFE0 -#define SIC1_APR_DEFAULT 0xFBD27186 -#define SIC2_APR_DEFAULT 0x801810C0 - -/* - * Default value representing the Activation Type of all internal - * interrupt sources. All are level sensitive. - */ -#define MIC_ATR_DEFAULT 0x00000000 -#define SIC1_ATR_DEFAULT 0x00026000 -#define SIC2_ATR_DEFAULT 0x00000000 - -struct lpc32xx_event_group_regs { - void __iomem *enab_reg; - void __iomem *edge_reg; - void __iomem *maskstat_reg; - void __iomem *rawstat_reg; -}; - -static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = { - .enab_reg = LPC32XX_CLKPWR_INT_ER, - .edge_reg = LPC32XX_CLKPWR_INT_AP, - .maskstat_reg = LPC32XX_CLKPWR_INT_SR, - .rawstat_reg = LPC32XX_CLKPWR_INT_RS, -}; - -static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = { - .enab_reg = LPC32XX_CLKPWR_PIN_ER, - .edge_reg = LPC32XX_CLKPWR_PIN_AP, - .maskstat_reg = LPC32XX_CLKPWR_PIN_SR, - .rawstat_reg = LPC32XX_CLKPWR_PIN_RS, -}; - -struct lpc32xx_event_info { - const struct lpc32xx_event_group_regs *event_group; - u32 mask; -}; - -/* - * Maps an IRQ number to and event mask and register - */ -static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = { - [IRQ_LPC32XX_GPI_08] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT, - }, - [IRQ_LPC32XX_GPI_09] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT, - }, - [IRQ_LPC32XX_GPI_19] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT, - }, - [IRQ_LPC32XX_GPI_07] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT, - }, - [IRQ_LPC32XX_GPI_00] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT, - }, - [IRQ_LPC32XX_GPI_01] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT, - }, - [IRQ_LPC32XX_GPI_02] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT, - }, - [IRQ_LPC32XX_GPI_03] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT, - }, - [IRQ_LPC32XX_GPI_04] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT, - }, - [IRQ_LPC32XX_GPI_05] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT, - }, - [IRQ_LPC32XX_GPI_06] = { - .event_group = &lpc32xx_event_pin_regs, - .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, - }, - [IRQ_LPC32XX_GPIO_00] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, - }, - [IRQ_LPC32XX_GPIO_01] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT, - }, - [IRQ_LPC32XX_GPIO_02] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT, - }, - [IRQ_LPC32XX_GPIO_03] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT, - }, - [IRQ_LPC32XX_GPIO_04] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT, - }, - [IRQ_LPC32XX_GPIO_05] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT, - }, - [IRQ_LPC32XX_KEY] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT, - }, - [IRQ_LPC32XX_USB_OTG_ATX] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT, - }, - [IRQ_LPC32XX_USB_HOST] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT, - }, - [IRQ_LPC32XX_RTC] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT, - }, - [IRQ_LPC32XX_MSTIMER] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT, - }, - [IRQ_LPC32XX_TS_AUX] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT, - }, - [IRQ_LPC32XX_TS_P] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT, - }, - [IRQ_LPC32XX_TS_IRQ] = { - .event_group = &lpc32xx_event_int_regs, - .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT, - }, -}; - -static void get_controller(unsigned int irq, unsigned int *base, - unsigned int *irqbit) -{ - if (irq < 32) { - *base = LPC32XX_MIC_BASE; - *irqbit = 1 << irq; - } else if (irq < 64) { - *base = LPC32XX_SIC1_BASE; - *irqbit = 1 << (irq - 32); - } else { - *base = LPC32XX_SIC2_BASE; - *irqbit = 1 << (irq - 64); - } -} - -static void lpc32xx_mask_irq(unsigned int irq) -{ - unsigned int reg, ctrl, mask; - - get_controller(irq, &ctrl, &mask); - - reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; - __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); -} - -static void lpc32xx_unmask_irq(unsigned int irq) -{ - unsigned int reg, ctrl, mask; - - get_controller(irq, &ctrl, &mask); - - reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; - __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); -} - -static void lpc32xx_ack_irq(unsigned int irq) -{ - unsigned int ctrl, mask; - - get_controller(irq, &ctrl, &mask); - - __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); - - /* Also need to clear pending wake event */ - if (lpc32xx_events[irq].mask != 0) - __raw_writel(lpc32xx_events[irq].mask, - lpc32xx_events[irq].event_group->rawstat_reg); -} - -static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, - int use_edge) -{ - unsigned int reg, ctrl, mask; - - get_controller(irq, &ctrl, &mask); - - /* Activation level, high or low */ - reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl)); - if (use_high_level) - reg |= mask; - else - reg &= ~mask; - __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl)); - - /* Activation type, edge or level */ - reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl)); - if (use_edge) - reg |= mask; - else - reg &= ~mask; - __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl)); - - /* Use same polarity for the wake events */ - if (lpc32xx_events[irq].mask != 0) { - reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg); - - if (use_high_level) - reg |= lpc32xx_events[irq].mask; - else - reg &= ~lpc32xx_events[irq].mask; - - __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg); - } -} - -static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type) -{ - switch (type) { - case IRQ_TYPE_EDGE_RISING: - /* Rising edge sensitive */ - __lpc32xx_set_irq_type(irq, 1, 1); - break; - - case IRQ_TYPE_EDGE_FALLING: - /* Falling edge sensitive */ - __lpc32xx_set_irq_type(irq, 0, 1); - break; - - case IRQ_TYPE_LEVEL_LOW: - /* Low level sensitive */ - __lpc32xx_set_irq_type(irq, 0, 0); - break; - - case IRQ_TYPE_LEVEL_HIGH: - /* High level sensitive */ - __lpc32xx_set_irq_type(irq, 1, 0); - break; - - /* Other modes are not supported */ - default: - return -EINVAL; - } - - /* Ok to use the level handler for all types */ - set_irq_handler(irq, handle_level_irq); - - return 0; -} - -static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state) -{ - unsigned long eventreg; - - if (lpc32xx_events[irqno].mask != 0) { - eventreg = __raw_readl(lpc32xx_events[irqno]. - event_group->enab_reg); - - if (state) - eventreg |= lpc32xx_events[irqno].mask; - else - eventreg &= ~lpc32xx_events[irqno].mask; - - __raw_writel(eventreg, - lpc32xx_events[irqno].event_group->enab_reg); - - return 0; - } - - /* Clear event */ - __raw_writel(lpc32xx_events[irqno].mask, - lpc32xx_events[irqno].event_group->rawstat_reg); - - return -ENODEV; -} - -static void __init lpc32xx_set_default_mappings(unsigned int apr, - unsigned int atr, unsigned int offset) -{ - unsigned int i; - - /* Set activation levels for each interrupt */ - i = 0; - while (i < 32) { - __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1), - ((atr >> i) & 0x1)); - i++; - } -} - -static struct irq_chip lpc32xx_irq_chip = { - .ack = lpc32xx_ack_irq, - .mask = lpc32xx_mask_irq, - .unmask = lpc32xx_unmask_irq, - .set_type = lpc32xx_set_irq_type, - .set_wake = lpc32xx_irq_wake -}; - -static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc) -{ - unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE)); - - while (ints != 0) { - int irqno = fls(ints) - 1; - - ints &= ~(1 << irqno); - - generic_handle_irq(LPC32XX_SIC1_IRQ(irqno)); - } -} - -static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc) -{ - unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE)); - - while (ints != 0) { - int irqno = fls(ints) - 1; - - ints &= ~(1 << irqno); - - generic_handle_irq(LPC32XX_SIC2_IRQ(irqno)); - } -} - -void __init lpc32xx_init_irq(void) -{ - unsigned int i; - - /* Setup MIC */ - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE)); - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE)); - - /* Setup SIC1 */ - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); - - /* Setup SIC2 */ - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); - - /* Configure supported IRQ's */ - for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &lpc32xx_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - - /* Set default mappings */ - lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0); - lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32); - lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64); - - /* mask all interrupts except SUBIRQ */ - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); - - /* MIC SUBIRQx interrupts will route handling to the chain handlers */ - set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); - set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); - - /* Initially disable all wake events */ - __raw_writel(0, LPC32XX_CLKPWR_P01_ER); - __raw_writel(0, LPC32XX_CLKPWR_INT_ER); - __raw_writel(0, LPC32XX_CLKPWR_PIN_ER); - - /* - * Default wake activation polarities, all pin sources are low edge - * triggered - */ - __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT | - LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT | - LPC32XX_CLKPWR_INTSRC_RTC_BIT, - LPC32XX_CLKPWR_INT_AP); - __raw_writel(0, LPC32XX_CLKPWR_PIN_AP); - - /* Clear latched wake event states */ - __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS), - LPC32XX_CLKPWR_PIN_RS); - __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS), - LPC32XX_CLKPWR_INT_RS); -} diff --git a/trunk/arch/arm/mach-lpc32xx/phy3250.c b/trunk/arch/arm/mach-lpc32xx/phy3250.c deleted file mode 100644 index bc9a42da2145..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/phy3250.c +++ /dev/null @@ -1,397 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/phy3250.c - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include "common.h" - -/* - * Mapped GPIOLIB GPIOs - */ -#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) -#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) -#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) -#define LED_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1) - -/* - * AMBA LCD controller - */ -static struct clcd_panel conn_lcd_panel = { - .mode = { - .name = "QVGA portrait", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 191828, - .left_margin = 22, - .right_margin = 11, - .upper_margin = 2, - .lower_margin = 1, - .hsync_len = 5, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = (TIM2_IVS | TIM2_IHS), - .cntl = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) | - CNTL_LCDBPP16_565), - .bpp = 16, -}; -#define PANEL_SIZE (3 * SZ_64K) - -static int lpc32xx_clcd_setup(struct clcd_fb *fb) -{ - dma_addr_t dma; - - fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, - PANEL_SIZE, &dma, GFP_KERNEL); - if (!fb->fb.screen_base) { - printk(KERN_ERR "CLCD: unable to map framebuffer\n"); - return -ENOMEM; - } - - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = PANEL_SIZE; - fb->panel = &conn_lcd_panel; - - if (gpio_request(LCD_POWER_GPIO, "LCD power")) - printk(KERN_ERR "Error requesting gpio %u", - LCD_POWER_GPIO); - else if (gpio_direction_output(LCD_POWER_GPIO, 1)) - printk(KERN_ERR "Error setting gpio %u to output", - LCD_POWER_GPIO); - - if (gpio_request(BKL_POWER_GPIO, "LCD backlight power")) - printk(KERN_ERR "Error requesting gpio %u", - BKL_POWER_GPIO); - else if (gpio_direction_output(BKL_POWER_GPIO, 1)) - printk(KERN_ERR "Error setting gpio %u to output", - BKL_POWER_GPIO); - - return 0; -} - -static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -{ - return dma_mmap_writecombine(&fb->dev->dev, vma, - fb->fb.screen_base, fb->fb.fix.smem_start, - fb->fb.fix.smem_len); -} - -static void lpc32xx_clcd_remove(struct clcd_fb *fb) -{ - dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, - fb->fb.screen_base, fb->fb.fix.smem_start); -} - -/* - * On some early LCD modules (1307.0), the backlight logic is inverted. - * For those board variants, swap the disable and enable states for - * BKL_POWER_GPIO. -*/ -static void clcd_disable(struct clcd_fb *fb) -{ - gpio_set_value(BKL_POWER_GPIO, 0); - gpio_set_value(LCD_POWER_GPIO, 0); -} - -static void clcd_enable(struct clcd_fb *fb) -{ - gpio_set_value(BKL_POWER_GPIO, 1); - gpio_set_value(LCD_POWER_GPIO, 1); -} - -static struct clcd_board lpc32xx_clcd_data = { - .name = "Phytec LCD", - .check = clcdfb_check, - .decode = clcdfb_decode, - .disable = clcd_disable, - .enable = clcd_enable, - .setup = lpc32xx_clcd_setup, - .mmap = lpc32xx_clcd_mmap, - .remove = lpc32xx_clcd_remove, -}; - -static struct amba_device lpc32xx_clcd_device = { - .dev = { - .coherent_dma_mask = ~0, - .init_name = "dev:clcd", - .platform_data = &lpc32xx_clcd_data, - }, - .res = { - .start = LPC32XX_LCD_BASE, - .end = (LPC32XX_LCD_BASE + SZ_4K - 1), - .flags = IORESOURCE_MEM, - }, - .dma_mask = ~0, - .irq = {IRQ_LPC32XX_LCD, NO_IRQ}, -}; - -/* - * AMBA SSP (SPI) - */ -static void phy3250_spi_cs_set(u32 control) -{ - gpio_set_value(SPI0_CS_GPIO, (int) control); -} - -static struct pl022_config_chip spi0_chip_info = { - .lbm = LOOPBACK_DISABLED, - .com_mode = INTERRUPT_TRANSFER, - .iface = SSP_INTERFACE_MOTOROLA_SPI, - .hierarchy = SSP_MASTER, - .slave_tx_disable = 0, - .endian_tx = SSP_TX_LSB, - .endian_rx = SSP_RX_LSB, - .data_size = SSP_DATA_BITS_8, - .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, - .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, - .clk_phase = SSP_CLK_FIRST_EDGE, - .clk_pol = SSP_CLK_POL_IDLE_LOW, - .ctrl_len = SSP_BITS_8, - .wait_state = SSP_MWIRE_WAIT_ZERO, - .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, - .cs_control = phy3250_spi_cs_set, -}; - -static struct pl022_ssp_controller lpc32xx_ssp0_data = { - .bus_id = 0, - .num_chipselect = 1, - .enable_dma = 0, -}; - -static struct amba_device lpc32xx_ssp0_device = { - .dev = { - .coherent_dma_mask = ~0, - .init_name = "dev:ssp0", - .platform_data = &lpc32xx_ssp0_data, - }, - .res = { - .start = LPC32XX_SSP0_BASE, - .end = (LPC32XX_SSP0_BASE + SZ_4K - 1), - .flags = IORESOURCE_MEM, - }, - .dma_mask = ~0, - .irq = {IRQ_LPC32XX_SSP0, NO_IRQ}, -}; - -/* AT25 driver registration */ -static int __init phy3250_spi_board_register(void) -{ -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) - static struct spi_board_info info[] = { - { - .modalias = "spidev", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, - .controller_data = &spi0_chip_info, - }, - }; - -#else - static struct spi_eeprom eeprom = { - .name = "at25256a", - .byte_len = 0x8000, - .page_size = 64, - .flags = EE_ADDR2, - }; - - static struct spi_board_info info[] = { - { - .modalias = "at25", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, - .platform_data = &eeprom, - .controller_data = &spi0_chip_info, - }, - }; -#endif - return spi_register_board_info(info, ARRAY_SIZE(info)); -} -arch_initcall(phy3250_spi_board_register); - -static struct i2c_board_info __initdata phy3250_i2c_board_info[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -static struct gpio_led phy_leds[] = { - { - .name = "led0", - .gpio = LED_GPIO, - .active_low = 1, - .default_trigger = "heartbeat", - }, -}; - -static struct gpio_led_platform_data led_data = { - .leds = phy_leds, - .num_leds = ARRAY_SIZE(phy_leds), -}; - -static struct platform_device lpc32xx_gpio_led_device = { - .name = "leds-gpio", - .id = -1, - .dev.platform_data = &led_data, -}; - -static struct platform_device *phy3250_devs[] __initdata = { - &lpc32xx_i2c0_device, - &lpc32xx_i2c1_device, - &lpc32xx_i2c2_device, - &lpc32xx_watchdog_device, - &lpc32xx_gpio_led_device, -}; - -static struct amba_device *amba_devs[] __initdata = { - &lpc32xx_clcd_device, - &lpc32xx_ssp0_device, -}; - -/* - * Board specific functions - */ -static void __init phy3250_board_init(void) -{ - u32 tmp; - int i; - - lpc32xx_gpio_init(); - - /* Register GPIOs used on this board */ - if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) - printk(KERN_ERR "Error requesting gpio %u", - SPI0_CS_GPIO); - else if (gpio_direction_output(SPI0_CS_GPIO, 1)) - printk(KERN_ERR "Error setting gpio %u to output", - SPI0_CS_GPIO); - - /* Setup network interface for RMII mode */ - tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); - tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; - tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; - __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); - - /* Setup SLC NAND controller muxing */ - __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, - LPC32XX_CLKPWR_NAND_CLK_CTRL); - - /* Setup LCD muxing to RGB565 */ - tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & - ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | - LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK); - tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; - __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); - - /* Set up I2C pull levels */ - tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); - tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | - LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; - __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); - - /* Disable IrDA pulsing support on UART6 */ - tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); - tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; - __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); - - /* Enable DMA for I2S1 channel */ - tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL); - tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA; - __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL); - - lpc32xx_serial_init(); - - /* - * AMBA peripheral clocks need to be enabled prior to AMBA device - * detection or a data fault will occur, so enable the clocks - * here. However, we don't want to enable them if the peripheral - * isn't included in the image - */ -#ifdef CONFIG_FB_ARMCLCD - tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); - __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), - LPC32XX_CLKPWR_LCDCLK_CTRL); -#endif -#ifdef CONFIG_SPI_PL022 - tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); - __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), - LPC32XX_CLKPWR_SSP_CLK_CTRL); -#endif - - platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs)); - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - struct amba_device *d = amba_devs[i]; - amba_device_register(d, &iomem_resource); - } - - /* Test clock needed for UDA1380 initial init */ - __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | - LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, - LPC32XX_CLKPWR_TEST_CLK_SEL); - - i2c_register_board_info(0, phy3250_i2c_board_info, - ARRAY_SIZE(phy3250_i2c_board_info)); -} - -static int __init lpc32xx_display_uid(void) -{ - u32 uid[4]; - - lpc32xx_get_uid(uid); - - printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", - uid[3], uid[2], uid[1], uid[0]); - - return 1; -} -arch_initcall(lpc32xx_display_uid); - -MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller") - /* Maintainer: Kevin Wells, NXP Semiconductors */ - .phys_io = LPC32XX_UART5_BASE, - .io_pg_offst = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = lpc32xx_map_io, - .init_irq = lpc32xx_init_irq, - .timer = &lpc32xx_timer, - .init_machine = phy3250_board_init, -MACHINE_END diff --git a/trunk/arch/arm/mach-lpc32xx/pm.c b/trunk/arch/arm/mach-lpc32xx/pm.c deleted file mode 100644 index a6e2aed9a49f..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/pm.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/pm.c - * - * Original authors: Vitaly Wool, Dmitry Chigirev - * Modified by Kevin Wells - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * LPC32XX CPU and system power management - * - * The LCP32XX has three CPU modes for controlling system power: run, - * direct-run, and halt modes. When switching between halt and run modes, - * the CPU transistions through direct-run mode. For Linux, direct-run - * mode is not used in normal operation. Halt mode is used when the - * system is fully suspended. - * - * Run mode: - * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are - * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from - * the HCLK_PLL rate. Linux runs in this mode. - * - * Direct-run mode: - * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from - * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK - * source or the frequency of the main oscillator. In this mode, the - * HCLK_PLL can be safely enabled, changed, or disabled. - * - * Halt mode: - * SYSCLK is gated off and the CPU and system clocks are halted. - * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch, - * key scanner, etc.) still operate if enabled. In this state, an enabled - * system event (ie, GPIO state change, RTC match, key press, etc.) will - * wake the system up back into direct-run mode. - * - * DRAM refresh - * DRAM clocking and refresh are slightly different for systems with DDR - * DRAM or regular SDRAM devices. If SDRAM is used in the system, the - * SDRAM will still be accessible in direct-run mode. In DDR based systems, - * a transistion to direct-run mode will stop all DDR accesses (no clocks). - * Because of this, the code to switch power modes and the code to enter - * and exit DRAM self-refresh modes must not be executed in DRAM. A small - * section of IRAM is used instead for this. - * - * Suspend is handled with the following logic: - * Backup a small area of IRAM used for the suspend code - * Copy suspend code to IRAM - * Transfer control to code in IRAM - * Places DRAMs in self-refresh mode - * Enter direct-run mode - * Save state of HCLK_PLL PLL - * Disable HCLK_PLL PLL - * Enter halt mode - CPU and buses will stop - * System enters direct-run mode when an enabled event occurs - * HCLK PLL state is restored - * Run mode is entered - * DRAMS are placed back into normal mode - * Code execution returns from IRAM - * IRAM code are used for suspend is restored - * Suspend mode is exited - */ - -#include -#include -#include - -#include - -#include -#include -#include "common.h" -#include "clock.h" - -#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE) - -/* - * Both STANDBY and MEM suspend states are handled the same with no - * loss of CPU or memory state - */ -static int lpc32xx_pm_enter(suspend_state_t state) -{ - int (*lpc32xx_suspend_ptr) (void); - void *iram_swap_area; - - /* Allocate some space for temporary IRAM storage */ - iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL); - if (!iram_swap_area) { - printk(KERN_ERR - "PM Suspend: cannot allocate memory to save portion " - "of SRAM\n"); - return -ENOMEM; - } - - /* Backup a small area of IRAM used for the suspend code */ - memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA, - lpc32xx_sys_suspend_sz); - - /* - * Copy code to suspend system into IRAM. The suspend code - * needs to run from IRAM as DRAM may no longer be available - * when the PLL is stopped. - */ - memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend, - lpc32xx_sys_suspend_sz); - flush_icache_range((unsigned long)TEMP_IRAM_AREA, - (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz); - - /* Transfer to suspend code in IRAM */ - lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA; - flush_cache_all(); - (void) lpc32xx_suspend_ptr(); - - /* Restore original IRAM contents */ - memcpy((void *) TEMP_IRAM_AREA, iram_swap_area, - lpc32xx_sys_suspend_sz); - - kfree(iram_swap_area); - - return 0; -} - -static struct platform_suspend_ops lpc32xx_pm_ops = { - .valid = suspend_valid_only_mem, - .enter = lpc32xx_pm_enter, -}; - -#define EMC_DYN_MEM_CTRL_OFS 0x20 -#define EMC_SRMMC (1 << 3) -#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS) -static int __init lpc32xx_pm_init(void) -{ - /* - * Setup SDRAM self-refresh clock to automatically disable o - * start of self-refresh. This only needs to be done once. - */ - __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG); - - suspend_set_ops(&lpc32xx_pm_ops); - - return 0; -} -arch_initcall(lpc32xx_pm_init); diff --git a/trunk/arch/arm/mach-lpc32xx/serial.c b/trunk/arch/arm/mach-lpc32xx/serial.c deleted file mode 100644 index 429cfdbb2b3d..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/serial.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/serial.c - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "common.h" - -#define LPC32XX_SUART_FIFO_SIZE 64 - -/* Standard 8250/16550 compatible serial ports */ -static struct plat_serial8250_port serial_std_platform_data[] = { -#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT - { - .membase = io_p2v(LPC32XX_UART5_BASE), - .mapbase = LPC32XX_UART5_BASE, - .irq = IRQ_LPC32XX_UART_IIR5, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT - { - .membase = io_p2v(LPC32XX_UART3_BASE), - .mapbase = LPC32XX_UART3_BASE, - .irq = IRQ_LPC32XX_UART_IIR3, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT - { - .membase = io_p2v(LPC32XX_UART4_BASE), - .mapbase = LPC32XX_UART4_BASE, - .irq = IRQ_LPC32XX_UART_IIR4, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT - { - .membase = io_p2v(LPC32XX_UART6_BASE), - .mapbase = LPC32XX_UART6_BASE, - .irq = IRQ_LPC32XX_UART_IIR6, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif - { }, -}; - -struct uartinit { - char *uart_ck_name; - u32 ck_mode_mask; - void __iomem *pdiv_clk_reg; -}; - -static struct uartinit uartinit_data[] __initdata = { -#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT - { - .uart_ck_name = "uart5_ck", - .ck_mode_mask = - LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5), - .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT - { - .uart_ck_name = "uart3_ck", - .ck_mode_mask = - LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3), - .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT - { - .uart_ck_name = "uart4_ck", - .ck_mode_mask = - LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4), - .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT - { - .uart_ck_name = "uart6_ck", - .ck_mode_mask = - LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6), - .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, - }, -#endif -}; - -static struct platform_device serial_std_platform_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_std_platform_data, - }, -}; - -static struct platform_device *lpc32xx_serial_devs[] __initdata = { - &serial_std_platform_device, -}; - -void __init lpc32xx_serial_init(void) -{ - u32 tmp, clkmodes = 0; - struct clk *clk; - unsigned int puart; - int i, j; - - /* UART clocks are off, let clock driver manage them */ - __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL); - - for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { - clk = clk_get(NULL, uartinit_data[i].uart_ck_name); - if (!IS_ERR(clk)) { - clk_enable(clk); - serial_std_platform_data[i].uartclk = - clk_get_rate(clk); - } - - /* Fall back on main osc rate if clock rate return fails */ - if (serial_std_platform_data[i].uartclk == 0) - serial_std_platform_data[i].uartclk = - LPC32XX_MAIN_OSC_FREQ; - - /* Setup UART clock modes for all UARTs, disable autoclock */ - clkmodes |= uartinit_data[i].ck_mode_mask; - - /* pre-UART clock divider set to 1 */ - __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); - } - - /* This needs to be done after all UART clocks are setup */ - __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); - for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) { - /* Force a flush of the RX FIFOs to work around a HW bug */ - puart = serial_std_platform_data[i].mapbase; - __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); - __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); - j = LPC32XX_SUART_FIFO_SIZE; - while (j--) - tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart)); - __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); - } - - /* Disable UART5->USB transparent mode or USB won't work */ - tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); - tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; - __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); - - platform_add_devices(lpc32xx_serial_devs, - ARRAY_SIZE(lpc32xx_serial_devs)); -} diff --git a/trunk/arch/arm/mach-lpc32xx/suspend.S b/trunk/arch/arm/mach-lpc32xx/suspend.S deleted file mode 100644 index 374f9f07fe48..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/suspend.S +++ /dev/null @@ -1,151 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/suspend.S - * - * Original authors: Dmitry Chigirev, Vitaly Wool - * Modified by Kevin Wells - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include - -/* Using named register defines makes the code easier to follow */ -#define WORK1_REG r0 -#define WORK2_REG r1 -#define SAVED_HCLK_DIV_REG r2 -#define SAVED_HCLK_PLL_REG r3 -#define SAVED_DRAM_CLKCTRL_REG r4 -#define SAVED_PWR_CTRL_REG r5 -#define CLKPWRBASE_REG r6 -#define EMCBASE_REG r7 - -#define LPC32XX_EMC_STATUS_OFFS 0x04 -#define LPC32XX_EMC_STATUS_BUSY 0x1 -#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4 - -#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44 -#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40 -#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58 - -#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F - - .text - -ENTRY(lpc32xx_sys_suspend) - @ Save a copy of the used registers in IRAM, r0 is corrupted - adr r0, tmp_stack_end - stmfd r0!, {r3 - r7, sp, lr} - - @ Load a few common register addresses - adr WORK1_REG, reg_bases - ldr CLKPWRBASE_REG, [WORK1_REG, #0] - ldr EMCBASE_REG, [WORK1_REG, #4] - - ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\ - #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH - - @ Wait for SDRAM busy status to go busy and then idle - @ This guarantees a small windows where DRAM isn't busy -1: - ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS] - and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY - cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY - bne 1b @ Branch while idle -2: - ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS] - and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY - cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY - beq 2b @ Branch until idle - - @ Setup self-refresh with support for manual exit of - @ self-refresh mode - str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH - str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - - @ Wait for self-refresh acknowledge, clocks to the DRAM device - @ will automatically stop on start of self-refresh -3: - ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS] - and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH - cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH - bne 3b @ Branch until self-refresh mode starts - - @ Enter direct-run mode from run mode - bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE - str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - - @ Safe disable of DRAM clock in EMC block, prevents DDR sync - @ issues on restart - ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\ - #LPC32XX_CLKPWR_HCLK_DIV_OFFS] - and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK - str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS] - - @ Save HCLK PLL state and disable HCLK PLL - ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\ - #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS] - bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP - str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS] - - @ Enter stop mode until an enabled event occurs - orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL - str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - .rept 9 - nop - .endr - - @ Clear stop status - bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL - - @ Restore original HCLK PLL value and wait for PLL lock - str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\ - #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS] -4: - ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS] - and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS - bne 4b - - @ Re-enter run mode with self-refresh flag cleared, but no DRAM - @ update yet. DRAM is still in self-refresh - str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\ - #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - - @ Restore original DRAM clock mode to restore DRAM clocks - str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\ - #LPC32XX_CLKPWR_HCLK_DIV_OFFS] - - @ Clear self-refresh mode - orr WORK1_REG, SAVED_PWR_CTRL_REG,\ - #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH - str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\ - #LPC32XX_CLKPWR_PWR_CTRL_OFFS] - - @ Wait for EMC to clear self-refresh mode -5: - ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS] - and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH - bne 5b @ Branch until self-refresh has exited - - @ restore regs and return - adr r0, tmp_stack - ldmfd r0!, {r3 - r7, sp, pc} - -reg_bases: - .long IO_ADDRESS(LPC32XX_CLK_PM_BASE) - .long IO_ADDRESS(LPC32XX_EMC_BASE) - -tmp_stack: - .long 0, 0, 0, 0, 0, 0, 0 -tmp_stack_end: - -ENTRY(lpc32xx_sys_suspend_sz) - .word . - lpc32xx_sys_suspend diff --git a/trunk/arch/arm/mach-lpc32xx/timer.c b/trunk/arch/arm/mach-lpc32xx/timer.c deleted file mode 100644 index 630dd4a74b26..000000000000 --- a/trunk/arch/arm/mach-lpc32xx/timer.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/timer.c - * - * Author: Kevin Wells - * - * Copyright (C) 2009 - 2010 NXP Semiconductors - * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven - * Ed Schouten - * Laurens Timmermans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -#include -#include -#include "common.h" - -static cycle_t lpc32xx_clksrc_read(struct clocksource *cs) -{ - return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE)); -} - -static struct clocksource lpc32xx_clksrc = { - .name = "lpc32xx_clksrc", - .shift = 24, - .rating = 300, - .read = lpc32xx_clksrc_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int lpc32xx_clkevt_next_event(unsigned long delta, - struct clock_event_device *dev) -{ - __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET, - LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); - __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE)); - __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, - LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); - - return 0; -} - -static void lpc32xx_clkevt_mode(enum clock_event_mode mode, - struct clock_event_device *dev) -{ - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - WARN_ON(1); - break; - - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_SHUTDOWN: - /* - * Disable the timer. When using oneshot, we must also - * disable the timer to wait for the first call to - * set_next_event(). - */ - __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); - break; - - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - break; - } -} - -static struct clock_event_device lpc32xx_clkevt = { - .name = "lpc32xx_clkevt", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .rating = 300, - .set_next_event = lpc32xx_clkevt_next_event, - .set_mode = lpc32xx_clkevt_mode, -}; - -static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &lpc32xx_clkevt; - - /* Clear match */ - __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0), - LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction lpc32xx_timer_irq = { - .name = "LPC32XX Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = lpc32xx_timer_interrupt, -}; - -/* - * The clock management driver isn't initialized at this point, so the - * clocks need to be enabled here manually and then tagged as used in - * the clock driver initialization - */ -static void __init lpc32xx_timer_init(void) -{ - u32 clkrate, pllreg; - - /* Enable timer clock */ - __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN | - LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN, - LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1); - - /* - * The clock driver isn't initialized at this point. So determine if - * the SYSCLK is driven from the PLL397 or main oscillator and then use - * it to compute the PLL frequency and the PCLK divider to get the base - * timer rates. This rate is needed to compute the tick rate. - */ - if (clk_is_sysclk_mainosc() != 0) - clkrate = LPC32XX_MAIN_OSC_FREQ; - else - clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ; - - /* Get ARM HCLKPLL register and convert it into a frequency */ - pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF; - clkrate = clk_get_pllrate_from_reg(clkrate, pllreg); - - /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */ - clkrate = clkrate / clk_get_pclk_div(); - - /* Initial timer setup */ - __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); - __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0), - LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); - __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE)); - __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) | - LCP32XX_TIMER_CNTR_MCR_STOP(0) | - LCP32XX_TIMER_CNTR_MCR_RESET(0), - LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE)); - - /* Setup tick interrupt */ - setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq); - - /* Setup the clockevent structure. */ - lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC, - lpc32xx_clkevt.shift); - lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1, - &lpc32xx_clkevt); - lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1, - &lpc32xx_clkevt) + 1; - lpc32xx_clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&lpc32xx_clkevt); - - /* Use timer1 as clock source. */ - __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET, - LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); - __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE)); - __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); - __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, - LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); - lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate, - lpc32xx_clksrc.shift); - clocksource_register(&lpc32xx_clksrc); -} - -struct sys_timer lpc32xx_timer = { - .init = &lpc32xx_timer_init, -}; - diff --git a/trunk/arch/arm/mach-msm/Makefile b/trunk/arch/arm/mach-msm/Makefile index 7ff8020d4d24..66677f0acaed 100644 --- a/trunk/arch/arm/mach-msm/Makefile +++ b/trunk/arch/arm/mach-msm/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o -obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o +obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o diff --git a/trunk/arch/arm/mach-msm/board-trout-gpio.c b/trunk/arch/arm/mach-msm/board-trout-gpio.c deleted file mode 100644 index 523d213bf79e..000000000000 --- a/trunk/arch/arm/mach-msm/board-trout-gpio.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * linux/arch/arm/mach-msm/gpio.c - * - * Copyright (C) 2005 HP Labs - * Copyright (C) 2008 Google, Inc. - * Copyright (C) 2009 Pavel Machek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include - -#include "board-trout.h" - -struct msm_gpio_chip { - struct gpio_chip chip; - void __iomem *reg; /* Base of register bank */ - u8 shadow; -}; - -#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip) - -static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset) -{ - struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip); - unsigned mask = 1 << offset; - - return !!(readb(msm_gpio->reg) & mask); -} - -static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) -{ - struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip); - unsigned mask = 1 << offset; - - if (val) - msm_gpio->shadow |= mask; - else - msm_gpio->shadow &= ~mask; - - writeb(msm_gpio->shadow, msm_gpio->reg); -} - -static int msm_gpiolib_direction_input(struct gpio_chip *chip, - unsigned offset) -{ - msm_gpiolib_set(chip, offset, 0); - return 0; -} - -static int msm_gpiolib_direction_output(struct gpio_chip *chip, - unsigned offset, int val) -{ - msm_gpiolib_set(chip, offset, val); - return 0; -} - -#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \ - { \ - .chip = { \ - .label = name, \ - .direction_input = msm_gpiolib_direction_input,\ - .direction_output = msm_gpiolib_direction_output, \ - .get = msm_gpiolib_get, \ - .set = msm_gpiolib_set, \ - .base = base_gpio, \ - .ngpio = 8, \ - }, \ - .reg = (void *) reg_num + TROUT_CPLD_BASE, \ - .shadow = shadow_val, \ - } - -static struct msm_gpio_chip msm_gpio_banks[] = { -#if defined(CONFIG_MSM_DEBUG_UART1) - /* H2W pins <-> UART1 */ - TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40), -#else - /* H2W pins <-> UART3, Bluetooth <-> UART1 */ - TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x80), -#endif - /* I2C pull */ - TROUT_GPIO_BANK("MISC3", 0x02, TROUT_GPIO_MISC3_BASE, 0x04), - TROUT_GPIO_BANK("MISC4", 0x04, TROUT_GPIO_MISC4_BASE, 0), - /* mmdi 32k en */ - TROUT_GPIO_BANK("MISC5", 0x06, TROUT_GPIO_MISC5_BASE, 0x04), - TROUT_GPIO_BANK("INT2", 0x08, TROUT_GPIO_INT2_BASE, 0), - TROUT_GPIO_BANK("MISC1", 0x0a, TROUT_GPIO_MISC1_BASE, 0), - TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0), -}; - -/* - * Called from the processor-specific init to enable GPIO pin support. - */ -int __init trout_init_gpio(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) - gpiochip_add(&msm_gpio_banks[i].chip); - - return 0; -} - -postcore_initcall(trout_init_gpio); - diff --git a/trunk/arch/arm/mach-msm/board-trout.c b/trunk/arch/arm/mach-msm/board-trout.c index e69a1502e4e8..dca5a5f062dc 100644 --- a/trunk/arch/arm/mach-msm/board-trout.c +++ b/trunk/arch/arm/mach-msm/board-trout.c @@ -50,6 +50,7 @@ static void __init trout_fixup(struct machine_desc *desc, struct tag *tags, { mi->nr_banks = 1; mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET); mi->bank[0].size = (101*1024*1024); } diff --git a/trunk/arch/arm/mach-msm/board-trout.h b/trunk/arch/arm/mach-msm/board-trout.h index 651851c3e1dd..4f345a5a0a61 100644 --- a/trunk/arch/arm/mach-msm/board-trout.h +++ b/trunk/arch/arm/mach-msm/board-trout.h @@ -1,162 +1,5 @@ -/* linux/arch/arm/mach-msm/board-trout.h -** Author: Brian Swetland -*/ -#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H -#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H - -#include - -#define MSM_SMI_BASE 0x00000000 -#define MSM_SMI_SIZE 0x00800000 - -#define MSM_EBI_BASE 0x10000000 -#define MSM_EBI_SIZE 0x06e00000 - -#define MSM_PMEM_GPU0_BASE 0x00000000 -#define MSM_PMEM_GPU0_SIZE 0x00700000 - -#define MSM_PMEM_MDP_BASE 0x02000000 -#define MSM_PMEM_MDP_SIZE 0x00800000 - -#define MSM_PMEM_ADSP_BASE 0x02800000 -#define MSM_PMEM_ADSP_SIZE 0x00800000 - -#define MSM_PMEM_CAMERA_BASE 0x03000000 -#define MSM_PMEM_CAMERA_SIZE 0x00800000 - -#define MSM_FB_BASE 0x03800000 -#define MSM_FB_SIZE 0x00100000 - -#define MSM_LINUX_BASE MSM_EBI_BASE -#define MSM_LINUX_SIZE 0x06500000 - -#define MSM_PMEM_GPU1_SIZE 0x800000 -#define MSM_PMEM_GPU1_BASE (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE) - -#define MSM_RAM_CONSOLE_BASE (MSM_EBI_BASE + 0x6d00000) -#define MSM_RAM_CONSOLE_SIZE (128 * SZ_1K) - -#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE) -#error invalid memory map -#endif - -#define DECLARE_MSM_IOMAP -#include - -#define TROUT_4_BALL_UP_0 1 -#define TROUT_4_BALL_LEFT_0 18 -#define TROUT_4_BALL_DOWN_0 57 -#define TROUT_4_BALL_RIGHT_0 91 - -#define TROUT_5_BALL_UP_0 94 -#define TROUT_5_BALL_LEFT_0 18 -#define TROUT_5_BALL_DOWN_0 90 -#define TROUT_5_BALL_RIGHT_0 19 - -#define TROUT_POWER_KEY 20 - -#define TROUT_4_TP_LS_EN 19 -#define TROUT_5_TP_LS_EN 1 #define TROUT_CPLD_BASE 0xE8100000 #define TROUT_CPLD_START 0x98000000 #define TROUT_CPLD_SIZE SZ_4K -#define TROUT_GPIO_CABLE_IN1 (83) -#define TROUT_GPIO_CABLE_IN2 (49) - -#define TROUT_GPIO_START (128) - -#define TROUT_GPIO_INT_MASK0_REG (0x0c) -#define TROUT_GPIO_INT_STAT0_REG (0x0e) -#define TROUT_GPIO_INT_MASK1_REG (0x14) -#define TROUT_GPIO_INT_STAT1_REG (0x10) - -#define TROUT_GPIO_HAPTIC_PWM (28) -#define TROUT_GPIO_PS_HOLD (25) - -#define TROUT_GPIO_MISC2_BASE (TROUT_GPIO_START + 0x00) -#define TROUT_GPIO_MISC3_BASE (TROUT_GPIO_START + 0x08) -#define TROUT_GPIO_MISC4_BASE (TROUT_GPIO_START + 0x10) -#define TROUT_GPIO_MISC5_BASE (TROUT_GPIO_START + 0x18) -#define TROUT_GPIO_INT2_BASE (TROUT_GPIO_START + 0x20) -#define TROUT_GPIO_MISC1_BASE (TROUT_GPIO_START + 0x28) -#define TROUT_GPIO_VIRTUAL_BASE (TROUT_GPIO_START + 0x30) -#define TROUT_GPIO_INT5_BASE (TROUT_GPIO_START + 0x48) - -#define TROUT_GPIO_CHARGER_EN (TROUT_GPIO_MISC2_BASE + 0) -#define TROUT_GPIO_ISET (TROUT_GPIO_MISC2_BASE + 1) -#define TROUT_GPIO_H2W_DAT_DIR (TROUT_GPIO_MISC2_BASE + 2) -#define TROUT_GPIO_H2W_CLK_DIR (TROUT_GPIO_MISC2_BASE + 3) -#define TROUT_GPIO_H2W_DAT_GPO (TROUT_GPIO_MISC2_BASE + 4) -#define TROUT_GPIO_H2W_CLK_GPO (TROUT_GPIO_MISC2_BASE + 5) -#define TROUT_GPIO_H2W_SEL0 (TROUT_GPIO_MISC2_BASE + 6) -#define TROUT_GPIO_H2W_SEL1 (TROUT_GPIO_MISC2_BASE + 7) - -#define TROUT_GPIO_SPOTLIGHT_EN (TROUT_GPIO_MISC3_BASE + 0) -#define TROUT_GPIO_FLASH_EN (TROUT_GPIO_MISC3_BASE + 1) -#define TROUT_GPIO_I2C_PULL (TROUT_GPIO_MISC3_BASE + 2) -#define TROUT_GPIO_TP_I2C_PULL (TROUT_GPIO_MISC3_BASE + 3) -#define TROUT_GPIO_TP_EN (TROUT_GPIO_MISC3_BASE + 4) -#define TROUT_GPIO_JOG_EN (TROUT_GPIO_MISC3_BASE + 5) -#define TROUT_GPIO_UI_LED_EN (TROUT_GPIO_MISC3_BASE + 6) -#define TROUT_GPIO_QTKEY_LED_EN (TROUT_GPIO_MISC3_BASE + 7) - -#define TROUT_GPIO_VCM_PWDN (TROUT_GPIO_MISC4_BASE + 0) -#define TROUT_GPIO_USB_H2W_SW (TROUT_GPIO_MISC4_BASE + 1) -#define TROUT_GPIO_COMPASS_RST_N (TROUT_GPIO_MISC4_BASE + 2) -#define TROUT_GPIO_HAPTIC_EN_UP (TROUT_GPIO_MISC4_BASE + 3) -#define TROUT_GPIO_HAPTIC_EN_MAIN (TROUT_GPIO_MISC4_BASE + 4) -#define TROUT_GPIO_USB_PHY_RST_N (TROUT_GPIO_MISC4_BASE + 5) -#define TROUT_GPIO_WIFI_PA_RESETX (TROUT_GPIO_MISC4_BASE + 6) -#define TROUT_GPIO_WIFI_EN (TROUT_GPIO_MISC4_BASE + 7) - -#define TROUT_GPIO_BT_32K_EN (TROUT_GPIO_MISC5_BASE + 0) -#define TROUT_GPIO_MAC_32K_EN (TROUT_GPIO_MISC5_BASE + 1) -#define TROUT_GPIO_MDDI_32K_EN (TROUT_GPIO_MISC5_BASE + 2) -#define TROUT_GPIO_COMPASS_32K_EN (TROUT_GPIO_MISC5_BASE + 3) - -#define TROUT_GPIO_NAVI_ACT_N (TROUT_GPIO_INT2_BASE + 0) -#define TROUT_GPIO_COMPASS_IRQ (TROUT_GPIO_INT2_BASE + 1) -#define TROUT_GPIO_SLIDING_DET (TROUT_GPIO_INT2_BASE + 2) -#define TROUT_GPIO_AUD_HSMIC_DET_N (TROUT_GPIO_INT2_BASE + 3) -#define TROUT_GPIO_SD_DOOR_N (TROUT_GPIO_INT2_BASE + 4) -#define TROUT_GPIO_CAM_BTN_STEP1_N (TROUT_GPIO_INT2_BASE + 5) -#define TROUT_GPIO_CAM_BTN_STEP2_N (TROUT_GPIO_INT2_BASE + 6) -#define TROUT_GPIO_TP_ATT_N (TROUT_GPIO_INT2_BASE + 7) -#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE (TROUT_GPIO_NAVI_ACT_N) -#define TROUT_GPIO_BANK0_LAST_INT_SOURCE (TROUT_GPIO_TP_ATT_N) - -#define TROUT_GPIO_H2W_DAT_GPI (TROUT_GPIO_MISC1_BASE + 0) -#define TROUT_GPIO_H2W_CLK_GPI (TROUT_GPIO_MISC1_BASE + 1) -#define TROUT_GPIO_CPLD128_VER_0 (TROUT_GPIO_MISC1_BASE + 4) -#define TROUT_GPIO_CPLD128_VER_1 (TROUT_GPIO_MISC1_BASE + 5) -#define TROUT_GPIO_CPLD128_VER_2 (TROUT_GPIO_MISC1_BASE + 6) -#define TROUT_GPIO_CPLD128_VER_3 (TROUT_GPIO_MISC1_BASE + 7) - -#define TROUT_GPIO_SDMC_CD_N (TROUT_GPIO_VIRTUAL_BASE + 0) -#define TROUT_GPIO_END (TROUT_GPIO_SDMC_CD_N) -#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N) -#define TROUT_GPIO_BANK1_LAST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N) - -#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \ - (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE) - -#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS) -#define TROUT_INT_BANK0_COUNT (8) -#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT) -#define TROUT_INT_BANK1_COUNT (1) -#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \ - TROUT_INT_BANK1_COUNT - 1) -#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \ - (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \ - (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n))) - -#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT) -#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7)) -#define TROUT_BANK_TO_MASK_REG(bank) \ - (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG) -#define TROUT_BANK_TO_STAT_REG(bank) \ - (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG) - -#endif /* GUARD */ diff --git a/trunk/arch/arm/mach-msm/include/mach/gpio.h b/trunk/arch/arm/mach-msm/include/mach/gpio.h index 83e47c0d5c2e..262b441b4374 100644 --- a/trunk/arch/arm/mach-msm/include/mach/gpio.h +++ b/trunk/arch/arm/mach-msm/include/mach/gpio.h @@ -16,13 +16,6 @@ #ifndef __ASM_ARCH_MSM_GPIO_H #define __ASM_ARCH_MSM_GPIO_H -#include - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep -#define gpio_to_irq __gpio_to_irq - /** * struct msm_gpio - GPIO pin description * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config() diff --git a/trunk/arch/arm/mach-mx1/Kconfig b/trunk/arch/arm/mach-mx1/Kconfig new file mode 100644 index 000000000000..eb7660f5d4b7 --- /dev/null +++ b/trunk/arch/arm/mach-mx1/Kconfig @@ -0,0 +1,19 @@ +if ARCH_MX1 + +comment "MX1 platforms:" + +config MACH_MXLADS + bool + +config ARCH_MX1ADS + bool "MX1ADS platform" + select MACH_MXLADS + help + Say Y here if you are using Motorola MX1ADS/MXLADS boards + +config MACH_SCB9328 + bool "Synertronixx scb9328" + help + Say Y here if you are using a Synertronixx scb9328 board + +endif diff --git a/trunk/arch/arm/mach-mx1/Makefile b/trunk/arch/arm/mach-mx1/Makefile new file mode 100644 index 000000000000..fc2ddf82441b --- /dev/null +++ b/trunk/arch/arm/mach-mx1/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS +obj-y += generic.o clock.o devices.o + +# Support for CMOS sensor interface +obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o + +# Specific board support +obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o +obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o diff --git a/trunk/arch/arm/mach-mx1/Makefile.boot b/trunk/arch/arm/mach-mx1/Makefile.boot new file mode 100644 index 000000000000..8ed1492288a2 --- /dev/null +++ b/trunk/arch/arm/mach-mx1/Makefile.boot @@ -0,0 +1,4 @@ + zreladdr-y := 0x08008000 +params_phys-y := 0x08000100 +initrd_phys-y := 0x08800000 + diff --git a/trunk/arch/arm/mach-imx/clock-imx1.c b/trunk/arch/arm/mach-mx1/clock.c similarity index 90% rename from trunk/arch/arm/mach-imx/clock-imx1.c rename to trunk/arch/arm/mach-mx1/clock.c index c05096c38301..6cf2d4a7511d 100644 --- a/trunk/arch/arm/mach-imx/clock-imx1.c +++ b/trunk/arch/arm/mach-mx1/clock.c @@ -2,17 +2,18 @@ * Copyright (C) 2008 Sascha Hauer , Pengutronix * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include @@ -28,41 +29,7 @@ #include #include #include - -#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off))) - -/* CCM register addresses */ -#define CCM_CSCR IO_ADDR_CCM(0x0) -#define CCM_MPCTL0 IO_ADDR_CCM(0x4) -#define CCM_SPCTL0 IO_ADDR_CCM(0xc) -#define CCM_PCDR IO_ADDR_CCM(0x20) - -#define CCM_CSCR_CLKO_OFFSET 29 -#define CCM_CSCR_CLKO_MASK (0x7 << 29) -#define CCM_CSCR_USB_OFFSET 26 -#define CCM_CSCR_USB_MASK (0x7 << 26) -#define CCM_CSCR_OSC_EN_SHIFT 17 -#define CCM_CSCR_SYSTEM_SEL (1 << 16) -#define CCM_CSCR_BCLK_OFFSET 10 -#define CCM_CSCR_BCLK_MASK (0xf << 10) -#define CCM_CSCR_PRESC (1 << 15) - -#define CCM_PCDR_PCLK3_OFFSET 16 -#define CCM_PCDR_PCLK3_MASK (0x7f << 16) -#define CCM_PCDR_PCLK2_OFFSET 4 -#define CCM_PCDR_PCLK2_MASK (0xf << 4) -#define CCM_PCDR_PCLK1_OFFSET 0 -#define CCM_PCDR_PCLK1_MASK 0xf - -#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off))) - -/* SCM register addresses */ -#define SCM_GCCR IO_ADDR_SCM(0xc) - -#define SCM_GCCR_DMA_CLK_EN_OFFSET 3 -#define SCM_GCCR_CSI_CLK_EN_OFFSET 2 -#define SCM_GCCR_MMA_CLK_EN_OFFSET 1 -#define SCM_GCCR_USBD_CLK_EN_OFFSET 0 +#include "crm_regs.h" static int _clk_enable(struct clk *clk) { @@ -629,8 +596,7 @@ int __init mx1_clocks_init(unsigned long fref) clk_enable(&hclk); clk_enable(&fclk); - mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), - MX1_TIM1_INT); + mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT); return 0; } diff --git a/trunk/arch/arm/mach-mx1/crm_regs.h b/trunk/arch/arm/mach-mx1/crm_regs.h new file mode 100644 index 000000000000..22e866ff0c09 --- /dev/null +++ b/trunk/arch/arm/mach-mx1/crm_regs.h @@ -0,0 +1,55 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (c) 2008 Paulius Zaleckas + * + * This file may be distributed under the terms of the GNU General + * Public License, version 2. + */ + +#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__ + +#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) +#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR) + +/* CCM register addresses */ +#define CCM_CSCR (CCM_BASE + 0x0) +#define CCM_MPCTL0 (CCM_BASE + 0x4) +#define CCM_MPCTL1 (CCM_BASE + 0x8) +#define CCM_SPCTL0 (CCM_BASE + 0xC) +#define CCM_SPCTL1 (CCM_BASE + 0x10) +#define CCM_PCDR (CCM_BASE + 0x20) + +#define CCM_CSCR_CLKO_OFFSET 29 +#define CCM_CSCR_CLKO_MASK (0x7 << 29) +#define CCM_CSCR_USB_OFFSET 26 +#define CCM_CSCR_USB_MASK (0x7 << 26) +#define CCM_CSCR_SPLL_RESTART (1 << 22) +#define CCM_CSCR_MPLL_RESTART (1 << 21) +#define CCM_CSCR_OSC_EN_SHIFT 17 +#define CCM_CSCR_SYSTEM_SEL (1 << 16) +#define CCM_CSCR_BCLK_OFFSET 10 +#define CCM_CSCR_BCLK_MASK (0xF << 10) +#define CCM_CSCR_PRESC (1 << 15) +#define CCM_CSCR_SPEN (1 << 1) +#define CCM_CSCR_MPEN (1 << 0) + +#define CCM_PCDR_PCLK3_OFFSET 16 +#define CCM_PCDR_PCLK3_MASK (0x7F << 16) +#define CCM_PCDR_PCLK2_OFFSET 4 +#define CCM_PCDR_PCLK2_MASK (0xF << 4) +#define CCM_PCDR_PCLK1_OFFSET 0 +#define CCM_PCDR_PCLK1_MASK 0xF + +/* SCM register addresses */ +#define SCM_SIDR (SCM_BASE + 0x0) +#define SCM_FMCR (SCM_BASE + 0x4) +#define SCM_GPCR (SCM_BASE + 0x8) +#define SCM_GCCR (SCM_BASE + 0xC) + +#define SCM_GCCR_DMA_CLK_EN_OFFSET 3 +#define SCM_GCCR_CSI_CLK_EN_OFFSET 2 +#define SCM_GCCR_MMA_CLK_EN_OFFSET 1 +#define SCM_GCCR_USBD_CLK_EN_OFFSET 0 + +#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */ diff --git a/trunk/arch/arm/mach-mx1/devices.c b/trunk/arch/arm/mach-mx1/devices.c new file mode 100644 index 000000000000..b6be29d1cb08 --- /dev/null +++ b/trunk/arch/arm/mach-mx1/devices.c @@ -0,0 +1,242 @@ +/* + * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Sascha Hauer, kernel@pengutronix.de + * Copyright (c) 2008 Paulius Zaleckas + * Copyright (c) 2008 Darius Augulis + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +static struct resource imx_csi_resources[] = { + { + .start = 0x00224000, + .end = 0x00224010, + .flags = IORESOURCE_MEM, + }, { + .start = CSI_INT, + .end = CSI_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 imx_csi_dmamask = 0xffffffffUL; + +struct platform_device imx_csi_device = { + .name = "mx1-camera", + .id = 0, /* This is used to put cameras on this interface */ + .dev = { + .dma_mask = &imx_csi_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = imx_csi_resources, + .num_resources = ARRAY_SIZE(imx_csi_resources), +}; + +static struct resource imx_i2c_resources[] = { + { + .start = 0x00217000, + .end = 0x00217010, + .flags = IORESOURCE_MEM, + }, { + .start = I2C_INT, + .end = I2C_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_i2c_device = { + .name = "imx-i2c", + .id = 0, + .resource = imx_i2c_resources, + .num_resources = ARRAY_SIZE(imx_i2c_resources), +}; + +static struct resource imx_uart1_resources[] = { + { + .start = UART1_BASE_ADDR, + .end = UART1_BASE_ADDR + 0xD0, + .flags = IORESOURCE_MEM, + }, { + .start = UART1_MINT_RX, + .end = UART1_MINT_RX, + .flags = IORESOURCE_IRQ, + }, { + .start = UART1_MINT_TX, + .end = UART1_MINT_TX, + .flags = IORESOURCE_IRQ, + }, { + .start = UART1_MINT_RTS, + .end = UART1_MINT_RTS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_uart1_device = { + .name = "imx-uart", + .id = 0, + .num_resources = ARRAY_SIZE(imx_uart1_resources), + .resource = imx_uart1_resources, +}; + +static struct resource imx_uart2_resources[] = { + { + .start = UART2_BASE_ADDR, + .end = UART2_BASE_ADDR + 0xD0, + .flags = IORESOURCE_MEM, + }, { + .start = UART2_MINT_RX, + .end = UART2_MINT_RX, + .flags = IORESOURCE_IRQ, + }, { + .start = UART2_MINT_TX, + .end = UART2_MINT_TX, + .flags = IORESOURCE_IRQ, + }, { + .start = UART2_MINT_RTS, + .end = UART2_MINT_RTS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_uart2_device = { + .name = "imx-uart", + .id = 1, + .num_resources = ARRAY_SIZE(imx_uart2_resources), + .resource = imx_uart2_resources, +}; + +static struct resource imx_rtc_resources[] = { + { + .start = 0x00204000, + .end = 0x00204024, + .flags = IORESOURCE_MEM, + }, { + .start = RTC_INT, + .end = RTC_INT, + .flags = IORESOURCE_IRQ, + }, { + .start = RTC_SAMINT, + .end = RTC_SAMINT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_rtc_device = { + .name = "rtc-imx", + .id = 0, + .resource = imx_rtc_resources, + .num_resources = ARRAY_SIZE(imx_rtc_resources), +}; + +static struct resource imx_wdt_resources[] = { + { + .start = 0x00201000, + .end = 0x00201008, + .flags = IORESOURCE_MEM, + }, { + .start = WDT_INT, + .end = WDT_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_wdt_device = { + .name = "imx-wdt", + .id = 0, + .resource = imx_wdt_resources, + .num_resources = ARRAY_SIZE(imx_wdt_resources), +}; + +static struct resource imx_usb_resources[] = { + { + .start = 0x00212000, + .end = 0x00212148, + .flags = IORESOURCE_MEM, + }, { + .start = USBD_INT0, + .end = USBD_INT0, + .flags = IORESOURCE_IRQ, + }, { + .start = USBD_INT1, + .end = USBD_INT1, + .flags = IORESOURCE_IRQ, + }, { + .start = USBD_INT2, + .end = USBD_INT2, + .flags = IORESOURCE_IRQ, + }, { + .start = USBD_INT3, + .end = USBD_INT3, + .flags = IORESOURCE_IRQ, + }, { + .start = USBD_INT4, + .end = USBD_INT4, + .flags = IORESOURCE_IRQ, + }, { + .start = USBD_INT5, + .end = USBD_INT5, + .flags = IORESOURCE_IRQ, + }, { + .start = USBD_INT6, + .end = USBD_INT6, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_usb_device = { + .name = "imx_udc", + .id = 0, + .num_resources = ARRAY_SIZE(imx_usb_resources), + .resource = imx_usb_resources, +}; + +/* GPIO port description */ +static struct mxc_gpio_port imx_gpio_ports[] = { + { + .chip.label = "gpio-0", + .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR), + .irq = GPIO_INT_PORTA, + .virtual_irq_start = MXC_GPIO_IRQ_START, + }, { + .chip.label = "gpio-1", + .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100), + .irq = GPIO_INT_PORTB, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32, + }, { + .chip.label = "gpio-2", + .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200), + .irq = GPIO_INT_PORTC, + .virtual_irq_start = MXC_GPIO_IRQ_START + 64, + }, { + .chip.label = "gpio-3", + .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300), + .irq = GPIO_INT_PORTD, + .virtual_irq_start = MXC_GPIO_IRQ_START + 96, + } +}; + +int __init mxc_register_gpios(void) +{ + return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); +} diff --git a/trunk/arch/arm/mach-mx1/devices.h b/trunk/arch/arm/mach-mx1/devices.h new file mode 100644 index 000000000000..0da5d7cce3a2 --- /dev/null +++ b/trunk/arch/arm/mach-mx1/devices.h @@ -0,0 +1,7 @@ +extern struct platform_device imx_csi_device; +extern struct platform_device imx_i2c_device; +extern struct platform_device imx_uart1_device; +extern struct platform_device imx_uart2_device; +extern struct platform_device imx_rtc_device; +extern struct platform_device imx_wdt_device; +extern struct platform_device imx_usb_device; diff --git a/trunk/arch/arm/mach-imx/mm-imx1.c b/trunk/arch/arm/mach-mx1/generic.c similarity index 68% rename from trunk/arch/arm/mach-imx/mm-imx1.c rename to trunk/arch/arm/mach-mx1/generic.c index 9be92b96dc89..7f9fc1034c08 100644 --- a/trunk/arch/arm/mach-imx/mm-imx1.c +++ b/trunk/arch/arm/mach-mx1/generic.c @@ -3,7 +3,7 @@ * Created: april 20th, 2004 * Copyright: Synertronixx GmbH * - * Common code for i.MX1 machines + * Common code for i.MX machines * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,6 +14,11 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * */ #include #include @@ -26,25 +31,23 @@ static struct map_desc imx_io_desc[] __initdata = { { - .virtual = MX1_IO_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR), - .length = MX1_IO_SIZE, - .type = MT_DEVICE + .virtual = IMX_IO_BASE, + .pfn = __phys_to_pfn(IMX_IO_PHYS), + .length = IMX_IO_SIZE, + .type = MT_DEVICE } }; void __init mx1_map_io(void) { mxc_set_cpu_type(MXC_CPU_MX1); - mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); + mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR)); iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); } -int imx1_register_gpios(void); - void __init mx1_init_irq(void) { - mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); - imx1_register_gpios(); + mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); } + diff --git a/trunk/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/trunk/arch/arm/mach-mx1/ksym_mx1.c similarity index 100% rename from trunk/arch/arm/mach-imx/mx1-camera-fiq-ksym.c rename to trunk/arch/arm/mach-mx1/ksym_mx1.c diff --git a/trunk/arch/arm/mach-imx/mach-mx1ads.c b/trunk/arch/arm/mach-mx1/mach-mx1ads.c similarity index 81% rename from trunk/arch/arm/mach-imx/mach-mx1ads.c rename to trunk/arch/arm/mach-mx1/mach-mx1ads.c index 77a760cfadc0..51f3cfd83db2 100644 --- a/trunk/arch/arm/mach-imx/mach-mx1ads.c +++ b/trunk/arch/arm/mach-mx1/mach-mx1ads.c @@ -26,10 +26,10 @@ #include #include #include +#include #include #include -#include "devices-imx1.h" #include "devices.h" static int mx1ads_pins[] = { @@ -58,12 +58,12 @@ static int mx1ads_pins[] = { * UARTs platform data */ -static const struct imxuart_platform_data uart0_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxuart_platform_data uart1_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, +static struct imxuart_platform_data uart_pdata[] = { + { + .flags = IMXUART_HAVE_RTSCTS, + }, { + .flags = IMXUART_HAVE_RTSCTS, + }, }; /* @@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = { }; static struct resource flash_resource = { - .start = MX1_CS0_PHYS, - .end = MX1_CS0_PHYS + SZ_32M - 1, + .start = IMX_CS0_PHYS, + .end = IMX_CS0_PHYS + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -98,7 +98,7 @@ static struct pcf857x_platform_data pcf857x_data[] = { } }; -static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = { +static struct imxi2c_platform_data mx1ads_i2c_data = { .bitrate = 100000, }; @@ -121,8 +121,8 @@ static void __init mx1ads_init(void) ARRAY_SIZE(mx1ads_pins), "mx1ads"); /* UART */ - imx1_add_imx_uart0(&uart0_pdata); - imx1_add_imx_uart1(&uart1_pdata); + mxc_register_device(&imx_uart1_device, &uart_pdata[0]); + mxc_register_device(&imx_uart2_device, &uart_pdata[1]); /* Physmap flash */ mxc_register_device(&flash_device, &mx1ads_flash_data); @@ -131,7 +131,7 @@ static void __init mx1ads_init(void) i2c_register_board_info(0, mx1ads_i2c_devices, ARRAY_SIZE(mx1ads_i2c_devices)); - imx1_add_i2c_imx(&mx1ads_i2c_data); + mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data); } static void __init mx1ads_timer_init(void) @@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = { MACHINE_START(MX1ADS, "Freescale MX1ADS") /* Maintainer: Sascha Hauer, Pengutronix */ - .phys_io = MX1_IO_BASE_ADDR, - .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc, + .phys_io = IMX_IO_PHYS, + .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, @@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") MACHINE_END MACHINE_START(MXLADS, "Freescale MXLADS") - .phys_io = MX1_IO_BASE_ADDR, - .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc, + .phys_io = IMX_IO_PHYS, + .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, diff --git a/trunk/arch/arm/mach-imx/mach-scb9328.c b/trunk/arch/arm/mach-mx1/mach-scb9328.c similarity index 89% rename from trunk/arch/arm/mach-imx/mach-scb9328.c rename to trunk/arch/arm/mach-mx1/mach-scb9328.c index 88bf0d1e26e6..7587a7a12460 100644 --- a/trunk/arch/arm/mach-imx/mach-scb9328.c +++ b/trunk/arch/arm/mach-mx1/mach-scb9328.c @@ -22,17 +22,17 @@ #include #include #include +#include #include -#include "devices-imx1.h" #include "devices.h" /* * This scb9328 has a 32MiB flash */ static struct resource flash_resource = { - .start = MX1_CS0_PHYS, - .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1, + .start = IMX_CS0_PHYS, + .end = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1, .flags = IORESOURCE_MEM, }; @@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = { static struct resource dm9000x_resources[] = { { .name = "address area", - .start = MX1_CS5_PHYS, - .end = MX1_CS5_PHYS + 1, + .start = IMX_CS5_PHYS, + .end = IMX_CS5_PHYS + 1, .flags = IORESOURCE_MEM, /* address access */ }, { .name = "data area", - .start = MX1_CS5_PHYS + 4, - .end = MX1_CS5_PHYS + 5, + .start = IMX_CS5_PHYS + 4, + .end = IMX_CS5_PHYS + 5, .flags = IORESOURCE_MEM, /* data access */ }, { .start = IRQ_GPIOC(3), @@ -108,13 +108,14 @@ static int uart1_mxc_init(struct platform_device *pdev) ARRAY_SIZE(mxc_uart1_pins), "UART1"); } -static void uart1_mxc_exit(struct platform_device *pdev) +static int uart1_mxc_exit(struct platform_device *pdev) { mxc_gpio_release_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins)); + return 0; } -static const struct imxuart_platform_data uart_pdata __initconst = { +static struct imxuart_platform_data uart_pdata = { .init = uart1_mxc_init, .exit = uart1_mxc_exit, .flags = IMXUART_HAVE_RTSCTS, @@ -130,7 +131,7 @@ static struct platform_device *devices[] __initdata = { */ static void __init scb9328_init(void) { - imx1_add_imx_uart0(&uart_pdata); + mxc_register_device(&imx_uart1_device, &uart_pdata); printk(KERN_INFO"Scb9328: Adding devices\n"); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/trunk/arch/arm/mach-imx/mx1-camera-fiq.S b/trunk/arch/arm/mach-mx1/mx1_camera_fiq.S similarity index 100% rename from trunk/arch/arm/mach-imx/mx1-camera-fiq.S rename to trunk/arch/arm/mach-mx1/mx1_camera_fiq.S diff --git a/trunk/arch/arm/mach-imx/Kconfig b/trunk/arch/arm/mach-mx2/Kconfig similarity index 57% rename from trunk/arch/arm/mach-imx/Kconfig rename to trunk/arch/arm/mach-mx2/Kconfig index c5c0369bb481..742fd4e6dcb9 100644 --- a/trunk/arch/arm/mach-imx/Kconfig +++ b/trunk/arch/arm/mach-mx2/Kconfig @@ -1,103 +1,42 @@ -config IMX_HAVE_DMA_V1 - bool - -if ARCH_MX1 - -config SOC_IMX1 - select CPU_ARM920T - select IMX_HAVE_DMA_V1 - select IMX_HAVE_IOMUX_V1 - bool - -comment "MX1 platforms:" -config MACH_MXLADS - bool - -config ARCH_MX1ADS - bool "MX1ADS platform" - select MACH_MXLADS - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - help - Say Y here if you are using Motorola MX1ADS/MXLADS boards - -config MACH_SCB9328 - bool "Synertronixx scb9328" - select IMX_HAVE_PLATFORM_IMX_UART - help - Say Y here if you are using a Synertronixx scb9328 board - -endif - if ARCH_MX2 -config SOC_IMX21 - select CPU_ARM926T - select ARCH_MXC_AUDMUX_V1 - select IMX_HAVE_DMA_V1 - select IMX_HAVE_IOMUX_V1 - bool - -config SOC_IMX27 - select CPU_ARM926T - select ARCH_MXC_AUDMUX_V1 - select IMX_HAVE_DMA_V1 - select IMX_HAVE_IOMUX_V1 - bool - choice prompt "CPUs:" default MACH_MX21 config MACH_MX21 bool "i.MX21 support" - select SOC_IMX21 + select ARCH_MXC_AUDMUX_V1 help This enables support for Freescale's MX2 based i.MX21 processor. config MACH_MX27 bool "i.MX27 support" - select SOC_IMX27 + select ARCH_MXC_AUDMUX_V1 help This enables support for Freescale's MX2 based i.MX27 processor. endchoice -endif - -if MACH_MX21 - -comment "MX21 platforms:" +comment "MX2 platforms:" config MACH_MX21ADS bool "MX21ADS platform" - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND + depends on MACH_MX21 help Include support for MX21ADS platform. This includes specific configurations for the board and its peripherals. -endif - -if MACH_MX27 - -comment "MX27 platforms:" - config MACH_MX27ADS bool "MX27ADS platform" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND + depends on MACH_MX27 help Include support for MX27ADS platform. This includes specific configurations for the board and its peripherals. config MACH_PCM038 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX + depends on MACH_MX27 select MXC_ULPI if USB_ULPI help Include support for phyCORE-i.MX27 (aka pcm038) platform. This @@ -119,9 +58,7 @@ endchoice config MACH_CPUIMX27 bool "Eukrea CPUIMX27 module" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND + depends on MACH_MX27 help Include support for Eukrea CPUIMX27 platform. This includes specific configurations for the module and its peripherals. @@ -130,16 +67,9 @@ config MACH_EUKREA_CPUIMX27_USESDHC2 bool "CPUIMX27 integrates SDHC2 module" depends on MACH_CPUIMX27 help - This adds support for the internal SDHC2 used on CPUIMX27 + This adds support for the internal SDHC2 used on CPUIMX27 used for wifi or eMMC. -config MACH_EUKREA_CPUIMX27_USEUART4 - bool "CPUIMX27 integrates UART4 module" - depends on MACH_CPUIMX27 - help - This adds support for the internal UART4 used on CPUIMX27 - for bluetooth. - choice prompt "Baseboard" depends on MACH_CPUIMX27 @@ -148,8 +78,6 @@ choice config MACH_EUKREA_MBIMX27_BASEBOARD prompt "Eukrea MBIMX27 development board" bool - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SPI_IMX help This adds board specific devices that can be found on Eukrea's MBIMX27 evaluation board. @@ -158,24 +86,21 @@ endchoice config MACH_MX27_3DS bool "MX27PDK platform" - select IMX_HAVE_PLATFORM_IMX_UART + depends on MACH_MX27 help Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" - select IMX_HAVE_PLATFORM_IMX_UART + depends on MACH_MX27 help Include support for MX27 LITEKIT platform. This includes specific configurations for the board and its peripherals. config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX + depends on MACH_MX27 select MXC_ULPI if USB_ULPI help Include support for phyCARD-s (aka pca100) platform. This @@ -183,9 +108,7 @@ config MACH_PCA100 config MACH_MXT_TD60 bool "Maxtrack i-MXT TD60" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND + depends on MACH_MX27 help Include support for i-MXT (aka td60) platform. This includes specific configurations for the module and its peripherals. diff --git a/trunk/arch/arm/mach-imx/Makefile b/trunk/arch/arm/mach-mx2/Makefile similarity index 55% rename from trunk/arch/arm/mach-imx/Makefile rename to trunk/arch/arm/mach-mx2/Makefile index 46a9fdfbbd15..e3254faac828 100644 --- a/trunk/arch/arm/mach-imx/Makefile +++ b/trunk/arch/arm/mach-mx2/Makefile @@ -4,24 +4,14 @@ # Object file lists. -obj-y := devices.o +obj-y := devices.o serial.o -obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o +obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o -obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o -obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o - -obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o -obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o - -# Support for CMOS sensor interface -obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o - -obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o -obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o +obj-$(CONFIG_MACH_MX27) += cpu_imx27.o +obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o - obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o diff --git a/trunk/arch/arm/mach-imx/Makefile.boot b/trunk/arch/arm/mach-mx2/Makefile.boot similarity index 67% rename from trunk/arch/arm/mach-imx/Makefile.boot rename to trunk/arch/arm/mach-mx2/Makefile.boot index 7988a85cf07d..e867398a8fdb 100644 --- a/trunk/arch/arm/mach-imx/Makefile.boot +++ b/trunk/arch/arm/mach-mx2/Makefile.boot @@ -1,7 +1,3 @@ -zreladdr-$(CONFIG_ARCH_MX1) := 0x08008000 -params_phys-$(CONFIG_ARCH_MX1) := 0x08000100 -initrd_phys-$(CONFIG_ARCH_MX1) := 0x08800000 - zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 diff --git a/trunk/arch/arm/mach-imx/clock-imx21.c b/trunk/arch/arm/mach-mx2/clock_imx21.c similarity index 100% rename from trunk/arch/arm/mach-imx/clock-imx21.c rename to trunk/arch/arm/mach-mx2/clock_imx21.c diff --git a/trunk/arch/arm/mach-imx/clock-imx27.c b/trunk/arch/arm/mach-mx2/clock_imx27.c similarity index 99% rename from trunk/arch/arm/mach-imx/clock-imx27.c rename to trunk/arch/arm/mach-mx2/clock_imx27.c index 5a1aa15c8a16..0f0823c8b170 100644 --- a/trunk/arch/arm/mach-imx/clock-imx27.c +++ b/trunk/arch/arm/mach-mx2/clock_imx27.c @@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) - _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) + _REGISTER_CLOCK(NULL, "csi", csi_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1) _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk) diff --git a/trunk/arch/arm/mach-imx/cpu-imx27.c b/trunk/arch/arm/mach-mx2/cpu_imx27.c similarity index 100% rename from trunk/arch/arm/mach-imx/cpu-imx27.c rename to trunk/arch/arm/mach-mx2/cpu_imx27.c diff --git a/trunk/arch/arm/mach-imx/devices.c b/trunk/arch/arm/mach-mx2/devices.c similarity index 67% rename from trunk/arch/arm/mach-imx/devices.c rename to trunk/arch/arm/mach-mx2/devices.c index 9c271a752b84..a0aeb8a4adc1 100644 --- a/trunk/arch/arm/mach-imx/devices.c +++ b/trunk/arch/arm/mach-mx2/devices.c @@ -11,9 +11,6 @@ * * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * Copyright (c) 2008 Paulius Zaleckas - * Copyright (c) 2008 Darius Augulis * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -35,7 +32,6 @@ #include #include #include -#include #include #include @@ -44,179 +40,38 @@ #include "devices.h" -#if defined(CONFIG_ARCH_MX1) -static struct resource imx1_camera_resources[] = { - { - .start = 0x00224000, - .end = 0x00224010, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_CSI_INT, - .end = MX1_CSI_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 imx1_camera_dmamask = DMA_BIT_MASK(32); - -struct platform_device imx1_camera_device = { - .name = "mx1-camera", - .id = 0, /* This is used to put cameras on this interface */ - .dev = { - .dma_mask = &imx1_camera_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = imx1_camera_resources, - .num_resources = ARRAY_SIZE(imx1_camera_resources), -}; - -static struct resource imx_rtc_resources[] = { - { - .start = 0x00204000, - .end = 0x00204024, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_RTC_INT, - .end = MX1_RTC_INT, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_RTC_SAMINT, - .end = MX1_RTC_SAMINT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_rtc_device = { - .name = "rtc-imx", - .id = 0, - .resource = imx_rtc_resources, - .num_resources = ARRAY_SIZE(imx_rtc_resources), -}; - -static struct resource imx_wdt_resources[] = { - { - .start = 0x00201000, - .end = 0x00201008, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_WDT_INT, - .end = MX1_WDT_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_wdt_device = { - .name = "imx-wdt", - .id = 0, - .resource = imx_wdt_resources, - .num_resources = ARRAY_SIZE(imx_wdt_resources), -}; - -static struct resource imx_usb_resources[] = { - { - .start = 0x00212000, - .end = 0x00212148, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_USBD_INT0, - .end = MX1_USBD_INT0, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT1, - .end = MX1_USBD_INT1, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT2, - .end = MX1_USBD_INT2, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT3, - .end = MX1_USBD_INT3, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT4, - .end = MX1_USBD_INT4, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT5, - .end = MX1_USBD_INT5, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT6, - .end = MX1_USBD_INT6, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_usb_device = { - .name = "imx_udc", - .id = 0, - .num_resources = ARRAY_SIZE(imx_usb_resources), - .resource = imx_usb_resources, -}; - -/* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), - .irq = MX1_GPIO_INT_PORTA, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100), - .irq = MX1_GPIO_INT_PORTB, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200), - .irq = MX1_GPIO_INT_PORTC, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300), - .irq = MX1_GPIO_INT_PORTD, - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, +/* + * SPI master controller + * + * - i.MX1: 2 channel (slighly different register setting) + * - i.MX21: 2 channel + * - i.MX27: 3 channel + */ +#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_spi_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device mxc_spi_device ## n = { \ + .name = "spi_imx", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ + .resource = mxc_spi_resources ## n, \ } -}; - -int __init imx1_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} -#endif -#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) +DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); +DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); #ifdef CONFIG_MACH_MX27 -static struct resource mx27_camera_resources[] = { - { - .start = MX27_CSI_BASE_ADDR, - .end = MX27_CSI_BASE_ADDR + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_EMMA_PRP_BASE_ADDR, - .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_CSI, - .end = MX27_INT_CSI, - .flags = IORESOURCE_IRQ, - },{ - .start = MX27_INT_EMMAPRP, - .end = MX27_INT_EMMAPRP, - .flags = IORESOURCE_IRQ, - }, -}; -struct platform_device mx27_camera_device = { - .name = "mx2-camera", - .id = 0, - .num_resources = ARRAY_SIZE(mx27_camera_resources), - .resource = mx27_camera_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; +DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); #endif /* @@ -285,6 +140,34 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; +#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ + static struct resource pfx ## _nand_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device pfx ## _nand_device = { \ + .name = "mxc_nand", \ + .id = 0, \ + .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ + .resource = pfx ## _nand_resources, \ + } + +#ifdef CONFIG_MACH_MX21 +DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); +#endif + +#ifdef CONFIG_MACH_MX27 +DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); +#endif + /* * lcdc: * - i.MX1: the basic controller @@ -335,6 +218,32 @@ struct platform_device mxc_fec_device = { }; #endif +#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_i2c_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_i2c_device ## n = { \ + .name = "imx-i2c", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ + .resource = mxc_i2c_resources ## n, \ + } + +DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); + +#ifdef CONFIG_MACH_MX27 +DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); +#endif + static struct resource mxc_pwm_resources[] = { { .start = MX2x_PWM_BASE_ADDR, @@ -545,21 +454,26 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); #ifdef CONFIG_MACH_MX21 DEFINE_MXC_GPIO_PORTS(MX21, imx21); - -int __init imx21_register_gpios(void) -{ - return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); -} #endif #ifdef CONFIG_MACH_MX27 DEFINE_MXC_GPIO_PORTS(MX27, imx27); +#endif -int __init imx27_register_gpios(void) +int __init mxc_register_gpios(void) { - return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); -} +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); + else #endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); + else +#endif + return 0; +} #ifdef CONFIG_MACH_MX21 static struct resource mx21_usbhc_resources[] = { @@ -587,23 +501,3 @@ struct platform_device mx21_usbhc_device = { }; #endif -static struct resource imx_kpp_resources[] = { - { - .start = MX2x_KPP_BASE_ADDR, - .end = MX2x_KPP_BASE_ADDR + 0xf, - .flags = IORESOURCE_MEM - }, { - .start = MX2x_INT_KPP, - .end = MX2x_INT_KPP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_kpp_device = { - .name = "imx-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(imx_kpp_resources), - .resource = imx_kpp_resources, -}; - -#endif diff --git a/trunk/arch/arm/mach-imx/devices.h b/trunk/arch/arm/mach-mx2/devices.h similarity index 54% rename from trunk/arch/arm/mach-imx/devices.h rename to trunk/arch/arm/mach-mx2/devices.h index efd4527506a5..84ed51380174 100644 --- a/trunk/arch/arm/mach-imx/devices.h +++ b/trunk/arch/arm/mach-mx2/devices.h @@ -1,11 +1,3 @@ -#ifdef CONFIG_ARCH_MX1 -extern struct platform_device imx1_camera_device; -extern struct platform_device imx_rtc_device; -extern struct platform_device imx_wdt_device; -extern struct platform_device imx_usb_device; -#endif - -#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) extern struct platform_device mxc_gpt1; extern struct platform_device mxc_gpt2; #ifdef CONFIG_MACH_MX27 @@ -14,19 +6,37 @@ extern struct platform_device mxc_gpt4; extern struct platform_device mxc_gpt5; #endif extern struct platform_device mxc_wdt; +extern struct platform_device mxc_uart_device0; +extern struct platform_device mxc_uart_device1; +extern struct platform_device mxc_uart_device2; +extern struct platform_device mxc_uart_device3; +extern struct platform_device mxc_uart_device4; +extern struct platform_device mxc_uart_device5; extern struct platform_device mxc_w1_master_device; +#ifdef CONFIG_MACH_MX21 +extern struct platform_device imx21_nand_device; +#endif +#ifdef CONFIG_MACH_MX27 +extern struct platform_device imx27_nand_device; +#endif extern struct platform_device mxc_fb_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_pwm_device; +extern struct platform_device mxc_i2c_device0; +#ifdef CONFIG_MACH_MX27 +extern struct platform_device mxc_i2c_device1; +#endif extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device1; extern struct platform_device mxc_otg_udc_device; -extern struct platform_device mx27_camera_device; extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; +extern struct platform_device mxc_spi_device0; +extern struct platform_device mxc_spi_device1; +#ifdef CONFIG_MACH_MX27 +extern struct platform_device mxc_spi_device2; +#endif extern struct platform_device mx21_usbhc_device; extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; -extern struct platform_device imx_kpp_device; -#endif diff --git a/trunk/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/trunk/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c similarity index 52% rename from trunk/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c rename to trunk/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c index 4edc5f439201..f3b169d5245f 100644 --- a/trunk/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/trunk/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com + * Copyright (C) 2009 Eric Benard - eric@eukrea.com * * Based on pcm970-baseboard.c which is : * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) @@ -24,9 +24,6 @@ #include #include #include -#include -#include