From 87c38eb620b309961e2de5305962bcf7e6ad1533 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Tue, 28 Mar 2006 13:32:24 -0800 Subject: [PATCH] --- yaml --- r: 25029 b: refs/heads/master c: 73c50a27a453a5ed0d21ff23bd67c1dd6d864cb8 h: refs/heads/master i: 25027: 9594ab7877f27f99e43cc28174e5a550d1f3151b v: v3 --- [refs] | 2 +- trunk/arch/sparc64/mm/fault.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 54fb584409f0..8a648c498f4e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6f25f3986af0353b0bdc220f79b89c997d0ceda4 +refs/heads/master: 73c50a27a453a5ed0d21ff23bd67c1dd6d864cb8 diff --git a/trunk/arch/sparc64/mm/fault.c b/trunk/arch/sparc64/mm/fault.c index 0db2f7d9fab5..6e002aacb961 100644 --- a/trunk/arch/sparc64/mm/fault.c +++ b/trunk/arch/sparc64/mm/fault.c @@ -327,8 +327,12 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs) insn = get_fault_insn(regs, 0); if (!insn) goto continue_fault; + /* All loads, stores and atomics have bits 30 and 31 both set + * in the instruction. Bit 21 is set in all stores, but we + * have to avoid prefetches which also have bit 21 set. + */ if ((insn & 0xc0200000) == 0xc0200000 && - (insn & 0x1780000) != 0x1680000) { + (insn & 0x01780000) != 0x01680000) { /* Don't bother updating thread struct value, * because update_mmu_cache only cares which tlb * the access came from.