From 87e4ea10b1a067b28603c8761f210c45b4f293d1 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Fri, 5 Apr 2013 09:15:01 -0500
Subject: [PATCH] --- yaml --- r: 370859 b: refs/heads/master c:
 9ac8f50a35a93928e750d6edc4133d1308f4f95d h: refs/heads/master i:   370857:
 21e4e2a0e5c94f10a7bee85daf7c41dca29494e9   370855:
 408df020c44491fb5e657133a2eef0d4e9322347 v: v3

---
 [refs]                                        |  2 +-
 .../powerpc/boot/dts/fsl/t4240si-post.dtsi    |  4 ++--
 .../powerpc/boot/dts/fsl/t4240si-pre.dtsi     | 22 +++++++++----------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/[refs] b/[refs]
index e855f58cb47c..420f34ed44b3 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ddb487dca347956ed3bedda1f5a00ab62d05ebff
+refs/heads/master: 9ac8f50a35a93928e750d6edc4133d1308f4f95d
diff --git a/trunk/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/trunk/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 1d7292627b72..e77e6adba05f 100644
--- a/trunk/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/trunk/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -364,12 +364,12 @@
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2";
+		compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
 		reg = <0xe1000 0x1000>;
 	};
 
 	rcpm: global-utilities@e2000 {
-		compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2";
+		compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
 		reg = <0xe2000 0x1000>;
 	};
 
diff --git a/trunk/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/trunk/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 9b39a438d691..a93c55a88560 100644
--- a/trunk/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/trunk/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -69,57 +69,57 @@
 			reg = <0 1>;
 			next-level-cache = <&L2_1>;
 		};
-		cpu1: PowerPC,e6500@1 {
+		cpu1: PowerPC,e6500@2 {
 			device_type = "cpu";
 			reg = <2 3>;
 			next-level-cache = <&L2_1>;
 		};
-		cpu2: PowerPC,e6500@2 {
+		cpu2: PowerPC,e6500@4 {
 			device_type = "cpu";
 			reg = <4 5>;
 			next-level-cache = <&L2_1>;
 		};
-		cpu3: PowerPC,e6500@3 {
+		cpu3: PowerPC,e6500@6 {
 			device_type = "cpu";
 			reg = <6 7>;
 			next-level-cache = <&L2_1>;
 		};
-		cpu4: PowerPC,e6500@4 {
+		cpu4: PowerPC,e6500@8 {
 			device_type = "cpu";
 			reg = <8 9>;
 			next-level-cache = <&L2_2>;
 		};
-		cpu5: PowerPC,e6500@5 {
+		cpu5: PowerPC,e6500@10 {
 			device_type = "cpu";
 			reg = <10 11>;
 			next-level-cache = <&L2_2>;
 		};
-		cpu6: PowerPC,e6500@6 {
+		cpu6: PowerPC,e6500@12 {
 			device_type = "cpu";
 			reg = <12 13>;
 			next-level-cache = <&L2_2>;
 		};
-		cpu7: PowerPC,e6500@7 {
+		cpu7: PowerPC,e6500@14 {
 			device_type = "cpu";
 			reg = <14 15>;
 			next-level-cache = <&L2_2>;
 		};
-		cpu8: PowerPC,e6500@8 {
+		cpu8: PowerPC,e6500@16 {
 			device_type = "cpu";
 			reg = <16 17>;
 			next-level-cache = <&L2_3>;
 		};
-		cpu9: PowerPC,e6500@9 {
+		cpu9: PowerPC,e6500@18 {
 			device_type = "cpu";
 			reg = <18 19>;
 			next-level-cache = <&L2_3>;
 		};
-		cpu10: PowerPC,e6500@10 {
+		cpu10: PowerPC,e6500@20 {
 			device_type = "cpu";
 			reg = <20 21>;
 			next-level-cache = <&L2_3>;
 		};
-		cpu11: PowerPC,e6500@11 {
+		cpu11: PowerPC,e6500@22 {
 			device_type = "cpu";
 			reg = <22 23>;
 			next-level-cache = <&L2_3>;