From 87fb1bff55bf8e7d0625ba60ea0fe021a30ebd75 Mon Sep 17 00:00:00 2001 From: Sean Paul Date: Mon, 14 Jan 2013 17:03:20 -0500 Subject: [PATCH] --- yaml --- r: 349365 b: refs/heads/master c: 09760ea34965a48d39e58607945e5e69edba01e6 h: refs/heads/master i: 349363: a18c23d2b0613512eb88dd9743c852c6df1b6287 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/exynos/exynos_hdmi.c | 14 +++++++------- trunk/drivers/gpu/drm/exynos/exynos_mixer.c | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index b73174b40bd4..8346de0ac0ad 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0bc4a0aa377ec5e6e3bd2b8ac963a008d8e1401b +refs/heads/master: 09760ea34965a48d39e58607945e5e69edba01e6 diff --git a/trunk/drivers/gpu/drm/exynos/exynos_hdmi.c b/trunk/drivers/gpu/drm/exynos/exynos_hdmi.c index 24dbb7f7c290..b490afa781dc 100644 --- a/trunk/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/trunk/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1647,9 +1647,9 @@ static void hdmi_conf_reset(struct hdmi_context *hdata) /* resetting HDMI core */ hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT); - mdelay(10); + usleep_range(10000, 12000); hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT); - mdelay(10); + usleep_range(10000, 12000); } static void hdmi_conf_init(struct hdmi_context *hdata) @@ -1774,7 +1774,7 @@ static void hdmi_v13_timing_apply(struct hdmi_context *hdata) u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS); if (val & HDMI_PHY_STATUS_READY) break; - mdelay(1); + usleep_range(1000, 2000); } /* steady state not achieved */ if (tries == 0) { @@ -1941,7 +1941,7 @@ static void hdmi_v14_timing_apply(struct hdmi_context *hdata) u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0); if (val & HDMI_PHY_STATUS_READY) break; - mdelay(1); + usleep_range(1000, 2000); } /* steady state not achieved */ if (tries == 0) { @@ -1993,9 +1993,9 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) /* reset hdmiphy */ hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT); - mdelay(10); + usleep_range(10000, 12000); hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT); - mdelay(10); + usleep_range(10000, 12000); } static void hdmiphy_poweron(struct hdmi_context *hdata) @@ -2043,7 +2043,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) return; } - mdelay(10); + usleep_range(10000, 12000); /* operation mode */ operation[0] = 0x1f; diff --git a/trunk/drivers/gpu/drm/exynos/exynos_mixer.c b/trunk/drivers/gpu/drm/exynos/exynos_mixer.c index c187ea33b748..1ff2d7a045b5 100644 --- a/trunk/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/trunk/drivers/gpu/drm/exynos/exynos_mixer.c @@ -600,7 +600,7 @@ static void vp_win_reset(struct mixer_context *ctx) /* waiting until VP_SRESET_PROCESSING is 0 */ if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING) break; - mdelay(10); + usleep_range(10000, 12000); } WARN(tries == 0, "failed to reset Video Processor\n"); }