From 8827a5592b6140c315bea24f8e302d493da60482 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Wed, 9 Apr 2008 17:58:22 +0900
Subject: [PATCH] --- yaml --- r: 90940 b: refs/heads/master c:
 440fc172ae333c52c458401fe059afcc6e91eebf h: refs/heads/master v: v3

---
 [refs]                               | 2 +-
 trunk/arch/sh/kernel/cpu/sh4/probe.c | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index cb3f9ef5bffd..30332c39b601 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: e5a4c65bef19366112ba002bc06d87450f02ad74
+refs/heads/master: 440fc172ae333c52c458401fe059afcc6e91eebf
diff --git a/trunk/arch/sh/kernel/cpu/sh4/probe.c b/trunk/arch/sh/kernel/cpu/sh4/probe.c
index 6ea87af7247e..ebceb0dadff5 100644
--- a/trunk/arch/sh/kernel/cpu/sh4/probe.c
+++ b/trunk/arch/sh/kernel/cpu/sh4/probe.c
@@ -220,6 +220,12 @@ int __init detect_cpu_and_cache_system(void)
 	 * SH-4A's have an optional PIPT L2.
 	 */
 	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+		/* Bug if we can't decode the L2 info */
+		BUG_ON(!(cvr & 0xf));
+
+		/* Silicon and specifications have clearly never met.. */
+		cvr ^= 0xf;
+
 		/*
 		 * Size calculation is much more sensible
 		 * than it is for the L1.