From 88a0c20b876e91785077fa21da293e29285ddaac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 24 Apr 2013 19:07:18 +0300 Subject: [PATCH] --- yaml --- r: 371569 b: refs/heads/master c: a90b590e957d66ea357aeff4cee8425f2567ed33 h: refs/heads/master i: 371567: cdefab566ab8747b8eaf260cc97dc9717f8d12b7 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/drm_edid.c | 27 ++++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 40ea40bb2a3d..90b2d9a01b0f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ee7925bb16bc7c4e02f3b64abc7e0dbfbd6ebe86 +refs/heads/master: a90b590e957d66ea357aeff4cee8425f2567ed33 diff --git a/trunk/drivers/gpu/drm/drm_edid.c b/trunk/drivers/gpu/drm/drm_edid.c index 9099eeaba818..9e62bbedb5ad 100644 --- a/trunk/drivers/gpu/drm/drm_edid.c +++ b/trunk/drivers/gpu/drm/drm_edid.c @@ -2330,13 +2330,34 @@ EXPORT_SYMBOL(drm_find_cea_extension); */ u8 drm_match_cea_mode(const struct drm_display_mode *to_match) { - struct drm_display_mode *cea_mode; u8 mode; + if (!to_match->clock) + return 0; + for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { - cea_mode = (struct drm_display_mode *)&edid_cea_modes[mode]; + const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; + unsigned int clock1, clock2; + + clock1 = clock2 = cea_mode->clock; + + /* Check both 60Hz and 59.94Hz */ + if (cea_mode->vrefresh % 6 == 0) { + /* + * edid_cea_modes contains the 59.94Hz + * variant for 240 and 480 line modes, + * and the 60Hz variant otherwise. + */ + if (cea_mode->vdisplay == 240 || + cea_mode->vdisplay == 480) + clock1 = clock1 * 1001 / 1000; + else + clock2 = DIV_ROUND_UP(clock2 * 1000, 1001); + } - if (drm_mode_equal(to_match, cea_mode)) + if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || + KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && + drm_mode_equal_no_clocks(to_match, cea_mode)) return mode + 1; } return 0;