From 88fd8041c56c7c992bdb65d94b207e446c3aa766 Mon Sep 17 00:00:00 2001 From: Sivaram Nair Date: Wed, 21 Nov 2012 13:42:27 +0200 Subject: [PATCH] --- yaml --- r: 347371 b: refs/heads/master c: 6e25e1b178ee3caf34f229bacfad5ae6780bcec6 h: refs/heads/master i: 347369: 7cd33dba47e5c75fb8a4b793f0a3cabf0e8178d4 347367: 33f115649716ebc27dc601f8887218b5cc383c11 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-tegra/tegra30_clocks.c | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 36b299fc33db..4d2a5ab6275f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6eb583da959cf751eb951cc5ff488dd4e41f1b2f +refs/heads/master: 6e25e1b178ee3caf34f229bacfad5ae6780bcec6 diff --git a/trunk/arch/arm/mach-tegra/tegra30_clocks.c b/trunk/arch/arm/mach-tegra/tegra30_clocks.c index e9de5dfd94ec..c2102a312bc5 100644 --- a/trunk/arch/arm/mach-tegra/tegra30_clocks.c +++ b/trunk/arch/arm/mach-tegra/tegra30_clocks.c @@ -1913,9 +1913,7 @@ struct clk_ops tegra30_periph_clk_ops = { static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) { struct clk *d = clk_get_sys(NULL, "pll_d"); - /* The DSIB parent selection bit is in PLLD base - register - can not do direct r-m-w, must be - protected by PLLD lock */ + /* The DSIB parent selection bit is in PLLD base register */ tegra_clk_cfg_ex( d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);