From 8a183441294a61985976a00ed3e3d36296edad1f Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Tue, 19 Mar 2013 09:56:57 +0100 Subject: [PATCH] --- yaml --- r: 361549 b: refs/heads/master c: c12aba5aa0e60b7947bc8b6ea25ef55c4acf81a4 h: refs/heads/master i: 361547: 5c9a13bfb5e4fa5b81c5ca40d69162e5706dd976 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_i2c.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 599d95f82ca9..418ac4f2da4c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 362132d228ef37c1e2d31ad5d649a7ed65efe539 +refs/heads/master: c12aba5aa0e60b7947bc8b6ea25ef55c4acf81a4 diff --git a/trunk/drivers/gpu/drm/i915/intel_i2c.c b/trunk/drivers/gpu/drm/i915/intel_i2c.c index acf8aec9ada7..ef4744e1bf0b 100644 --- a/trunk/drivers/gpu/drm/i915/intel_i2c.c +++ b/trunk/drivers/gpu/drm/i915/intel_i2c.c @@ -203,7 +203,13 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin) algo->data = bus; } -#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 4) +/* + * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI + * mode. This results in spurious interrupt warnings if the legacy irq no. is + * shared with another device. The kernel then disables that interrupt source + * and so prevents the other device from working properly. + */ +#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) static int gmbus_wait_hw_status(struct drm_i915_private *dev_priv, u32 gmbus2_status, @@ -214,6 +220,9 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv, u32 gmbus2 = 0; DEFINE_WAIT(wait); + if (!HAS_GMBUS_IRQ(dev_priv->dev)) + gmbus4_irq_en = 0; + /* Important: The hw handles only the first bit, so set only one! Since * we also need to check for NAKs besides the hw ready/idle signal, we * need to wake up periodically and check that ourselves. */