From 8a6220e21275e256b51f66fa171181d7c127b90d Mon Sep 17 00:00:00 2001 From: Paulius Zaleckas Date: Tue, 9 Sep 2008 10:19:43 +0200 Subject: [PATCH] --- yaml --- r: 112493 b: refs/heads/master c: b72f92ff551d9151c146c8d0f1c5c743611df982 h: refs/heads/master i: 112491: 25003da7e703dd87a8880d2cf4227ea2d31b6008 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-imx/include/mach/irqs.h | 5 ++++ trunk/arch/arm/mach-imx/irq.c | 32 ++++++++++++++++++--- 3 files changed, 34 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 9565aac085d8..1616eed04a73 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8b69ac577e644e5084a9d7a93e4ccd5184c77626 +refs/heads/master: b72f92ff551d9151c146c8d0f1c5c743611df982 diff --git a/trunk/arch/arm/mach-imx/include/mach/irqs.h b/trunk/arch/arm/mach-imx/include/mach/irqs.h index eb8d5bd05d56..67812c5ac1f9 100644 --- a/trunk/arch/arm/mach-imx/include/mach/irqs.h +++ b/trunk/arch/arm/mach-imx/include/mach/irqs.h @@ -111,6 +111,11 @@ /* decode irq number to use with IMR(x), ISR(x) and friends */ #define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5) +/* all normal IRQs can be FIQs */ +#define FIQ_START 0 +/* switch betwean IRQ and FIQ */ +extern int imx_set_irq_fiq(unsigned int irq, unsigned int type); + #define NR_IRQS (IRQ_GPIOD(32) + 1) #define IRQ_GPIO(x) #endif diff --git a/trunk/arch/arm/mach-imx/irq.c b/trunk/arch/arm/mach-imx/irq.c index 798f221eb3b7..2bb829e721cd 100644 --- a/trunk/arch/arm/mach-imx/irq.c +++ b/trunk/arch/arm/mach-imx/irq.c @@ -36,10 +36,7 @@ /* * * We simply use the ENABLE DISABLE registers inside of the IMX - * to turn on/off specific interrupts. FIXME- We should - * also add support for the accelerated interrupt controller - * by putting offets to irq jump code in the appropriate - * places. + * to turn on/off specific interrupts. * */ @@ -102,6 +99,28 @@ imx_unmask_irq(unsigned int irq) __raw_writel(irq, IMX_AITC_INTENNUM); } +#ifdef CONFIG_FIQ +int imx_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int irqt; + + if (irq >= IMX_IRQS) + return -EINVAL; + + if (irq < IMX_IRQS / 2) { + irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL); + } else { + irq -= IMX_IRQS / 2; + irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH); + } + + return 0; +} +EXPORT_SYMBOL(imx_set_irq_fiq); +#endif /* CONFIG_FIQ */ + static int imx_gpio_irq_type(unsigned int _irq, unsigned int type) { @@ -286,4 +305,9 @@ imx_init_irq(void) /* Release masking of interrupts according to priority */ __raw_writel(-1, IMX_AITC_NIMASK); + +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif }