From 8b0b3d14f7a4cd893957bd1922b31f3532709a08 Mon Sep 17 00:00:00 2001
From: Senthil Balasubramanian <senthilkumar@atheros.com>
Date: Fri, 22 Apr 2011 11:32:09 +0530
Subject: [PATCH] --- yaml --- r: 247176 b: refs/heads/master c:
 d1c038d620c45fbbc65bcadf813a86bca686dd31 h: refs/heads/master v: v3

---
 [refs]                                    | 2 +-
 trunk/drivers/net/wireless/ath/ath9k/hw.c | 4 ----
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/[refs] b/[refs]
index 5d925de0f991..3883f7980048 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 353e5019e048562dc8f434c6237d41ef5e758922
+refs/heads/master: d1c038d620c45fbbc65bcadf813a86bca686dd31
diff --git a/trunk/drivers/net/wireless/ath/ath9k/hw.c b/trunk/drivers/net/wireless/ath/ath9k/hw.c
index 577ca59b02bf..6166ba0bca54 100644
--- a/trunk/drivers/net/wireless/ath/ath9k/hw.c
+++ b/trunk/drivers/net/wireless/ath/ath9k/hw.c
@@ -686,7 +686,6 @@ unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
 
-#define DPLL3_PHASE_SHIFT_VAL 0x1
 static void ath9k_hw_init_pll(struct ath_hw *ah,
 			      struct ath9k_channel *chan)
 {
@@ -723,9 +722,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
 		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 			      AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
 		udelay(1000);
-
-		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
-			      AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
 	} else if (AR_SREV_9340(ah)) {
 		u32 regval, pll2_divint, pll2_divfrac, refdiv;