From 8b2d92662376847212aec0f3e2e1645b33ece8be Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 19 Oct 2012 12:27:58 -0600 Subject: [PATCH] --- yaml --- r: 342403 b: refs/heads/master c: 7a28106509463529d7b0408d3f5a0ab99f6810ee h: refs/heads/master i: 342401: 9db630654fbbd7ef13d5869129e0849892e66905 342399: 40c8d4b44cdbb266ec247c352730e4fedd6da6ed v: v3 --- [refs] | 2 +- .../arm/mach-tegra/include/mach/debug-macro.S | 24 +++++++++++++++---- trunk/arch/arm/mach-tegra/io.c | 1 + 3 files changed, 21 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 6ec36c3d4ac4..8f2d17b87a23 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1a6d3da8bc45502940efb19604d4c94c470ef6be +refs/heads/master: 7a28106509463529d7b0408d3f5a0ab99f6810ee diff --git a/trunk/arch/arm/mach-tegra/include/mach/debug-macro.S b/trunk/arch/arm/mach-tegra/include/mach/debug-macro.S index d4c23d60d448..f67fd6df0e2f 100644 --- a/trunk/arch/arm/mach-tegra/include/mach/debug-macro.S +++ b/trunk/arch/arm/mach-tegra/include/mach/debug-macro.S @@ -26,10 +26,18 @@ #include -#include "../../iomap.h" - #define UART_SHIFT 2 +/* Physical addresses */ +#define TEGRA_CLK_RESET_BASE 0x60006000 +#define TEGRA_APB_MISC_BASE 0x70000000 +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTE_BASE 0x70006400 +#define TEGRA_PMC_BASE 0x7000e400 + #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04) #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08) #define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c) @@ -39,6 +47,12 @@ #define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0) #define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804) +/* + * Must be 1MB-aligned since a 1MB mapping is used early on. + * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[]. + */ +#define UART_VIRTUAL_BASE 0xfe100000 + #define checkuart(rp, rv, lhu, bit, uart) \ /* Load address of CLK_RST register */ \ movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \ @@ -139,10 +153,10 @@ 91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys cmp \rp, #0 @ Valid UART address? bne 92f @ Yes, go process it - str \rp, [\tmp, #8] @ Store 0 in tegra_uart_phys + str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt b 100f @ Done -92: sub \rv, \rp, #IO_APB_PHYS @ Calculate virt address - add \rv, \rv, #IO_APB_VIRT +92: and \rv, \rp, #0xffffff @ offset within 1MB section + add \rv, \rv, #UART_VIRTUAL_BASE str \rv, [\tmp, #8] @ Store in tegra_uart_virt movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16 diff --git a/trunk/arch/arm/mach-tegra/io.c b/trunk/arch/arm/mach-tegra/io.c index 7d09f301b3a1..bb9c9c29d181 100644 --- a/trunk/arch/arm/mach-tegra/io.c +++ b/trunk/arch/arm/mach-tegra/io.c @@ -59,5 +59,6 @@ static struct map_desc tegra_io_desc[] __initdata = { void __init tegra_map_common_io(void) { + debug_ll_io_init(); iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc)); }