From 8b5baa0eafcb30196a9101acbfacb5eadb7b65ab Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Mon, 4 Mar 2013 13:39:30 +0200 Subject: [PATCH] --- yaml --- r: 374711 b: refs/heads/master c: 7d321ec171a74cfb1f54e568dc02997d98b6f9d6 h: refs/heads/master i: 374709: b6ac840061dffa0cb8572353a1404346cf645c35 374707: c06293f7040641566441f5de3b6402c5c055b15a 374703: ebcb46d6daa34b5974da1c0a7fcbf2b01778b62e v: v3 --- [refs] | 2 +- trunk/drivers/mtd/nand/nand_ids.c | 34 ++++++++++++++----------------- 2 files changed, 16 insertions(+), 20 deletions(-) diff --git a/[refs] b/[refs] index d97895e6e8cd..b5addeb69ff1 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5dc63fa2c2e149dd3e8128e54c9ca251d0558ea0 +refs/heads/master: 7d321ec171a74cfb1f54e568dc02997d98b6f9d6 diff --git a/trunk/drivers/mtd/nand/nand_ids.c b/trunk/drivers/mtd/nand/nand_ids.c index 9c612388e5de..c44e89fbbf79 100644 --- a/trunk/drivers/mtd/nand/nand_ids.c +++ b/trunk/drivers/mtd/nand/nand_ids.c @@ -10,21 +10,21 @@ */ #include #include -/* -* Chip ID list -* -* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size, -* options -* -* Pagesize; 0, 256, 512 -* 0 get this information from the extended chip ID -+ 256 256 Byte page size -* 512 512 Byte page size -*/ -struct nand_flash_dev nand_flash_ids[] = { + +#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS +#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) + #define SP_OPTIONS NAND_NEED_READRDY #define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16) +/* + * The chip ID list: + * name, device ID, page size, chip size in MiB, eraseblock size, options + * + * If page size and eraseblock size are 0, the sizes are taken from the + * extended chip ID. + */ +struct nand_flash_dev nand_flash_ids[] = { #ifdef CONFIG_MTD_NAND_MUSEUM_IDS {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, SP_OPTIONS}, {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, SP_OPTIONS}, @@ -69,11 +69,9 @@ struct nand_flash_dev nand_flash_ids[] = { {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, SP_OPTIONS}, /* - * These are the new chips with large page size. The pagesize and the - * erasesize is determined from the extended id bytes + * These are the new chips with large page size. Their page size and + * eraseblock size are determined from the extended ID bytes. */ -#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS -#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) /* 512 Megabit */ {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS}, @@ -164,9 +162,7 @@ struct nand_flash_dev nand_flash_ids[] = { {NULL,} }; -/* -* Manufacturer ID list -*/ +/* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_TOSHIBA, "Toshiba"}, {NAND_MFR_SAMSUNG, "Samsung"},