From 8baafdabf7d4c865b7c95a686d83aadad44fb137 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 4 Dec 2006 17:27:36 +1000 Subject: [PATCH] --- yaml --- r: 42011 b: refs/heads/master c: 5a31be3fb52c276b4913bd89e77481fae0001510 h: refs/heads/master i: 42009: 84fb3278bc57bb7889b2dd6b0b9d9be400552b99 42007: fc35c720e557c645487e9d2e977c533d24b4fdea v: v3 --- [refs] | 2 +- trunk/include/asm-m68knommu/m520xsim.h | 12 +++++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 17993201f150..b0532df98b19 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 552984050958fc0f51bff38948d0bf4d31ea2b03 +refs/heads/master: 5a31be3fb52c276b4913bd89e77481fae0001510 diff --git a/trunk/include/asm-m68knommu/m520xsim.h b/trunk/include/asm-m68knommu/m520xsim.h index 1dac22ea95ba..49d016e6391a 100644 --- a/trunk/include/asm-m68knommu/m520xsim.h +++ b/trunk/include/asm-m68knommu/m520xsim.h @@ -31,6 +31,16 @@ #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ +/* + * SDRAM configuration registers. + */ +#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ +#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ +#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ +#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ +#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ +#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ + #define MCF_GPIO_PAR_UART (0xA4036) #define MCF_GPIO_PAR_FECI2C (0xA4033) @@ -47,7 +57,7 @@ #define ICR_INTRCONF 0x05 #define MCFPIT_IMR MCFINTC_IMRL -#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) +#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) /****************************************************************************/ #endif /* m520xsim_h */