From 8bb3fe4549f95d743f6a57de65245408c1e77099 Mon Sep 17 00:00:00 2001
From: Joachim Deguara <joachim.deguara@amd.com>
Date: Wed, 2 May 2007 19:27:18 +0200
Subject: [PATCH] --- yaml --- r: 53909 b: refs/heads/master c:
 2f3c30e6a886ddaf65cb74df82c03245050ff0aa h: refs/heads/master i:   53907:
 dfd77f0ab01ef6796561ddb64b4e1e8fb142addc v: v3

---
 [refs]                                  | 2 +-
 trunk/arch/i386/kernel/cpu/mcheck/k7.c  | 3 +++
 trunk/arch/i386/kernel/cpu/mcheck/mce.c | 3 +--
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index 5a9573d5c1ea..5557f3ec2d8f 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1bdae4583e7abd2c1daedfc9f46ac6420a26c1b0
+refs/heads/master: 2f3c30e6a886ddaf65cb74df82c03245050ff0aa
diff --git a/trunk/arch/i386/kernel/cpu/mcheck/k7.c b/trunk/arch/i386/kernel/cpu/mcheck/k7.c
index 7a2472557bbb..f9fa4142551e 100644
--- a/trunk/arch/i386/kernel/cpu/mcheck/k7.c
+++ b/trunk/arch/i386/kernel/cpu/mcheck/k7.c
@@ -75,6 +75,9 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)
 	machine_check_vector = k7_machine_check;
 	wmb();
 
+	if (!cpu_has(c, X86_FEATURE_MCE))
+		return;
+
 	printk (KERN_INFO "Intel machine check architecture supported.\n");
 	rdmsr (MSR_IA32_MCG_CAP, l, h);
 	if (l & (1<<8))	/* Control register present ? */
diff --git a/trunk/arch/i386/kernel/cpu/mcheck/mce.c b/trunk/arch/i386/kernel/cpu/mcheck/mce.c
index 4f10c62d180c..56cd485b127c 100644
--- a/trunk/arch/i386/kernel/cpu/mcheck/mce.c
+++ b/trunk/arch/i386/kernel/cpu/mcheck/mce.c
@@ -38,8 +38,7 @@ void mcheck_init(struct cpuinfo_x86 *c)
 
 	switch (c->x86_vendor) {
 		case X86_VENDOR_AMD:
-			if (c->x86==6 || c->x86==15)
-				amd_mcheck_init(c);
+			amd_mcheck_init(c);
 			break;
 
 		case X86_VENDOR_INTEL: