From 8beb0587bb6ff4329b6f3c14eaa4ad9bed057c2f Mon Sep 17 00:00:00 2001 From: Roland Vossen Date: Fri, 13 May 2011 11:59:25 +0200 Subject: [PATCH] --- yaml --- r: 249628 b: refs/heads/master c: f6265746765a3f7e5158b5b779e6657d0c646adc h: refs/heads/master v: v3 --- [refs] | 2 +- .../staging/brcm80211/brcmsmac/hnddma.c | 11 +---------- .../staging/brcm80211/include/hnddma.h | 19 +++++++++++++++++++ 3 files changed, 21 insertions(+), 11 deletions(-) diff --git a/[refs] b/[refs] index b515ba357839..9fb22a4d7fd3 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: de3170671a0620254703def8e01ed4242676e952 +refs/heads/master: f6265746765a3f7e5158b5b779e6657d0c646adc diff --git a/trunk/drivers/staging/brcm80211/brcmsmac/hnddma.c b/trunk/drivers/staging/brcm80211/brcmsmac/hnddma.c index 962010f569b2..f607315f8143 100644 --- a/trunk/drivers/staging/brcm80211/brcmsmac/hnddma.c +++ b/trunk/drivers/staging/brcm80211/brcmsmac/hnddma.c @@ -728,16 +728,7 @@ static void *_dma_rx(dma_info_t *di) len = le16_to_cpu(*(u16 *) (head->data)); DMA_TRACE(("%s: dma_rx len %d\n", di->name, len)); - -#if defined(__mips__) -#define OSL_UNCACHED(va) ((void *)KSEG1ADDR((va))) - if (!len) { - while (!(len = *(u16 *) OSL_UNCACHED(head->data))) - udelay(1); - - *(u16 *) (head->data) = cpu_to_le16((u16) len); - } -#endif /* defined(__mips__) */ + dma_spin_for_len(len, head); /* set actual length */ pkt_len = min((di->rxoffset + len), di->rxbufsize); diff --git a/trunk/drivers/staging/brcm80211/include/hnddma.h b/trunk/drivers/staging/brcm80211/include/hnddma.h index 5d079e77490e..fbbcb9b5ae62 100644 --- a/trunk/drivers/staging/brcm80211/include/hnddma.h +++ b/trunk/drivers/staging/brcm80211/include/hnddma.h @@ -204,4 +204,23 @@ extern const di_fcn_t dma64proc; extern uint dma_addrwidth(si_t *sih, void *dmaregs); void dma_walk_packets(struct hnddma_pub *dmah, void (*callback_fnc) (void *pkt, void *arg_a), void *arg_a); + +/* + * DMA(Bug) on some chips seems to declare that the packet is ready, but the + * packet length is not updated yet (by DMA) on the expected time. + * Workaround is to hold processor till DMA updates the length, and stay off + * the bus to allow DMA update the length in buffer + */ +static inline void dma_spin_for_len(uint len, struct sk_buff *head) +{ +#if defined(__mips__) + if (!len) { + while (!(len = *(u16 *) KSEG1ADDR(head->data))) + udelay(1); + + *(u16 *) (head->data) = cpu_to_le16((u16) len); + } +#endif /* defined(__mips__) */ +} + #endif /* _hnddma_h_ */