From 8cfa788d151e037b1fa987ffe20046692ba263b3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 20 Jul 2007 13:49:29 -0500 Subject: [PATCH] --- yaml --- r: 62862 b: refs/heads/master c: 7391ff35b241dbcba471e05059b5c05fdc8196db h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 928525d94bfd..15366bfc9b6d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f64fddbeac737bfc8d966423f067a9af9eeec887 +refs/heads/master: 7391ff35b241dbcba471e05059b5c05fdc8196db diff --git a/trunk/arch/powerpc/sysdev/fsl_pci.c b/trunk/arch/powerpc/sysdev/fsl_pci.c index dcd0ca86bdf6..f88a9aecdf16 100644 --- a/trunk/arch/powerpc/sysdev/fsl_pci.c +++ b/trunk/arch/powerpc/sysdev/fsl_pci.c @@ -118,11 +118,24 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) return; } + /* Clear out any of the virtual P2P bridge registers */ + pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); + pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0); + pci_write_config_byte(dev, PCI_IO_BASE, 0x10); + pci_write_config_byte(dev, PCI_IO_LIMIT, 0); + pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10); + pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0); + pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0); + pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0); + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10); + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0); + if (hose->io_resource.flags) { res = &dev->resource[res_idx++]; res->start = hose->io_resource.start; res->end = hose->io_resource.end; res->flags = hose->io_resource.flags; + update_bridge_resource(dev, res); } for (i = 0; i < 3; i++) { @@ -130,6 +143,7 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) res->start = hose->mem_resources[i].start; res->end = hose->mem_resources[i].end; res->flags = hose->mem_resources[i].flags; + update_bridge_resource(dev, res); } }