From 8dde2d4412dfe514c1257b43fa6e49f0d8eaec2a Mon Sep 17 00:00:00 2001 From: Lauri Hintsala Date: Wed, 4 Jul 2012 13:49:54 +0300 Subject: [PATCH] --- yaml --- r: 316613 b: refs/heads/master c: 64e2bc41304726a5ca8a4d37754db69b88841ebf h: refs/heads/master i: 316611: b814533e862e1ecc3e7a2e2a272a5e7800be9a1e v: v3 --- [refs] | 2 +- trunk/drivers/clk/mxs/clk-imx28.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index c362f5b8916b..754c4ff7ea32 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 275d58025f8d59c493384e1e9660c9c5b7b28d2d +refs/heads/master: 64e2bc41304726a5ca8a4d37754db69b88841ebf diff --git a/trunk/drivers/clk/mxs/clk-imx28.c b/trunk/drivers/clk/mxs/clk-imx28.c index 365053f052cd..98624eec5dd4 100644 --- a/trunk/drivers/clk/mxs/clk-imx28.c +++ b/trunk/drivers/clk/mxs/clk-imx28.c @@ -112,11 +112,11 @@ static void __init clk_misc_init(void) /* * 480 MHz seems too high to be ssp clock source directly, - * so set frac0 to get a 288 MHz ref_io0. + * so set frac0 to get a 288 MHz ref_io0 and ref_io1. */ val = readl_relaxed(FRAC0); - val &= ~(0x3f << BP_FRAC0_IO0FRAC); - val |= 30 << BP_FRAC0_IO0FRAC; + val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC)); + val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC); writel_relaxed(val, FRAC0); }