From 8e8fce1f9045372648baa4cd7fbc97369439531f Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Mon, 29 Oct 2012 15:25:35 +0000 Subject: [PATCH] --- yaml --- r: 345203 b: refs/heads/master c: f5d8491a92e4e5146edf61ed5dda8b4f808b460a h: refs/heads/master i: 345201: 3ade5d49624a838f2411e1209a6b986d8af12600 345199: 28cd624713b1ee5ac2fffe814c1714925f97c86b v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_tv.c | 7 ++----- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 475cc9d26e99..00264e9e1b75 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 01a415fd026c1a413a7016ee880fff7a113af6c8 +refs/heads/master: f5d8491a92e4e5146edf61ed5dda8b4f808b460a diff --git a/trunk/drivers/gpu/drm/i915/intel_tv.c b/trunk/drivers/gpu/drm/i915/intel_tv.c index 62bb048c135e..86d5c20c325a 100644 --- a/trunk/drivers/gpu/drm/i915/intel_tv.c +++ b/trunk/drivers/gpu/drm/i915/intel_tv.c @@ -1088,13 +1088,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, int dspcntr_reg = DSPCNTR(intel_crtc->plane); int pipeconf = I915_READ(pipeconf_reg); int dspcntr = I915_READ(dspcntr_reg); - int dspbase_reg = DSPADDR(intel_crtc->plane); int xpos = 0x0, ypos = 0x0; unsigned int xsize, ysize; /* Pipe must be off here */ I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE); - /* Flush the plane changes */ - I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); + intel_flush_display_plane(dev_priv, intel_crtc->plane); /* Wait for vblank for the disable to take effect */ if (IS_GEN2(dev)) @@ -1123,8 +1121,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, I915_WRITE(pipeconf_reg, pipeconf); I915_WRITE(dspcntr_reg, dspcntr); - /* Flush the plane changes */ - I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); + intel_flush_display_plane(dev_priv, intel_crtc->plane); } j = 0;