From 8ec9b8828c80da190614b6962d20f8d0e92efd97 Mon Sep 17 00:00:00 2001 From: Alexander Shishkin Date: Wed, 4 Aug 2010 11:25:20 +0100 Subject: [PATCH] --- yaml --- r: 208573 b: refs/heads/master c: 9e354ea8e0710baf05804168fdabe90231b3d363 h: refs/heads/master i: 208571: 447431cdd0f53050c0368acb3c5e415769c4e32c v: v3 --- [refs] | 2 +- trunk/arch/arm/include/asm/hardware/coresight.h | 8 ++++++-- trunk/arch/arm/kernel/etm.c | 2 +- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 3fd7421f2fd3..9080a06e5ebe 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 686ff22812d908eaa537edd62fb1eb3d64336301 +refs/heads/master: 9e354ea8e0710baf05804168fdabe90231b3d363 diff --git a/trunk/arch/arm/include/asm/hardware/coresight.h b/trunk/arch/arm/include/asm/hardware/coresight.h index f82b25d4f73e..212e47828c79 100644 --- a/trunk/arch/arm/include/asm/hardware/coresight.h +++ b/trunk/arch/arm/include/asm/hardware/coresight.h @@ -48,8 +48,6 @@ struct tracectx { /* CoreSight Component Registers */ #define CSCR_CLASS 0xff4 -#define CSCR_PRSR 0x314 - #define UNLOCK_MAGIC 0xc5acce55 /* ETM control register, "ETM Architecture", 3.3.1 */ @@ -132,6 +130,12 @@ struct tracectx { ETMCTRL_BRANCH_OUTPUT | \ ETMCTRL_DO_CONTEXTID) +/* ETM management registers, "ETM Architecture", 3.5.24 */ +#define ETMMR_OSLAR 0x300 +#define ETMMR_OSLSR 0x304 +#define ETMMR_OSSRR 0x308 +#define ETMMR_PDSR 0x314 + /* ETB registers, "CoreSight Components TRM", 9.3 */ #define ETBR_DEPTH 0x04 #define ETBR_STATUS 0x0c diff --git a/trunk/arch/arm/kernel/etm.c b/trunk/arch/arm/kernel/etm.c index 827753966301..9e9db63c298a 100644 --- a/trunk/arch/arm/kernel/etm.c +++ b/trunk/arch/arm/kernel/etm.c @@ -543,7 +543,7 @@ static int __init etm_probe(struct amba_device *dev, struct amba_id *id) t->etm_portsz = 1; etm_unlock(t); - ret = etm_readl(t, CSCR_PRSR); + ret = etm_readl(t, ETMMR_PDSR); t->ncmppairs = etm_readl(t, ETMR_CONFCODE) & 0xf; etm_writel(t, 0x440, ETMR_CTRL);