From 8ed654406c43ddcea11c3cbd6e45026044e9fcc2 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sun, 22 Jan 2012 01:36:48 +0100 Subject: [PATCH] --- yaml --- r: 293541 b: refs/heads/master c: 8e636784b6f76653d358d521af9c2a8c246df38b h: refs/heads/master i: 293539: b1a4bc90458bd1bc29b06f311443e9c24ff4b2aa v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 76a35526c1bd..1f6dd7ead10b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: aca258482ed7c600b5aeed03aa8727d94d8dd07e +refs/heads/master: 8e636784b6f76653d358d521af9c2a8c246df38b diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index cfd3a87807f1..ebb345244909 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -936,6 +936,10 @@ void assert_pipe(struct drm_i915_private *dev_priv, u32 val; bool cur_state; + /* if we need the pipe A quirk it must be always on */ + if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) + state = true; + reg = PIPECONF(pipe); val = I915_READ(reg); cur_state = !!(val & PIPECONF_ENABLE);