From 8f7013f75f8e9f5da1fb5918ac286de20f487090 Mon Sep 17 00:00:00 2001
From: Rob Herring <rob.herring@calxeda.com>
Date: Mon, 9 Jan 2012 15:39:19 -0600
Subject: [PATCH] --- yaml --- r: 286155 b: refs/heads/master c:
 f7597c02a2e6fada7a065b03efe283ae7ef0e0bc h: refs/heads/master i:   286153:
 6788de706ba306eca8bb11b44b857056c090f650   286151:
 70df11c5dd343d7db9dc8e7d506183124a30d7e2 v: v3

---
 [refs]                               | 2 +-
 trunk/arch/arm/mach-exynos/headsmp.S | 2 ++
 trunk/arch/arm/mach-exynos/platsmp.c | 5 ++---
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index 217a94a0a8a5..95d7a3d5f77d 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 09f759f66b82bbfe21e165acf0e57e7725466312
+refs/heads/master: f7597c02a2e6fada7a065b03efe283ae7ef0e0bc
diff --git a/trunk/arch/arm/mach-exynos/headsmp.S b/trunk/arch/arm/mach-exynos/headsmp.S
index 3cdeb3647542..5364d4bfa8bc 100644
--- a/trunk/arch/arm/mach-exynos/headsmp.S
+++ b/trunk/arch/arm/mach-exynos/headsmp.S
@@ -36,6 +36,8 @@ pen:	ldr	r7, [r6]
 	 * should now contain the SVC stack for this core
 	 */
 	b	secondary_startup
+ENDPROC(exynos4_secondary_startup)
 
+	.align 2
 1:	.long	.
 	.long	pen_release
diff --git a/trunk/arch/arm/mach-exynos/platsmp.c b/trunk/arch/arm/mach-exynos/platsmp.c
index 69ffb2fb3875..b89bfa5b6b71 100644
--- a/trunk/arch/arm/mach-exynos/platsmp.c
+++ b/trunk/arch/arm/mach-exynos/platsmp.c
@@ -24,7 +24,6 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
-#include <asm/unified.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
@@ -163,7 +162,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	while (time_before(jiffies, timeout)) {
 		smp_rmb();
 
-		__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+		__raw_writel(virt_to_phys(exynos4_secondary_startup),
 			CPU1_BOOT_REG);
 		gic_raise_softirq(cpumask_of(cpu), 1);
 
@@ -218,6 +217,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
-	__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+	__raw_writel(virt_to_phys(exynos4_secondary_startup),
 			CPU1_BOOT_REG);
 }