diff --git a/[refs] b/[refs]
index ee81d004e8d8..0b0cb771e8ac 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3c2047cd32b1a8c782d7efab72707e7daa251625
+refs/heads/master: 0d7a1819e97ef89be5bcbb4b724acb9f6c873c97
diff --git a/trunk/include/asm-x86/system.h b/trunk/include/asm-x86/system.h
index 9cff02ffe6c2..428d9471497f 100644
--- a/trunk/include/asm-x86/system.h
+++ b/trunk/include/asm-x86/system.h
@@ -296,16 +296,7 @@ void default_idle(void);
  */
 #ifdef CONFIG_X86_32
 /*
- * For now, "wmb()" doesn't actually do anything, as all
- * Intel CPU's follow what Intel calls a *Processor Order*,
- * in which all writes are seen in the program order even
- * outside the CPU.
- *
- * I expect future Intel CPU's to have a weaker ordering,
- * but I'd also expect them to finally get their act together
- * and add some real memory barriers if so.
- *
- * Some non intel clones support out of order store. wmb() ceases to be a
+ * Some non-Intel clones support out of order store. wmb() ceases to be a
  * nop for these.
  */
 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)