From 90ee2ab3fe5f5ea65d8bdd89ddb79571cee95aac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Thu, 29 Mar 2012 16:47:43 +0200 Subject: [PATCH] --- yaml --- r: 298515 b: refs/heads/master c: e199fd422420d1620cf64fd9bdd4ff8bc255cc76 h: refs/heads/master i: 298513: d9b1d2828455ae925a22d99017fb0454decbe04c 298511: 58281254da03bc4e45605967ffdd297c2754e8b4 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/radeon_object.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index e67a54a8d757..32d68c019e6f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fa9e855025b19e96e493ee00de7d933a9794f742 +refs/heads/master: e199fd422420d1620cf64fd9bdd4ff8bc255cc76 diff --git a/trunk/drivers/gpu/drm/radeon/radeon_object.c b/trunk/drivers/gpu/drm/radeon/radeon_object.c index 6f70158d34e4..df6a4dbd93f8 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_object.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_object.c @@ -241,7 +241,8 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, domain_start = bo->rdev->mc.vram_start; else domain_start = bo->rdev->mc.gtt_start; - WARN_ON_ONCE((*gpu_addr - domain_start) > max_offset); + WARN_ON_ONCE(max_offset < + (radeon_bo_gpu_offset(bo) - domain_start)); } return 0;