diff --git a/[refs] b/[refs] index 9a432ff8205d..3d84c0237818 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 19e3f4858d4a2863ad66b2c92d0f9270879eac04 +refs/heads/master: d6662c351a827264706bf880a36cdd376808ba1c diff --git a/trunk/arch/arm/common/Kconfig b/trunk/arch/arm/common/Kconfig index 38518d450bc0..a2cd9beaf37d 100644 --- a/trunk/arch/arm/common/Kconfig +++ b/trunk/arch/arm/common/Kconfig @@ -4,13 +4,6 @@ config ARM_GIC config ARM_VIC bool -config ARM_VIC_NR - int - default 2 - help - The maximum number of VICs available in the system, for - power management. - config ICST525 bool diff --git a/trunk/arch/arm/common/vic.c b/trunk/arch/arm/common/vic.c index 887c6eb3a18a..b2a781d9ce05 100644 --- a/trunk/arch/arm/common/vic.c +++ b/trunk/arch/arm/common/vic.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -40,219 +39,11 @@ static void vic_unmask_irq(unsigned int irq) writel(1 << irq, base + VIC_INT_ENABLE); } -/** - * vic_init2 - common initialisation code - * @base: Base of the VIC. - * - * Common initialisation code for registeration - * and resume. -*/ -static void vic_init2(void __iomem *base) -{ - int i; - - for (i = 0; i < 16; i++) { - void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); - writel(VIC_VECT_CNTL_ENABLE | i, reg); - } - - writel(32, base + VIC_PL190_DEF_VECT_ADDR); -} - -#if defined(CONFIG_PM) -/** - * struct vic_device - VIC PM device - * @sysdev: The system device which is registered. - * @irq: The IRQ number for the base of the VIC. - * @base: The register base for the VIC. - * @resume_sources: A bitmask of interrupts for resume. - * @resume_irqs: The IRQs enabled for resume. - * @int_select: Save for VIC_INT_SELECT. - * @int_enable: Save for VIC_INT_ENABLE. - * @soft_int: Save for VIC_INT_SOFT. - * @protect: Save for VIC_PROTECT. - */ -struct vic_device { - struct sys_device sysdev; - - void __iomem *base; - int irq; - u32 resume_sources; - u32 resume_irqs; - u32 int_select; - u32 int_enable; - u32 soft_int; - u32 protect; -}; - -/* we cannot allocate memory when VICs are initially registered */ -static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; - -static inline struct vic_device *to_vic(struct sys_device *sys) -{ - return container_of(sys, struct vic_device, sysdev); -} - -static int vic_id; - -static int vic_class_resume(struct sys_device *dev) -{ - struct vic_device *vic = to_vic(dev); - void __iomem *base = vic->base; - - printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); - - /* re-initialise static settings */ - vic_init2(base); - - writel(vic->int_select, base + VIC_INT_SELECT); - writel(vic->protect, base + VIC_PROTECT); - - /* set the enabled ints and then clear the non-enabled */ - writel(vic->int_enable, base + VIC_INT_ENABLE); - writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); - - /* and the same for the soft-int register */ - - writel(vic->soft_int, base + VIC_INT_SOFT); - writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); - - return 0; -} - -static int vic_class_suspend(struct sys_device *dev, pm_message_t state) -{ - struct vic_device *vic = to_vic(dev); - void __iomem *base = vic->base; - - printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); - - vic->int_select = readl(base + VIC_INT_SELECT); - vic->int_enable = readl(base + VIC_INT_ENABLE); - vic->soft_int = readl(base + VIC_INT_SOFT); - vic->protect = readl(base + VIC_PROTECT); - - /* set the interrupts (if any) that are used for - * resuming the system */ - - writel(vic->resume_irqs, base + VIC_INT_ENABLE); - writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); - - return 0; -} - -struct sysdev_class vic_class = { - .name = "vic", - .suspend = vic_class_suspend, - .resume = vic_class_resume, -}; - -/** - * vic_pm_register - Register a VIC for later power management control - * @base: The base address of the VIC. - * @irq: The base IRQ for the VIC. - * @resume_sources: bitmask of interrupts allowed for resume sources. - * - * Register the VIC with the system device tree so that it can be notified - * of suspend and resume requests and ensure that the correct actions are - * taken to re-instate the settings on resume. - */ -static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources) -{ - struct vic_device *v; - - if (vic_id >= ARRAY_SIZE(vic_devices)) - printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); - else { - v = &vic_devices[vic_id]; - v->base = base; - v->resume_sources = resume_sources; - v->irq = irq; - vic_id++; - } -} - -/** - * vic_pm_init - initicall to register VIC pm - * - * This is called via late_initcall() to register - * the resources for the VICs due to the early - * nature of the VIC's registration. -*/ -static int __init vic_pm_init(void) -{ - struct vic_device *dev = vic_devices; - int err; - int id; - - if (vic_id == 0) - return 0; - - err = sysdev_class_register(&vic_class); - if (err) { - printk(KERN_ERR "%s: cannot register class\n", __func__); - return err; - } - - for (id = 0; id < vic_id; id++, dev++) { - dev->sysdev.id = id; - dev->sysdev.cls = &vic_class; - - err = sysdev_register(&dev->sysdev); - if (err) { - printk(KERN_ERR "%s: failed to register device\n", - __func__); - return err; - } - } - - return 0; -} - -late_initcall(vic_pm_init); - -static struct vic_device *vic_from_irq(unsigned int irq) -{ - struct vic_device *v = vic_devices; - unsigned int base_irq = irq & ~31; - int id; - - for (id = 0; id < vic_id; id++, v++) { - if (v->irq == base_irq) - return v; - } - - return NULL; -} - -static int vic_set_wake(unsigned int irq, unsigned int on) -{ - struct vic_device *v = vic_from_irq(irq); - unsigned int off = irq & 31; - - if (!v) - return -EINVAL; - - if (on) - v->resume_irqs |= 1 << off; - else - v->resume_irqs &= ~(1 << off); - - return 0; -} - -#else -static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { } - -#define vic_set_wake NULL -#endif /* CONFIG_PM */ - static struct irq_chip vic_chip = { .name = "VIC", .ack = vic_mask_irq, .mask = vic_mask_irq, .unmask = vic_unmask_irq, - .set_wake = vic_set_wake, }; /** @@ -260,10 +51,9 @@ static struct irq_chip vic_chip = { * @base: iomem base address * @irq_start: starting interrupt number, must be muliple of 32 * @vic_sources: bitmask of interrupt sources to allow - * @resume_sources: bitmask of interrupt sources to allow for resume */ void __init vic_init(void __iomem *base, unsigned int irq_start, - u32 vic_sources, u32 resume_sources) + u32 vic_sources) { unsigned int i; @@ -287,7 +77,12 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, writel(value, base + VIC_PL190_VECT_ADDR); } - vic_init2(base); + for (i = 0; i < 16; i++) { + void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); + writel(VIC_VECT_CNTL_ENABLE | i, reg); + } + + writel(32, base + VIC_PL190_DEF_VECT_ADDR); for (i = 0; i < 32; i++) { if (vic_sources & (1 << i)) { @@ -299,6 +94,4 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } - - vic_pm_register(base, irq_start, resume_sources); } diff --git a/trunk/arch/arm/include/asm/hardware/vic.h b/trunk/arch/arm/include/asm/hardware/vic.h index 5d72550a8097..f87328d4a180 100644 --- a/trunk/arch/arm/include/asm/hardware/vic.h +++ b/trunk/arch/arm/include/asm/hardware/vic.h @@ -41,7 +41,7 @@ #define VIC_PL192_VECT_ADDR 0xF00 #ifndef __ASSEMBLY__ -void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); +void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); #endif #endif diff --git a/trunk/arch/arm/mach-ep93xx/core.c b/trunk/arch/arm/mach-ep93xx/core.c index 6faa3dc29cec..ae24486f858a 100644 --- a/trunk/arch/arm/mach-ep93xx/core.c +++ b/trunk/arch/arm/mach-ep93xx/core.c @@ -362,8 +362,8 @@ void __init ep93xx_init_irq(void) { int gpio_irq; - vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); - vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); + vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK); + vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK); for (gpio_irq = gpio_to_irq(0); gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { diff --git a/trunk/arch/arm/mach-netx/generic.c b/trunk/arch/arm/mach-netx/generic.c index 43da8bb4926b..79df60c20e70 100644 --- a/trunk/arch/arm/mach-netx/generic.c +++ b/trunk/arch/arm/mach-netx/generic.c @@ -168,7 +168,7 @@ void __init netx_init_irq(void) { int irq; - vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); + vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0); for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { set_irq_chip(irq, &netx_hif_chip); diff --git a/trunk/arch/arm/mach-s3c2410/Kconfig b/trunk/arch/arm/mach-s3c2410/Kconfig index 41bb65d5b91f..63a30d1dd425 100644 --- a/trunk/arch/arm/mach-s3c2410/Kconfig +++ b/trunk/arch/arm/mach-s3c2410/Kconfig @@ -59,7 +59,6 @@ config ARCH_H1940 bool "IPAQ H1940" select CPU_S3C2410 select PM_H1940 if PM - select S3C_DEV_USB_HOST help Say Y here if you are using the HP IPAQ H1940 @@ -71,7 +70,6 @@ config PM_H1940 config MACH_N30 bool "Acer N30 family" select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you want suppt for the Acer N30, Acer N35, Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. @@ -84,7 +82,6 @@ config ARCH_BAST select MACH_BAST_IDE select S3C24XX_DCLK select ISA - select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec Electronics EB2410ITX development board (also known as BAST) @@ -92,7 +89,6 @@ config ARCH_BAST config MACH_OTOM bool "NexVision OTOM Board" select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you are using the Nex Vision OTOM board @@ -100,7 +96,6 @@ config MACH_AML_M5900 bool "AML M5900 Series" select CPU_S3C2410 select PM_SIMTEC if PM - select S3C_DEV_USB_HOST help Say Y here if you are using the American Microsystems M5900 Series @@ -116,7 +111,6 @@ config BAST_PC104_IRQ config MACH_TCT_HAMMER bool "TCT Hammer Board" select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you are using the TinCanTools Hammer Board @@ -128,14 +122,12 @@ config MACH_VR1000 select SIMTEC_NOR select MACH_BAST_IDE select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you are using the Thorcom VR1000 board. config MACH_QT2410 bool "QT2410" select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you are using the Armzone QT2410 diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/map.h b/trunk/arch/arm/mach-s3c2410/include/mach/map.h index e99b212cb1ca..255fdfeaf957 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/map.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/map.h @@ -84,6 +84,7 @@ #define S3C24XX_PA_IRQ S3C2410_PA_IRQ #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL +#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST #define S3C24XX_PA_DMA S3C2410_PA_DMA #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR #define S3C24XX_PA_LCD S3C2410_PA_LCD @@ -101,7 +102,6 @@ #define S3C_PA_IIC S3C2410_PA_IIC #define S3C_PA_UART S3C24XX_PA_UART -#define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC #endif /* __ASM_ARCH_MAP_H */ diff --git a/trunk/arch/arm/mach-s3c2412/Kconfig b/trunk/arch/arm/mach-s3c2412/Kconfig index 63586ffd0ae7..ca99564ae4b5 100644 --- a/trunk/arch/arm/mach-s3c2412/Kconfig +++ b/trunk/arch/arm/mach-s3c2412/Kconfig @@ -38,7 +38,6 @@ menu "S3C2412 Machines" config MACH_JIVE bool "Logitech Jive" select CPU_S3C2412 - select S3C_DEV_USB_HOST help Say Y here if you are using the Logitech Jive. @@ -51,7 +50,6 @@ config MACH_SMDK2413 select CPU_S3C2412 select MACH_S3C2413 select MACH_SMDK - select S3C_DEV_USB_HOST help Say Y here if you are using an SMDK2413 @@ -74,7 +72,6 @@ config MACH_SMDK2412 config MACH_VSTMS bool "VMSTMS" select CPU_S3C2412 - select S3C_DEV_USB_HOST help Say Y here if you are using an VSTMS board diff --git a/trunk/arch/arm/mach-s3c2440/Kconfig b/trunk/arch/arm/mach-s3c2440/Kconfig index 5df73cbf2b40..cde5ae9a4340 100644 --- a/trunk/arch/arm/mach-s3c2440/Kconfig +++ b/trunk/arch/arm/mach-s3c2440/Kconfig @@ -33,7 +33,6 @@ config MACH_ANUBIS select PM_SIMTEC if PM select HAVE_PATA_PLATFORM select S3C24XX_GPIO_EXTRA64 - select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec Electronics ANUBIS development system @@ -44,7 +43,6 @@ config MACH_OSIRIS select S3C24XX_DCLK select PM_SIMTEC if PM select S3C24XX_GPIO_EXTRA128 - select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec IM2440D20 module, also known as the Osiris. @@ -60,14 +58,12 @@ config ARCH_S3C2440 bool "SMDK2440" select CPU_S3C2440 select MACH_SMDK - select S3C_DEV_USB_HOST help Say Y here if you are using the SMDK2440. config MACH_NEXCODER_2440 bool "NexVision NEXCODER 2440 Light Board" select CPU_S3C2440 - select S3C_DEV_USB_HOST help Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board @@ -80,7 +76,6 @@ config SMDK2440_CPU2440 config MACH_AT2440EVB bool "Avantech AT2440EVB development board" select CPU_S3C2440 - select S3C_DEV_USB_HOST help Say Y here if you are using the AT2440EVB development board diff --git a/trunk/arch/arm/mach-s3c6400/Kconfig b/trunk/arch/arm/mach-s3c6400/Kconfig index f5af212066c3..6da82b5c09ba 100644 --- a/trunk/arch/arm/mach-s3c6400/Kconfig +++ b/trunk/arch/arm/mach-s3c6400/Kconfig @@ -5,27 +5,4 @@ # # Licensed under GPLv2 -# Configuration options for the S3C6410 CPU - -config CPU_S3C6400 - bool - select CPU_S3C6400_INIT - select CPU_S3C6400_CLOCK - help - Enable S3C6400 CPU support - -config S3C6400_SETUP_SDHCI - bool - help - Internal configuration for default SDHCI - setup for S3C6400. - -# S36400 Macchine support - -config MACH_SMDK6400 - bool "SMDK6400" - select CPU_S3C6400 - select S3C_DEV_HSMMC - select S3C6400_SETUP_SDHCI - help - Machine support for the Samsung SMDK6400 +# Currently nothing here, this will be added later diff --git a/trunk/arch/arm/mach-s3c6400/Makefile b/trunk/arch/arm/mach-s3c6400/Makefile index df1ce4aa03e5..8f397db25b87 100644 --- a/trunk/arch/arm/mach-s3c6400/Makefile +++ b/trunk/arch/arm/mach-s3c6400/Makefile @@ -12,12 +12,4 @@ obj- := # Core support for S3C6400 system -obj-$(CONFIG_CPU_S3C6400) += s3c6400.o - -# setup support - -obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o - -# Machine support - -obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o +obj-n += blank.o diff --git a/trunk/arch/arm/mach-s3c6400/include/mach/map.h b/trunk/arch/arm/mach-s3c6400/include/mach/map.h index ea4223b55099..baf1c0f1ea5a 100644 --- a/trunk/arch/arm/mach-s3c6400/include/mach/map.h +++ b/trunk/arch/arm/mach-s3c6400/include/mach/map.h @@ -55,8 +55,6 @@ #define S3C64XX_PA_MODEM (0x74108000) #define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) -#define S3C64XX_PA_USBHOST (0x74300000) - /* place VICs close together */ #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) @@ -69,6 +67,5 @@ #define S3C_PA_IIC S3C64XX_PA_IIC0 #define S3C_PA_IIC1 S3C64XX_PA_IIC1 #define S3C_PA_FB S3C64XX_PA_FB -#define S3C_PA_USBHOST S3C64XX_PA_USBHOST #endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/trunk/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/trunk/arch/arm/mach-s3c6400/include/mach/regs-clock.h deleted file mode 100644 index a6c7f4eb3a1b..000000000000 --- a/trunk/arch/arm/mach-s3c6400/include/mach/regs-clock.h +++ /dev/null @@ -1,16 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C64XX - clock register compatibility with s3c24xx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - diff --git a/trunk/arch/arm/mach-s3c6400/mach-smdk6400.c b/trunk/arch/arm/mach-s3c6400/mach-smdk6400.c deleted file mode 100644 index ab19285389a7..000000000000 --- a/trunk/arch/arm/mach-s3c6400/mach-smdk6400.c +++ /dev/null @@ -1,96 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, -}; - -static struct map_desc smdk6400_iodesc[] = {}; - -static void __init smdk6400_map_io(void) -{ - s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); -} - -static struct platform_device *smdk6400_devices[] __initdata = { - &s3c_device_hsmmc1, - &s3c_device_i2c0, -}; - -static struct i2c_board_info i2c_devs[] __initdata = { - { I2C_BOARD_INFO("wm8753", 0x1A), }, - { I2C_BOARD_INFO("24c08", 0x50), }, -}; - -static void __init smdk6400_machine_init(void) -{ - i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs)); - platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices)); -} - -MACHINE_START(SMDK6400, "SMDK6400") - /* Maintainer: Ben Dooks */ - .phys_io = S3C_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C64XX_PA_SDRAM + 0x100, - - .init_irq = s3c6400_init_irq, - .map_io = smdk6400_map_io, - .init_machine = smdk6400_machine_init, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-s3c6400/s3c6400.c b/trunk/arch/arm/mach-s3c6400/s3c6400.c deleted file mode 100644 index bd17f3db2c21..000000000000 --- a/trunk/arch/arm/mach-s3c6400/s3c6400.c +++ /dev/null @@ -1,88 +0,0 @@ -/* linux/arch/arm/mach-s3c6410/cpu.c - * - * Copyright 2009 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include - -void __init s3c6400_map_io(void) -{ - /* setup SDHCI */ - - s3c6400_default_sdhci0(); - s3c6400_default_sdhci1(); - - /* the i2c devices are directly compatible with s3c2440 */ - s3c_i2c0_setname("s3c2440-i2c"); -} - -void __init s3c6400_init_clocks(int xtal) -{ - printk(KERN_DEBUG "%s: initialising clocks\n", __func__); - s3c24xx_register_baseclocks(xtal); - s3c64xx_register_clocks(); - s3c6400_register_clocks(); - s3c6400_setup_clocks(); -} - -void __init s3c6400_init_irq(void) -{ - /* VIC0 does not have IRQS 5..7, - * VIC1 is fully populated. */ - s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); -} - -struct sysdev_class s3c6400_sysclass = { - .name = "s3c6400-core", -}; - -static struct sys_device s3c6400_sysdev = { - .cls = &s3c6400_sysclass, -}; - -static int __init s3c6400_core_init(void) -{ - return sysdev_class_register(&s3c6400_sysclass); -} - -core_initcall(s3c6400_core_init); - -int __init s3c6400_init(void) -{ - printk("S3C6400: Initialising architecture\n"); - - return sysdev_register(&s3c6400_sysdev); -} diff --git a/trunk/arch/arm/mach-s3c6400/setup-sdhci.c b/trunk/arch/arm/mach-s3c6400/setup-sdhci.c deleted file mode 100644 index b93dafbee1f4..000000000000 --- a/trunk/arch/arm/mach-s3c6400/setup-sdhci.c +++ /dev/null @@ -1,63 +0,0 @@ -/* linux/arch/arm/mach-s3c6410/setup-sdhci.c - * - * Copyright 2008 Simtec Electronics - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c6400_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "mmc_bus", - /* [3] = "48m", - note not succesfully used yet */ -}; - -void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} - diff --git a/trunk/arch/arm/mach-s3c6410/Kconfig b/trunk/arch/arm/mach-s3c6410/Kconfig index 4f7ffc7ce859..1d5010070027 100644 --- a/trunk/arch/arm/mach-s3c6410/Kconfig +++ b/trunk/arch/arm/mach-s3c6410/Kconfig @@ -16,7 +16,6 @@ config CPU_S3C6410 config S3C6410_SETUP_SDHCI bool - select S3C64XX_SETUP_SDHCI_GPIO help Internal helper functions for S3C6410 based SDHCI systems @@ -27,7 +26,6 @@ config MACH_SMDK6410 select S3C_DEV_HSMMC1 select S3C_DEV_I2C1 select S3C_DEV_FB - select S3C_DEV_USB_HOST select S3C6410_SETUP_SDHCI select S3C64XX_SETUP_I2C1 select S3C64XX_SETUP_FB_24BPP diff --git a/trunk/arch/arm/mach-s3c6410/mach-smdk6410.c b/trunk/arch/arm/mach-s3c6410/mach-smdk6410.c index 678b728fee12..d0b9f09b7269 100644 --- a/trunk/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/trunk/arch/arm/mach-s3c6410/mach-smdk6410.c @@ -39,6 +39,9 @@ #include #include +#include +#include +#include #include #include @@ -141,7 +144,6 @@ static struct platform_device *smdk6410_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_i2c1, &s3c_device_fb, - &s3c_device_usb, &smdk6410_lcd_powerdev, }; @@ -156,9 +158,23 @@ static struct i2c_board_info i2c_devs1[] __initdata = { static void __init smdk6410_map_io(void) { + u32 tmp; + s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); + + /* set the LCD type */ + + tmp = __raw_readl(S3C64XX_SPCON); + tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; + tmp |= S3C64XX_SPCON_LCD_SEL_RGB; + __raw_writel(tmp, S3C64XX_SPCON); + + /* remove the lcd bypass */ + tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); + tmp &= ~MIFPCON_LCD_BYPASS; + __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); } static void __init smdk6410_machine_init(void) diff --git a/trunk/arch/arm/mach-s3c6410/setup-sdhci.c b/trunk/arch/arm/mach-s3c6410/setup-sdhci.c index 20666f3bd478..0b5788bd5985 100644 --- a/trunk/arch/arm/mach-s3c6410/setup-sdhci.c +++ b/trunk/arch/arm/mach-s3c6410/setup-sdhci.c @@ -21,6 +21,8 @@ #include #include +#include +#include #include #include @@ -33,6 +35,22 @@ char *s3c6410_hsmmc_clksrcs[4] = { /* [3] = "48m", - note not succesfully used yet */ }; +void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + unsigned int end; + + end = S3C64XX_GPG(2 + width); + + /* Set all the necessary GPG pins to special-function 0 */ + for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); +} void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, void __iomem *r, @@ -66,3 +84,19 @@ void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, writel(ctrl3, r + S3C_SDHCI_CONTROL3); } +void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + unsigned int end; + + end = S3C64XX_GPH(2 + width); + + /* Set all the necessary GPG pins to special-function 0 */ + for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); +} diff --git a/trunk/arch/arm/mach-versatile/core.c b/trunk/arch/arm/mach-versatile/core.c index c39c788e2731..1f929c391af7 100644 --- a/trunk/arch/arm/mach-versatile/core.c +++ b/trunk/arch/arm/mach-versatile/core.c @@ -116,7 +116,7 @@ void __init versatile_init_irq(void) { unsigned int i; - vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0); + vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0); set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq); diff --git a/trunk/arch/arm/plat-s3c/Kconfig b/trunk/arch/arm/plat-s3c/Kconfig index a4c5027421d3..de9383814e5e 100644 --- a/trunk/arch/arm/plat-s3c/Kconfig +++ b/trunk/arch/arm/plat-s3c/Kconfig @@ -71,15 +71,6 @@ config S3C2410_PM_DEBUG Resume code. See for more information. -config S3C_PM_DEBUG_LED_SMDK - bool "SMDK LED suspend/resume debugging" - depends on PM && (MACH_SMDK6410) - help - Say Y here to enable the use of the SMDK LEDs on the baseboard - for debugging of the state of the suspend and resume process. - - Note, this currently only works for S3C64XX based SMDK boards. - config S3C2410_PM_CHECK bool "S3C2410 PM Suspend Memory CRC" depends on PM && CRC32 @@ -181,9 +172,4 @@ config S3C_DEV_FB help Compile in platform device definition for framebuffer -config S3C_DEV_USB_HOST - bool - help - Compile in platform device definition for USB host. - endif diff --git a/trunk/arch/arm/plat-s3c/Makefile b/trunk/arch/arm/plat-s3c/Makefile index bfc8f537db18..8d7815d25a51 100644 --- a/trunk/arch/arm/plat-s3c/Makefile +++ b/trunk/arch/arm/plat-s3c/Makefile @@ -21,7 +21,6 @@ obj-y += gpio-config.o # PM support obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm-gpio.o obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o # devices @@ -31,4 +30,3 @@ obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o -obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o diff --git a/trunk/arch/arm/plat-s3c/dev-usb.c b/trunk/arch/arm/plat-s3c/dev-usb.c deleted file mode 100644 index 2ee85abed6d9..000000000000 --- a/trunk/arch/arm/plat-s3c/dev-usb.c +++ /dev/null @@ -1,50 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-usb.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for USB host - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include - -#include -#include - -#include - - -static struct resource s3c_usb_resource[] = { - [0] = { - .start = S3C_PA_USBHOST, - .end = S3C_PA_USBHOST + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBH, - .end = IRQ_USBH, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_usb_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_usb = { - .name = "s3c2410-ohci", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_usb_resource), - .resource = s3c_usb_resource, - .dev = { - .dma_mask = &s3c_device_usb_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_usb); diff --git a/trunk/arch/arm/plat-s3c/gpio.c b/trunk/arch/arm/plat-s3c/gpio.c index 260fdc6ad685..d71dd6d9ce5c 100644 --- a/trunk/arch/arm/plat-s3c/gpio.c +++ b/trunk/arch/arm/plat-s3c/gpio.c @@ -16,7 +16,7 @@ #include #include -#include +#include #ifdef CONFIG_S3C_GPIO_TRACK struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; @@ -140,15 +140,6 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) if (!gc->get) gc->get = s3c_gpiolib_get; -#ifdef CONFIG_PM - if (chip->pm != NULL) { - if (!chip->pm->save || !chip->pm->resume) - printk(KERN_ERR "gpio: %s has missing PM functions\n", - gc->label); - } else - printk(KERN_ERR "gpio: %s has no PM function\n", gc->label); -#endif - /* gpiochip_add() prints own failure message on error. */ ret = gpiochip_add(gc); if (ret >= 0) diff --git a/trunk/arch/arm/plat-s3c/include/plat/cpu.h b/trunk/arch/arm/plat-s3c/include/plat/cpu.h index be541cbba070..e62ae0fcfe56 100644 --- a/trunk/arch/arm/plat-s3c/include/plat/cpu.h +++ b/trunk/arch/arm/plat-s3c/include/plat/cpu.h @@ -69,6 +69,3 @@ extern struct sysdev_class s3c2412_sysclass; extern struct sysdev_class s3c2440_sysclass; extern struct sysdev_class s3c2442_sysclass; extern struct sysdev_class s3c2443_sysclass; -extern struct sysdev_class s3c6410_sysclass; -extern struct sysdev_class s3c64xx_sysclass; - diff --git a/trunk/arch/arm/plat-s3c/include/plat/gpio-core.h b/trunk/arch/arm/plat-s3c/include/plat/gpio-core.h index 32af612767aa..2fc60a580ac8 100644 --- a/trunk/arch/arm/plat-s3c/include/plat/gpio-core.h +++ b/trunk/arch/arm/plat-s3c/include/plat/gpio-core.h @@ -20,18 +20,6 @@ * specific code. */ -struct s3c_gpio_chip; - -/** - * struct s3c_gpio_pm - power management (suspend/resume) information - * @save: Routine to save the state of the GPIO block - * @resume: Routine to resume the GPIO block. - */ -struct s3c_gpio_pm { - void (*save)(struct s3c_gpio_chip *chip); - void (*resume)(struct s3c_gpio_chip *chip); -}; - struct s3c_gpio_cfg; /** @@ -39,7 +27,6 @@ struct s3c_gpio_cfg; * @chip: The chip structure to be exported via gpiolib. * @base: The base pointer to the gpio configuration registers. * @config: special function and pull-resistor control information. - * @pm_save: Save information for suspend/resume support. * * This wrapper provides the necessary information for the Samsung * specific gpios being registered with gpiolib. @@ -47,11 +34,7 @@ struct s3c_gpio_cfg; struct s3c_gpio_chip { struct gpio_chip chip; struct s3c_gpio_cfg *config; - struct s3c_gpio_pm *pm; void __iomem *base; -#ifdef CONFIG_PM - u32 pm_save[4]; -#endif }; static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) @@ -92,16 +75,3 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } #endif - -#ifdef CONFIG_PM -extern struct s3c_gpio_pm s3c_gpio_pm_1bit; -extern struct s3c_gpio_pm s3c_gpio_pm_2bit; -extern struct s3c_gpio_pm s3c_gpio_pm_4bit; -#define __gpio_pm(x) x -#else -#define s3c_gpio_pm_1bit NULL -#define s3c_gpio_pm_2bit NULL -#define s3c_gpio_pm_4bit NULL -#define __gpio_pm(x) NULL - -#endif /* CONFIG_PM */ diff --git a/trunk/arch/arm/plat-s3c/include/plat/pm.h b/trunk/arch/arm/plat-s3c/include/plat/pm.h index 7a797192fcf3..3779775133a9 100644 --- a/trunk/arch/arm/plat-s3c/include/plat/pm.h +++ b/trunk/arch/arm/plat-s3c/include/plat/pm.h @@ -44,8 +44,6 @@ extern void (*pm_cpu_sleep)(void); extern unsigned long s3c_pm_flags; -extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ - /* from sleep.S */ extern int s3c_cpu_save(unsigned long *saveblk); @@ -90,7 +88,6 @@ struct pm_uart_save { u32 ufcon; u32 umcon; u32 ubrdiv; - u32 udivslot; }; /* helper functions to save/restore lists of registers. */ @@ -127,18 +124,6 @@ extern void s3c_pm_dbg(const char *msg, ...); #define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) #endif -#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK -/** - * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs - * @set: set bits for the state of the LEDs - * @clear: clear bits for the state of the LEDs. - */ -extern void s3c_pm_debug_smdkled(u32 set, u32 clear); - -#else -static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } -#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */ - /* suspend memory checking */ #ifdef CONFIG_S3C2410_PM_CHECK diff --git a/trunk/arch/arm/plat-s3c/include/plat/regs-serial.h b/trunk/arch/arm/plat-s3c/include/plat/regs-serial.h index 66af75a5cdd1..487d7d2a7e1d 100644 --- a/trunk/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/trunk/arch/arm/plat-s3c/include/plat/regs-serial.h @@ -189,11 +189,6 @@ #define S3C2443_DIVSLOT (0x2C) -/* S3C64XX interrupt registers. */ -#define S3C64XX_UINTP 0x30 -#define S3C64XX_UINTSP 0x34 -#define S3C64XX_UINTM 0x38 - #ifndef __ASSEMBLY__ /* struct s3c24xx_uart_clksrc diff --git a/trunk/arch/arm/plat-s3c/include/plat/sdhci.h b/trunk/arch/arm/plat-s3c/include/plat/sdhci.h index f615308ccdfb..c4ca3920ca4b 100644 --- a/trunk/arch/arm/plat-s3c/include/plat/sdhci.h +++ b/trunk/arch/arm/plat-s3c/include/plat/sdhci.h @@ -67,52 +67,12 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; /* Helper function availablity */ -extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); -extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); - -/* S3C6400 SDHCI setup */ - -#ifdef CONFIG_S3C6400_SETUP_SDHCI -extern char *s3c6400_hsmmc_clksrcs[4]; - -#ifdef CONFIG_S3C_DEV_HSMMC -extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); - -static inline void s3c6400_default_sdhci0(void) -{ - s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs; - s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; -} - -#else -static inline void s3c6400_default_sdhci0(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC */ - -#ifdef CONFIG_S3C_DEV_HSMMC1 -static inline void s3c6400_default_sdhci1(void) -{ - s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs; - s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; -} -#else -static inline void s3c6400_default_sdhci1(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC1 */ - -#else -static inline void s3c6400_default_sdhci0(void) { } -static inline void s3c6400_default_sdhci1(void) { } -#endif /* CONFIG_S3C6400_SETUP_SDHCI */ - -/* S3C6410 SDHCI setup */ - #ifdef CONFIG_S3C6410_SETUP_SDHCI extern char *s3c6410_hsmmc_clksrcs[4]; +extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w); + extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, void __iomem *r, struct mmc_ios *ios, @@ -122,7 +82,7 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, static inline void s3c6410_default_sdhci0(void) { s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; - s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio; s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; } #else @@ -133,7 +93,7 @@ static inline void s3c6410_default_sdhci0(void) { } static inline void s3c6410_default_sdhci1(void) { s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; - s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio; s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; } #else diff --git a/trunk/arch/arm/plat-s3c/pm-gpio.c b/trunk/arch/arm/plat-s3c/pm-gpio.c deleted file mode 100644 index cfd326a8b693..000000000000 --- a/trunk/arch/arm/plat-s3c/pm-gpio.c +++ /dev/null @@ -1,380 +0,0 @@ - -/* linux/arch/arm/plat-s3c/pm-gpio.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C series GPIO PM code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include - -/* PM GPIO helpers */ - -#define OFFS_CON (0x00) -#define OFFS_DAT (0x04) -#define OFFS_UP (0x08) - -static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip) -{ - chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); - chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); -} - -static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip) -{ - void __iomem *base = chip->base; - u32 old_gpcon = __raw_readl(base + OFFS_CON); - u32 old_gpdat = __raw_readl(base + OFFS_DAT); - u32 gps_gpcon = chip->pm_save[0]; - u32 gps_gpdat = chip->pm_save[1]; - u32 gpcon; - - /* GPACON only has one bit per control / data and no PULLUPs. - * GPACON[x] = 0 => Output, 1 => SFN */ - - /* first set all SFN bits to SFN */ - - gpcon = old_gpcon | gps_gpcon; - __raw_writel(gpcon, base + OFFS_CON); - - /* now set all the other bits */ - - __raw_writel(gps_gpdat, base + OFFS_DAT); - __raw_writel(gps_gpcon, base + OFFS_CON); - - S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n", - chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); -} - -struct s3c_gpio_pm s3c_gpio_pm_1bit = { - .save = s3c_gpio_pm_1bit_save, - .resume = s3c_gpio_pm_1bit_resume, -}; - -static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip) -{ - chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); - chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); - chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); -} - -/* Test whether the given masked+shifted bits of an GPIO configuration - * are one of the SFN (special function) modes. */ - -static inline int is_sfn(unsigned long con) -{ - return con >= 2; -} - -/* Test if the given masked+shifted GPIO configuration is an input */ - -static inline int is_in(unsigned long con) -{ - return con == 0; -} - -/* Test if the given masked+shifted GPIO configuration is an output */ - -static inline int is_out(unsigned long con) -{ - return con == 1; -} - -/** - * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank - * @chip: The chip information to resume. - * - * Restore one of the GPIO banks that was saved during suspend. This is - * not as simple as once thought, due to the possibility of glitches - * from the order that the CON and DAT registers are set in. - * - * The three states the pin can be are {IN,OUT,SFN} which gives us 9 - * combinations of changes to check. Three of these, if the pin stays - * in the same configuration can be discounted. This leaves us with - * the following: - * - * { IN => OUT } Change DAT first - * { IN => SFN } Change CON first - * { OUT => SFN } Change CON first, so new data will not glitch - * { OUT => IN } Change CON first, so new data will not glitch - * { SFN => IN } Change CON first - * { SFN => OUT } Change DAT first, so new data will not glitch [1] - * - * We do not currently deal with the UP registers as these control - * weak resistors, so a small delay in change should not need to bring - * these into the calculations. - * - * [1] this assumes that writing to a pin DAT whilst in SFN will set the - * state for when it is next output. - */ -static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip) -{ - void __iomem *base = chip->base; - u32 old_gpcon = __raw_readl(base + OFFS_CON); - u32 old_gpdat = __raw_readl(base + OFFS_DAT); - u32 gps_gpcon = chip->pm_save[0]; - u32 gps_gpdat = chip->pm_save[1]; - u32 gpcon, old, new, mask; - u32 change_mask = 0x0; - int nr; - - /* restore GPIO pull-up settings */ - __raw_writel(chip->pm_save[2], base + OFFS_UP); - - /* Create a change_mask of all the items that need to have - * their CON value changed before their DAT value, so that - * we minimise the work between the two settings. - */ - - for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) { - old = (old_gpcon & mask) >> nr; - new = (gps_gpcon & mask) >> nr; - - /* If there is no change, then skip */ - - if (old == new) - continue; - - /* If both are special function, then skip */ - - if (is_sfn(old) && is_sfn(new)) - continue; - - /* Change is IN => OUT, do not change now */ - - if (is_in(old) && is_out(new)) - continue; - - /* Change is SFN => OUT, do not change now */ - - if (is_sfn(old) && is_out(new)) - continue; - - /* We should now be at the case of IN=>SFN, - * OUT=>SFN, OUT=>IN, SFN=>IN. */ - - change_mask |= mask; - } - - - /* Write the new CON settings */ - - gpcon = old_gpcon & ~change_mask; - gpcon |= gps_gpcon & change_mask; - - __raw_writel(gpcon, base + OFFS_CON); - - /* Now change any items that require DAT,CON */ - - __raw_writel(gps_gpdat, base + OFFS_DAT); - __raw_writel(gps_gpcon, base + OFFS_CON); - - S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n", - chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); -} - -struct s3c_gpio_pm s3c_gpio_pm_2bit = { - .save = s3c_gpio_pm_2bit_save, - .resume = s3c_gpio_pm_2bit_resume, -}; - -#ifdef CONFIG_ARCH_S3C64XX -static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) -{ - chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); - chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); - chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); - - if (chip->chip.ngpio > 8) - chip->pm_save[0] = __raw_readl(chip->base - 4); -} - -static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) -{ - u32 old, new, mask; - u32 change_mask = 0x0; - int nr; - - for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) { - old = (old_gpcon & mask) >> nr; - new = (gps_gpcon & mask) >> nr; - - /* If there is no change, then skip */ - - if (old == new) - continue; - - /* If both are special function, then skip */ - - if (is_sfn(old) && is_sfn(new)) - continue; - - /* Change is IN => OUT, do not change now */ - - if (is_in(old) && is_out(new)) - continue; - - /* Change is SFN => OUT, do not change now */ - - if (is_sfn(old) && is_out(new)) - continue; - - /* We should now be at the case of IN=>SFN, - * OUT=>SFN, OUT=>IN, SFN=>IN. */ - - change_mask |= mask; - } - - return change_mask; -} - -static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index) -{ - void __iomem *con = chip->base + (index * 4); - u32 old_gpcon = __raw_readl(con); - u32 gps_gpcon = chip->pm_save[index + 1]; - u32 gpcon, mask; - - mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon); - - gpcon = old_gpcon & ~mask; - gpcon |= gps_gpcon & mask; - - __raw_writel(gpcon, con); -} - -static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) -{ - void __iomem *base = chip->base; - u32 old_gpcon[2]; - u32 old_gpdat = __raw_readl(base + OFFS_DAT); - u32 gps_gpdat = chip->pm_save[2]; - - /* First, modify the CON settings */ - - old_gpcon[0] = 0; - old_gpcon[1] = __raw_readl(base + OFFS_CON); - - s3c_gpio_pm_4bit_con(chip, 0); - if (chip->chip.ngpio > 8) { - old_gpcon[0] = __raw_readl(base - 4); - s3c_gpio_pm_4bit_con(chip, -1); - } - - /* Now change the configurations that require DAT,CON */ - - __raw_writel(chip->pm_save[2], base + OFFS_DAT); - __raw_writel(chip->pm_save[1], base + OFFS_CON); - if (chip->chip.ngpio > 8) - __raw_writel(chip->pm_save[0], base - 4); - - __raw_writel(chip->pm_save[2], base + OFFS_DAT); - __raw_writel(chip->pm_save[3], base + OFFS_UP); - - if (chip->chip.ngpio > 8) { - S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n", - chip->chip.label, old_gpcon[0], old_gpcon[1], - __raw_readl(base - 4), - __raw_readl(base + OFFS_CON), - old_gpdat, gps_gpdat); - } else - S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n", - chip->chip.label, old_gpcon[1], - __raw_readl(base + OFFS_CON), - old_gpdat, gps_gpdat); -} - -struct s3c_gpio_pm s3c_gpio_pm_4bit = { - .save = s3c_gpio_pm_4bit_save, - .resume = s3c_gpio_pm_4bit_resume, -}; -#endif /* CONFIG_ARCH_S3C64XX */ - -/** - * s3c_pm_save_gpio() - save gpio chip data for suspend - * @ourchip: The chip for suspend. - */ -static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip) -{ - struct s3c_gpio_pm *pm = ourchip->pm; - - if (pm == NULL || pm->save == NULL) - S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); - else - pm->save(ourchip); -} - -/** - * s3c_pm_save_gpios() - Save the state of the GPIO banks. - * - * For all the GPIO banks, save the state of each one ready for going - * into a suspend mode. - */ -void s3c_pm_save_gpios(void) -{ - struct s3c_gpio_chip *ourchip; - unsigned int gpio_nr; - - for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { - ourchip = s3c_gpiolib_getchip(gpio_nr); - if (!ourchip) - continue; - - s3c_pm_save_gpio(ourchip); - - S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n", - ourchip->chip.label, - ourchip->pm_save[0], - ourchip->pm_save[1], - ourchip->pm_save[2], - ourchip->pm_save[3]); - - gpio_nr += ourchip->chip.ngpio; - gpio_nr += CONFIG_S3C_GPIO_SPACE; - } -} - -/** - * s3c_pm_resume_gpio() - restore gpio chip data after suspend - * @ourchip: The suspended chip. - */ -static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip) -{ - struct s3c_gpio_pm *pm = ourchip->pm; - - if (pm == NULL || pm->resume == NULL) - S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); - else - pm->resume(ourchip); -} - -void s3c_pm_restore_gpios(void) -{ - struct s3c_gpio_chip *ourchip; - unsigned int gpio_nr; - - for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { - ourchip = s3c_gpiolib_getchip(gpio_nr); - if (!ourchip) - continue; - - s3c_pm_resume_gpio(ourchip); - - gpio_nr += ourchip->chip.ngpio; - gpio_nr += CONFIG_S3C_GPIO_SPACE; - } -} diff --git a/trunk/arch/arm/plat-s3c/pm.c b/trunk/arch/arm/plat-s3c/pm.c index 8d97db2c7a0d..061182ca66e3 100644 --- a/trunk/arch/arm/plat-s3c/pm.c +++ b/trunk/arch/arm/plat-s3c/pm.c @@ -21,10 +21,11 @@ #include #include -#include #include #include +#include +#include #include #include @@ -69,8 +70,6 @@ static inline void s3c_pm_debug_init(void) /* Save the UART configurations if we are configured for debug. */ -unsigned char pm_uart_udivslot; - #ifdef CONFIG_S3C2410_PM_DEBUG struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; @@ -84,12 +83,6 @@ static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) save->ufcon = __raw_readl(regs + S3C2410_UFCON); save->umcon = __raw_readl(regs + S3C2410_UMCON); save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); - - if (pm_uart_udivslot) - save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); - - S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", - uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); } static void s3c_pm_save_uarts(void) @@ -105,16 +98,11 @@ static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) { void __iomem *regs = S3C_VA_UARTx(uart); - s3c_pm_arch_update_uart(regs, save); - __raw_writel(save->ulcon, regs + S3C2410_ULCON); __raw_writel(save->ucon, regs + S3C2410_UCON); __raw_writel(save->ufcon, regs + S3C2410_UFCON); __raw_writel(save->umcon, regs + S3C2410_UMCON); __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); - - if (pm_uart_udivslot) - __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); } static void s3c_pm_restore_uarts(void) @@ -325,9 +313,6 @@ static int s3c_pm_enter(suspend_state_t state) S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); - /* LEDs should now be 1110 */ - s3c_pm_debug_smdkled(1 << 1, 0); - s3c_pm_check_restore(); /* ok, let's return from sleep */ diff --git a/trunk/arch/arm/plat-s3c24xx/devs.c b/trunk/arch/arm/plat-s3c24xx/devs.c index 4eb378c89a39..16ac01d9b8ab 100644 --- a/trunk/arch/arm/plat-s3c24xx/devs.c +++ b/trunk/arch/arm/plat-s3c24xx/devs.c @@ -136,6 +136,36 @@ struct platform_device *s3c24xx_uart_src[4] = { struct platform_device *s3c24xx_uart_devs[4] = { }; +/* USB Host Controller */ + +static struct resource s3c_usb_resource[] = { + [0] = { + .start = S3C24XX_PA_USBHOST, + .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USBH, + .end = IRQ_USBH, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_usb_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_usb = { + .name = "s3c2410-ohci", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usb_resource), + .resource = s3c_usb_resource, + .dev = { + .dma_mask = &s3c_device_usb_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_usb); + /* LCD Controller */ static struct resource s3c_lcd_resource[] = { diff --git a/trunk/arch/arm/plat-s3c24xx/gpiolib.c b/trunk/arch/arm/plat-s3c24xx/gpiolib.c index 4bac12dc0733..5c0491bf738b 100644 --- a/trunk/arch/arm/plat-s3c24xx/gpiolib.c +++ b/trunk/arch/arm/plat-s3c24xx/gpiolib.c @@ -22,7 +22,6 @@ #include #include #include -#include #include @@ -79,7 +78,6 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset) struct s3c_gpio_chip s3c24xx_gpios[] = { [0] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), - .pm = __gpio_pm(&s3c_gpio_pm_1bit), .chip = { .base = S3C2410_GPA0, .owner = THIS_MODULE, @@ -91,7 +89,6 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [1] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPB0), - .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPB0, .owner = THIS_MODULE, @@ -101,7 +98,6 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [2] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPC0), - .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPC0, .owner = THIS_MODULE, @@ -111,7 +107,6 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [3] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPD0), - .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPD0, .owner = THIS_MODULE, @@ -121,7 +116,6 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [4] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPE0), - .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPE0, .label = "GPIOE", @@ -131,7 +125,6 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [5] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPF0), - .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPF0, .owner = THIS_MODULE, @@ -142,7 +135,6 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [6] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPG0), - .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPG0, .owner = THIS_MODULE, diff --git a/trunk/arch/arm/plat-s3c24xx/include/plat/map.h b/trunk/arch/arm/plat-s3c24xx/include/plat/map.h index c4d133436fc7..eed8f78e7593 100644 --- a/trunk/arch/arm/plat-s3c24xx/include/plat/map.h +++ b/trunk/arch/arm/plat-s3c24xx/include/plat/map.h @@ -58,6 +58,7 @@ #define S3C24XX_SZ_SPI SZ_1M #define S3C24XX_SZ_SDI SZ_1M #define S3C24XX_SZ_NAND SZ_1M +#define S3C24XX_SZ_USBHOST SZ_1M /* GPIO ports */ diff --git a/trunk/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/trunk/arch/arm/plat-s3c24xx/include/plat/pm-core.h index fb45dd9adca5..c75882113e04 100644 --- a/trunk/arch/arm/plat-s3c24xx/include/plat/pm-core.h +++ b/trunk/arch/arm/plat-s3c24xx/include/plat/pm-core.h @@ -57,8 +57,3 @@ static inline void s3c_pm_arch_show_resume_irqs(void) s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), s3c_irqwake_eintmask); } - -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) -{ -} diff --git a/trunk/arch/arm/plat-s3c24xx/pm.c b/trunk/arch/arm/plat-s3c24xx/pm.c index 5135c40a1b90..062a29339a91 100644 --- a/trunk/arch/arm/plat-s3c24xx/pm.c +++ b/trunk/arch/arm/plat-s3c24xx/pm.c @@ -75,10 +75,43 @@ static struct sleep_save core_save[] = { SAVE_ITEM(S3C2410_CLKSLOW), }; +static struct gpio_sleep { + void __iomem *base; + unsigned int gpcon; + unsigned int gpdat; + unsigned int gpup; +} gpio_save[] = { + [0] = { + .base = S3C2410_GPACON, + }, + [1] = { + .base = S3C2410_GPBCON, + }, + [2] = { + .base = S3C2410_GPCCON, + }, + [3] = { + .base = S3C2410_GPDCON, + }, + [4] = { + .base = S3C2410_GPECON, + }, + [5] = { + .base = S3C2410_GPFCON, + }, + [6] = { + .base = S3C2410_GPGCON, + }, + [7] = { + .base = S3C2410_GPHCON, + }, +}; + static struct sleep_save misc_save[] = { SAVE_ITEM(S3C2410_DCLKCON), }; + /* s3c_pm_check_resume_pin * * check to see if the pin is configured correctly for sleep mode, and @@ -132,6 +165,186 @@ void s3c_pm_configure_extint(void) } } +/* offsets for CON/DAT/UP registers */ + +#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON) +#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) +#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) + +/* s3c_pm_save_gpios() + * + * Save the state of the GPIOs + */ + +void s3c_pm_save_gpios(void) +{ + struct gpio_sleep *gps = gpio_save; + unsigned int gpio; + + for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) { + void __iomem *base = gps->base; + + gps->gpcon = __raw_readl(base + OFFS_CON); + gps->gpdat = __raw_readl(base + OFFS_DAT); + + if (gpio > 0) + gps->gpup = __raw_readl(base + OFFS_UP); + + } +} + +/* Test whether the given masked+shifted bits of an GPIO configuration + * are one of the SFN (special function) modes. */ + +static inline int is_sfn(unsigned long con) +{ + return (con == 2 || con == 3); +} + +/* Test if the given masked+shifted GPIO configuration is an input */ + +static inline int is_in(unsigned long con) +{ + return con == 0; +} + +/* Test if the given masked+shifted GPIO configuration is an output */ + +static inline int is_out(unsigned long con) +{ + return con == 1; +} + +/** + * s3c2410_pm_restore_gpio() - restore the given GPIO bank + * @index: The number of the GPIO bank being resumed. + * @gps: The sleep confgiuration for the bank. + * + * Restore one of the GPIO banks that was saved during suspend. This is + * not as simple as once thought, due to the possibility of glitches + * from the order that the CON and DAT registers are set in. + * + * The three states the pin can be are {IN,OUT,SFN} which gives us 9 + * combinations of changes to check. Three of these, if the pin stays + * in the same configuration can be discounted. This leaves us with + * the following: + * + * { IN => OUT } Change DAT first + * { IN => SFN } Change CON first + * { OUT => SFN } Change CON first, so new data will not glitch + * { OUT => IN } Change CON first, so new data will not glitch + * { SFN => IN } Change CON first + * { SFN => OUT } Change DAT first, so new data will not glitch [1] + * + * We do not currently deal with the UP registers as these control + * weak resistors, so a small delay in change should not need to bring + * these into the calculations. + * + * [1] this assumes that writing to a pin DAT whilst in SFN will set the + * state for when it is next output. + */ + +static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps) +{ + void __iomem *base = gps->base; + unsigned long gps_gpcon = gps->gpcon; + unsigned long gps_gpdat = gps->gpdat; + unsigned long old_gpcon; + unsigned long old_gpdat; + unsigned long old_gpup = 0x0; + unsigned long gpcon; + int nr; + + old_gpcon = __raw_readl(base + OFFS_CON); + old_gpdat = __raw_readl(base + OFFS_DAT); + + if (base == S3C2410_GPACON) { + /* GPACON only has one bit per control / data and no PULLUPs. + * GPACON[x] = 0 => Output, 1 => SFN */ + + /* first set all SFN bits to SFN */ + + gpcon = old_gpcon | gps->gpcon; + __raw_writel(gpcon, base + OFFS_CON); + + /* now set all the other bits */ + + __raw_writel(gps_gpdat, base + OFFS_DAT); + __raw_writel(gps_gpcon, base + OFFS_CON); + } else { + unsigned long old, new, mask; + unsigned long change_mask = 0x0; + + old_gpup = __raw_readl(base + OFFS_UP); + + /* Create a change_mask of all the items that need to have + * their CON value changed before their DAT value, so that + * we minimise the work between the two settings. + */ + + for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) { + old = (old_gpcon & mask) >> nr; + new = (gps_gpcon & mask) >> nr; + + /* If there is no change, then skip */ + + if (old == new) + continue; + + /* If both are special function, then skip */ + + if (is_sfn(old) && is_sfn(new)) + continue; + + /* Change is IN => OUT, do not change now */ + + if (is_in(old) && is_out(new)) + continue; + + /* Change is SFN => OUT, do not change now */ + + if (is_sfn(old) && is_out(new)) + continue; + + /* We should now be at the case of IN=>SFN, + * OUT=>SFN, OUT=>IN, SFN=>IN. */ + + change_mask |= mask; + } + + /* Write the new CON settings */ + + gpcon = old_gpcon & ~change_mask; + gpcon |= gps_gpcon & change_mask; + + __raw_writel(gpcon, base + OFFS_CON); + + /* Now change any items that require DAT,CON */ + + __raw_writel(gps_gpdat, base + OFFS_DAT); + __raw_writel(gps_gpcon, base + OFFS_CON); + __raw_writel(gps->gpup, base + OFFS_UP); + } + + S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", + index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); +} + + +/** s3c2410_pm_restore_gpios() + * + * Restore the state of the GPIOs + */ + +void s3c_pm_restore_gpios(void) +{ + struct gpio_sleep *gps = gpio_save; + int gpio; + + for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) { + s3c2410_pm_restore_gpio(gpio, gps); + } +} void s3c_pm_restore_core(void) { diff --git a/trunk/arch/arm/plat-s3c64xx/Kconfig b/trunk/arch/arm/plat-s3c64xx/Kconfig index eb088db0e650..54375a00a7d2 100644 --- a/trunk/arch/arm/plat-s3c64xx/Kconfig +++ b/trunk/arch/arm/plat-s3c64xx/Kconfig @@ -19,7 +19,6 @@ config PLAT_S3C64XX select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX select S3C_GPIO_CFG_S3C64XX - select USB_ARCH_HAS_OHCI help Base platform code for any Samsung S3C64XX device @@ -60,9 +59,4 @@ config S3C64XX_SETUP_FB_24BPP help Common setup code for S3C64XX with an 24bpp RGB display helper. -config S3C64XX_SETUP_SDHCI_GPIO - bool - help - Common setup code for S3C64XX SDHCI GPIO configurations - endif diff --git a/trunk/arch/arm/plat-s3c64xx/Makefile b/trunk/arch/arm/plat-s3c64xx/Makefile index 030050f5c76d..2e6d79bf8f33 100644 --- a/trunk/arch/arm/plat-s3c64xx/Makefile +++ b/trunk/arch/arm/plat-s3c64xx/Makefile @@ -24,15 +24,8 @@ obj-y += gpiolib.o obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o -# PM support - -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += sleep.o -obj-$(CONFIG_PM) += irq-pm.o - # Device setup obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o -obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o \ No newline at end of file diff --git a/trunk/arch/arm/plat-s3c64xx/cpu.c b/trunk/arch/arm/plat-s3c64xx/cpu.c index 19f68b5f0d36..91f49a3a665d 100644 --- a/trunk/arch/arm/plat-s3c64xx/cpu.c +++ b/trunk/arch/arm/plat-s3c64xx/cpu.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -105,16 +104,6 @@ static struct map_desc s3c_iodesc[] __initdata = { }, }; - -struct sysdev_class s3c64xx_sysclass = { - .name = "s3c64xx-core", -}; - -static struct sys_device s3c64xx_sysdev = { - .cls = &s3c64xx_sysclass, -}; - - /* read cpu identification code */ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) @@ -126,21 +115,5 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) iotable_init(mach_desc, size); idcode = __raw_readl(S3C_VA_SYS + 0x118); - if (!idcode) { - /* S3C6400 has the ID register in a different place, - * and needs a write before it can be read. */ - - __raw_writel(0x0, S3C_VA_SYS + 0xA1C); - idcode = __raw_readl(S3C_VA_SYS + 0xA1C); - } - s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); } - -static __init int s3c64xx_sysdev_init(void) -{ - sysdev_class_register(&s3c64xx_sysclass); - return sysdev_register(&s3c64xx_sysdev); -} - -core_initcall(s3c64xx_sysdev_init); diff --git a/trunk/arch/arm/plat-s3c64xx/gpiolib.c b/trunk/arch/arm/plat-s3c64xx/gpiolib.c index ccb82e854962..ee9188add8fb 100644 --- a/trunk/arch/arm/plat-s3c64xx/gpiolib.c +++ b/trunk/arch/arm/plat-s3c64xx/gpiolib.c @@ -385,19 +385,12 @@ static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) { chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); } static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) { chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) -{ - chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); } static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, @@ -419,8 +412,7 @@ static __init int s3c64xx_gpiolib_init(void) s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), s3c64xx_gpiolib_add_4bit2); - s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), - s3c64xx_gpiolib_add_2bit); + s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); return 0; } diff --git a/trunk/arch/arm/plat-s3c64xx/include/plat/irqs.h b/trunk/arch/arm/plat-s3c64xx/include/plat/irqs.h index 743a70094d04..f865bf4d709e 100644 --- a/trunk/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ b/trunk/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -157,7 +157,6 @@ #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) #define IRQ_EINT(x) S3C_EINT(x) -#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) /* Next the external interrupt groups. These are similar to the IRQ_EINT(x) * that they are sourced from the GPIO pins but with a different scheme for diff --git a/trunk/arch/arm/plat-s3c64xx/include/plat/pm-core.h b/trunk/arch/arm/plat-s3c64xx/include/plat/pm-core.h deleted file mode 100644 index d347de3ba0dc..000000000000 --- a/trunk/arch/arm/plat-s3c64xx/include/plat/pm-core.h +++ /dev/null @@ -1,98 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -static inline void s3c_pm_debug_init_uart(void) -{ - u32 tmp = __raw_readl(S3C_PCLK_GATE); - - /* As a note, since the S3C64XX UARTs generally have multiple - * clock sources, we simply enable PCLK at the moment and hope - * that the resume settings for the UART are suitable for the - * use with PCLK. - */ - - tmp |= S3C_CLKCON_PCLK_UART0; - tmp |= S3C_CLKCON_PCLK_UART1; - tmp |= S3C_CLKCON_PCLK_UART2; - tmp |= S3C_CLKCON_PCLK_UART3; - - __raw_writel(tmp, S3C_PCLK_GATE); - udelay(10); -} - -static inline void s3c_pm_arch_prepare_irqs(void) -{ - /* VIC should have already been taken care of */ - - /* clear any pending EINT0 interrupts */ - __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); -} - -static inline void s3c_pm_arch_stop_clocks(void) -{ -} - -static inline void s3c_pm_arch_show_resume_irqs(void) -{ -} - -/* make these defines, we currently do not have any need to change - * the IRQ wake controls depending on the CPU we are running on */ - -#define s3c_irqwake_eintallow ((1 << 28) - 1) -#define s3c_irqwake_intallow (0) - -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) -{ - u32 ucon = __raw_readl(regs + S3C2410_UCON); - u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; - u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; - u32 new_ucon; - u32 delta; - - /* S3C64XX UART blocks only support level interrupts, so ensure that - * when we restore unused UART blocks we force the level interrupt - * settigs. */ - save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; - - /* We have a constraint on changing the clock type of the UART - * between UCLKx and PCLK, so ensure that when we restore UCON - * that the CLK field is correctly modified if the bootloader - * has changed anything. - */ - if (ucon_clk != save_clk) { - new_ucon = save->ucon; - delta = ucon_clk ^ save_clk; - - /* change from UCLKx => wrong PCLK, - * either UCLK can be tested for by a bit-test - * with UCLK0 */ - if (ucon_clk & S3C6400_UCON_UCLK0 && - !(save_clk & S3C6400_UCON_UCLK0) && - delta & S3C6400_UCON_PCLK2) { - new_ucon &= ~S3C6400_UCON_UCLK0; - } else if (delta == S3C6400_UCON_PCLK2) { - /* as an precaution, don't change from - * PCLK2 => PCLK or vice-versa */ - new_ucon ^= S3C6400_UCON_PCLK2; - } - - S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", - ucon, new_ucon, save->ucon); - save->ucon = new_ucon; - } -} diff --git a/trunk/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/trunk/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index 52836d41e333..b1082c163247 100644 --- a/trunk/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/trunk/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -32,7 +32,6 @@ #define S3C_HCLK_GATE S3C_CLKREG(0x30) #define S3C_PCLK_GATE S3C_CLKREG(0x34) #define S3C_SCLK_GATE S3C_CLKREG(0x38) -#define S3C_MEM0_GATE S3C_CLKREG(0x3C) /* CLKDIV0 */ #define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) diff --git a/trunk/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/trunk/arch/arm/plat-s3c64xx/include/plat/s3c6400.h index e12296666d46..571eaa2e54f1 100644 --- a/trunk/arch/arm/plat-s3c64xx/include/plat/s3c6400.h +++ b/trunk/arch/arm/plat-s3c64xx/include/plat/s3c6400.h @@ -21,7 +21,6 @@ extern void s3c6400_setup_clocks(void); #ifdef CONFIG_CPU_S3C6400 extern int s3c6400_init(void); -extern void s3c6400_init_irq(void); extern void s3c6400_map_io(void); extern void s3c6400_init_clocks(int xtal); diff --git a/trunk/arch/arm/plat-s3c64xx/irq-eint.c b/trunk/arch/arm/plat-s3c64xx/irq-eint.c index f81b7b818ba0..47e5155bb13e 100644 --- a/trunk/arch/arm/plat-s3c64xx/irq-eint.c +++ b/trunk/arch/arm/plat-s3c64xx/irq-eint.c @@ -14,7 +14,6 @@ #include #include -#include #include #include #include @@ -27,7 +26,6 @@ #include #include -#include #define eint_offset(irq) ((irq) - IRQ_EINT(0)) #define eint_irq_to_bit(irq) (1 << eint_offset(irq)) @@ -136,7 +134,6 @@ static struct irq_chip s3c_irq_eint = { .mask_ack = s3c_irq_eint_maskack, .ack = s3c_irq_eint_ack, .set_type = s3c_irq_eint_set_type, - .set_wake = s3c_irqext_wake, }; /* s3c_irq_demux_eint diff --git a/trunk/arch/arm/plat-s3c64xx/irq-pm.c b/trunk/arch/arm/plat-s3c64xx/irq-pm.c deleted file mode 100644 index ca523b5d4c17..000000000000 --- a/trunk/arch/arm/plat-s3c64xx/irq-pm.c +++ /dev/null @@ -1,111 +0,0 @@ -/* arch/arm/plat-s3c64xx/irq-pm.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - Interrupt handling Power Management - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -/* We handled all the IRQ types in this code, to save having to make several - * small files to handle each different type separately. Having the EINT_GRP - * code here shouldn't be as much bloat as the IRQ table space needed when - * they are enabled. The added benefit is we ensure that these registers are - * in the same state as we suspended. - */ - -static struct sleep_save irq_save[] = { - SAVE_ITEM(S3C64XX_PRIORITY), - SAVE_ITEM(S3C64XX_EINT0CON0), - SAVE_ITEM(S3C64XX_EINT0CON1), - SAVE_ITEM(S3C64XX_EINT0FLTCON0), - SAVE_ITEM(S3C64XX_EINT0FLTCON1), - SAVE_ITEM(S3C64XX_EINT0FLTCON2), - SAVE_ITEM(S3C64XX_EINT0FLTCON3), - SAVE_ITEM(S3C64XX_EINT0MASK), - SAVE_ITEM(S3C64XX_TINT_CSTAT), -}; - -static struct irq_grp_save { - u32 fltcon; - u32 con; - u32 mask; -} eint_grp_save[5]; - -static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; - -static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state) -{ - struct irq_grp_save *grp = eint_grp_save; - int i; - - S3C_PMDBG("%s: suspending IRQs\n", __func__); - - s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); - - for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) - irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); - - for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { - grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4)); - grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4)); - grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4)); - } - - return 0; -} - -static int s3c64xx_irq_pm_resume(struct sys_device *dev) -{ - struct irq_grp_save *grp = eint_grp_save; - int i; - - S3C_PMDBG("%s: resuming IRQs\n", __func__); - - s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); - - for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) - __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); - - for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { - __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4)); - __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4)); - __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4)); - } - - S3C_PMDBG("%s: IRQ configuration restored\n", __func__); - return 0; -} - -static struct sysdev_driver s3c64xx_irq_driver = { - .suspend = s3c64xx_irq_pm_suspend, - .resume = s3c64xx_irq_pm_resume, -}; - -static int __init s3c64xx_irq_pm_init(void) -{ - return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver); -} - -arch_initcall(s3c64xx_irq_pm_init); - diff --git a/trunk/arch/arm/plat-s3c64xx/irq.c b/trunk/arch/arm/plat-s3c64xx/irq.c index 8dc5b6da9789..f22edf7c2d2d 100644 --- a/trunk/arch/arm/plat-s3c64xx/irq.c +++ b/trunk/arch/arm/plat-s3c64xx/irq.c @@ -14,14 +14,12 @@ #include #include -#include #include #include #include #include -#include #include #include @@ -137,6 +135,9 @@ static inline unsigned int s3c_irq_uart_bit(unsigned int irq) } /* UART interrupt registers, not worth adding to seperate include header */ +#define S3C64XX_UINTP 0x30 +#define S3C64XX_UINTSP 0x34 +#define S3C64XX_UINTM 0x38 static void s3c_irq_uart_mask(unsigned int irq) { @@ -232,8 +233,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ - vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0); - vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0); + vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid); + vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid); /* add the timer sub-irqs */ diff --git a/trunk/arch/arm/plat-s3c64xx/pm.c b/trunk/arch/arm/plat-s3c64xx/pm.c deleted file mode 100644 index 07a6516a4f3c..000000000000 --- a/trunk/arch/arm/plat-s3c64xx/pm.c +++ /dev/null @@ -1,175 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/pm.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX CPU PM support. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK -#include - -void s3c_pm_debug_smdkled(u32 set, u32 clear) -{ - unsigned long flags; - u32 reg; - - local_irq_save(flags); - reg = __raw_readl(S3C64XX_GPNCON); - reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | - S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)); - reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | - S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15); - __raw_writel(reg, S3C64XX_GPNCON); - - reg = __raw_readl(S3C64XX_GPNDAT); - reg &= ~(clear << 12); - reg |= set << 12; - __raw_writel(reg, S3C64XX_GPNDAT); - - local_irq_restore(flags); -} -#endif - -static struct sleep_save core_save[] = { - SAVE_ITEM(S3C_APLL_LOCK), - SAVE_ITEM(S3C_MPLL_LOCK), - SAVE_ITEM(S3C_EPLL_LOCK), - SAVE_ITEM(S3C_CLK_SRC), - SAVE_ITEM(S3C_CLK_DIV0), - SAVE_ITEM(S3C_CLK_DIV1), - SAVE_ITEM(S3C_CLK_DIV2), - SAVE_ITEM(S3C_CLK_OUT), - SAVE_ITEM(S3C_HCLK_GATE), - SAVE_ITEM(S3C_PCLK_GATE), - SAVE_ITEM(S3C_SCLK_GATE), - SAVE_ITEM(S3C_MEM0_GATE), - - SAVE_ITEM(S3C_EPLL_CON1), - SAVE_ITEM(S3C_EPLL_CON0), - - SAVE_ITEM(S3C64XX_MEM0DRVCON), - SAVE_ITEM(S3C64XX_MEM1DRVCON), - -#ifndef CONFIG_CPU_FREQ - SAVE_ITEM(S3C_APLL_CON), - SAVE_ITEM(S3C_MPLL_CON), -#endif -}; - -static struct sleep_save misc_save[] = { - SAVE_ITEM(S3C64XX_AHB_CON0), - SAVE_ITEM(S3C64XX_AHB_CON1), - SAVE_ITEM(S3C64XX_AHB_CON2), - - SAVE_ITEM(S3C64XX_SPCON), - - SAVE_ITEM(S3C64XX_MEM0CONSTOP), - SAVE_ITEM(S3C64XX_MEM1CONSTOP), - SAVE_ITEM(S3C64XX_MEM0CONSLP0), - SAVE_ITEM(S3C64XX_MEM0CONSLP1), - SAVE_ITEM(S3C64XX_MEM1CONSLP), -}; - -void s3c_pm_configure_extint(void) -{ - __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); -} - -void s3c_pm_restore_core(void) -{ - __raw_writel(0, S3C64XX_EINT_MASK); - - s3c_pm_debug_smdkled(1 << 2, 0); - - s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); - s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); -} - -void s3c_pm_save_core(void) -{ - s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); - s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); -} - -/* since both s3c6400 and s3c6410 share the same sleep pm calls, we - * put the per-cpu code in here until any new cpu comes along and changes - * this. - */ - -#include - -static void s3c64xx_cpu_suspend(void) -{ - unsigned long tmp; - - /* set our standby method to sleep */ - - tmp = __raw_readl(S3C64XX_PWR_CFG); - tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; - tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP; - __raw_writel(tmp, S3C64XX_PWR_CFG); - - /* clear any old wakeup */ - - __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), - S3C64XX_WAKEUP_STAT); - - /* set the LED state to 0110 over sleep */ - s3c_pm_debug_smdkled(3 << 1, 0xf); - - /* issue the standby signal into the pm unit. Note, we - * issue a write-buffer drain just in case */ - - tmp = 0; - - asm("b 1f\n\t" - ".align 5\n\t" - "1:\n\t" - "mcr p15, 0, %0, c7, c10, 5\n\t" - "mcr p15, 0, %0, c7, c10, 4\n\t" - "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); - - /* we should never get past here */ - - panic("sleep resumed to originator?"); -} - -static void s3c64xx_pm_prepare(void) -{ - /* store address of resume. */ - __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); - - /* ensure previous wakeup state is cleared before sleeping */ - __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); -} - -static int s3c64xx_pm_init(void) -{ - pm_cpu_prep = s3c64xx_pm_prepare; - pm_cpu_sleep = s3c64xx_cpu_suspend; - pm_uart_udivslot = 1; - return 0; -} - -arch_initcall(s3c64xx_pm_init); diff --git a/trunk/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/trunk/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c deleted file mode 100644 index 5417123b0ac1..000000000000 --- a/trunk/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c +++ /dev/null @@ -1,55 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include - -void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) -{ - unsigned int gpio; - unsigned int end; - - end = S3C64XX_GPG(2 + width); - - /* Set all the necessary GPG pins to special-function 0 */ - for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } - - s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); -} - -void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) -{ - unsigned int gpio; - unsigned int end; - - end = S3C64XX_GPH(2 + width); - - /* Set all the necessary GPG pins to special-function 0 */ - for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } - - s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); -} diff --git a/trunk/arch/arm/plat-s3c64xx/sleep.S b/trunk/arch/arm/plat-s3c64xx/sleep.S deleted file mode 100644 index 8e71fe90a373..000000000000 --- a/trunk/arch/arm/plat-s3c64xx/sleep.S +++ /dev/null @@ -1,144 +0,0 @@ -/* linux/0arch/arm/plat-s3c64xx/sleep.S - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX CPU sleep code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include - -#undef S3C64XX_VA_GPIO -#define S3C64XX_VA_GPIO (0x0) - -#include -#include - -#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) - - .text - - /* s3c_cpu_save - * - * Save enough processor state to allow the restart of the pm.c - * code after resume. - * - * entry: - * r0 = pointer to the save block - */ - -ENTRY(s3c_cpu_save) - stmfd sp!, { r4 - r12, lr } - - mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID - mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control - mrc p15, 0, r9, c1, c0, 0 @ Control register - mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register - mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls - - stmia r0, { r4 - r13 } @ Save CP registers and SP - - @@ save our state to ram - bl s3c_pm_cb_flushcache - - @@ call final suspend code - ldr r0, =pm_cpu_sleep - ldr pc, [r0] - - @@ return to the caller, after the MMU is turned on. - @@ restore the last bits of the stack and return. -resume_with_mmu: - ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save - - .data - - /* the next bit is code, but it requires easy access to the - * s3c_sleep_save_phys data before the MMU is switched on, so - * we store the code that needs this variable in the .data where - * the value can be written to (the .text segment is RO). - */ - - .global s3c_sleep_save_phys -s3c_sleep_save_phys: - .word 0 - - /* Sleep magic, the word before the resume entry point so that the - * bootloader can check for a resumeable image. */ - - .word 0x2bedf00d - - /* s3c_cpu_reusme - * - * This is the entry point, stored by whatever method the bootloader - * requires to get the kernel runnign again. This code expects to be - * entered with no caches live and the MMU disabled. It will then - * restore the MMU and other basic CP registers saved and restart - * the kernel C code to finish the resume code. - */ - -ENTRY(s3c_cpu_resume) - msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE - ldr r2, =LL_UART /* for debug */ - -#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK - /* Initialise the GPIO state if we are debugging via the SMDK LEDs, - * as the uboot version supplied resets these to inputs during the - * resume checks. - */ - - ldr r3, =S3C64XX_PA_GPIO - ldr r0, [ r3, #S3C64XX_GPNCON ] - bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ - S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) - orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ - S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) - str r0, [ r3, #S3C64XX_GPNCON ] - - ldr r0, [ r3, #S3C64XX_GPNDAT ] - bic r0, r0, #0xf << 12 @ GPN12..15 - orr r0, r0, #1 << 15 @ GPN15 - str r0, [ r3, #S3C64XX_GPNDAT ] -#endif - - /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches - * are thoroughly cleaned just in case the bootloader didn't do it - * for us. */ - mov r0, #0 - mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache - mcr p15, 0, r0, c7, c10, 4 @ drain write buffer - @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs - @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches - - ldr r0, s3c_sleep_save_phys - ldmia r0, { r4 - r13 } - - mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID - mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register - - mov r0, #0 @ restore copro access controls - mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls - mcr p15, 0, r0, c7, c5, 4 - - ldr r2, =resume_with_mmu - mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ - nop - mov pc, r2 /* jump back */ - - .end