From 91eb73709d8dc3c9497b6a04c606423aac0bcfe5 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 11 Apr 2012 20:42:41 +0200 Subject: [PATCH] --- yaml --- r: 307166 b: refs/heads/master c: bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 1 + trunk/drivers/gpu/drm/i915/intel_display.c | 4 ++++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index e1511340af2e..9da67ce1025a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 48ecfa1090b65390b1cfa4c693ece6b171a407e4 +refs/heads/master: bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6 diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index a9030f852cf9..6d9205436121 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -497,6 +497,7 @@ */ # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) #define _3D_CHICKEN3 0x02090 +#define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5) #define MI_MODE 0x0209c # define VS_TIMER_DISPATCH (1 << 6) diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 813cc3cda059..1a6bb6101491 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -8897,6 +8897,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); + /* Bspec says we need to always set all mask bits. */ + I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) | + _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL); + /* * According to the spec the following bits should be * set in order to enable memory self-refresh and fbc: