From 9290c4cd49b469db9e3ac8fd77caeae259bbcf7e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 31 Mar 2010 13:41:35 +1000 Subject: [PATCH] --- yaml --- r: 189373 b: refs/heads/master c: d668046c13024d74af7d04a124ba55f406380fe7 h: refs/heads/master i: 189371: 622ab7ca32db5b90fbe066d0aca540127d5b8b30 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/r100.c | 7 +++++++ trunk/drivers/gpu/drm/radeon/radeon_reg.h | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 422a311826eb..e289ea32f156 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 08a370fa758fae7e387274ca3571ce625d7f829b +refs/heads/master: d668046c13024d74af7d04a124ba55f406380fe7 diff --git a/trunk/drivers/gpu/drm/radeon/r100.c b/trunk/drivers/gpu/drm/radeon/r100.c index c8f4b0300b70..3ae51ada1abf 100644 --- a/trunk/drivers/gpu/drm/radeon/r100.c +++ b/trunk/drivers/gpu/drm/radeon/r100.c @@ -1809,6 +1809,7 @@ void r100_set_common_regs(struct radeon_device *rdev) { struct drm_device *dev = rdev->ddev; bool force_dac2 = false; + u32 tmp; /* set these so they don't interfere with anything */ WREG32(RADEON_OV0_SCALE_CNTL, 0); @@ -1880,6 +1881,12 @@ void r100_set_common_regs(struct radeon_device *rdev) WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); WREG32(RADEON_DAC_CNTL2, dac2_cntl); } + + /* switch PM block to ACPI mode */ + tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); + tmp &= ~RADEON_PM_MODE_SEL; + WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); + } /* diff --git a/trunk/drivers/gpu/drm/radeon/radeon_reg.h b/trunk/drivers/gpu/drm/radeon/radeon_reg.h index 5c0dc082d330..eabbc9cf30a7 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_reg.h +++ b/trunk/drivers/gpu/drm/radeon/radeon_reg.h @@ -346,6 +346,7 @@ # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) # define RADEON_TVCLK_TURNOFF (1 << 31) #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ +# define RADEON_PM_MODE_SEL (1 << 13) # define RADEON_TCL_BYPASS_DISABLE (1 << 20) #define RADEON_CLR_CMP_CLR_3D 0x1a24 #define RADEON_CLR_CMP_CLR_DST 0x15c8