From 93844297e52b11a5a2c474a066c67abe30eeb123 Mon Sep 17 00:00:00 2001
From: Peter Ujfalusi <peter.ujfalusi@ti.com>
Date: Fri, 8 Jun 2012 17:02:00 +0300
Subject: [PATCH] --- yaml --- r: 313277 b: refs/heads/master c:
 a4c383196ed11283f26411dc152b7553a1f0ee9b h: refs/heads/master i:   313275:
 f1435ae88cbd2bb6176ab1f661dcd45bbb32a374 v: v3

---
 [refs]                             | 2 +-
 trunk/arch/arm/boot/dts/omap4.dtsi | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 7674c7b623fb..eeeab4e54f27 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4f4b5c7418692342551d38e28e8a686b1bb311db
+refs/heads/master: a4c383196ed11283f26411dc152b7553a1f0ee9b
diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi
index 5a5b5e84bd65..04cbbcb6ff91 100644
--- a/trunk/arch/arm/boot/dts/omap4.dtsi
+++ b/trunk/arch/arm/boot/dts/omap4.dtsi
@@ -286,5 +286,14 @@
 			interrupt-parent = <&gic>;
 			ti,hwmods = "mcpdm";
 		};
+
+		dmic: dmic@4012e000 {
+			compatible = "ti,omap4-dmic";
+			reg = <0x4012e000 0x7f>, /* MPU private access */
+			      <0x4902e000 0x7f>; /* L3 Interconnect */
+			interrupts = <0 114 0x4>;
+			interrupt-parent = <&gic>;
+			ti,hwmods = "dmic";
+		};
 	};
 };