From 95a2c354bc5a8cb89a3341b3f0a4d8a0af81ce97 Mon Sep 17 00:00:00 2001
From: Paul Walmsley <paul@pwsan.com>
Date: Tue, 27 Jan 2009 19:12:54 -0700
Subject: [PATCH] --- yaml --- r: 137319 b: refs/heads/master c:
 9299fd85a00a52b7c575fa02b3031ad407a15344 h: refs/heads/master i:   137317:
 7776229e6cf00695bb3b3fafab6da1ac7c406630   137315:
 88e65ed90f94b4096de5ca1d653626efe8fb61f6   137311:
 3f91a5731f59e04c11f7adcd8d15faa101f0d46b v: v3

---
 [refs]                                |  2 +-
 trunk/arch/arm/mach-omap2/clock24xx.c |  1 +
 trunk/arch/arm/mach-omap2/clock24xx.h | 14 ++++++++++++++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 99937df88ccb..9c8aa36995e8 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: fecb494beef09e4caaa80313834af26f57091195
+refs/heads/master: 9299fd85a00a52b7c575fa02b3031ad407a15344
diff --git a/trunk/arch/arm/mach-omap2/clock24xx.c b/trunk/arch/arm/mach-omap2/clock24xx.c
index 91ad2070264d..421728a7f903 100644
--- a/trunk/arch/arm/mach-omap2/clock24xx.c
+++ b/trunk/arch/arm/mach-omap2/clock24xx.c
@@ -112,6 +112,7 @@ static struct omap_clk omap24xx_clks[] = {
 	CLK(NULL,	"usb_l4_ick",	&usb_l4_ick,	CK_243X | CK_242X),
 	/* L4 domain clocks */
 	CLK(NULL,	"l4_ck",	&l4_ck,		CK_243X | CK_242X),
+	CLK(NULL,	"ssi_l4_ick",	&ssi_l4_ick,	CK_243X | CK_242X),
 	/* virtual meta-group clock */
 	CLK(NULL,	"virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
 	/* general l4 interface ck, multi-parent functional clk */
diff --git a/trunk/arch/arm/mach-omap2/clock24xx.h b/trunk/arch/arm/mach-omap2/clock24xx.h
index b2442475fb47..32dd8573e56b 100644
--- a/trunk/arch/arm/mach-omap2/clock24xx.h
+++ b/trunk/arch/arm/mach-omap2/clock24xx.h
@@ -1276,6 +1276,20 @@ static struct clk ssi_ssr_sst_fck = {
 	.set_rate	= &omap2_clksel_set_rate
 };
 
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+	.name		= "ssi_l4_ick",
+	.ops		= &clkops_omap2_dflt_wait,
+	.parent		= &l4_ck,
+	.clkdm_name	= "core_l4_clkdm",
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+	.enable_bit	= OMAP24XX_EN_SSI_SHIFT,
+	.recalc		= &followparent_recalc,
+};
+
 
 /*
  * GFX clock domain