From 95b49809749a0529b9ef85b68c2fdf847ba89310 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 8 Oct 2007 16:08:52 -0500 Subject: [PATCH] --- yaml --- r: 67578 b: refs/heads/master c: ab9683ca8162f9d4b38e04b956278d8cc647dcfc h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/powerpc/boot/dts/mpc8541cds.dts | 36 ++++++++++++++++++++++ trunk/arch/powerpc/boot/dts/mpc8555cds.dts | 36 ++++++++++++++++++++++ 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index a45080d07412..9c011e63dc5d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8abc8f5f1eda7a34394c8006fe1cb4c13ffca682 +refs/heads/master: ab9683ca8162f9d4b38e04b956278d8cc647dcfc diff --git a/trunk/arch/powerpc/boot/dts/mpc8541cds.dts b/trunk/arch/powerpc/boot/dts/mpc8541cds.dts index 6633e07d9f4d..f3f4d79deb63 100644 --- a/trunk/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/trunk/arch/powerpc/boot/dts/mpc8541cds.dts @@ -145,6 +145,42 @@ device_type = "open-pic"; big-endian; }; + + cpm@919c0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; + reg = <919c0 30>; + ranges; + + muram@80000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 80000 10000>; + + data@0 { + compatible = "fsl,cpm-muram-data"; + reg = <0 2000 9000 1000>; + }; + }; + + brg@919f0 { + compatible = "fsl,mpc8541-brg", + "fsl,cpm2-brg", + "fsl,cpm-brg"; + reg = <919f0 10 915f0 10>; + }; + + cpmpic: pic@90c00 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + interrupts = <2e 2>; + interrupt-parent = <&mpic>; + reg = <90c00 80>; + compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; + }; + }; }; pci1: pci@e0008000 { diff --git a/trunk/arch/powerpc/boot/dts/mpc8555cds.dts b/trunk/arch/powerpc/boot/dts/mpc8555cds.dts index 99199295147e..57029cca32b2 100644 --- a/trunk/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/trunk/arch/powerpc/boot/dts/mpc8555cds.dts @@ -145,6 +145,42 @@ device_type = "open-pic"; big-endian; }; + + cpm@919c0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; + reg = <919c0 30>; + ranges; + + muram@80000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 80000 10000>; + + data@0 { + compatible = "fsl,cpm-muram-data"; + reg = <0 2000 9000 1000>; + }; + }; + + brg@919f0 { + compatible = "fsl,mpc8555-brg", + "fsl,cpm2-brg", + "fsl,cpm-brg"; + reg = <919f0 10 915f0 10>; + }; + + cpmpic: pic@90c00 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + interrupts = <2e 2>; + interrupt-parent = <&mpic>; + reg = <90c00 80>; + compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; + }; + }; }; pci1: pci@e0008000 {