From 95efa8c28d26fe7e198756a03e693e8c7e6d80a6 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Thu, 6 May 2010 22:01:53 -0700 Subject: [PATCH] --- yaml --- r: 194802 b: refs/heads/master c: 39e0786d3cf39c6d2f47b4818ae2da8b8ebc9ce2 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/microblaze/include/asm/system.h | 10 ---------- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/[refs] b/[refs] index 217bd58ec46e..c2d85779d3d6 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 18e8c134f4e984e6639e62846345192816f06d5c +refs/heads/master: 39e0786d3cf39c6d2f47b4818ae2da8b8ebc9ce2 diff --git a/trunk/arch/microblaze/include/asm/system.h b/trunk/arch/microblaze/include/asm/system.h index 48c4f0335e3f..b1e2f0710098 100644 --- a/trunk/arch/microblaze/include/asm/system.h +++ b/trunk/arch/microblaze/include/asm/system.h @@ -97,14 +97,4 @@ extern struct dentry *of_debugfs_root; #define arch_align_stack(x) (x) -/* - * MicroBlaze doesn't handle unaligned accesses in hardware. - * - * Based on this we force the IP header alignment in network drivers. - * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining - * cacheline alignment of buffers. - */ -#define NET_IP_ALIGN 2 -#define NET_SKB_PAD L1_CACHE_BYTES - #endif /* _ASM_MICROBLAZE_SYSTEM_H */