From 96f8f411211b1d85f80b61e992594cddce9a3405 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Sat, 15 May 2010 08:39:09 +0200 Subject: [PATCH] --- yaml --- r: 191364 b: refs/heads/master c: 7ebaa2838a751125c113072486334d7b4e63f9ad h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/x86/kernel/cpu/perf_event_p4.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 170f0b80f1fb..4f6c15af5905 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3e1bbdc3a721f4b1ed44f4554402a8dbc60fa97f +refs/heads/master: 7ebaa2838a751125c113072486334d7b4e63f9ad diff --git a/trunk/arch/x86/kernel/cpu/perf_event_p4.c b/trunk/arch/x86/kernel/cpu/perf_event_p4.c index cb875b1e2e87..424fc8de68e4 100644 --- a/trunk/arch/x86/kernel/cpu/perf_event_p4.c +++ b/trunk/arch/x86/kernel/cpu/perf_event_p4.c @@ -18,7 +18,7 @@ struct p4_event_bind { unsigned int opcode; /* Event code and ESCR selector */ unsigned int escr_msr[2]; /* ESCR MSR for this event */ - unsigned char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on abscence */ + char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on abscence */ }; struct p4_cache_event_bind { @@ -747,11 +747,11 @@ static int p4_get_escr_idx(unsigned int addr) static int p4_next_cntr(int thread, unsigned long *used_mask, struct p4_event_bind *bind) { - int i = 0, j; + int i, j; for (i = 0; i < P4_CNTR_LIMIT; i++) { - j = bind->cntr[thread][i++]; - if (j == -1 || !test_bit(j, used_mask)) + j = bind->cntr[thread][i]; + if (j != -1 && !test_bit(j, used_mask)) return j; }