From 970183b5fdaf2606c471d03026061c9273863ded Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 6 Jan 2011 18:49:34 -0500 Subject: [PATCH] --- yaml --- r: 228854 b: refs/heads/master c: 3313e3d4333ccbf8bd7c816775cfe9aca623bd8a h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/drm_crtc_helper.c | 5 +- trunk/drivers/gpu/drm/drm_fb_helper.c | 41 +++--- trunk/drivers/gpu/drm/i915/intel_fb.c | 1 + trunk/drivers/gpu/drm/nouveau/Kconfig | 2 +- .../drivers/gpu/drm/nouveau/nouveau_channel.c | 35 +++--- trunk/drivers/gpu/drm/nouveau/nouveau_drv.h | 1 - trunk/drivers/gpu/drm/nouveau/nouveau_fbcon.c | 1 + trunk/drivers/gpu/drm/nouveau/nouveau_fence.c | 2 +- .../drivers/gpu/drm/nouveau/nouveau_object.c | 3 +- trunk/drivers/gpu/drm/nouveau/nouveau_pm.c | 3 +- trunk/drivers/gpu/drm/nouveau/nv40_fifo.c | 1 + trunk/drivers/gpu/drm/nouveau/nv40_graph.c | 12 -- trunk/drivers/gpu/drm/nouveau/nv50_graph.c | 49 ++------ trunk/drivers/gpu/drm/nouveau/nvc0_fbcon.c | 2 + trunk/drivers/gpu/drm/nouveau/nvc0_fifo.c | 18 +-- trunk/drivers/gpu/drm/nouveau/nvc0_graph.c | 46 +++---- trunk/drivers/gpu/drm/nouveau/nvc0_graph.h | 2 + trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c | 46 ++----- trunk/drivers/gpu/drm/radeon/r300.c | 5 +- trunk/drivers/gpu/drm/radeon/r600.c | 118 ++++++++++++++++++ trunk/drivers/gpu/drm/radeon/radeon.h | 8 ++ trunk/drivers/gpu/drm/radeon/radeon_asic.c | 14 +-- trunk/drivers/gpu/drm/radeon/radeon_asic.h | 2 + trunk/drivers/gpu/drm/radeon/radeon_fb.c | 2 + trunk/drivers/gpu/drm/radeon/radeon_reg.h | 9 ++ trunk/drivers/gpu/vga/vga_switcheroo.c | 4 +- trunk/include/drm/drm_fb_helper.h | 3 + 28 files changed, 255 insertions(+), 182 deletions(-) diff --git a/[refs] b/[refs] index 2e8c69d67e4c..3f107447c20d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0ba41e449fd0f45f5b29c1009020ab1b298bedda +refs/heads/master: 3313e3d4333ccbf8bd7c816775cfe9aca623bd8a diff --git a/trunk/drivers/gpu/drm/drm_crtc_helper.c b/trunk/drivers/gpu/drm/drm_crtc_helper.c index 952b3d4fb2a6..8de333aeeca3 100644 --- a/trunk/drivers/gpu/drm/drm_crtc_helper.c +++ b/trunk/drivers/gpu/drm/drm_crtc_helper.c @@ -661,7 +661,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) old_fb)) { DRM_ERROR("failed to set mode on [CRTC:%d]\n", set->crtc->base.id); - set->crtc->fb = old_fb; ret = -EINVAL; goto fail; } @@ -676,10 +675,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) set->crtc->fb = set->fb; ret = crtc_funcs->mode_set_base(set->crtc, set->x, set->y, old_fb); - if (ret != 0) { - set->crtc->fb = old_fb; + if (ret != 0) goto fail; - } } DRM_DEBUG_KMS("Setting connector DPMS state to on\n"); for (i = 0; i < set->num_connectors; i++) { diff --git a/trunk/drivers/gpu/drm/drm_fb_helper.c b/trunk/drivers/gpu/drm/drm_fb_helper.c index 0307d601f5e5..5c4f9b9ecdc0 100644 --- a/trunk/drivers/gpu/drm/drm_fb_helper.c +++ b/trunk/drivers/gpu/drm/drm_fb_helper.c @@ -607,25 +607,6 @@ void drm_fb_helper_fini(struct drm_fb_helper *fb_helper) } EXPORT_SYMBOL(drm_fb_helper_fini); -void drm_fb_helper_fill_fix(struct fb_info *info, struct drm_framebuffer *fb) -{ - info->fix.type = FB_TYPE_PACKED_PIXELS; - info->fix.visual = fb->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : - FB_VISUAL_TRUECOLOR; - info->fix.mmio_start = 0; - info->fix.mmio_len = 0; - info->fix.type_aux = 0; - info->fix.xpanstep = 1; /* doing it in hw */ - info->fix.ypanstep = 1; /* doing it in hw */ - info->fix.ywrapstep = 0; - info->fix.accel = FB_ACCEL_NONE; - info->fix.type_aux = 0; - - info->fix.line_length = fb->pitch; - return; -} -EXPORT_SYMBOL(drm_fb_helper_fill_fix); - static int setcolreg(struct drm_crtc *crtc, u16 red, u16 green, u16 blue, u16 regno, struct fb_info *info) { @@ -835,7 +816,6 @@ int drm_fb_helper_set_par(struct fb_info *info) mutex_unlock(&dev->mode_config.mutex); return ret; } - drm_fb_helper_fill_fix(info, fb_helper->fb); } mutex_unlock(&dev->mode_config.mutex); @@ -973,7 +953,6 @@ int drm_fb_helper_single_fb_probe(struct drm_fb_helper *fb_helper, if (new_fb) { info->var.pixclock = 0; - drm_fb_helper_fill_fix(info, fb_helper->fb); if (register_framebuffer(info) < 0) { return -EINVAL; } @@ -1000,6 +979,26 @@ int drm_fb_helper_single_fb_probe(struct drm_fb_helper *fb_helper, } EXPORT_SYMBOL(drm_fb_helper_single_fb_probe); +void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch, + uint32_t depth) +{ + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.visual = depth == 8 ? FB_VISUAL_PSEUDOCOLOR : + FB_VISUAL_TRUECOLOR; + info->fix.mmio_start = 0; + info->fix.mmio_len = 0; + info->fix.type_aux = 0; + info->fix.xpanstep = 1; /* doing it in hw */ + info->fix.ypanstep = 1; /* doing it in hw */ + info->fix.ywrapstep = 0; + info->fix.accel = FB_ACCEL_NONE; + info->fix.type_aux = 0; + + info->fix.line_length = pitch; + return; +} +EXPORT_SYMBOL(drm_fb_helper_fill_fix); + void drm_fb_helper_fill_var(struct fb_info *info, struct drm_fb_helper *fb_helper, uint32_t fb_width, uint32_t fb_height) { diff --git a/trunk/drivers/gpu/drm/i915/intel_fb.c b/trunk/drivers/gpu/drm/i915/intel_fb.c index 701e830d0012..67738f32dfd4 100644 --- a/trunk/drivers/gpu/drm/i915/intel_fb.c +++ b/trunk/drivers/gpu/drm/i915/intel_fb.c @@ -150,6 +150,7 @@ static int intelfb_create(struct intel_fbdev *ifbdev, // memset(info->screen_base, 0, size); + drm_fb_helper_fill_fix(info, fb->pitch, fb->depth); drm_fb_helper_fill_var(info, &ifbdev->helper, sizes->fb_width, sizes->fb_height); info->pixmap.size = 64*1024; diff --git a/trunk/drivers/gpu/drm/nouveau/Kconfig b/trunk/drivers/gpu/drm/nouveau/Kconfig index 21d6c29c2d21..72730e9ca06c 100644 --- a/trunk/drivers/gpu/drm/nouveau/Kconfig +++ b/trunk/drivers/gpu/drm/nouveau/Kconfig @@ -10,7 +10,7 @@ config DRM_NOUVEAU select FB select FRAMEBUFFER_CONSOLE if !EMBEDDED select FB_BACKLIGHT if DRM_NOUVEAU_BACKLIGHT - select ACPI_VIDEO if ACPI && X86 && BACKLIGHT_CLASS_DEVICE && VIDEO_OUTPUT_CONTROL && INPUT + select ACPI_VIDEO if ACPI help Choose this option for open-source nVidia support. diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_channel.c b/trunk/drivers/gpu/drm/nouveau/nouveau_channel.c index 3960d66d7aba..e37977d02463 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_channel.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_channel.c @@ -121,6 +121,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, uint32_t vram_handle, uint32_t gart_handle) { struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; struct nouveau_channel *chan; unsigned long flags; @@ -201,6 +202,15 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, /* disable the fifo caches */ pfifo->reassign(dev, false); + /* Create a graphics context for new channel */ + if (dev_priv->card_type < NV_50) { + ret = pgraph->create_context(chan); + if (ret) { + nouveau_channel_put(&chan); + return ret; + } + } + /* Construct inital RAMFC for new channel */ ret = pfifo->create_context(chan); if (ret) { @@ -243,9 +253,6 @@ nouveau_channel_get(struct drm_device *dev, struct drm_file *file_priv, int id) struct nouveau_channel *chan; unsigned long flags; - if (unlikely(id < 0 || id >= NOUVEAU_MAX_CHANNEL_NR)) - return ERR_PTR(-EINVAL); - spin_lock_irqsave(&dev_priv->channels.lock, flags); chan = nouveau_channel_get_unlocked(dev_priv->channels.ptr[id]); spin_unlock_irqrestore(&dev_priv->channels.lock, flags); @@ -436,20 +443,14 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, else init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART; - if (dev_priv->card_type < NV_C0) { - init->subchan[0].handle = NvM2MF; - if (dev_priv->card_type < NV_50) - init->subchan[0].grclass = 0x0039; - else - init->subchan[0].grclass = 0x5039; - init->subchan[1].handle = NvSw; - init->subchan[1].grclass = NV_SW; - init->nr_subchan = 2; - } else { - init->subchan[0].handle = 0x9039; - init->subchan[0].grclass = 0x9039; - init->nr_subchan = 1; - } + init->subchan[0].handle = NvM2MF; + if (dev_priv->card_type < NV_50) + init->subchan[0].grclass = 0x0039; + else + init->subchan[0].grclass = 0x5039; + init->subchan[1].handle = NvSw; + init->subchan[1].grclass = NV_SW; + init->nr_subchan = 2; /* Named memory object area */ ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem, diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_drv.h b/trunk/drivers/gpu/drm/nouveau/nouveau_drv.h index 46e32573b3a3..e59f5bcab1ad 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -1191,7 +1191,6 @@ extern int nv50_graph_unload_context(struct drm_device *); extern int nv50_grctx_init(struct nouveau_grctx *); extern void nv50_graph_tlb_flush(struct drm_device *dev); extern void nv86_graph_tlb_flush(struct drm_device *dev); -extern struct nouveau_enum nv50_data_error_names[]; /* nvc0_graph.c */ extern int nvc0_graph_init(struct drm_device *); diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/trunk/drivers/gpu/drm/nouveau/nouveau_fbcon.c index a26d04740c88..6d56a54b6e2e 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -359,6 +359,7 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev, info->screen_base = nvbo_kmap_obj_iovirtual(nouveau_fb->nvbo); info->screen_size = size; + drm_fb_helper_fill_fix(info, fb->pitch, fb->depth); drm_fb_helper_fill_var(info, &nfbdev->helper, sizes->fb_width, sizes->fb_height); /* Set aperture base/size for vesafb takeover */ diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_fence.c b/trunk/drivers/gpu/drm/nouveau/nouveau_fence.c index 221b8462ea37..88b2f29ca3e4 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -165,7 +165,7 @@ nouveau_fence_emit(struct nouveau_fence *fence) if (dev_priv->card_type < NV_C0) BEGIN_RING(chan, NvSubSw, 0x0050, 1); else - BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0050, 1); + BEGIN_NVC0(chan, 2, NvSubSw, 0x0050, 1); } else { BEGIN_RING(chan, NvSubSw, 0x0150, 1); } diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_object.c b/trunk/drivers/gpu/drm/nouveau/nouveau_object.c index 30b6544467ca..d77b1fcd19d4 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_object.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_object.c @@ -651,8 +651,7 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class) } break; case NVOBJ_ENGINE_GR: - if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) || - (dev_priv->card_type < NV_20 && !chan->pgraph_ctx)) { + if (dev_priv->card_type >= NV_50 && !chan->ramin_grctx) { struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_pm.c b/trunk/drivers/gpu/drm/nouveau/nouveau_pm.c index fb846a3fef15..d93814160bcf 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_pm.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_pm.c @@ -422,7 +422,8 @@ nouveau_hwmon_init(struct drm_device *dev) return ret; } dev_set_drvdata(hwmon_dev, dev); - ret = sysfs_create_group(&dev->pdev->dev.kobj, &hwmon_attrgroup); + ret = sysfs_create_group(&hwmon_dev->kobj, + &hwmon_attrgroup); if (ret) { NV_ERROR(dev, "Unable to create hwmon sysfs file: %d\n", ret); diff --git a/trunk/drivers/gpu/drm/nouveau/nv40_fifo.c b/trunk/drivers/gpu/drm/nouveau/nv40_fifo.c index 49b9a35a9cd6..c86e4d4e9b96 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv40_fifo.c +++ b/trunk/drivers/gpu/drm/nouveau/nv40_fifo.c @@ -64,6 +64,7 @@ nv40_fifo_create_context(struct nouveau_channel *chan) NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0x30000000 /* no idea.. */); + nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4); nv_wi32(dev, fc + 60, 0x0001FFFF); /* enable the fifo dma operation */ diff --git a/trunk/drivers/gpu/drm/nouveau/nv40_graph.c b/trunk/drivers/gpu/drm/nouveau/nv40_graph.c index 19ef92a0375a..0618846a97ce 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv40_graph.c +++ b/trunk/drivers/gpu/drm/nouveau/nv40_graph.c @@ -62,7 +62,6 @@ nv40_graph_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; struct nouveau_grctx ctx = {}; - unsigned long flags; int ret; ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16, @@ -77,17 +76,6 @@ nv40_graph_create_context(struct nouveau_channel *chan) nv40_grctx_init(&ctx); nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst); - - /* init grctx pointer in ramfc, and on PFIFO if channel is - * already active there - */ - spin_lock_irqsave(&dev_priv->context_switch_lock, flags); - nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4); - nv_mask(dev, 0x002500, 0x00000001, 0x00000000); - if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id) - nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4); - nv_mask(dev, 0x002500, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); return 0; } diff --git a/trunk/drivers/gpu/drm/nouveau/nv50_graph.c b/trunk/drivers/gpu/drm/nouveau/nv50_graph.c index 2d7ea75a09d4..c510e74acf4d 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/trunk/drivers/gpu/drm/nouveau/nv50_graph.c @@ -554,48 +554,13 @@ static struct nouveau_bitfield nv50_graph_trap_ccache[] = { }; /* There must be a *lot* of these. Will take some time to gather them up. */ -struct nouveau_enum nv50_data_error_names[] = { - { 0x00000003, "INVALID_QUERY_OR_TEXTURE" }, - { 0x00000004, "INVALID_VALUE" }, - { 0x00000005, "INVALID_ENUM" }, - { 0x00000008, "INVALID_OBJECT" }, - { 0x00000009, "READ_ONLY_OBJECT" }, - { 0x0000000a, "SUPERVISOR_OBJECT" }, - { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT" }, - { 0x0000000c, "INVALID_BITFIELD" }, - { 0x0000000d, "BEGIN_END_ACTIVE" }, - { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT" }, - { 0x0000000f, "VIEWPORT_ID_NEEDS_GP" }, - { 0x00000010, "RT_DOUBLE_BIND" }, - { 0x00000011, "RT_TYPES_MISMATCH" }, - { 0x00000012, "RT_LINEAR_WITH_ZETA" }, - { 0x00000015, "FP_TOO_FEW_REGS" }, - { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH" }, - { 0x00000017, "RT_LINEAR_WITH_MSAA" }, - { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT" }, - { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT" }, - { 0x0000001a, "RT_INVALID_ALIGNMENT" }, - { 0x0000001b, "SAMPLER_OVER_LIMIT" }, - { 0x0000001c, "TEXTURE_OVER_LIMIT" }, - { 0x0000001e, "GP_TOO_MANY_OUTPUTS" }, - { 0x0000001f, "RT_BPP128_WITH_MS8" }, - { 0x00000021, "Z_OUT_OF_BOUNDS" }, - { 0x00000023, "XY_OUT_OF_BOUNDS" }, - { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED" }, - { 0x00000028, "CP_NO_REG_SPACE_STRIPED" }, - { 0x00000029, "CP_NO_REG_SPACE_PACKED" }, - { 0x0000002a, "CP_NOT_ENOUGH_WARPS" }, - { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH" }, - { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS" }, - { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS" }, - { 0x0000002e, "CP_NO_BLOCKDIM_LATCH" }, - { 0x00000031, "ENG2D_FORMAT_MISMATCH" }, - { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP" }, - { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT" }, - { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT" }, - { 0x00000046, "LAYER_ID_NEEDS_GP" }, - { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT" }, - { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT" }, +static struct nouveau_enum nv50_data_error_names[] = { + { 4, "INVALID_VALUE" }, + { 5, "INVALID_ENUM" }, + { 8, "INVALID_OBJECT" }, + { 0xc, "INVALID_BITFIELD" }, + { 0x28, "MP_NO_REG_SPACE" }, + { 0x2b, "MP_BLOCK_SIZE_MISMATCH" }, {} }; diff --git a/trunk/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/trunk/drivers/gpu/drm/nouveau/nvc0_fbcon.c index fa5d4c234383..cbb4a1ae20b1 100644 --- a/trunk/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/trunk/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -200,6 +200,8 @@ nvc0_fbcon_accel_init(struct fb_info *info) return ret; } + printk(KERN_ERR "fb vma 0x%010llx\n", nvbo->vma.offset); + BEGIN_NVC0(chan, 2, NvSub2D, 0x0000, 1); OUT_RING (chan, 0x0000902d); BEGIN_NVC0(chan, 2, NvSub2D, 0x0104, 2); diff --git a/trunk/drivers/gpu/drm/nouveau/nvc0_fifo.c b/trunk/drivers/gpu/drm/nouveau/nvc0_fifo.c index e6f92c541dba..82a4ded5dae8 100644 --- a/trunk/drivers/gpu/drm/nouveau/nvc0_fifo.c +++ b/trunk/drivers/gpu/drm/nouveau/nvc0_fifo.c @@ -33,7 +33,6 @@ struct nvc0_fifo_priv { struct nouveau_gpuobj *playlist[2]; int cur_playlist; struct nouveau_vma user_vma; - int spoon_nr; }; struct nvc0_fifo_chan { @@ -325,18 +324,13 @@ nvc0_fifo_init(struct drm_device *dev) nv_wr32(dev, 0x000204, 0xffffffff); nv_wr32(dev, 0x002204, 0xffffffff); - priv->spoon_nr = hweight32(nv_rd32(dev, 0x002204)); - NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr); - /* assign engines to subfifos */ - if (priv->spoon_nr >= 3) { - nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */ - nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */ - nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */ - nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */ - nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */ - nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */ - } + nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */ + nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */ + nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */ + nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */ + nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */ + nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */ /* PSUBFIFO[n] */ for (i = 0; i < 3; i++) { diff --git a/trunk/drivers/gpu/drm/nouveau/nvc0_graph.c b/trunk/drivers/gpu/drm/nouveau/nvc0_graph.c index 5feacd5d5fa4..cf2f6aa920b4 100644 --- a/trunk/drivers/gpu/drm/nouveau/nvc0_graph.c +++ b/trunk/drivers/gpu/drm/nouveau/nvc0_graph.c @@ -244,6 +244,7 @@ nvc0_graph_load_context(struct nouveau_channel *chan) if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010)) NV_ERROR(dev, "PGRAPH: load_ctx timeout\n"); + printk(KERN_ERR "load_ctx 0x%08x\n", nv_rd32(dev, 0x409b00)); return 0; } @@ -333,6 +334,8 @@ nvc0_graph_create(struct drm_device *dev) case 0xc0: if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */ priv->magic_not_rop_nr = 0x07; + priv->magic419bd0 = 0x0a360000; + priv->magic419be4 = 0x04c33a54; /* filled values up to tp_total, the rest 0 */ priv->magicgpc980[0] = 0x22111000; priv->magicgpc980[1] = 0x00000233; @@ -342,6 +345,8 @@ nvc0_graph_create(struct drm_device *dev) } else if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */ priv->magic_not_rop_nr = 0x05; + priv->magic419bd0 = 0x043c0000; + priv->magic419be4 = 0x09041208; priv->magicgpc980[0] = 0x11110000; priv->magicgpc980[1] = 0x00233222; priv->magicgpc980[2] = 0x00000000; @@ -350,6 +355,8 @@ nvc0_graph_create(struct drm_device *dev) } else if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */ priv->magic_not_rop_nr = 0x06; + priv->magic419bd0 = 0x023e0000; + priv->magic419be4 = 0x10414104; priv->magicgpc980[0] = 0x11110000; priv->magicgpc980[1] = 0x03332222; priv->magicgpc980[2] = 0x00000000; @@ -359,6 +366,8 @@ nvc0_graph_create(struct drm_device *dev) break; case 0xc3: /* 450, 4/0/0/0, 2 */ priv->magic_not_rop_nr = 0x03; + priv->magic419bd0 = 0x00500000; + priv->magic419be4 = 0x00000000; priv->magicgpc980[0] = 0x00003210; priv->magicgpc980[1] = 0x00000000; priv->magicgpc980[2] = 0x00000000; @@ -367,6 +376,8 @@ nvc0_graph_create(struct drm_device *dev) break; case 0xc4: /* 460, 3/4/0/0, 4 */ priv->magic_not_rop_nr = 0x01; + priv->magic419bd0 = 0x045c0000; + priv->magic419be4 = 0x09041208; priv->magicgpc980[0] = 0x02321100; priv->magicgpc980[1] = 0x00000000; priv->magicgpc980[2] = 0x00000000; @@ -375,12 +386,14 @@ nvc0_graph_create(struct drm_device *dev) break; } - if (!priv->magic_not_rop_nr) { + if (!priv->magic419bd0) { NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n", priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2], priv->tp_nr[3], priv->rop_nr); /* use 0xc3's values... */ priv->magic_not_rop_nr = 0x03; + priv->magic419bd0 = 0x00500000; + priv->magic419be4 = 0x00000000; priv->magicgpc980[0] = 0x00003210; priv->magicgpc980[1] = 0x00000000; priv->magicgpc980[2] = 0x00000000; @@ -584,7 +597,7 @@ nvc0_graph_init_ctxctl(struct drm_device *dev) r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d"); if (ret == 0) - ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad"); + nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad"); nv_wr32(dev, 0x000260, r000260); if (ret) @@ -686,11 +699,18 @@ nvc0_graph_init(struct drm_device *dev) nv_wr32(dev, 0x400054, 0x34ce3464); ret = nvc0_graph_init_ctxctl(dev); - if (ret == 0) - dev_priv->engine.graph.accel_blocked = false; + if (ret) + return ret; + + dev_priv->engine.graph.accel_blocked = false; return 0; } +static struct nouveau_enum nvc0_graph_data_error[] = { + { 5, "INVALID_ENUM" }, + {} +}; + static int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst) { @@ -733,17 +753,9 @@ nvc0_graph_isr(struct drm_device *dev) stat &= ~0x00000010; } - if (stat & 0x00000020) { - NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d " - "class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst, subc, class, mthd, data); - nv_wr32(dev, 0x400100, 0x00000020); - stat &= ~0x00000020; - } - if (stat & 0x00100000) { NV_INFO(dev, "PGRAPH: DATA_ERROR ["); - nouveau_enum_print(nv50_data_error_names, code); + nouveau_enum_print(nvc0_graph_data_error, code); printk("] ch %d [0x%010llx] subc %d class 0x%04x " "mthd 0x%04x data 0x%08x\n", chid, inst, subc, class, mthd, data); @@ -751,14 +763,6 @@ nvc0_graph_isr(struct drm_device *dev) stat &= ~0x00100000; } - if (stat & 0x00200000) { - u32 trap = nv_rd32(dev, 0x400108); - NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap); - nv_wr32(dev, 0x400108, trap); - nv_wr32(dev, 0x400100, 0x00200000); - stat &= ~0x00200000; - } - if (stat & 0x00080000) { u32 ustat = nv_rd32(dev, 0x409c18); diff --git a/trunk/drivers/gpu/drm/nouveau/nvc0_graph.h b/trunk/drivers/gpu/drm/nouveau/nvc0_graph.h index 40e26f9c56c4..1e1f24f3fd34 100644 --- a/trunk/drivers/gpu/drm/nouveau/nvc0_graph.h +++ b/trunk/drivers/gpu/drm/nouveau/nvc0_graph.h @@ -46,6 +46,8 @@ struct nvc0_graph_priv { struct nouveau_gpuobj *unk4188b8; u8 magic_not_rop_nr; + u32 magic419bd0; + u32 magic419be4; u32 magicgpc980[4]; u32 magicgpc918; }; diff --git a/trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c b/trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c index b9e68b2d30aa..88fa6211ac19 100644 --- a/trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c +++ b/trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c @@ -1557,7 +1557,7 @@ nvc0_grctx_generate_unk47xx(struct drm_device *dev) } static void -nvc0_grctx_generate_shaders(struct drm_device *dev) +nvc0_grctx_generate_unk58xx(struct drm_device *dev) { nv_wr32(dev, 0x405800, 0x078000bf); nv_wr32(dev, 0x405830, 0x02180000); @@ -1593,7 +1593,7 @@ nvc0_grctx_generate_unk64xx(struct drm_device *dev) } static void -nvc0_grctx_generate_tpbus(struct drm_device *dev) +nvc0_grctx_generate_unk78xx(struct drm_device *dev) { nv_wr32(dev, 0x407804, 0x00000023); nv_wr32(dev, 0x40780c, 0x0a418820); @@ -1606,7 +1606,7 @@ nvc0_grctx_generate_tpbus(struct drm_device *dev) } static void -nvc0_grctx_generate_ccache(struct drm_device *dev) +nvc0_grctx_generate_unk80xx(struct drm_device *dev) { nv_wr32(dev, 0x408000, 0x00000000); nv_wr32(dev, 0x408004, 0x00000000); @@ -1801,7 +1801,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan) struct nvc0_graph_chan *grch = chan->pgraph_ctx; struct drm_device *dev = chan->dev; int i, gpc, tp, id; - u32 r000260, tmp; + u32 r000260; r000260 = nv_rd32(dev, 0x000260); nv_wr32(dev, 0x000260, r000260 & ~1); @@ -1811,11 +1811,11 @@ nvc0_grctx_generate(struct nouveau_channel *chan) nvc0_grctx_generate_macro(dev); nvc0_grctx_generate_m2mf(dev); nvc0_grctx_generate_unk47xx(dev); - nvc0_grctx_generate_shaders(dev); + nvc0_grctx_generate_unk58xx(dev); nvc0_grctx_generate_unk60xx(dev); nvc0_grctx_generate_unk64xx(dev); - nvc0_grctx_generate_tpbus(dev); - nvc0_grctx_generate_ccache(dev); + nvc0_grctx_generate_unk78xx(dev); + nvc0_grctx_generate_unk80xx(dev); nvc0_grctx_generate_rop(dev); nvc0_grctx_generate_gpc(dev); nvc0_grctx_generate_tp(dev); @@ -1843,12 +1843,8 @@ nvc0_grctx_generate(struct nouveau_channel *chan) } } - tmp = 0; - for (i = 0; i < priv->gpc_nr; i++) - tmp |= priv->tp_nr[i] << (i * 4); - nv_wr32(dev, 0x406028, tmp); - nv_wr32(dev, 0x405870, tmp); - + nv_wr32(dev, 0x406028, 0x00000443); + nv_wr32(dev, 0x405870, 0x00000443); nv_wr32(dev, 0x40602c, 0x00000000); nv_wr32(dev, 0x405874, 0x00000000); nv_wr32(dev, 0x406030, 0x00000000); @@ -1879,11 +1875,9 @@ nvc0_grctx_generate(struct nouveau_channel *chan) } if (1) { - u32 data[6] = {}, data2[2] = {}; + u32 data[6] = {}; u8 tpnr[GPC_MAX]; - u8 shift, ntpcv; - /* calculate first set of magics */ memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr)); for (tp = 0; tp < priv->tp_total; tp++) { @@ -1898,20 +1892,6 @@ nvc0_grctx_generate(struct nouveau_channel *chan) for (; tp < 32; tp++) data[tp / 6] |= 7 << ((tp % 6) * 5); - /* and the second... */ - shift = 0; - ntpcv = priv->tp_total; - while (!(ntpcv & (1 << 4))) { - ntpcv <<= 1; - shift++; - } - - data2[0] = (ntpcv << 16); - data2[0] |= (shift << 21); - data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); - for (i = 1; i < 7; i++) - data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); - // GPC_BROADCAST nv_wr32(dev, 0x418bb8, (priv->tp_total << 8) | priv->magic_not_rop_nr); @@ -1920,9 +1900,9 @@ nvc0_grctx_generate(struct nouveau_channel *chan) // GPC_BROADCAST.TP_BROADCAST nv_wr32(dev, 0x419bd0, (priv->tp_total << 8) | - priv->magic_not_rop_nr | - data2[0]); - nv_wr32(dev, 0x419be4, data2[1]); + priv->magic_not_rop_nr | + priv->magic419bd0); + nv_wr32(dev, 0x419be4, priv->magic419be4); for (i = 0; i < 6; i++) nv_wr32(dev, 0x419b00 + (i * 4), data[i]); diff --git a/trunk/drivers/gpu/drm/radeon/r300.c b/trunk/drivers/gpu/drm/radeon/r300.c index 23fee54c3b75..fae5e709f270 100644 --- a/trunk/drivers/gpu/drm/radeon/r300.c +++ b/trunk/drivers/gpu/drm/radeon/r300.c @@ -558,10 +558,7 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev) /* FIXME wait for idle */ - if (rdev->family < CHIP_R600) - link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); - else - link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); + link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { case RADEON_PCIE_LC_LINK_WIDTH_X0: diff --git a/trunk/drivers/gpu/drm/radeon/r600.c b/trunk/drivers/gpu/drm/radeon/r600.c index 279794c391e9..60ad8c03081a 100644 --- a/trunk/drivers/gpu/drm/radeon/r600.c +++ b/trunk/drivers/gpu/drm/radeon/r600.c @@ -3531,3 +3531,121 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) } else WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); } + +void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) +{ + u32 link_width_cntl, mask, target_reg; + + if (rdev->flags & RADEON_IS_IGP) + return; + + if (!(rdev->flags & RADEON_IS_PCIE)) + return; + + /* x2 cards have a special sequence */ + if (ASIC_IS_X2(rdev)) + return; + + /* FIXME wait for idle */ + + switch (lanes) { + case 0: + mask = RADEON_PCIE_LC_LINK_WIDTH_X0; + break; + case 1: + mask = RADEON_PCIE_LC_LINK_WIDTH_X1; + break; + case 2: + mask = RADEON_PCIE_LC_LINK_WIDTH_X2; + break; + case 4: + mask = RADEON_PCIE_LC_LINK_WIDTH_X4; + break; + case 8: + mask = RADEON_PCIE_LC_LINK_WIDTH_X8; + break; + case 12: + mask = RADEON_PCIE_LC_LINK_WIDTH_X12; + break; + case 16: + default: + mask = RADEON_PCIE_LC_LINK_WIDTH_X16; + break; + } + + link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); + + if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == + (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) + return; + + if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) + return; + + link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | + RADEON_PCIE_LC_RECONFIG_NOW | + R600_PCIE_LC_RENEGOTIATE_EN | + R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); + link_width_cntl |= mask; + + WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); + + /* some northbridges can renegotiate the link rather than requiring + * a complete re-config. + * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) + */ + if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) + link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; + else + link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; + + WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | + RADEON_PCIE_LC_RECONFIG_NOW)); + + if (rdev->family >= CHIP_RV770) + target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; + else + target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; + + /* wait for lane set to complete */ + link_width_cntl = RREG32(target_reg); + while (link_width_cntl == 0xffffffff) + link_width_cntl = RREG32(target_reg); + +} + +int r600_get_pcie_lanes(struct radeon_device *rdev) +{ + u32 link_width_cntl; + + if (rdev->flags & RADEON_IS_IGP) + return 0; + + if (!(rdev->flags & RADEON_IS_PCIE)) + return 0; + + /* x2 cards have a special sequence */ + if (ASIC_IS_X2(rdev)) + return 0; + + /* FIXME wait for idle */ + + link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); + + switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { + case RADEON_PCIE_LC_LINK_WIDTH_X0: + return 0; + case RADEON_PCIE_LC_LINK_WIDTH_X1: + return 1; + case RADEON_PCIE_LC_LINK_WIDTH_X2: + return 2; + case RADEON_PCIE_LC_LINK_WIDTH_X4: + return 4; + case RADEON_PCIE_LC_LINK_WIDTH_X8: + return 8; + case RADEON_PCIE_LC_LINK_WIDTH_X16: + default: + return 16; + } +} + diff --git a/trunk/drivers/gpu/drm/radeon/radeon.h b/trunk/drivers/gpu/drm/radeon/radeon.h index aff8080026a1..e9fb64c1e20b 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon.h +++ b/trunk/drivers/gpu/drm/radeon/radeon.h @@ -1317,6 +1317,14 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); (rdev->family == CHIP_RV410) || \ (rdev->family == CHIP_RS400) || \ (rdev->family == CHIP_RS480)) +#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ + (rdev->ddev->pdev->device == 0x9443) || \ + (rdev->ddev->pdev->device == 0x944B) || \ + (rdev->ddev->pdev->device == 0x9506) || \ + (rdev->ddev->pdev->device == 0x9509) || \ + (rdev->ddev->pdev->device == 0x950F) || \ + (rdev->ddev->pdev->device == 0x689C) || \ + (rdev->ddev->pdev->device == 0x689D)) #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ (rdev->family == CHIP_RS690) || \ diff --git a/trunk/drivers/gpu/drm/radeon/radeon_asic.c b/trunk/drivers/gpu/drm/radeon/radeon_asic.c index 3d73fe484f42..53c62404795d 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_asic.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_asic.c @@ -94,7 +94,7 @@ static void radeon_register_accessor_init(struct radeon_device *rdev) rdev->mc_rreg = &rs600_mc_rreg; rdev->mc_wreg = &rs600_mc_wreg; } - if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { + if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_HEMLOCK)) { rdev->pciep_rreg = &r600_pciep_rreg; rdev->pciep_wreg = &r600_pciep_wreg; } @@ -631,8 +631,8 @@ static struct radeon_asic r600_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, - .get_pcie_lanes = &rv370_get_pcie_lanes, - .set_pcie_lanes = NULL, + .get_pcie_lanes = &r600_get_pcie_lanes, + .set_pcie_lanes = &r600_set_pcie_lanes, .set_clock_gating = NULL, .set_surface_reg = r600_set_surface_reg, .clear_surface_reg = r600_clear_surface_reg, @@ -725,8 +725,8 @@ static struct radeon_asic rv770_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, - .get_pcie_lanes = &rv370_get_pcie_lanes, - .set_pcie_lanes = NULL, + .get_pcie_lanes = &r600_get_pcie_lanes, + .set_pcie_lanes = &r600_set_pcie_lanes, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r600_set_surface_reg, .clear_surface_reg = r600_clear_surface_reg, @@ -772,8 +772,8 @@ static struct radeon_asic evergreen_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, - .get_pcie_lanes = NULL, - .set_pcie_lanes = NULL, + .get_pcie_lanes = &r600_get_pcie_lanes, + .set_pcie_lanes = &r600_set_pcie_lanes, .set_clock_gating = NULL, .set_surface_reg = r600_set_surface_reg, .clear_surface_reg = r600_clear_surface_reg, diff --git a/trunk/drivers/gpu/drm/radeon/radeon_asic.h b/trunk/drivers/gpu/drm/radeon/radeon_asic.h index 4970eda1bd41..9ac71b8d1b9d 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_asic.h +++ b/trunk/drivers/gpu/drm/radeon/radeon_asic.h @@ -284,6 +284,8 @@ extern void r600_pm_misc(struct radeon_device *rdev); extern void r600_pm_init_profile(struct radeon_device *rdev); extern void rs780_pm_init_profile(struct radeon_device *rdev); extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); +extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); +extern int r600_get_pcie_lanes(struct radeon_device *rdev); /* * rv770,rv730,rv710,rv740 diff --git a/trunk/drivers/gpu/drm/radeon/radeon_fb.c b/trunk/drivers/gpu/drm/radeon/radeon_fb.c index ca32e9c1e91d..66324b5bb5ba 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_fb.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_fb.c @@ -225,6 +225,8 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev, strcpy(info->fix.id, "radeondrmfb"); + drm_fb_helper_fill_fix(info, fb->pitch, fb->depth); + info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; info->fbops = &radeonfb_ops; diff --git a/trunk/drivers/gpu/drm/radeon/radeon_reg.h b/trunk/drivers/gpu/drm/radeon/radeon_reg.h index 0a310b7f71c3..3369ce984af1 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_reg.h +++ b/trunk/drivers/gpu/drm/radeon/radeon_reg.h @@ -320,6 +320,15 @@ # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) +# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) +# define R600_PCIE_LC_RENEGOTIATION_SUPPORT (1 << 9) +# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10) +# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11) +# define R600_PCIE_LC_UPCONFIGURE_SUPPORT (1 << 12) +# define R600_PCIE_LC_UPCONFIGURE_DIS (1 << 13) + +#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c +#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c #define RADEON_CACHE_CNTL 0x1724 #define RADEON_CACHE_LINE 0x0f0c /* PCI */ diff --git a/trunk/drivers/gpu/vga/vga_switcheroo.c b/trunk/drivers/gpu/vga/vga_switcheroo.c index e01cacba685f..d2d8543686d3 100644 --- a/trunk/drivers/gpu/vga/vga_switcheroo.c +++ b/trunk/drivers/gpu/vga/vga_switcheroo.c @@ -346,11 +346,11 @@ vga_switcheroo_debugfs_write(struct file *filp, const char __user *ubuf, if (strncmp(usercmd, "DIS", 3) == 0) client_id = VGA_SWITCHEROO_DIS; - if (strncmp(usercmd, "MIGD", 4) == 0) { + if (strncmp(usercmd, "MIGD", 3) == 0) { just_mux = true; client_id = VGA_SWITCHEROO_IGD; } - if (strncmp(usercmd, "MDIS", 4) == 0) { + if (strncmp(usercmd, "MDIS", 3) == 0) { just_mux = true; client_id = VGA_SWITCHEROO_DIS; } diff --git a/trunk/include/drm/drm_fb_helper.h b/trunk/include/drm/drm_fb_helper.h index aac27bd56e89..f22e7fe4b6db 100644 --- a/trunk/include/drm/drm_fb_helper.h +++ b/trunk/include/drm/drm_fb_helper.h @@ -121,6 +121,9 @@ int drm_fb_helper_setcolreg(unsigned regno, void drm_fb_helper_restore(void); void drm_fb_helper_fill_var(struct fb_info *info, struct drm_fb_helper *fb_helper, uint32_t fb_width, uint32_t fb_height); +void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch, + uint32_t depth); + int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info); bool drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper);