From 9728e308def6c3df7a9a7e4252c36aefded6befa Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 10 May 2012 11:10:07 -0700 Subject: [PATCH] --- yaml --- r: 308157 b: refs/heads/master c: 33959553b81e46640994cbcdb4888d60022dc6fd h: refs/heads/master i: 308155: ff1412f6633b18c72164af41682fa91afa8d1d2b v: v3 --- [refs] | 2 +- trunk/arch/arm/Makefile | 4 +- trunk/arch/arm/mach-omap1/Kconfig | 1 + trunk/arch/arm/mach-omap2/Kconfig | 6 +- trunk/arch/arm/mach-omap2/Makefile | 165 +- trunk/arch/arm/mach-omap2/board-4430sdp.c | 44 - trunk/arch/arm/mach-omap2/board-igep0020.c | 10 +- trunk/arch/arm/mach-omap2/board-omap4panda.c | 57 +- trunk/arch/arm/mach-omap2/clockdomain44xx.c | 6 - .../mach-omap2/clockdomains2xxx_3xxx_data.c | 10 + .../arm/mach-omap2/clockdomains44xx_data.c | 2 - .../arm/mach-omap2/clockdomains_common_data.c | 24 - trunk/arch/arm/mach-omap2/common.h | 5 +- trunk/arch/arm/mach-omap2/dma.c | 11 +- trunk/arch/arm/mach-omap2/dsp.c | 5 +- trunk/arch/arm/mach-omap2/gpmc.c | 30 +- trunk/arch/arm/mach-omap2/hsmmc.c | 8 +- trunk/arch/arm/mach-omap2/id.c | 12 +- .../mach-omap2/include/mach/omap-wakeupgen.h | 8 + trunk/arch/arm/mach-omap2/io.c | 34 +- trunk/arch/arm/mach-omap2/iomap.h | 28 + trunk/arch/arm/mach-omap2/irq.c | 3 +- trunk/arch/arm/mach-omap2/mailbox.c | 6 +- trunk/arch/arm/mach-omap2/omap4-common.c | 58 + trunk/arch/arm/mach-omap2/omap_hwmod.c | 1143 +-- .../arm/mach-omap2/omap_hwmod_2420_data.c | 1548 +++- .../arm/mach-omap2/omap_hwmod_2430_data.c | 2321 ++++-- .../omap_hwmod_2xxx_interconnect_data.c | 266 +- .../mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 562 -- .../arm/mach-omap2/omap_hwmod_3xxx_data.c | 5007 +++++++------ .../arm/mach-omap2/omap_hwmod_44xx_data.c | 6613 ++++++++--------- .../arm/mach-omap2/omap_hwmod_common_data.h | 71 +- .../arm/mach-omap2/powerdomains3xxx_data.c | 2 +- trunk/arch/arm/mach-omap2/timer.c | 15 +- trunk/arch/arm/mach-omap2/usb-musb.c | 2 +- .../arm/mach-omap2/voltagedomains3xxx_data.c | 2 +- trunk/arch/arm/plat-omap/devices.c | 4 +- trunk/arch/arm/plat-omap/dma.c | 4 +- trunk/arch/arm/plat-omap/dmtimer.c | 2 + trunk/arch/arm/plat-omap/include/plat/cpu.h | 9 +- trunk/arch/arm/plat-omap/include/plat/dma.h | 5 - .../arch/arm/plat-omap/include/plat/dmtimer.h | 1 + .../arm/plat-omap/include/plat/omap_hwmod.h | 41 +- 43 files changed, 9480 insertions(+), 8677 deletions(-) delete mode 100644 trunk/arch/arm/mach-omap2/clockdomains_common_data.c diff --git a/[refs] b/[refs] index cff799bd5c73..9a8c7e95a1ae 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 812655e9c199c13cad206b40237463f861e3c5a6 +refs/heads/master: 33959553b81e46640994cbcdb4888d60022dc6fd diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index 7a6bde07e787..047a20780fc1 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -164,7 +164,9 @@ machine-$(CONFIG_ARCH_MXS) := mxs machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik machine-$(CONFIG_ARCH_OMAP1) := omap1 -machine-$(CONFIG_ARCH_OMAP2PLUS) := omap2 +machine-$(CONFIG_ARCH_OMAP2) := omap2 +machine-$(CONFIG_ARCH_OMAP3) := omap2 +machine-$(CONFIG_ARCH_OMAP4) := omap2 machine-$(CONFIG_ARCH_ORION5X) := orion5x machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell machine-$(CONFIG_ARCH_PNX4008) := pnx4008 diff --git a/trunk/arch/arm/mach-omap1/Kconfig b/trunk/arch/arm/mach-omap1/Kconfig index dfab466ebd1d..cba3f7191cfc 100644 --- a/trunk/arch/arm/mach-omap1/Kconfig +++ b/trunk/arch/arm/mach-omap1/Kconfig @@ -132,6 +132,7 @@ config MACH_OMAP_PALMTT config MACH_SX1 bool "Siemens SX1" + select I2C depends on ARCH_OMAP1 && ARCH_OMAP15XX help Support for the Siemens SX1 phone. To boot the kernel, diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index 8141b76283a6..7f89697aa5c2 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -77,7 +77,7 @@ config SOC_OMAP3430 default y select ARCH_OMAP_OTG -config SOC_OMAPTI81XX +config SOC_TI81XX bool "TI81XX support" depends on ARCH_OMAP3 default y @@ -319,12 +319,12 @@ config MACH_OMAP_3630SDP config MACH_TI8168EVM bool "TI8168 Evaluation Module" - depends on SOC_OMAPTI81XX + depends on SOC_TI81XX default y config MACH_TI8148EVM bool "TI8148 Evaluation Module" - depends on SOC_OMAPTI81XX + depends on SOC_TI81XX default y config MACH_OMAP_4430SDP diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index 7cdb9401ffa1..49f92bc1c311 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -24,11 +24,10 @@ endif obj-$(CONFIG_TWL4030_CORE) += omap_twl.o # SMP support ONLY available for OMAP4 - obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o +obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o \ + sleep44xx.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -65,10 +64,10 @@ endif ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o -obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o -obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \ + cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o \ + cpuidle44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o @@ -85,86 +84,88 @@ endif # PRCM obj-y += prm_common.o obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o -obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o -obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o +obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \ + vc3xxx_data.o vp3xxx_data.o +# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and +# will be removed once the OMAP4 part of the codebase is converted to +# use OMAP4-specific PRCM functions. +obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \ + cm44xx.o prcm_mpu44xx.o \ + prminst44xx.o vc44xx_data.o \ + vp44xx_data.o prm44xx.o # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o -obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) -obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) -obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) -obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o +obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \ + voltagedomains2xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \ + voltagedomains3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \ + voltagedomains44xx_data.o # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o -obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) -obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o -obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) -obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) -obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o -obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o +obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) \ + powerdomain2xxx_3xxx.o \ + powerdomains2xxx_data.o \ + powerdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) \ + powerdomain2xxx_3xxx.o \ + powerdomains3xxx_data.o \ + powerdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \ + powerdomain44xx.o \ + powerdomains44xx_data.o # PRCM clockdomain control -clockdomain-common += clockdomain.o -clockdomain-common += clockdomains_common_data.o -obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) -obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ + clockdomain2xxx_3xxx.o \ + clockdomains2xxx_3xxx_data.o obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) -obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) -obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o -obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o +obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ + clockdomain2xxx_3xxx.o \ + clockdomains2xxx_3xxx_data.o \ + clockdomains3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ + clockdomain44xx.o \ + clockdomains44xx_data.o # Clock framework -obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o +obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ + clkt2xxx_sys.o \ + clkt2xxx_dpllcore.o \ + clkt2xxx_virt_prcm_set.o \ + clkt2xxx_apll.o clkt2xxx_osc.o \ + clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o -obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o -obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ + clock34xx.o clkt34xx_dpll3m2.o \ + clock3517.o clock36xx.o \ + dpll3xxx.o clock3xxx_data.o \ + clkt_iclk.o +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ + dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_interconnect_data.o -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_interconnect_data.o -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o -obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o -obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o +obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \ + omap_hwmod_2xxx_3xxx_ipblock_data.o \ + omap_hwmod_2xxx_interconnect_data.o \ + omap_hwmod_2xxx_3xxx_interconnect_data.o \ + omap_hwmod_2420_data.o +obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \ + omap_hwmod_2xxx_3xxx_ipblock_data.o \ + omap_hwmod_2xxx_interconnect_data.o \ + omap_hwmod_2xxx_3xxx_interconnect_data.o \ + omap_hwmod_2430_data.o +obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \ + omap_hwmod_2xxx_3xxx_interconnect_data.o \ + omap_hwmod_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals @@ -202,19 +203,23 @@ obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o -obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o sdram-nokia.o -obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o -obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o -obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o -obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o board-zoom-peripherals.o -obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom-display.o -obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom-debugboard.o -obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o board-zoom-peripherals.o -obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom-display.o -obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom-debugboard.o -obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o -obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-peripherals.o -obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o +obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \ + sdram-nokia.o +obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ + sdram-nokia.o \ + board-rx51-peripherals.o \ + board-rx51-video.o +obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \ + board-zoom-peripherals.o \ + board-zoom-display.o \ + board-zoom-debugboard.o +obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \ + board-zoom-peripherals.o \ + board-zoom-display.o \ + board-zoom-debugboard.o +obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ + board-zoom-peripherals.o \ + board-zoom-display.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o diff --git a/trunk/arch/arm/mach-omap2/board-4430sdp.c b/trunk/arch/arm/mach-omap2/board-4430sdp.c index 130ab00c09a2..6dc184841892 100644 --- a/trunk/arch/arm/mach-omap2/board-4430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-4430sdp.c @@ -489,50 +489,6 @@ static struct platform_device omap_vwlan_device = { }, }; -static int omap4_twl6030_hsmmc_late_init(struct device *dev) -{ - int irq = 0; - struct platform_device *pdev = container_of(dev, - struct platform_device, dev); - struct omap_mmc_platform_data *pdata = dev->platform_data; - - /* Setting MMC1 Card detect Irq */ - if (pdev->id == 0) { - irq = twl6030_mmc_card_detect_config(); - if (irq < 0) { - pr_err("Failed configuring MMC1 card detect\n"); - return irq; - } - pdata->slots[0].card_detect_irq = irq; - pdata->slots[0].card_detect = twl6030_mmc_card_detect; - } - return 0; -} - -static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) -{ - struct omap_mmc_platform_data *pdata; - - /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ - if (!dev) { - pr_err("Failed %s\n", __func__); - return; - } - pdata = dev->platform_data; - pdata->init = omap4_twl6030_hsmmc_late_init; -} - -static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) -{ - struct omap2_hsmmc_info *c; - - omap_hsmmc_init(controllers); - for (c = controllers; c->mmc; c++) - omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev); - - return 0; -} - static struct regulator_init_data sdp4430_vaux1 = { .constraints = { .min_uV = 1000000, diff --git a/trunk/arch/arm/mach-omap2/board-igep0020.c b/trunk/arch/arm/mach-omap2/board-igep0020.c index 930c0d380435..8f67861405bc 100644 --- a/trunk/arch/arm/mach-omap2/board-igep0020.c +++ b/trunk/arch/arm/mach-omap2/board-igep0020.c @@ -540,7 +540,10 @@ static void __init igep_i2c_init(void) { int ret; - omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0); + omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, + TWL_COMMON_REGULATOR_VPLL2); + igep_twldata.vpll2->constraints.apply_uV = true; + igep_twldata.vpll2->constraints.name = "VDVI"; if (machine_is_igep0020()) { /* @@ -554,10 +557,7 @@ static void __init igep_i2c_init(void) igep_twldata.keypad = &igep2_keypad_pdata; /* Get common pmic data */ - omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, - TWL_COMMON_REGULATOR_VPLL2); - igep_twldata.vpll2->constraints.apply_uV = true; - igep_twldata.vpll2->constraints.name = "VDVI"; + omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0); } omap3_pmic_init("twl4030", &igep_twldata); diff --git a/trunk/arch/arm/mach-omap2/board-omap4panda.c b/trunk/arch/arm/mach-omap2/board-omap4panda.c index 1b782ba53433..d53b07345f0b 100644 --- a/trunk/arch/arm/mach-omap2/board-omap4panda.c +++ b/trunk/arch/arm/mach-omap2/board-omap4panda.c @@ -231,60 +231,11 @@ static struct platform_device omap_vwlan_device = { }, }; -struct wl12xx_platform_data omap_panda_wlan_data __initdata = { +static struct wl12xx_platform_data omap_panda_wlan_data __initdata = { /* PANDA ref clock is 38.4 MHz */ .board_ref_clock = 2, }; -static int omap4_twl6030_hsmmc_late_init(struct device *dev) -{ - int irq = 0; - struct platform_device *pdev = container_of(dev, - struct platform_device, dev); - struct omap_mmc_platform_data *pdata = dev->platform_data; - - if (!pdata) { - dev_err(dev, "%s: NULL platform data\n", __func__); - return -EINVAL; - } - /* Setting MMC1 Card detect Irq */ - if (pdev->id == 0) { - irq = twl6030_mmc_card_detect_config(); - if (irq < 0) { - dev_err(dev, "%s: Error card detect config(%d)\n", - __func__, irq); - return irq; - } - pdata->slots[0].card_detect = twl6030_mmc_card_detect; - } - return 0; -} - -static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) -{ - struct omap_mmc_platform_data *pdata; - - /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ - if (!dev) { - pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n"); - return; - } - pdata = dev->platform_data; - - pdata->init = omap4_twl6030_hsmmc_late_init; -} - -static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) -{ - struct omap2_hsmmc_info *c; - - omap_hsmmc_init(controllers); - for (c = controllers; c->mmc; c++) - omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev); - - return 0; -} - static struct twl6040_codec_data twl6040_codec = { /* single-step ramp for headset and handsfree */ .hs_left_step = 0x0f, @@ -438,7 +389,7 @@ static struct panel_dvi_platform_data omap4_dvi_panel = { .i2c_bus_num = 3, }; -struct omap_dss_device omap4_panda_dvi_device = { +static struct omap_dss_device omap4_panda_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", .driver_name = "dvi", @@ -448,7 +399,7 @@ struct omap_dss_device omap4_panda_dvi_device = { .channel = OMAP_DSS_CHANNEL_LCD2, }; -int __init omap4_panda_dvi_init(void) +static int __init omap4_panda_dvi_init(void) { int r; @@ -509,7 +460,7 @@ static struct omap_dss_board_info omap4_panda_dss_data = { .default_device = &omap4_panda_dvi_device, }; -void __init omap4_panda_display_init(void) +static void __init omap4_panda_display_init(void) { int r; diff --git a/trunk/arch/arm/mach-omap2/clockdomain44xx.c b/trunk/arch/arm/mach-omap2/clockdomain44xx.c index 4f04dd11d655..935c7f03dab9 100644 --- a/trunk/arch/arm/mach-omap2/clockdomain44xx.c +++ b/trunk/arch/arm/mach-omap2/clockdomain44xx.c @@ -51,9 +51,6 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) struct clkdm_dep *cd; u32 mask = 0; - if (!clkdm->prcm_partition) - return 0; - for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { if (!cd->clkdm) continue; /* only happens if data is erroneous */ @@ -106,9 +103,6 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) { bool hwsup = false; - if (!clkdm->prcm_partition) - return 0; - hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, clkdm->cm_inst, clkdm->clkdm_offs); diff --git a/trunk/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/trunk/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 839145e1cfbe..0a6a04897d89 100644 --- a/trunk/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -89,3 +89,13 @@ struct clockdomain wkup_common_clkdm = { .pwrdm = { .name = "wkup_pwrdm" }, .dep_bit = OMAP_EN_WKUP_SHIFT, }; + +struct clockdomain prm_common_clkdm = { + .name = "prm_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, +}; + +struct clockdomain cm_common_clkdm = { + .name = "cm_clkdm", + .pwrdm = { .name = "core_pwrdm" }, +}; diff --git a/trunk/arch/arm/mach-omap2/clockdomains44xx_data.c b/trunk/arch/arm/mach-omap2/clockdomains44xx_data.c index c53425847493..bd7ed13515cc 100644 --- a/trunk/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/trunk/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -430,8 +430,6 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { &l4_wkup_44xx_clkdm, &emu_sys_44xx_clkdm, &l3_dma_44xx_clkdm, - &prm_common_clkdm, - &cm_common_clkdm, NULL }; diff --git a/trunk/arch/arm/mach-omap2/clockdomains_common_data.c b/trunk/arch/arm/mach-omap2/clockdomains_common_data.c deleted file mode 100644 index 615b1f04967d..000000000000 --- a/trunk/arch/arm/mach-omap2/clockdomains_common_data.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * OMAP2+-common clockdomain data - * - * Copyright (C) 2008-2012 Texas Instruments, Inc. - * Copyright (C) 2008-2010 Nokia Corporation - * - * Paul Walmsley, Jouni Högander - */ - -#include -#include - -#include "clockdomain.h" - -/* These are implicit clockdomains - they are never defined as such in TRM */ -struct clockdomain prm_common_clkdm = { - .name = "prm_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, -}; - -struct clockdomain cm_common_clkdm = { - .name = "cm_clkdm", - .pwrdm = { .name = "core_pwrdm" }, -}; diff --git a/trunk/arch/arm/mach-omap2/common.h b/trunk/arch/arm/mach-omap2/common.h index 57da7f406e28..f6be402611b0 100644 --- a/trunk/arch/arm/mach-omap2/common.h +++ b/trunk/arch/arm/mach-omap2/common.h @@ -27,6 +27,7 @@ #ifndef __ASSEMBLER__ #include +#include #include #include @@ -54,7 +55,7 @@ static inline void omap34xx_map_common_io(void) } #endif -#ifdef CONFIG_SOC_OMAPTI81XX +#ifdef CONFIG_SOC_TI81XX extern void omapti81xx_map_common_io(void); #else static inline void omapti81xx_map_common_io(void) @@ -254,6 +255,8 @@ static inline u32 omap4_mpuss_read_prev_context_state(void) struct omap_sdrc_params; extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1); +struct omap2_hsmmc_info; +extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers); #endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ diff --git a/trunk/arch/arm/mach-omap2/dma.c b/trunk/arch/arm/mach-omap2/dma.c index ff75abe60af2..b19d8496c16e 100644 --- a/trunk/arch/arm/mach-omap2/dma.c +++ b/trunk/arch/arm/mach-omap2/dma.c @@ -227,6 +227,10 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) dma_stride = OMAP2_DMA_STRIDE; dma_common_ch_start = CSDP; + if (cpu_is_omap3630() || cpu_is_omap44xx()) + dma_common_ch_end = CCDN; + else + dma_common_ch_end = CCFN; p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); if (!p) { @@ -273,13 +277,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__); return -ENOMEM; } - - /* Check the capabilities register for descriptor loading feature */ - if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) - dma_common_ch_end = CCDN; - else - dma_common_ch_end = CCFN; - return 0; } diff --git a/trunk/arch/arm/mach-omap2/dsp.c b/trunk/arch/arm/mach-omap2/dsp.c index 74f18f2952df..3376388b317a 100644 --- a/trunk/arch/arm/mach-omap2/dsp.c +++ b/trunk/arch/arm/mach-omap2/dsp.c @@ -57,8 +57,9 @@ static int __init omap_dsp_init(void) if (pdata->phys_mempool_base) { pdata->phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE; - pr_info("%s: %x bytes @ %x\n", __func__, - pdata->phys_mempool_size, pdata->phys_mempool_base); + pr_info("%s: %llx bytes @ %llx\n", __func__, + (unsigned long long)pdata->phys_mempool_size, + (unsigned long long)pdata->phys_mempool_base); } pdev = platform_device_alloc("omap-dsp", -1); diff --git a/trunk/arch/arm/mach-omap2/gpmc.c b/trunk/arch/arm/mach-omap2/gpmc.c index 212018d4e320..00d510858e28 100644 --- a/trunk/arch/arm/mach-omap2/gpmc.c +++ b/trunk/arch/arm/mach-omap2/gpmc.c @@ -50,19 +50,6 @@ #define GPMC_ECC_SIZE_CONFIG 0x1fc #define GPMC_ECC1_RESULT 0x200 -/* GPMC ECC control settings */ -#define GPMC_ECC_CTRL_ECCCLEAR 0x100 -#define GPMC_ECC_CTRL_ECCDISABLE 0x000 -#define GPMC_ECC_CTRL_ECCREG1 0x001 -#define GPMC_ECC_CTRL_ECCREG2 0x002 -#define GPMC_ECC_CTRL_ECCREG3 0x003 -#define GPMC_ECC_CTRL_ECCREG4 0x004 -#define GPMC_ECC_CTRL_ECCREG5 0x005 -#define GPMC_ECC_CTRL_ECCREG6 0x006 -#define GPMC_ECC_CTRL_ECCREG7 0x007 -#define GPMC_ECC_CTRL_ECCREG8 0x008 -#define GPMC_ECC_CTRL_ECCREG9 0x009 - #define GPMC_CS0_OFFSET 0x60 #define GPMC_CS_SIZE 0x30 @@ -874,9 +861,8 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) gpmc_ecc_used = cs; /* clear ecc and enable bits */ - gpmc_write_reg(GPMC_ECC_CONTROL, - GPMC_ECC_CTRL_ECCCLEAR | - GPMC_ECC_CTRL_ECCREG1); + val = ((0x00000001<<8) | 0x00000001); + gpmc_write_reg(GPMC_ECC_CONTROL, val); /* program ecc and result sizes */ val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); @@ -884,15 +870,13 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) switch (mode) { case GPMC_ECC_READ: - case GPMC_ECC_WRITE: - gpmc_write_reg(GPMC_ECC_CONTROL, - GPMC_ECC_CTRL_ECCCLEAR | - GPMC_ECC_CTRL_ECCREG1); + gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); break; case GPMC_ECC_READSYN: - gpmc_write_reg(GPMC_ECC_CONTROL, - GPMC_ECC_CTRL_ECCCLEAR | - GPMC_ECC_CTRL_ECCDISABLE); + gpmc_write_reg(GPMC_ECC_CONTROL, 0x100); + break; + case GPMC_ECC_WRITE: + gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); break; default: printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); diff --git a/trunk/arch/arm/mach-omap2/hsmmc.c b/trunk/arch/arm/mach-omap2/hsmmc.c index be697d4e0843..b0268eaffe13 100644 --- a/trunk/arch/arm/mach-omap2/hsmmc.c +++ b/trunk/arch/arm/mach-omap2/hsmmc.c @@ -355,7 +355,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, * * temporary HACK: ocr_mask instead of fixed supply */ - if (soc_is_am35xx()) + if (cpu_is_omap3505() || cpu_is_omap3517()) mmc->slots[0].ocr_mask = MMC_VDD_165_195 | MMC_VDD_26_27 | MMC_VDD_27_28 | @@ -365,7 +365,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, else mmc->slots[0].ocr_mask = c->ocr_mask; - if (!soc_is_am35xx()) + if (!cpu_is_omap3517() && !cpu_is_omap3505()) mmc->slots[0].features |= HSMMC_HAS_PBIAS; if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) @@ -388,7 +388,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, } } - if (soc_is_am35xx()) + if (cpu_is_omap3517() || cpu_is_omap3505()) mmc->slots[0].set_power = nop_mmc_set_power; /* OMAP3630 HSMMC1 supports only 4-bit */ @@ -400,7 +400,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, } break; case 2: - if (soc_is_am35xx()) + if (cpu_is_omap3517() || cpu_is_omap3505()) mmc->slots[0].set_power = am35x_hsmmc2_set_power; if (c->ext_clock) diff --git a/trunk/arch/arm/mach-omap2/id.c b/trunk/arch/arm/mach-omap2/id.c index f611e3097157..f1398171d8a2 100644 --- a/trunk/arch/arm/mach-omap2/id.c +++ b/trunk/arch/arm/mach-omap2/id.c @@ -185,7 +185,8 @@ static void __init omap3_cpuinfo(void) */ if (cpu_is_omap3630()) { cpu_name = "OMAP3630"; - } else if (soc_is_am35xx()) { + } else if (cpu_is_omap3517()) { + /* AM35xx devices */ cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; } else if (cpu_is_ti816x()) { cpu_name = "TI816X"; @@ -351,13 +352,13 @@ void __init omap3xxx_check_revision(void) */ switch (rev) { case 0: - omap_revision = AM35XX_REV_ES1_0; + omap_revision = OMAP3517_REV_ES1_0; cpu_rev = "1.0"; break; case 1: /* FALLTHROUGH */ default: - omap_revision = AM35XX_REV_ES1_1; + omap_revision = OMAP3517_REV_ES1_1; cpu_rev = "1.1"; } break; @@ -477,9 +478,12 @@ void __init omap4xxx_check_revision(void) case 0xb94e: switch (rev) { case 0: - default: omap_revision = OMAP4460_REV_ES1_0; break; + case 2: + default: + omap_revision = OMAP4460_REV_ES1_1; + break; } break; case 0xb975: diff --git a/trunk/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/trunk/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h index 548de90b58c2..d79321b0f2a2 100644 --- a/trunk/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +++ b/trunk/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h @@ -16,10 +16,18 @@ #define OMAP_WKG_ENB_B_0 0x14 #define OMAP_WKG_ENB_C_0 0x18 #define OMAP_WKG_ENB_D_0 0x1c +#define OMAP_WKG_ENB_SECURE_A_0 0x20 +#define OMAP_WKG_ENB_SECURE_B_0 0x24 +#define OMAP_WKG_ENB_SECURE_C_0 0x28 +#define OMAP_WKG_ENB_SECURE_D_0 0x2c #define OMAP_WKG_ENB_A_1 0x410 #define OMAP_WKG_ENB_B_1 0x414 #define OMAP_WKG_ENB_C_1 0x418 #define OMAP_WKG_ENB_D_1 0x41c +#define OMAP_WKG_ENB_SECURE_A_1 0x420 +#define OMAP_WKG_ENB_SECURE_B_1 0x424 +#define OMAP_WKG_ENB_SECURE_C_1 0x428 +#define OMAP_WKG_ENB_SECURE_D_1 0x42c #define OMAP_AUX_CORE_BOOT_0 0x800 #define OMAP_AUX_CORE_BOOT_1 0x804 #define OMAP_PTMSYNCREQ_MASK 0xc00 diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index 595a5ddcad4b..646a1cd335d3 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -172,7 +172,7 @@ static struct map_desc omap34xx_io_desc[] __initdata = { }; #endif -#ifdef CONFIG_SOC_OMAPTI81XX +#ifdef CONFIG_SOC_TI81XX static struct map_desc omapti81xx_io_desc[] __initdata = { { .virtual = L4_34XX_VIRT, @@ -214,12 +214,42 @@ static struct map_desc omap44xx_io_desc[] __initdata = { .length = L4_44XX_SIZE, .type = MT_DEVICE, }, + { + .virtual = OMAP44XX_GPMC_VIRT, + .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), + .length = OMAP44XX_GPMC_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = OMAP44XX_EMIF1_VIRT, + .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS), + .length = OMAP44XX_EMIF1_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = OMAP44XX_EMIF2_VIRT, + .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS), + .length = OMAP44XX_EMIF2_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = OMAP44XX_DMM_VIRT, + .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS), + .length = OMAP44XX_DMM_SIZE, + .type = MT_DEVICE, + }, { .virtual = L4_PER_44XX_VIRT, .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), .length = L4_PER_44XX_SIZE, .type = MT_DEVICE, }, + { + .virtual = L4_EMU_44XX_VIRT, + .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS), + .length = L4_EMU_44XX_SIZE, + .type = MT_DEVICE, + }, #ifdef CONFIG_OMAP4_ERRATA_I688 { .virtual = OMAP4_SRAM_VA, @@ -255,7 +285,7 @@ void __init omap34xx_map_common_io(void) } #endif -#ifdef CONFIG_SOC_OMAPTI81XX +#ifdef CONFIG_SOC_TI81XX void __init omapti81xx_map_common_io(void) { iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); diff --git a/trunk/arch/arm/mach-omap2/iomap.h b/trunk/arch/arm/mach-omap2/iomap.h index 80b88921faba..0812b154f5b5 100644 --- a/trunk/arch/arm/mach-omap2/iomap.h +++ b/trunk/arch/arm/mach-omap2/iomap.h @@ -37,6 +37,9 @@ #define OMAP4_L3_PER_IO_OFFSET 0xb1100000 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) +#define OMAP4_GPMC_IO_OFFSET 0xa9000000 +#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) + #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) @@ -167,3 +170,28 @@ #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) #define L4_ABE_44XX_SIZE SZ_1M +#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE + /* 0x54000000 --> 0xfe800000 */ +#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) +#define L4_EMU_44XX_SIZE SZ_8M + +#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE + /* 0x50000000 --> 0xf9000000 */ +#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET) +#define OMAP44XX_GPMC_SIZE SZ_1M + + +#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE + /* 0x4c000000 --> 0xfd100000 */ +#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET) +#define OMAP44XX_EMIF1_SIZE SZ_1M + +#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE + /* 0x4d000000 --> 0xfd200000 */ +#define OMAP44XX_EMIF2_SIZE SZ_1M +#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE) + +#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE + /* 0x4e000000 --> 0xfd300000 */ +#define OMAP44XX_DMM_SIZE SZ_1M +#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE) diff --git a/trunk/arch/arm/mach-omap2/irq.c b/trunk/arch/arm/mach-omap2/irq.c index 65f0d2571c9a..12949dd3c156 100644 --- a/trunk/arch/arm/mach-omap2/irq.c +++ b/trunk/arch/arm/mach-omap2/irq.c @@ -149,7 +149,6 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; - ct->regs.ack = INTC_CONTROL; ct->regs.enable = INTC_MIR_CLEAR0; ct->regs.disable = INTC_MIR_SET0; irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, @@ -231,7 +230,7 @@ static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs goto out; irqnr = readl_relaxed(base_addr + 0xd8); -#ifdef CONFIG_SOC_OMAPTI816X +#ifdef CONFIG_SOC_TI81XX if (irqnr) goto out; irqnr = readl_relaxed(base_addr + 0xf8); diff --git a/trunk/arch/arm/mach-omap2/mailbox.c b/trunk/arch/arm/mach-omap2/mailbox.c index 415a6f1cf419..19b8b6774862 100644 --- a/trunk/arch/arm/mach-omap2/mailbox.c +++ b/trunk/arch/arm/mach-omap2/mailbox.c @@ -26,9 +26,9 @@ #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) -#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u)) -#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u)) -#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u)) +#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u)) +#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u)) +#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u)) #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) diff --git a/trunk/arch/arm/mach-omap2/omap4-common.c b/trunk/arch/arm/mach-omap2/omap4-common.c index 70de277f5c15..a8161e5f3204 100644 --- a/trunk/arch/arm/mach-omap2/omap4-common.c +++ b/trunk/arch/arm/mach-omap2/omap4-common.c @@ -25,11 +25,13 @@ #include #include #include +#include #include #include #include "common.h" +#include "hsmmc.h" #include "omap4-sar-layout.h" #include @@ -207,3 +209,59 @@ static int __init omap4_sar_ram_init(void) return 0; } early_initcall(omap4_sar_ram_init); + +#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) +static int omap4_twl6030_hsmmc_late_init(struct device *dev) +{ + int irq = 0; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_mmc_platform_data *pdata = dev->platform_data; + + /* Setting MMC1 Card detect Irq */ + if (pdev->id == 0) { + irq = twl6030_mmc_card_detect_config(); + if (irq < 0) { + dev_err(dev, "%s: Error card detect config(%d)\n", + __func__, irq); + return irq; + } + pdata->slots[0].card_detect_irq = irq; + pdata->slots[0].card_detect = twl6030_mmc_card_detect; + } + return 0; +} + +static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) +{ + struct omap_mmc_platform_data *pdata; + + /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ + if (!dev) { + pr_err("Failed %s\n", __func__); + return; + } + pdata = dev->platform_data; + pdata->init = omap4_twl6030_hsmmc_late_init; +} + +int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + struct omap2_hsmmc_info *c; + + omap_hsmmc_init(controllers); + for (c = controllers; c->mmc; c++) { + /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */ + if (!c->pdev) + continue; + omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev); + } + + return 0; +} +#else +int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + return 0; +} +#endif diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index bf86f7e8f91f..7144ae651d3d 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -2,7 +2,7 @@ * omap_hwmod implementation for OMAP2/3/4 * * Copyright (C) 2009-2011 Nokia Corporation - * Copyright (C) 2011-2012 Texas Instruments, Inc. + * Copyright (C) 2011 Texas Instruments, Inc. * * Paul Walmsley, Benoît Cousson, Kevin Hilman * @@ -137,7 +137,6 @@ #include #include #include -#include #include "common.h" #include @@ -160,57 +159,15 @@ /* Name of the OMAP hwmod for the MPU */ #define MPU_INITIATOR_NAME "mpu" -/* - * Number of struct omap_hwmod_link records per struct - * omap_hwmod_ocp_if record (master->slave and slave->master) - */ -#define LINKS_PER_OCP_IF 2 - /* omap_hwmod_list contains all registered struct omap_hwmods */ static LIST_HEAD(omap_hwmod_list); /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ static struct omap_hwmod *mpu_oh; -/* - * linkspace: ptr to a buffer that struct omap_hwmod_link records are - * allocated from - used to reduce the number of small memory - * allocations, which has a significant impact on performance - */ -static struct omap_hwmod_link *linkspace; - -/* - * free_ls, max_ls: array indexes into linkspace; representing the - * next free struct omap_hwmod_link index, and the maximum number of - * struct omap_hwmod_link records allocated (respectively) - */ -static unsigned short free_ls, max_ls, ls_supp; /* Private functions */ -/** - * _fetch_next_ocp_if - return the next OCP interface in a list - * @p: ptr to a ptr to the list_head inside the ocp_if to return - * @i: pointer to the index of the element pointed to by @p in the list - * - * Return a pointer to the struct omap_hwmod_ocp_if record - * containing the struct list_head pointed to by @p, and increment - * @p such that a future call to this routine will return the next - * record. - */ -static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, - int *i) -{ - struct omap_hwmod_ocp_if *oi; - - oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; - *p = (*p)->next; - - *i = *i + 1; - - return oi; -} - /** * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy * @oh: struct omap_hwmod * @@ -625,16 +582,16 @@ static int _init_main_clk(struct omap_hwmod *oh) */ static int _init_interface_clks(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; - struct list_head *p; struct clk *c; - int i = 0; + int i; int ret = 0; - p = oh->slave_ports.next; + if (oh->slaves_cnt == 0) + return 0; + + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; - while (i < oh->slaves_cnt) { - os = _fetch_next_ocp_if(&p, &i); if (!os->clk) continue; @@ -686,22 +643,21 @@ static int _init_opt_clks(struct omap_hwmod *oh) */ static int _enable_clocks(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; - struct list_head *p; - int i = 0; + int i; pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); if (oh->_clk) clk_enable(oh->_clk); - p = oh->slave_ports.next; - - while (i < oh->slaves_cnt) { - os = _fetch_next_ocp_if(&p, &i); + if (oh->slaves_cnt > 0) { + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; + struct clk *c = os->_clk; - if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_enable(os->_clk); + if (c && (os->flags & OCPIF_SWSUP_IDLE)) + clk_enable(c); + } } /* The opt clocks are controlled by the device driver. */ @@ -717,22 +673,21 @@ static int _enable_clocks(struct omap_hwmod *oh) */ static int _disable_clocks(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; - struct list_head *p; - int i = 0; + int i; pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); if (oh->_clk) clk_disable(oh->_clk); - p = oh->slave_ports.next; - - while (i < oh->slaves_cnt) { - os = _fetch_next_ocp_if(&p, &i); + if (oh->slaves_cnt > 0) { + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; + struct clk *c = os->_clk; - if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_disable(os->_clk); + if (c && (os->flags & OCPIF_SWSUP_IDLE)) + clk_disable(c); + } } /* The opt clocks are controlled by the device driver. */ @@ -825,6 +780,39 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh) oh->prcm.omap4.clkctrl_offs); } +/** + * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 + * @oh: struct omap_hwmod * + * + * Disable the PRCM module mode related to the hwmod @oh. + * Return EINVAL if the modulemode is not supported and 0 in case of success. + */ +static int _omap4_disable_module(struct omap_hwmod *oh) +{ + int v; + + /* The module mode does not exist prior OMAP4 */ + if (!cpu_is_omap44xx()) + return -EINVAL; + + if (!oh->clkdm || !oh->prcm.omap4.modulemode) + return -EINVAL; + + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); + + omap4_cminst_module_disable(oh->clkdm->prcm_partition, + oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); + + v = _omap4_wait_target_disable(oh); + if (v) + pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", + oh->name); + + return 0; +} + /** * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh * @oh: struct omap_hwmod *oh @@ -895,220 +883,59 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) } /** - * _get_mpu_irq_by_name - fetch MPU interrupt line number by name - * @oh: struct omap_hwmod * to operate on - * @name: pointer to the name of the MPU interrupt number to fetch (optional) - * @irq: pointer to an unsigned int to store the MPU IRQ number to + * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use + * @oh: struct omap_hwmod * * - * Retrieve a MPU hardware IRQ line number named by @name associated - * with the IP block pointed to by @oh. The IRQ number will be filled - * into the address pointed to by @dma. When @name is non-null, the - * IRQ line number associated with the named entry will be returned. - * If @name is null, the first matching entry will be returned. Data - * order is not meaningful in hwmod data, so callers are strongly - * encouraged to use a non-null @name whenever possible to avoid - * unpredictable effects if hwmod data is later added that causes data - * ordering to change. Returns 0 upon success or a negative error - * code upon error. + * Returns the array index of the OCP slave port that the MPU + * addresses the device on, or -EINVAL upon error or not found. */ -static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, - unsigned int *irq) +static int __init _find_mpu_port_index(struct omap_hwmod *oh) { int i; - bool found = false; - - if (!oh->mpu_irqs) - return -ENOENT; - - i = 0; - while (oh->mpu_irqs[i].irq != -1) { - if (name == oh->mpu_irqs[i].name || - !strcmp(name, oh->mpu_irqs[i].name)) { - found = true; - break; - } - i++; - } - - if (!found) - return -ENOENT; + int found = 0; - *irq = oh->mpu_irqs[i].irq; - - return 0; -} - -/** - * _get_sdma_req_by_name - fetch SDMA request line ID by name - * @oh: struct omap_hwmod * to operate on - * @name: pointer to the name of the SDMA request line to fetch (optional) - * @dma: pointer to an unsigned int to store the request line ID to - * - * Retrieve an SDMA request line ID named by @name on the IP block - * pointed to by @oh. The ID will be filled into the address pointed - * to by @dma. When @name is non-null, the request line ID associated - * with the named entry will be returned. If @name is null, the first - * matching entry will be returned. Data order is not meaningful in - * hwmod data, so callers are strongly encouraged to use a non-null - * @name whenever possible to avoid unpredictable effects if hwmod - * data is later added that causes data ordering to change. Returns 0 - * upon success or a negative error code upon error. - */ -static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, - unsigned int *dma) -{ - int i; - bool found = false; + if (!oh || oh->slaves_cnt == 0) + return -EINVAL; - if (!oh->sdma_reqs) - return -ENOENT; + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; - i = 0; - while (oh->sdma_reqs[i].dma_req != -1) { - if (name == oh->sdma_reqs[i].name || - !strcmp(name, oh->sdma_reqs[i].name)) { - found = true; + if (os->user & OCP_USER_MPU) { + found = 1; break; } - i++; - } - - if (!found) - return -ENOENT; - - *dma = oh->sdma_reqs[i].dma_req; - - return 0; -} - -/** - * _get_addr_space_by_name - fetch address space start & end by name - * @oh: struct omap_hwmod * to operate on - * @name: pointer to the name of the address space to fetch (optional) - * @pa_start: pointer to a u32 to store the starting address to - * @pa_end: pointer to a u32 to store the ending address to - * - * Retrieve address space start and end addresses for the IP block - * pointed to by @oh. The data will be filled into the addresses - * pointed to by @pa_start and @pa_end. When @name is non-null, the - * address space data associated with the named entry will be - * returned. If @name is null, the first matching entry will be - * returned. Data order is not meaningful in hwmod data, so callers - * are strongly encouraged to use a non-null @name whenever possible - * to avoid unpredictable effects if hwmod data is later added that - * causes data ordering to change. Returns 0 upon success or a - * negative error code upon error. - */ -static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, - u32 *pa_start, u32 *pa_end) -{ - int i, j; - struct omap_hwmod_ocp_if *os; - struct list_head *p = NULL; - bool found = false; - - p = oh->slave_ports.next; - - i = 0; - while (i < oh->slaves_cnt) { - os = _fetch_next_ocp_if(&p, &i); - - if (!os->addr) - return -ENOENT; - - j = 0; - while (os->addr[j].pa_start != os->addr[j].pa_end) { - if (name == os->addr[j].name || - !strcmp(name, os->addr[j].name)) { - found = true; - break; - } - j++; - } - - if (found) - break; } - if (!found) - return -ENOENT; - - *pa_start = os->addr[j].pa_start; - *pa_end = os->addr[j].pa_end; + if (found) + pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", + oh->name, i); + else + pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", + oh->name); - return 0; + return (found) ? i : -EINVAL; } /** - * _save_mpu_port_index - find and save the index to @oh's MPU port + * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU * @oh: struct omap_hwmod * * - * Determines the array index of the OCP slave port that the MPU uses - * to address the device, and saves it into the struct omap_hwmod. - * Intended to be called during hwmod registration only. No return - * value. + * Return the virtual address of the base of the register target of + * device @oh, or NULL on error. */ -static void __init _save_mpu_port_index(struct omap_hwmod *oh) +static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) { - struct omap_hwmod_ocp_if *os = NULL; - struct list_head *p; - int i = 0; - - if (!oh) - return; - - oh->_int_flags |= _HWMOD_NO_MPU_PORT; - - p = oh->slave_ports.next; - - while (i < oh->slaves_cnt) { - os = _fetch_next_ocp_if(&p, &i); - if (os->user & OCP_USER_MPU) { - oh->_mpu_port = os; - oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; - break; - } - } - - return; -} + struct omap_hwmod_ocp_if *os; + struct omap_hwmod_addr_space *mem; + int i = 0, found = 0; + void __iomem *va_start; -/** - * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU - * @oh: struct omap_hwmod * - * - * Given a pointer to a struct omap_hwmod record @oh, return a pointer - * to the struct omap_hwmod_ocp_if record that is used by the MPU to - * communicate with the IP block. This interface need not be directly - * connected to the MPU (and almost certainly is not), but is directly - * connected to the IP block represented by @oh. Returns a pointer - * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon - * error or if there does not appear to be a path from the MPU to this - * IP block. - */ -static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) -{ - if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) + if (!oh || oh->slaves_cnt == 0) return NULL; - return oh->_mpu_port; -}; - -/** - * _find_mpu_rt_addr_space - return MPU register target address space for @oh - * @oh: struct omap_hwmod * - * - * Returns a pointer to the struct omap_hwmod_addr_space record representing - * the register target MPU address space; or returns NULL upon error. - */ -static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) -{ - struct omap_hwmod_ocp_if *os; - struct omap_hwmod_addr_space *mem; - int found = 0, i = 0; + os = oh->slaves[index]; - os = _find_mpu_rt_port(oh); - if (!os || !os->addr) + if (!os->addr) return NULL; do { @@ -1117,7 +944,20 @@ static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap found = 1; } while (!found && mem->pa_start != mem->pa_end); - return (found) ? mem : NULL; + if (found) { + va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); + if (!va_start) { + pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); + return NULL; + } + pr_debug("omap_hwmod: %s: MPU register target at va %p\n", + oh->name, va_start); + } else { + pr_debug("omap_hwmod: %s: no MPU register target found\n", + oh->name); + } + + return (found) ? va_start : NULL; } /** @@ -1365,11 +1205,12 @@ static int _wait_target_ready(struct omap_hwmod *oh) if (!oh) return -EINVAL; - if (oh->flags & HWMOD_NO_IDLEST) + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) return 0; - os = _find_mpu_rt_port(oh); - if (!os) + os = oh->slaves[oh->_mpu_port_index]; + + if (oh->flags & HWMOD_NO_IDLEST) return 0; /* XXX check module SIDLEMODE */ @@ -1536,74 +1377,14 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) } } -/** - * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset - * @oh: struct omap_hwmod * - * - * If any hardreset line associated with @oh is asserted, then return true. - * Otherwise, if @oh has no hardreset lines associated with it, or if - * no hardreset lines associated with @oh are asserted, then return false. - * This function is used to avoid executing some parts of the IP block - * enable/disable sequence if a hardreset line is set. - */ -static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) -{ - int i; - - if (oh->rst_lines_cnt == 0) - return false; - - for (i = 0; i < oh->rst_lines_cnt; i++) - if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) - return true; - - return false; -} - -/** - * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 - * @oh: struct omap_hwmod * - * - * Disable the PRCM module mode related to the hwmod @oh. - * Return EINVAL if the modulemode is not supported and 0 in case of success. - */ -static int _omap4_disable_module(struct omap_hwmod *oh) -{ - int v; - - /* The module mode does not exist prior OMAP4 */ - if (!cpu_is_omap44xx()) - return -EINVAL; - - if (!oh->clkdm || !oh->prcm.omap4.modulemode) - return -EINVAL; - - pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); - - omap4_cminst_module_disable(oh->clkdm->prcm_partition, - oh->clkdm->cm_inst, - oh->clkdm->clkdm_offs, - oh->prcm.omap4.clkctrl_offs); - - if (_are_any_hardreset_lines_asserted(oh)) - return 0; - - v = _omap4_wait_target_disable(oh); - if (v) - pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", - oh->name); - - return 0; -} - /** * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit * @oh: struct omap_hwmod * * * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be - * enabled for this to work. Returns -ENOENT if the hwmod cannot be - * reset this way, -EINVAL if the hwmod is in the wrong state, - * -ETIMEDOUT if the module did not reset in time, or 0 upon success. + * enabled for this to work. Returns -EINVAL if the hwmod cannot be + * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if + * the module did not reset in time, or 0 upon success. * * In OMAP3 a specific SYSSTATUS register is used to get the reset status. * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead @@ -1620,7 +1401,7 @@ static int _ocp_softreset(struct omap_hwmod *oh) if (!oh->class->sysc || !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) - return -ENOENT; + return -EINVAL; /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { @@ -1681,60 +1462,32 @@ static int _ocp_softreset(struct omap_hwmod *oh) * _reset - reset an omap_hwmod * @oh: struct omap_hwmod * * - * Resets an omap_hwmod @oh. If the module has a custom reset - * function pointer defined, then call it to reset the IP block, and - * pass along its return value to the caller. Otherwise, if the IP - * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield - * associated with it, call a function to reset the IP block via that - * method, and pass along the return value to the caller. Finally, if - * the IP block has some hardreset lines associated with it, assert - * all of those, but do _not_ deassert them. (This is because driver - * authors have expressed an apparent requirement to control the - * deassertion of the hardreset lines themselves.) - * - * The default software reset mechanism for most OMAP IP blocks is - * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some - * hwmods cannot be reset via this method. Some are not targets and - * therefore have no OCP header registers to access. Others (like the - * IVA) have idiosyncratic reset sequences. So for these relatively - * rare cases, custom reset code can be supplied in the struct - * omap_hwmod_class .reset function pointer. Passes along the return - * value from either _ocp_softreset() or the custom reset function - - * these must return -EINVAL if the hwmod cannot be reset this way or - * if the hwmod is in the wrong state, -ETIMEDOUT if the module did - * not reset in time, or 0 upon success. + * Resets an omap_hwmod @oh. The default software reset mechanism for + * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET + * bit. However, some hwmods cannot be reset via this method: some + * are not targets and therefore have no OCP header registers to + * access; others (like the IVA) have idiosyncratic reset sequences. + * So for these relatively rare cases, custom reset code can be + * supplied in the struct omap_hwmod_class .reset function pointer. + * Passes along the return value from either _reset() or the custom + * reset function - these must return -EINVAL if the hwmod cannot be + * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if + * the module did not reset in time, or 0 upon success. */ static int _reset(struct omap_hwmod *oh) { - int i, r; + int ret; pr_debug("omap_hwmod: %s: resetting\n", oh->name); - if (oh->class->reset) { - r = oh->class->reset(oh); - } else { - if (oh->rst_lines_cnt > 0) { - for (i = 0; i < oh->rst_lines_cnt; i++) - _assert_hardreset(oh, oh->rst_lines[i].name); - return 0; - } else { - r = _ocp_softreset(oh); - if (r == -ENOENT) - r = 0; - } - } + ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); - /* - * OCP_SYSCONFIG bits need to be reprogrammed after a - * softreset. The _enable() function should be split to avoid - * the rewrite of the OCP_SYSCONFIG register. - */ if (oh->class->sysc) { _update_sysc_cache(oh); _enable_sysc(oh); } - return r; + return ret; } /** @@ -1753,9 +1506,10 @@ static int _enable(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling\n", oh->name); /* - * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled - * state at init. Now that someone is really trying to enable - * them, just ensure that the hwmod mux is set. + * hwmods with HWMOD_INIT_NO_IDLE flag set are left + * in enabled state at init. + * Now that someone is really trying to enable them, + * just ensure that the hwmod mux is set. */ if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { /* @@ -1778,17 +1532,15 @@ static int _enable(struct omap_hwmod *oh) return -EINVAL; } + /* - * If an IP block contains HW reset lines and any of them are - * asserted, we let integration code associated with that - * block handle the enable. We've received very little - * information on what those driver authors need, and until - * detailed information is provided and the driver code is - * posted to the public lists, this is probably the best we - * can do. + * If an IP contains only one HW reset line, then de-assert it in order + * to allow the module state transition. Otherwise the PRCM will return + * Intransition status, and the init will failed. */ - if (_are_any_hardreset_lines_asserted(oh)) - return 0; + if ((oh->_state == _HWMOD_STATE_INITIALIZED || + oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) + _deassert_hardreset(oh, oh->rst_lines[0].name); /* Mux pins for device runtime if populated */ if (oh->mux && (!oh->mux->enabled || @@ -1863,9 +1615,6 @@ static int _idle(struct omap_hwmod *oh) return -EINVAL; } - if (_are_any_hardreset_lines_asserted(oh)) - return 0; - if (oh->class->sysc) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); @@ -1938,7 +1687,7 @@ int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) */ static int _shutdown(struct omap_hwmod *oh) { - int ret, i; + int ret; u8 prev_state; if (oh->_state != _HWMOD_STATE_IDLE && @@ -1948,9 +1697,6 @@ static int _shutdown(struct omap_hwmod *oh) return -EINVAL; } - if (_are_any_hardreset_lines_asserted(oh)) - return 0; - pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->pre_shutdown) { @@ -1982,8 +1728,12 @@ static int _shutdown(struct omap_hwmod *oh) } /* XXX Should this code also force-disable the optional clocks? */ - for (i = 0; i < oh->rst_lines_cnt; i++) - _assert_hardreset(oh, oh->rst_lines[i].name); + /* + * If an IP contains only one HW reset line, then assert it + * after disabling the clocks and before shutting down the IP. + */ + if (oh->rst_lines_cnt == 1) + _assert_hardreset(oh, oh->rst_lines[0].name); /* Mux pins to safe mode or use populated off mode values */ if (oh->mux) @@ -1995,186 +1745,59 @@ static int _shutdown(struct omap_hwmod *oh) } /** - * _init_mpu_rt_base - populate the virtual address for a hwmod - * @oh: struct omap_hwmod * to locate the virtual address - * - * Cache the virtual address used by the MPU to access this IP block's - * registers. This address is needed early so the OCP registers that - * are part of the device's address space can be ioremapped properly. - * No return value. - */ -static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) -{ - struct omap_hwmod_addr_space *mem; - void __iomem *va_start; - - if (!oh) - return; - - _save_mpu_port_index(oh); - - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) - return; - - mem = _find_mpu_rt_addr_space(oh); - if (!mem) { - pr_debug("omap_hwmod: %s: no MPU register target found\n", - oh->name); - return; - } - - va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); - if (!va_start) { - pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); - return; - } - - pr_debug("omap_hwmod: %s: MPU register target at va %p\n", - oh->name, va_start); - - oh->_mpu_rt_va = va_start; -} - -/** - * _init - initialize internal data for the hwmod @oh + * _setup - do initial configuration of omap_hwmod * @oh: struct omap_hwmod * - * @n: (unused) - * - * Look up the clocks and the address space used by the MPU to access - * registers belonging to the hwmod @oh. @oh must already be - * registered at this point. This is the first of two phases for - * hwmod initialization. Code called here does not touch any hardware - * registers, it simply prepares internal data structures. Returns 0 - * upon success or if the hwmod isn't registered, or -EINVAL upon - * failure. + * + * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh + * OCP_SYSCONFIG register. Returns 0. */ -static int __init _init(struct omap_hwmod *oh, void *data) +static int _setup(struct omap_hwmod *oh, void *data) { - int r; + int i, r; + u8 postsetup_state; - if (oh->_state != _HWMOD_STATE_REGISTERED) + if (oh->_state != _HWMOD_STATE_CLKS_INITED) return 0; - _init_mpu_rt_base(oh, NULL); - - r = _init_clocks(oh, NULL); - if (IS_ERR_VALUE(r)) { - WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); - return -EINVAL; - } - - oh->_state = _HWMOD_STATE_INITIALIZED; - - return 0; -} + /* Set iclk autoidle mode */ + if (oh->slaves_cnt > 0) { + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os = oh->slaves[i]; + struct clk *c = os->_clk; -/** - * _setup_iclk_autoidle - configure an IP block's interface clocks - * @oh: struct omap_hwmod * - * - * Set up the module's interface clocks. XXX This function is still mostly - * a stub; implementing this properly requires iclk autoidle usecounting in - * the clock code. No return value. - */ -static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) -{ - struct omap_hwmod_ocp_if *os; - struct list_head *p; - int i = 0; - if (oh->_state != _HWMOD_STATE_INITIALIZED) - return; - - p = oh->slave_ports.next; + if (!c) + continue; - while (i < oh->slaves_cnt) { - os = _fetch_next_ocp_if(&p, &i); - if (!os->_clk) - continue; - - if (os->flags & OCPIF_SWSUP_IDLE) { - /* XXX omap_iclk_deny_idle(c); */ - } else { - /* XXX omap_iclk_allow_idle(c); */ - clk_enable(os->_clk); + if (os->flags & OCPIF_SWSUP_IDLE) { + /* XXX omap_iclk_deny_idle(c); */ + } else { + /* XXX omap_iclk_allow_idle(c); */ + clk_enable(c); + } } } - return; -} - -/** - * _setup_reset - reset an IP block during the setup process - * @oh: struct omap_hwmod * - * - * Reset the IP block corresponding to the hwmod @oh during the setup - * process. The IP block is first enabled so it can be successfully - * reset. Returns 0 upon success or a negative error code upon - * failure. - */ -static int __init _setup_reset(struct omap_hwmod *oh) -{ - int r; + oh->_state = _HWMOD_STATE_INITIALIZED; - if (oh->_state != _HWMOD_STATE_INITIALIZED) - return -EINVAL; + /* + * In the case of hwmod with hardreset that should not be + * de-assert at boot time, we have to keep the module + * initialized, because we cannot enable it properly with the + * reset asserted. Exit without warning because that behavior is + * expected. + */ + if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) + return 0; - if (oh->rst_lines_cnt == 0) { - r = _enable(oh); - if (r) { - pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", - oh->name, oh->_state); - return -EINVAL; - } + r = _enable(oh); + if (r) { + pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", + oh->name, oh->_state); + return 0; } if (!(oh->flags & HWMOD_INIT_NO_RESET)) - r = _reset(oh); - - return r; -} - -/** - * _setup_postsetup - transition to the appropriate state after _setup - * @oh: struct omap_hwmod * - * - * Place an IP block represented by @oh into a "post-setup" state -- - * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that - * this function is called at the end of _setup().) The postsetup - * state for an IP block can be changed by calling - * omap_hwmod_enter_postsetup_state() early in the boot process, - * before one of the omap_hwmod_setup*() functions are called for the - * IP block. - * - * The IP block stays in this state until a PM runtime-based driver is - * loaded for that IP block. A post-setup state of IDLE is - * appropriate for almost all IP blocks with runtime PM-enabled - * drivers, since those drivers are able to enable the IP block. A - * post-setup state of ENABLED is appropriate for kernels with PM - * runtime disabled. The DISABLED state is appropriate for unusual IP - * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers - * included, since the WDTIMER starts running on reset and will reset - * the MPU if left active. - * - * This post-setup mechanism is deprecated. Once all of the OMAP - * drivers have been converted to use PM runtime, and all of the IP - * block data and interconnect data is available to the hwmod code, it - * should be possible to replace this mechanism with a "lazy reset" - * arrangement. In a "lazy reset" setup, each IP block is enabled - * when the driver first probes, then all remaining IP blocks without - * drivers are either shut down or enabled after the drivers have - * loaded. However, this cannot take place until the above - * preconditions have been met, since otherwise the late reset code - * has no way of knowing which IP blocks are in use by drivers, and - * which ones are unused. - * - * No return value. - */ -static void __init _setup_postsetup(struct omap_hwmod *oh) -{ - u8 postsetup_state; - - if (oh->rst_lines_cnt > 0) - return; + _reset(oh); postsetup_state = oh->_postsetup_state; if (postsetup_state == _HWMOD_STATE_UNKNOWN) @@ -2198,35 +1821,6 @@ static void __init _setup_postsetup(struct omap_hwmod *oh) WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", oh->name, postsetup_state); - return; -} - -/** - * _setup - prepare IP block hardware for use - * @oh: struct omap_hwmod * - * @n: (unused, pass NULL) - * - * Configure the IP block represented by @oh. This may include - * enabling the IP block, resetting it, and placing it into a - * post-setup state, depending on the type of IP block and applicable - * flags. IP blocks are reset to prevent any previous configuration - * by the bootloader or previous operating system from interfering - * with power management or other parts of the system. The reset can - * be avoided; see omap_hwmod_no_setup_reset(). This is the second of - * two phases for hwmod initialization. Code called here generally - * affects the IP block hardware, or system integration hardware - * associated with the IP block. Returns 0. - */ -static int __init _setup(struct omap_hwmod *oh, void *data) -{ - if (oh->_state != _HWMOD_STATE_INITIALIZED) - return 0; - - _setup_iclk_autoidle(oh); - - if (!_setup_reset(oh)) - _setup_postsetup(oh); - return 0; } @@ -2249,6 +1843,8 @@ static int __init _setup(struct omap_hwmod *oh, void *data) */ static int __init _register(struct omap_hwmod *oh) { + int ms_id; + if (!oh || !oh->name || !oh->class || !oh->class->name || (oh->_state != _HWMOD_STATE_UNKNOWN)) return -EINVAL; @@ -2258,10 +1854,14 @@ static int __init _register(struct omap_hwmod *oh) if (_lookup(oh->name)) return -EEXIST; + ms_id = _find_mpu_port_index(oh); + if (!IS_ERR_VALUE(ms_id)) + oh->_mpu_port_index = ms_id; + else + oh->_int_flags |= _HWMOD_NO_MPU_PORT; + list_add_tail(&oh->node, &omap_hwmod_list); - INIT_LIST_HEAD(&oh->master_ports); - INIT_LIST_HEAD(&oh->slave_ports); spin_lock_init(&oh->_lock); oh->_state = _HWMOD_STATE_REGISTERED; @@ -2276,160 +1876,6 @@ static int __init _register(struct omap_hwmod *oh) return 0; } -/** - * _alloc_links - return allocated memory for hwmod links - * @ml: pointer to a struct omap_hwmod_link * for the master link - * @sl: pointer to a struct omap_hwmod_link * for the slave link - * - * Return pointers to two struct omap_hwmod_link records, via the - * addresses pointed to by @ml and @sl. Will first attempt to return - * memory allocated as part of a large initial block, but if that has - * been exhausted, will allocate memory itself. Since ideally this - * second allocation path will never occur, the number of these - * 'supplemental' allocations will be logged when debugging is - * enabled. Returns 0. - */ -static int __init _alloc_links(struct omap_hwmod_link **ml, - struct omap_hwmod_link **sl) -{ - unsigned int sz; - - if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { - *ml = &linkspace[free_ls++]; - *sl = &linkspace[free_ls++]; - return 0; - } - - sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; - - *sl = NULL; - *ml = alloc_bootmem(sz); - - memset(*ml, 0, sz); - - *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); - - ls_supp++; - pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", - ls_supp * LINKS_PER_OCP_IF); - - return 0; -}; - -/** - * _add_link - add an interconnect between two IP blocks - * @oi: pointer to a struct omap_hwmod_ocp_if record - * - * Add struct omap_hwmod_link records connecting the master IP block - * specified in @oi->master to @oi, and connecting the slave IP block - * specified in @oi->slave to @oi. This code is assumed to run before - * preemption or SMP has been enabled, thus avoiding the need for - * locking in this code. Changes to this assumption will require - * additional locking. Returns 0. - */ -static int __init _add_link(struct omap_hwmod_ocp_if *oi) -{ - struct omap_hwmod_link *ml, *sl; - - pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, - oi->slave->name); - - _alloc_links(&ml, &sl); - - ml->ocp_if = oi; - INIT_LIST_HEAD(&ml->node); - list_add(&ml->node, &oi->master->master_ports); - oi->master->masters_cnt++; - - sl->ocp_if = oi; - INIT_LIST_HEAD(&sl->node); - list_add(&sl->node, &oi->slave->slave_ports); - oi->slave->slaves_cnt++; - - return 0; -} - -/** - * _register_link - register a struct omap_hwmod_ocp_if - * @oi: struct omap_hwmod_ocp_if * - * - * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it - * has already been registered; -EINVAL if @oi is NULL or if the - * record pointed to by @oi is missing required fields; or 0 upon - * success. - * - * XXX The data should be copied into bootmem, so the original data - * should be marked __initdata and freed after init. This would allow - * unneeded omap_hwmods to be freed on multi-OMAP configurations. - */ -static int __init _register_link(struct omap_hwmod_ocp_if *oi) -{ - if (!oi || !oi->master || !oi->slave || !oi->user) - return -EINVAL; - - if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) - return -EEXIST; - - pr_debug("omap_hwmod: registering link from %s to %s\n", - oi->master->name, oi->slave->name); - - /* - * Register the connected hwmods, if they haven't been - * registered already - */ - if (oi->master->_state != _HWMOD_STATE_REGISTERED) - _register(oi->master); - - if (oi->slave->_state != _HWMOD_STATE_REGISTERED) - _register(oi->slave); - - _add_link(oi); - - oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; - - return 0; -} - -/** - * _alloc_linkspace - allocate large block of hwmod links - * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count - * - * Allocate a large block of struct omap_hwmod_link records. This - * improves boot time significantly by avoiding the need to allocate - * individual records one by one. If the number of records to - * allocate in the block hasn't been manually specified, this function - * will count the number of struct omap_hwmod_ocp_if records in @ois - * and use that to determine the allocation size. For SoC families - * that require multiple list registrations, such as OMAP3xxx, this - * estimation process isn't optimal, so manual estimation is advised - * in those cases. Returns -EEXIST if the allocation has already occurred - * or 0 upon success. - */ -static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) -{ - unsigned int i = 0; - unsigned int sz; - - if (linkspace) { - WARN(1, "linkspace already allocated\n"); - return -EEXIST; - } - - if (max_ls == 0) - while (ois[i++]) - max_ls += LINKS_PER_OCP_IF; - - sz = sizeof(struct omap_hwmod_link) * max_ls; - - pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", - __func__, sz, max_ls); - - linkspace = alloc_bootmem(sz); - - memset(linkspace, 0, sz); - - return 0; -} /* Public functions */ @@ -2558,101 +2004,120 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), } /** - * omap_hwmod_register_links - register an array of hwmod links - * @ois: pointer to an array of omap_hwmod_ocp_if to register + * omap_hwmod_register - register an array of hwmods + * @ohs: pointer to an array of omap_hwmods to register * * Intended to be called early in boot before the clock framework is - * initialized. If @ois is not null, will register all omap_hwmods - * listed in @ois that are valid for this chip. Returns 0. + * initialized. If @ohs is not null, will register all omap_hwmods + * listed in @ohs that are valid for this chip. Returns 0. */ -int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) +int __init omap_hwmod_register(struct omap_hwmod **ohs) { int r, i; - if (!ois) + if (!ohs) return 0; - if (!linkspace) { - if (_alloc_linkspace(ois)) { - pr_err("omap_hwmod: could not allocate link space\n"); - return -ENOMEM; - } - } - i = 0; do { - r = _register_link(ois[i]); - WARN(r && r != -EEXIST, - "omap_hwmod: _register_link(%s -> %s) returned %d\n", - ois[i]->master->name, ois[i]->slave->name, r); - } while (ois[++i]); + r = _register(ohs[i]); + WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, + r); + } while (ohs[++i]); return 0; } -/** - * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up - * @oh: pointer to the hwmod currently being set up (usually not the MPU) +/* + * _populate_mpu_rt_base - populate the virtual address for a hwmod * - * If the hwmod data corresponding to the MPU subsystem IP block - * hasn't been initialized and set up yet, do so now. This must be - * done first since sleep dependencies may be added from other hwmods - * to the MPU. Intended to be called only by omap_hwmod_setup*(). No - * return value. + * Must be called only from omap_hwmod_setup_*() so ioremap works properly. + * Assumes the caller takes care of locking if needed. */ -static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) +static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) { - if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) - pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", - __func__, MPU_INITIATOR_NAME); - else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) - omap_hwmod_setup_one(MPU_INITIATOR_NAME); + if (oh->_state != _HWMOD_STATE_REGISTERED) + return 0; + + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return 0; + + oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); + + return 0; } /** * omap_hwmod_setup_one - set up a single hwmod * @oh_name: const char * name of the already-registered hwmod to set up * - * Initialize and set up a single hwmod. Intended to be used for a - * small number of early devices, such as the timer IP blocks used for - * the scheduler clock. Must be called after omap2_clk_init(). - * Resolves the struct clk names to struct clk pointers for each - * registered omap_hwmod. Also calls _setup() on each hwmod. Returns - * -EINVAL upon error or 0 upon success. + * Must be called after omap2_clk_init(). Resolves the struct clk + * names to struct clk pointers for each registered omap_hwmod. Also + * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon + * success. */ int __init omap_hwmod_setup_one(const char *oh_name) { struct omap_hwmod *oh; + int r; pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); + if (!mpu_oh) { + pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", + oh_name, MPU_INITIATOR_NAME); + return -EINVAL; + } + oh = _lookup(oh_name); if (!oh) { WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); return -EINVAL; } - _ensure_mpu_hwmod_is_setup(oh); + if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) + omap_hwmod_setup_one(MPU_INITIATOR_NAME); + + r = _populate_mpu_rt_base(oh, NULL); + if (IS_ERR_VALUE(r)) { + WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); + return -EINVAL; + } + + r = _init_clocks(oh, NULL); + if (IS_ERR_VALUE(r)) { + WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); + return -EINVAL; + } - _init(oh, NULL); _setup(oh, NULL); return 0; } /** - * omap_hwmod_setup_all - set up all registered IP blocks + * omap_hwmod_setup - do some post-clock framework initialization * - * Initialize and set up all IP blocks registered with the hwmod code. - * Must be called after omap2_clk_init(). Resolves the struct clk - * names to struct clk pointers for each registered omap_hwmod. Also - * calls _setup() on each hwmod. Returns 0 upon success. + * Must be called after omap2_clk_init(). Resolves the struct clk names + * to struct clk pointers for each registered omap_hwmod. Also calls + * _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) { - _ensure_mpu_hwmod_is_setup(NULL); + int r; + + if (!mpu_oh) { + pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", + __func__, MPU_INITIATOR_NAME); + return -EINVAL; + } + + r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); + + r = omap_hwmod_for_each(_init_clocks, NULL); + WARN(IS_ERR_VALUE(r), + "omap_hwmod: %s: _init_clocks failed\n", __func__); - omap_hwmod_for_each(_init, NULL); omap_hwmod_for_each(_setup, NULL); return 0; @@ -2809,10 +2274,6 @@ int omap_hwmod_reset(struct omap_hwmod *oh) return r; } -/* - * IP block data retrieval functions - */ - /** * omap_hwmod_count_resources - count number of struct resources needed by hwmod * @oh: struct omap_hwmod * @@ -2831,19 +2292,12 @@ int omap_hwmod_reset(struct omap_hwmod *oh) */ int omap_hwmod_count_resources(struct omap_hwmod *oh) { - struct omap_hwmod_ocp_if *os; - struct list_head *p; - int ret; - int i = 0; + int ret, i; ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); - p = oh->slave_ports.next; - - while (i < oh->slaves_cnt) { - os = _fetch_next_ocp_if(&p, &i); - ret += _count_ocp_if_addr_spaces(os); - } + for (i = 0; i < oh->slaves_cnt; i++) + ret += _count_ocp_if_addr_spaces(oh->slaves[i]); return ret; } @@ -2860,9 +2314,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) */ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) { - struct omap_hwmod_ocp_if *os; - struct list_head *p; - int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; + int i, j, mpu_irqs_cnt, sdma_reqs_cnt; int r = 0; /* For each IRQ, DMA, memory area, fill in array.*/ @@ -2885,11 +2337,11 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) r++; } - p = oh->slave_ports.next; + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os; + int addr_cnt; - i = 0; - while (i < oh->slaves_cnt) { - os = _fetch_next_ocp_if(&p, &i); + os = oh->slaves[i]; addr_cnt = _count_ocp_if_addr_spaces(os); for (j = 0; j < addr_cnt; j++) { @@ -2904,69 +2356,6 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) return r; } -/** - * omap_hwmod_get_resource_byname - fetch IP block integration data by name - * @oh: struct omap_hwmod * to operate on - * @type: one of the IORESOURCE_* constants from include/linux/ioport.h - * @name: pointer to the name of the data to fetch (optional) - * @rsrc: pointer to a struct resource, allocated by the caller - * - * Retrieve MPU IRQ, SDMA request line, or address space start/end - * data for the IP block pointed to by @oh. The data will be filled - * into a struct resource record pointed to by @rsrc. The struct - * resource must be allocated by the caller. When @name is non-null, - * the data associated with the matching entry in the IRQ/SDMA/address - * space hwmod data arrays will be returned. If @name is null, the - * first array entry will be returned. Data order is not meaningful - * in hwmod data, so callers are strongly encouraged to use a non-null - * @name whenever possible to avoid unpredictable effects if hwmod - * data is later added that causes data ordering to change. This - * function is only intended for use by OMAP core code. Device - * drivers should not call this function - the appropriate bus-related - * data accessor functions should be used instead. Returns 0 upon - * success or a negative error code upon error. - */ -int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, - const char *name, struct resource *rsrc) -{ - int r; - unsigned int irq, dma; - u32 pa_start, pa_end; - - if (!oh || !rsrc) - return -EINVAL; - - if (type == IORESOURCE_IRQ) { - r = _get_mpu_irq_by_name(oh, name, &irq); - if (r) - return r; - - rsrc->start = irq; - rsrc->end = irq; - } else if (type == IORESOURCE_DMA) { - r = _get_sdma_req_by_name(oh, name, &dma); - if (r) - return r; - - rsrc->start = dma; - rsrc->end = dma; - } else if (type == IORESOURCE_MEM) { - r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); - if (r) - return r; - - rsrc->start = pa_start; - rsrc->end = pa_end; - } else { - return -EINVAL; - } - - rsrc->flags = type; - rsrc->name = name; - - return 0; -} - /** * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain * @oh: struct omap_hwmod * @@ -2981,7 +2370,6 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { struct clk *c; - struct omap_hwmod_ocp_if *oi; if (!oh) return NULL; @@ -2989,10 +2377,9 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) if (oh->_clk) { c = oh->_clk; } else { - oi = _find_mpu_rt_port(oh); - if (!oi) + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) return NULL; - c = oi->_clk; + c = oh->slaves[oh->_mpu_port_index]->_clk; } if (!c->clkdm) @@ -3266,10 +2653,10 @@ int omap_hwmod_for_each_by_class(const char *classname, * @state: state that _setup() should leave the hwmod in * * Sets the hwmod state that @oh will enter at the end of _setup() - * (called by omap_hwmod_setup_*()). See also the documentation - * for _setup_postsetup(), above. Returns 0 upon success or - * -EINVAL if there is a problem with the arguments or if the hwmod is - * in the wrong state. + * (called by omap_hwmod_setup_*()). Only valid to call between + * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns + * 0 upon success or -EINVAL if there is a problem with the arguments + * or if the hwmod is in the wrong state. */ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) { diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 2c087ffc6a92..a6bde34e443a 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -2,7 +2,6 @@ * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips * * Copyright (C) 2009-2011 Nokia Corporation - * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -33,284 +32,1073 @@ /* * OMAP2420 hardware module integration data * - * All of the data in this section should be autogeneratable from the + * ALl of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ +static struct omap_hwmod omap2420_mpu_hwmod; +static struct omap_hwmod omap2420_iva_hwmod; +static struct omap_hwmod omap2420_l3_main_hwmod; +static struct omap_hwmod omap2420_l4_core_hwmod; +static struct omap_hwmod omap2420_dss_core_hwmod; +static struct omap_hwmod omap2420_dss_dispc_hwmod; +static struct omap_hwmod omap2420_dss_rfbi_hwmod; +static struct omap_hwmod omap2420_dss_venc_hwmod; +static struct omap_hwmod omap2420_wd_timer2_hwmod; +static struct omap_hwmod omap2420_gpio1_hwmod; +static struct omap_hwmod omap2420_gpio2_hwmod; +static struct omap_hwmod omap2420_gpio3_hwmod; +static struct omap_hwmod omap2420_gpio4_hwmod; +static struct omap_hwmod omap2420_dma_system_hwmod; +static struct omap_hwmod omap2420_mcspi1_hwmod; +static struct omap_hwmod omap2420_mcspi2_hwmod; + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { + .master = &omap2420_l3_main_hwmod, + .slave = &omap2420_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { + .master = &omap2420_mpu_hwmod, + .slave = &omap2420_l3_main_hwmod, + .user = OCP_USER_MPU, +}; + +/* Slave interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { + &omap2420_mpu__l3_main, +}; + +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap2420_dss__l3 = { + .master = &omap2420_dss_core_hwmod, + .slave = &omap2420_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* Master interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { + &omap2420_l3_main__l4_core, +}; + +/* L3 */ +static struct omap_hwmod omap2420_l3_main_hwmod = { + .name = "l3_main", + .class = &l3_hwmod_class, + .masters = omap2420_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), + .slaves = omap2420_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod omap2420_l4_wkup_hwmod; +static struct omap_hwmod omap2420_uart1_hwmod; +static struct omap_hwmod omap2420_uart2_hwmod; +static struct omap_hwmod omap2420_uart3_hwmod; +static struct omap_hwmod omap2420_i2c1_hwmod; +static struct omap_hwmod omap2420_i2c2_hwmod; +static struct omap_hwmod omap2420_mcbsp1_hwmod; +static struct omap_hwmod omap2420_mcbsp2_hwmod; + +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* Slave interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { + &omap2420_l3_main__l4_core, +}; + +/* Master interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { + &omap2420_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, + &omap2420_l4_core__i2c1, + &omap2420_l4_core__i2c2 +}; + +/* L4 CORE */ +static struct omap_hwmod omap2420_l4_core_hwmod = { + .name = "l4_core", + .class = &l4_hwmod_class, + .masters = omap2420_l4_core_masters, + .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), + .slaves = omap2420_l4_core_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), + .flags = HWMOD_NO_IDLEST, +}; + +/* Slave interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { + &omap2420_l4_core__l4_wkup, +}; + +/* Master interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { +}; + +/* L4 WKUP */ +static struct omap_hwmod omap2420_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &l4_hwmod_class, + .masters = omap2420_l4_wkup_masters, + .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), + .slaves = omap2420_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), + .flags = HWMOD_NO_IDLEST, +}; + +/* Master interfaces on the MPU device */ +static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { + &omap2420_mpu__l3_main, +}; + +/* MPU */ +static struct omap_hwmod omap2420_mpu_hwmod = { + .name = "mpu", + .class = &mpu_hwmod_class, + .main_clk = "mpu_ck", + .masters = omap2420_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), +}; + /* - * IP blocks + * IVA1 interface data */ -/* IVA1 (IVA1) */ -static struct omap_hwmod_class iva1_hwmod_class = { - .name = "iva1", +/* IVA <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__iva = { + .master = &omap2420_l3_main_hwmod, + .slave = &omap2420_iva_hwmod, + .clk = "iva1_ifck", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_rst_info omap2420_iva_resets[] = { - { .name = "iva", .rst_shift = 8 }, +static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { + &omap2420_l3__iva, }; +/* + * IVA2 (IVA2) + */ + static struct omap_hwmod omap2420_iva_hwmod = { .name = "iva", - .class = &iva1_hwmod_class, - .clkdm_name = "iva1_clkdm", - .rst_lines = omap2420_iva_resets, - .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets), - .main_clk = "iva1_ifck", + .class = &iva_hwmod_class, + .masters = omap2420_iva_masters, + .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), }; -/* DSP */ -static struct omap_hwmod_class dsp_hwmod_class = { - .name = "dsp", +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, }; -static struct omap_hwmod_rst_info omap2420_dsp_resets[] = { - { .name = "logic", .rst_shift = 0 }, - { .name = "mmu", .rst_shift = 1 }, +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, }; -static struct omap_hwmod omap2420_dsp_hwmod = { - .name = "dsp", - .class = &dsp_hwmod_class, - .clkdm_name = "dsp_clkdm", - .rst_lines = omap2420_dsp_resets, - .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets), - .main_clk = "dsp_fck", +/* timer1 */ +static struct omap_hwmod omap2420_timer1_hwmod; + +static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { + { + .pa_start = 0x48028000, + .pa_end = 0x48028000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -/* I2C common */ -static struct omap_hwmod_class_sysconfig i2c_sysc = { - .rev_offs = 0x00, - .sysc_offs = 0x20, - .syss_offs = 0x10, - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2420_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class i2c_class = { - .name = "i2c", - .sysc = &i2c_sysc, - .rev = OMAP_I2C_IP_VERSION_1, - .reset = &omap_i2c_reset, +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { + &omap2420_l4_wkup__timer1, }; -static struct omap_i2c_dev_attr i2c_dev_attr = { - .flags = OMAP_I2C_FLAG_NO_FIFO | - OMAP_I2C_FLAG_SIMPLE_CLOCK | - OMAP_I2C_FLAG_16BIT_DATA_REG | - OMAP_I2C_FLAG_BUS_SHIFT_2, +/* timer1 hwmod */ +static struct omap_hwmod omap2420_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2_timer1_mpu_irqs, + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2420_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* I2C1 */ -static struct omap_hwmod omap2420_i2c1_hwmod = { - .name = "i2c1", - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, - .main_clk = "i2c1_fck", +/* timer2 */ +static struct omap_hwmod omap2420_timer2_hwmod; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { + &omap2420_l4_core__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap2420_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2_timer2_mpu_irqs, + .main_clk = "gpt2_fck", .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_I2C1_SHIFT, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, + .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, }, }, - .class = &i2c_class, - .dev_attr = &i2c_dev_attr, - .flags = HWMOD_16BIT_REG, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2420_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* I2C2 */ -static struct omap_hwmod omap2420_i2c2_hwmod = { - .name = "i2c2", - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, - .main_clk = "i2c2_fck", +/* timer3 */ +static struct omap_hwmod omap2420_timer3_hwmod; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { + &omap2420_l4_core__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap2420_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2_timer3_mpu_irqs, + .main_clk = "gpt3_fck", .prcm = { .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2420_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer4 */ +static struct omap_hwmod omap2420_timer4_hwmod; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { + &omap2420_l4_core__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap2420_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2_timer4_mpu_irqs, + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_I2C2_SHIFT, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, }, }, - .class = &i2c_class, - .dev_attr = &i2c_dev_attr, - .flags = HWMOD_16BIT_REG, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2420_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32, - .lch_count = 32, +/* timer5 */ +static struct omap_hwmod omap2420_timer5_hwmod; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2420_dma_system_hwmod = { - .name = "dma", - .class = &omap2xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, - .main_clk = "core_l3_ck", - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { + &omap2420_l4_core__timer5, }; -/* mailbox */ -static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { - { .name = "dsp", .irq = 26 }, - { .name = "iva", .irq = 34 }, - { .irq = -1 } +/* timer5 hwmod */ +static struct omap_hwmod omap2420_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2_timer5_mpu_irqs, + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2420_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -static struct omap_hwmod omap2420_mailbox_hwmod = { - .name = "mailbox", - .class = &omap2xxx_mailbox_hwmod_class, - .mpu_irqs = omap2420_mailbox_irqs, - .main_clk = "mailboxes_ick", + +/* timer6 */ +static struct omap_hwmod omap2420_timer6_hwmod; + +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { + &omap2420_l4_core__timer6, +}; + +/* timer6 hwmod */ +static struct omap_hwmod omap2420_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2_timer6_mpu_irqs, + .main_clk = "gpt6_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2420_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* - * 'mcbsp' class - * multi channel buffered serial port controller - */ +/* timer7 */ +static struct omap_hwmod omap2420_timer7_hwmod; -static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { - .name = "mcbsp", +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp1 */ -static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { + &omap2420_l4_core__timer7, }; -static struct omap_hwmod omap2420_mcbsp1_hwmod = { - .name = "mcbsp1", - .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, - .main_clk = "mcbsp1_fck", +/* timer7 hwmod */ +static struct omap_hwmod omap2420_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2_timer7_mpu_irqs, + .main_clk = "gpt7_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2420_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* mcbsp2 */ -static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } +/* timer8 */ +static struct omap_hwmod omap2420_timer8_hwmod; + +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2420_mcbsp2_hwmod = { - .name = "mcbsp2", - .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, - .main_clk = "mcbsp2_fck", +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { + &omap2420_l4_core__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap2420_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2_timer8_mpu_irqs, + .main_clk = "gpt8_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2420_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* - * interfaces - */ +/* timer9 */ +static struct omap_hwmod omap2420_timer9_hwmod; -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2420_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2xxx_timer9_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2420_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { + &omap2420_l4_core__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap2420_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2_timer9_mpu_irqs, + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap2420_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer10 */ +static struct omap_hwmod omap2420_timer10_hwmod; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* IVA <- L3 interface */ -static struct omap_hwmod_ocp_if omap2420_l3__iva = { - .master = &omap2xxx_l3_main_hwmod, - .slave = &omap2420_iva_hwmod, - .clk = "core_l3_ck", +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { + &omap2420_l4_core__timer10, +}; + +/* timer10 hwmod */ +static struct omap_hwmod omap2420_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2_timer10_mpu_irqs, + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap2420_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer11 */ +static struct omap_hwmod omap2420_timer11_hwmod; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* DSP <- L3 interface */ -static struct omap_hwmod_ocp_if omap2420_l3__dsp = { - .master = &omap2xxx_l3_main_hwmod, - .slave = &omap2420_dsp_hwmod, - .clk = "dsp_ick", +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { + &omap2420_l4_core__timer11, +}; + +/* timer11 hwmod */ +static struct omap_hwmod omap2420_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2_timer11_mpu_irqs, + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap2420_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer12 */ +static struct omap_hwmod omap2420_timer12_hwmod; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2xxx_timer12_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { + &omap2420_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap2420_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2xxx_timer12_mpu_irqs, + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap2420_timer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), + .class = &omap2xxx_timer_hwmod_class, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { { - .pa_start = 0x48028000, - .pa_end = 0x48028000 + SZ_1K - 1, + .pa_start = 0x48022000, + .pa_end = 0x4802207f, .flags = ADDR_TYPE_RT }, - { } + { } +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2420_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { + &omap2420_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap2420_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2xxx_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, + }, + .slaves = omap2420_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), +}; + +/* UART1 */ + +static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { + &omap2_l4_core__uart1, +}; + +static struct omap_hwmod omap2420_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = omap2_uart1_mpu_irqs, + .sdma_reqs = omap2_uart1_sdma_reqs, + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, + }, + .slaves = omap2420_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), + .class = &omap2_uart_class, +}; + +/* UART2 */ + +static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { + &omap2_l4_core__uart2, +}; + +static struct omap_hwmod omap2420_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = omap2_uart2_mpu_irqs, + .sdma_reqs = omap2_uart2_sdma_reqs, + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, + }, + .slaves = omap2420_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), + .class = &omap2_uart_class, +}; + +/* UART3 */ + +static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { + &omap2_l4_core__uart3, +}; + +static struct omap_hwmod omap2420_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = omap2_uart3_mpu_irqs, + .sdma_reqs = omap2_uart3_sdma_reqs, + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, + .slaves = omap2420_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), + .class = &omap2_uart_class, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { + &omap2420_dss__l3, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { + &omap2420_l4_core__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + /* + * The DSS HW needs all DSS clocks enabled during reset. The dss_core + * driver does not use these clocks. + */ + { .role = "tv_clk", .clk = "dss_54m_fck" }, + { .role = "sys_clk", .clk = "dss2_fck" }, +}; + +static struct omap_hwmod omap2420_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2_dss_hwmod_class, + .main_clk = "dss1_fck", /* instead of dss_fck */ + .sdma_reqs = omap2xxx_dss_sdma_chs, + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap2420_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), + .masters = omap2420_dss_masters, + .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), + .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { + &omap2420_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap2420_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap2_dispc_hwmod_class, + .mpu_irqs = omap2_dispc_irqs, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .slaves = omap2420_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), + .flags = HWMOD_NO_IDLEST, + .dev_attr = &omap2_3_dss_dispc_dev_attr +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { + &omap2420_l4_core__dss_rfbi, +}; + +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { + { .role = "ick", .clk = "dss_ick" }, +}; + +static struct omap_hwmod omap2420_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2_rfbi_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .opt_clks = dss_rfbi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), + .slaves = omap2420_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), + .flags = HWMOD_NO_IDLEST, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { + &omap2420_l4_core__dss_venc, +}; + +static struct omap_hwmod omap2420_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2_venc_hwmod_class, + .main_clk = "dss_54m_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2420_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), + .flags = HWMOD_NO_IDLEST, +}; + +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_1, + .reset = &omap_i2c_reset, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_NO_FIFO | + OMAP_I2C_FLAG_SIMPLE_CLOCK | + OMAP_I2C_FLAG_16BIT_DATA_REG | + OMAP_I2C_FLAG_BUS_SHIFT_2, +}; + +/* I2C1 */ + +static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { + &omap2420_l4_core__i2c1, +}; + +static struct omap_hwmod omap2420_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = omap2_i2c1_mpu_irqs, + .sdma_reqs = omap2_i2c1_sdma_reqs, + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_I2C1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, + }, + }, + .slaves = omap2420_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .flags = HWMOD_16BIT_REG, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap2420_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* I2C2 */ -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { - { - .pa_start = 0x48022000, - .pa_end = 0x4802207f, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { + &omap2420_l4_core__i2c2, }; -static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_wd_timer2_hwmod, - .clk = "mpu_wdt_ick", - .addr = omap2420_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap2420_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = omap2_i2c2_mpu_irqs, + .sdma_reqs = omap2_i2c2_sdma_reqs, + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_I2C2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, + }, + }, + .slaves = omap2420_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .flags = HWMOD_16BIT_REG, }; /* l4_wkup -> gpio1 */ @@ -324,8 +1112,8 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_gpio1_hwmod, + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio1_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -342,8 +1130,8 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_gpio2_hwmod, + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio2_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -360,8 +1148,8 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_gpio3_hwmod, + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio3_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -378,100 +1166,408 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_gpio4_hwmod, + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio4_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, +}; + +/* gpio1 */ +static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { + &omap2420_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap2420_gpio1_hwmod = { + .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio1_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* gpio2 */ +static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { + &omap2420_l4_wkup__gpio2, +}; + +static struct omap_hwmod omap2420_gpio2_hwmod = { + .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio2_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* gpio3 */ +static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { + &omap2420_l4_wkup__gpio3, +}; + +static struct omap_hwmod omap2420_gpio3_hwmod = { + .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio3_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* gpio4 */ +static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { + &omap2420_l4_wkup__gpio4, +}; + +static struct omap_hwmod omap2420_gpio4_hwmod = { + .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio4_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .lch_count = 32, +}; + /* dma_system -> L3 */ static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { .master = &omap2420_dma_system_hwmod, - .slave = &omap2xxx_l3_main_hwmod, + .slave = &omap2420_l3_main_hwmod, .clk = "core_l3_ck", .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { + &omap2420_dma_system__l3, +}; + /* l4_core -> dma_system */ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { - .master = &omap2xxx_l4_core_hwmod, + .master = &omap2420_l4_core_hwmod, .slave = &omap2420_dma_system_hwmod, .clk = "sdma_ick", .addr = omap2_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { + &omap2420_l4_core__dma_system, +}; + +static struct omap_hwmod omap2420_dma_system_hwmod = { + .name = "dma", + .class = &omap2xxx_dma_hwmod_class, + .mpu_irqs = omap2_dma_system_irqs, + .main_clk = "core_l3_ck", + .slaves = omap2420_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), + .masters = omap2420_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), + .dev_attr = &dma_dev_attr, + .flags = HWMOD_NO_IDLEST, +}; + +/* mailbox */ +static struct omap_hwmod omap2420_mailbox_hwmod; +static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { + { .name = "dsp", .irq = 26 }, + { .name = "iva", .irq = 34 }, + { .irq = -1 } +}; + /* l4_core -> mailbox */ static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { - .master = &omap2xxx_l4_core_hwmod, + .master = &omap2420_l4_core_hwmod, .slave = &omap2420_mailbox_hwmod, .addr = omap2_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { + &omap2420_l4_core__mailbox, +}; + +static struct omap_hwmod omap2420_mailbox_hwmod = { + .name = "mailbox", + .class = &omap2xxx_mailbox_hwmod_class, + .mpu_irqs = omap2420_mailbox_irqs, + .main_clk = "mailboxes_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, + }, + }, + .slaves = omap2420_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), +}; + +/* mcspi1 */ +static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { + &omap2420_l4_core__mcspi1, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap2420_mcspi1_hwmod = { + .name = "mcspi1_hwmod", + .mpu_irqs = omap2_mcspi1_mpu_irqs, + .sdma_reqs = omap2_mcspi1_sdma_reqs, + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, + }, + }, + .slaves = omap2420_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, +}; + +/* mcspi2 */ +static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { + &omap2420_l4_core__mcspi2, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2420_mcspi2_hwmod = { + .name = "mcspi2_hwmod", + .mpu_irqs = omap2_mcspi2_mpu_irqs, + .sdma_reqs = omap2_mcspi2_sdma_reqs, + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, + }, + }, + .slaves = omap2420_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, +}; + +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { + .name = "mcbsp", +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .irq = -1 } +}; + /* l4_core -> mcbsp1 */ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { - .master = &omap2xxx_l4_core_hwmod, + .master = &omap2420_l4_core_hwmod, .slave = &omap2420_mcbsp1_hwmod, .clk = "mcbsp1_ick", .addr = omap2_mcbsp1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { + &omap2420_l4_core__mcbsp1, +}; + +static struct omap_hwmod omap2420_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2420_mcbsp_hwmod_class, + .mpu_irqs = omap2420_mcbsp1_irqs, + .sdma_reqs = omap2_mcbsp1_sdma_reqs, + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + }, + }, + .slaves = omap2420_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), +}; + +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, + { .irq = -1 } +}; + /* l4_core -> mcbsp2 */ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { - .master = &omap2xxx_l4_core_hwmod, + .master = &omap2420_l4_core_hwmod, .slave = &omap2420_mcbsp2_hwmod, .clk = "mcbsp2_ick", .addr = omap2xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { - &omap2xxx_l3_main__l4_core, - &omap2xxx_mpu__l3_main, - &omap2xxx_dss__l3, - &omap2xxx_l4_core__mcspi1, - &omap2xxx_l4_core__mcspi2, - &omap2xxx_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, - &omap2420_l4_core__i2c1, - &omap2420_l4_core__i2c2, - &omap2420_l3__iva, - &omap2420_l3__dsp, - &omap2420_l4_wkup__timer1, - &omap2xxx_l4_core__timer2, - &omap2xxx_l4_core__timer3, - &omap2xxx_l4_core__timer4, - &omap2xxx_l4_core__timer5, - &omap2xxx_l4_core__timer6, - &omap2xxx_l4_core__timer7, - &omap2xxx_l4_core__timer8, - &omap2xxx_l4_core__timer9, - &omap2xxx_l4_core__timer10, - &omap2xxx_l4_core__timer11, - &omap2xxx_l4_core__timer12, - &omap2420_l4_wkup__wd_timer2, - &omap2xxx_l4_core__dss, - &omap2xxx_l4_core__dss_dispc, - &omap2xxx_l4_core__dss_rfbi, - &omap2xxx_l4_core__dss_venc, - &omap2420_l4_wkup__gpio1, - &omap2420_l4_wkup__gpio2, - &omap2420_l4_wkup__gpio3, - &omap2420_l4_wkup__gpio4, - &omap2420_dma_system__l3, - &omap2420_l4_core__dma_system, - &omap2420_l4_core__mailbox, - &omap2420_l4_core__mcbsp1, +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { &omap2420_l4_core__mcbsp2, +}; + +static struct omap_hwmod omap2420_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap2420_mcbsp_hwmod_class, + .mpu_irqs = omap2420_mcbsp2_irqs, + .sdma_reqs = omap2_mcbsp2_sdma_reqs, + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap2420_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), +}; + +static __initdata struct omap_hwmod *omap2420_hwmods[] = { + &omap2420_l3_main_hwmod, + &omap2420_l4_core_hwmod, + &omap2420_l4_wkup_hwmod, + &omap2420_mpu_hwmod, + &omap2420_iva_hwmod, + + &omap2420_timer1_hwmod, + &omap2420_timer2_hwmod, + &omap2420_timer3_hwmod, + &omap2420_timer4_hwmod, + &omap2420_timer5_hwmod, + &omap2420_timer6_hwmod, + &omap2420_timer7_hwmod, + &omap2420_timer8_hwmod, + &omap2420_timer9_hwmod, + &omap2420_timer10_hwmod, + &omap2420_timer11_hwmod, + &omap2420_timer12_hwmod, + + &omap2420_wd_timer2_hwmod, + &omap2420_uart1_hwmod, + &omap2420_uart2_hwmod, + &omap2420_uart3_hwmod, + /* dss class */ + &omap2420_dss_core_hwmod, + &omap2420_dss_dispc_hwmod, + &omap2420_dss_rfbi_hwmod, + &omap2420_dss_venc_hwmod, + /* i2c class */ + &omap2420_i2c1_hwmod, + &omap2420_i2c2_hwmod, + + /* gpio class */ + &omap2420_gpio1_hwmod, + &omap2420_gpio2_hwmod, + &omap2420_gpio3_hwmod, + &omap2420_gpio4_hwmod, + + /* dma_system class*/ + &omap2420_dma_system_hwmod, + + /* mailbox class */ + &omap2420_mailbox_hwmod, + + /* mcbsp class */ + &omap2420_mcbsp1_hwmod, + &omap2420_mcbsp2_hwmod, + + /* mcspi class */ + &omap2420_mcspi1_hwmod, + &omap2420_mcspi2_hwmod, NULL, }; int __init omap2420_hwmod_init(void) { - return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); + return omap_hwmod_register(omap2420_hwmods); } diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 71d9f8824f9d..04a3885f4475 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -2,7 +2,6 @@ * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips * * Copyright (C) 2009-2011 Nokia Corporation - * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -34,600 +33,777 @@ /* * OMAP2430 hardware module integration data * - * All of the data in this section should be autogeneratable from the + * ALl of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -/* - * IP blocks - */ +static struct omap_hwmod omap2430_mpu_hwmod; +static struct omap_hwmod omap2430_iva_hwmod; +static struct omap_hwmod omap2430_l3_main_hwmod; +static struct omap_hwmod omap2430_l4_core_hwmod; +static struct omap_hwmod omap2430_dss_core_hwmod; +static struct omap_hwmod omap2430_dss_dispc_hwmod; +static struct omap_hwmod omap2430_dss_rfbi_hwmod; +static struct omap_hwmod omap2430_dss_venc_hwmod; +static struct omap_hwmod omap2430_wd_timer2_hwmod; +static struct omap_hwmod omap2430_gpio1_hwmod; +static struct omap_hwmod omap2430_gpio2_hwmod; +static struct omap_hwmod omap2430_gpio3_hwmod; +static struct omap_hwmod omap2430_gpio4_hwmod; +static struct omap_hwmod omap2430_gpio5_hwmod; +static struct omap_hwmod omap2430_dma_system_hwmod; +static struct omap_hwmod omap2430_mcbsp1_hwmod; +static struct omap_hwmod omap2430_mcbsp2_hwmod; +static struct omap_hwmod omap2430_mcbsp3_hwmod; +static struct omap_hwmod omap2430_mcbsp4_hwmod; +static struct omap_hwmod omap2430_mcbsp5_hwmod; +static struct omap_hwmod omap2430_mcspi1_hwmod; +static struct omap_hwmod omap2430_mcspi2_hwmod; +static struct omap_hwmod omap2430_mcspi3_hwmod; +static struct omap_hwmod omap2430_mmc1_hwmod; +static struct omap_hwmod omap2430_mmc2_hwmod; -/* IVA2 (IVA2) */ -static struct omap_hwmod_rst_info omap2430_iva_resets[] = { - { .name = "logic", .rst_shift = 0 }, - { .name = "mmu", .rst_shift = 1 }, +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { + .master = &omap2430_l3_main_hwmod, + .slave = &omap2430_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2430_iva_hwmod = { - .name = "iva", - .class = &iva_hwmod_class, - .clkdm_name = "dsp_clkdm", - .rst_lines = omap2430_iva_resets, - .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), - .main_clk = "dsp_fck", +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { + .master = &omap2430_mpu_hwmod, + .slave = &omap2430_l3_main_hwmod, + .user = OCP_USER_MPU, }; -/* I2C common */ -static struct omap_hwmod_class_sysconfig i2c_sysc = { - .rev_offs = 0x00, - .sysc_offs = 0x20, - .syss_offs = 0x10, - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .sysc_fields = &omap_hwmod_sysc_type1, +/* Slave interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { + &omap2430_mpu__l3_main, }; -static struct omap_hwmod_class i2c_class = { - .name = "i2c", - .sysc = &i2c_sysc, - .rev = OMAP_I2C_IP_VERSION_1, - .reset = &omap_i2c_reset, +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap2430_dss__l3 = { + .master = &omap2430_dss_core_hwmod, + .slave = &omap2430_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_i2c_dev_attr i2c_dev_attr = { - .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_BUS_SHIFT_2 | - OMAP_I2C_FLAG_FORCE_19200_INT_CLK, +/* Master interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { + &omap2430_l3_main__l4_core, }; -/* I2C1 */ -static struct omap_hwmod omap2430_i2c1_hwmod = { - .name = "i2c1", - .flags = HWMOD_16BIT_REG, - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, - .main_clk = "i2chs1_fck", - .prcm = { - .omap2 = { - /* - * NOTE: The CM_FCLKEN* and CM_ICLKEN* for - * I2CHS IP's do not follow the usual pattern. - * prcm_reg_id alone cannot be used to program - * the iclk and fclk. Needs to be handled using - * additional flags when clk handling is moved - * to hwmod framework. - */ - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_I2CHS1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, - }, - }, - .class = &i2c_class, - .dev_attr = &i2c_dev_attr, +/* L3 */ +static struct omap_hwmod omap2430_l3_main_hwmod = { + .name = "l3_main", + .class = &l3_hwmod_class, + .masters = omap2430_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), + .slaves = omap2430_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), + .flags = HWMOD_NO_IDLEST, }; -/* I2C2 */ -static struct omap_hwmod omap2430_i2c2_hwmod = { - .name = "i2c2", - .flags = HWMOD_16BIT_REG, - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, - .main_clk = "i2chs2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_I2CHS2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, - }, - }, - .class = &i2c_class, - .dev_attr = &i2c_dev_attr, +static struct omap_hwmod omap2430_l4_wkup_hwmod; +static struct omap_hwmod omap2430_uart1_hwmod; +static struct omap_hwmod omap2430_uart2_hwmod; +static struct omap_hwmod omap2430_uart3_hwmod; +static struct omap_hwmod omap2430_i2c1_hwmod; +static struct omap_hwmod omap2430_i2c2_hwmod; + +static struct omap_hwmod omap2430_usbhsotg_hwmod; + +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { + .master = &omap2430_usbhsotg_hwmod, + .slave = &omap2430_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU, }; -/* gpio5 */ -static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { - { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ - { .irq = -1 } +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2430_gpio5_hwmod = { - .name = "gpio5", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap243x_gpio5_irqs, - .main_clk = "gpio5_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 2, - .module_bit = OMAP2430_EN_GPIO5_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, - }, - }, - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2430_dma_system_hwmod = { - .name = "dma", - .class = &omap2xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, - .main_clk = "core_l3_ck", - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mailbox */ -static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { - { .irq = 26 }, - { .irq = -1 } +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2430_mailbox_hwmod = { - .name = "mailbox", - .class = &omap2xxx_mailbox_hwmod_class, - .mpu_irqs = omap2430_mailbox_irqs, - .main_clk = "mailboxes_ick", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, - }, +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* +* usbhsotg interface data +*/ +static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { + { + .pa_start = OMAP243X_HS_BASE, + .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT }, + { } }; -/* mcspi3 */ -static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { - { .irq = 91 }, - { .irq = -1 } +/* l4_core ->usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_usbhsotg_hwmod, + .clk = "usb_l4_ick", + .addr = omap2430_usbhsotg_addrs, + .user = OCP_USER_MPU, }; -static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { - { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ - { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ - { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ - { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ - { .dma_req = -1 } +static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { + &omap2430_usbhsotg__l3, }; -static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { - .num_chipselect = 2, +static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { + &omap2430_l4_core__usbhsotg, }; -static struct omap_hwmod omap2430_mcspi3_hwmod = { - .name = "mcspi3", - .mpu_irqs = omap2430_mcspi3_mpu_irqs, - .sdma_reqs = omap2430_mcspi3_sdma_reqs, - .main_clk = "mcspi3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP2430_EN_MCSPI3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, - }, - }, - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi3_dev_attr, +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* usbhsotg */ -static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { - .rev_offs = 0x0400, - .sysc_offs = 0x0404, - .syss_offs = 0x0408, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class usbotg_class = { - .name = "usbotg", - .sysc = &omap2430_usbhsotg_sysc, +/* Slave interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { + &omap2430_l3_main__l4_core, }; -/* usb_otg_hs */ -static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { +/* Master interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { + &omap2430_l4_core__l4_wkup, + &omap2430_l4_core__mmc1, + &omap2430_l4_core__mmc2, +}; - { .name = "mc", .irq = 92 }, - { .name = "dma", .irq = 93 }, - { .irq = -1 } +/* L4 CORE */ +static struct omap_hwmod omap2430_l4_core_hwmod = { + .name = "l4_core", + .class = &l4_hwmod_class, + .masters = omap2430_l4_core_masters, + .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), + .slaves = omap2430_l4_core_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), + .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod omap2430_usbhsotg_hwmod = { - .name = "usb_otg_hs", - .mpu_irqs = omap2430_usbhsotg_mpu_irqs, - .main_clk = "usbhs_ick", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_USBHS_MASK, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, - }, - }, - .class = &usbotg_class, - /* - * Erratum ID: i479 idle_req / idle_ack mechanism potentially - * broken when autoidle is enabled - * workaround is to disable the autoidle bit at module level. - */ - .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE - | HWMOD_SWSUP_MSTANDBY, +/* Slave interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { + &omap2430_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, }; -/* - * 'mcbsp' class - * multi channel buffered serial port controller - */ +/* Master interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { +}; -static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { - .rev_offs = 0x007C, - .sysc_offs = 0x008C, - .sysc_flags = (SYSC_HAS_SOFTRESET), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { - .name = "mcbsp", - .sysc = &omap2430_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE2, +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp1 */ -static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .name = "ovr", .irq = 61 }, - { .name = "common", .irq = 64 }, - { .irq = -1 } +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi3_hwmod, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2430_mcbsp1_hwmod = { - .name = "mcbsp1", - .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, - .main_clk = "mcbsp1_fck", +/* L4 WKUP */ +static struct omap_hwmod omap2430_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &l4_hwmod_class, + .masters = omap2430_l4_wkup_masters, + .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), + .slaves = omap2430_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), + .flags = HWMOD_NO_IDLEST, +}; + +/* Master interfaces on the MPU device */ +static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { + &omap2430_mpu__l3_main, +}; + +/* MPU */ +static struct omap_hwmod omap2430_mpu_hwmod = { + .name = "mpu", + .class = &mpu_hwmod_class, + .main_clk = "mpu_ck", + .masters = omap2430_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), +}; + +/* + * IVA2_1 interface data + */ + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap2430_l3__iva = { + .master = &omap2430_l3_main_hwmod, + .slave = &omap2430_iva_hwmod, + .clk = "dsp_fck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { + &omap2430_l3__iva, +}; + +/* + * IVA2 (IVA2) + */ + +static struct omap_hwmod omap2430_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .masters = omap2430_iva_masters, + .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), +}; + +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, +}; + +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, +}; + +/* timer1 */ +static struct omap_hwmod omap2430_timer1_hwmod; + +static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { + { + .pa_start = 0x49018000, + .pa_end = 0x49018000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2430_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { + &omap2430_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap2430_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2_timer1_mpu_irqs, + .main_clk = "gpt1_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .module_offs = CORE_MOD, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2430_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* mcbsp2 */ -static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .name = "common", .irq = 16 }, - { .irq = -1 } +/* timer2 */ +static struct omap_hwmod omap2430_timer2_hwmod; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2430_mcbsp2_hwmod = { - .name = "mcbsp2", - .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, - .main_clk = "mcbsp2_fck", +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { + &omap2430_l4_core__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap2430_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2_timer2_mpu_irqs, + .main_clk = "gpt2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2430_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* mcbsp3 */ -static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { - { .name = "tx", .irq = 89 }, - { .name = "rx", .irq = 90 }, - { .name = "common", .irq = 17 }, - { .irq = -1 } +/* timer3 */ +static struct omap_hwmod omap2430_timer3_hwmod; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2430_mcbsp3_hwmod = { - .name = "mcbsp3", - .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp3_irqs, - .sdma_reqs = omap2_mcbsp3_sdma_reqs, - .main_clk = "mcbsp3_fck", +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { + &omap2430_l4_core__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap2430_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2_timer3_mpu_irqs, + .main_clk = "gpt3_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_MCBSP3_SHIFT, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, .module_offs = CORE_MOD, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2430_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* mcbsp4 */ -static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { - { .name = "tx", .irq = 54 }, - { .name = "rx", .irq = 55 }, - { .name = "common", .irq = 18 }, - { .irq = -1 } +/* timer4 */ +static struct omap_hwmod omap2430_timer4_hwmod; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { - { .name = "rx", .dma_req = 20 }, - { .name = "tx", .dma_req = 19 }, - { .dma_req = -1 } +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { + &omap2430_l4_core__timer4, }; -static struct omap_hwmod omap2430_mcbsp4_hwmod = { - .name = "mcbsp4", - .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp4_irqs, - .sdma_reqs = omap2430_mcbsp4_sdma_chs, - .main_clk = "mcbsp4_fck", +/* timer4 hwmod */ +static struct omap_hwmod omap2430_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2_timer4_mpu_irqs, + .main_clk = "gpt4_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_MCBSP4_SHIFT, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, .module_offs = CORE_MOD, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2430_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* mcbsp5 */ -static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { - { .name = "tx", .irq = 81 }, - { .name = "rx", .irq = 82 }, - { .name = "common", .irq = 19 }, - { .irq = -1 } +/* timer5 */ +static struct omap_hwmod omap2430_timer5_hwmod; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { - { .name = "rx", .dma_req = 22 }, - { .name = "tx", .dma_req = 21 }, - { .dma_req = -1 } +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { + &omap2430_l4_core__timer5, }; -static struct omap_hwmod omap2430_mcbsp5_hwmod = { - .name = "mcbsp5", - .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp5_irqs, - .sdma_reqs = omap2430_mcbsp5_sdma_chs, - .main_clk = "mcbsp5_fck", +/* timer5 hwmod */ +static struct omap_hwmod omap2430_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2_timer5_mpu_irqs, + .main_clk = "gpt5_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_MCBSP5_SHIFT, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, .module_offs = CORE_MOD, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2430_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* MMC/SD/SDIO common */ -static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { - .rev_offs = 0x1fc, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; +/* timer6 */ +static struct omap_hwmod omap2430_timer6_hwmod; -static struct omap_hwmod_class omap2430_mmc_class = { - .name = "mmc", - .sysc = &omap2430_mmc_sysc, +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* MMC/SD/SDIO1 */ -static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { - { .irq = 83 }, - { .irq = -1 } +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { + &omap2430_l4_core__timer6, }; -static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { - { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ - { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ - { .dma_req = -1 } +/* timer6 hwmod */ +static struct omap_hwmod omap2430_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2_timer6_mpu_irqs, + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2430_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { - { .role = "dbck", .clk = "mmchsdb1_fck" }, +/* timer7 */ +static struct omap_hwmod omap2430_timer7_hwmod; + +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_mmc_dev_attr mmc1_dev_attr = { - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { + &omap2430_l4_core__timer7, }; -static struct omap_hwmod omap2430_mmc1_hwmod = { - .name = "mmc1", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2430_mmc1_mpu_irqs, - .sdma_reqs = omap2430_mmc1_sdma_reqs, - .opt_clks = omap2430_mmc1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), - .main_clk = "mmchs1_fck", +/* timer7 hwmod */ +static struct omap_hwmod omap2430_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2_timer7_mpu_irqs, + .main_clk = "gpt7_fck", .prcm = { .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP2430_EN_MMCHS1_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, }, }, - .dev_attr = &mmc1_dev_attr, - .class = &omap2430_mmc_class, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2430_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* MMC/SD/SDIO2 */ -static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { - { .irq = 86 }, - { .irq = -1 } -}; +/* timer8 */ +static struct omap_hwmod omap2430_timer8_hwmod; -static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { - { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ - { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ - { .dma_req = -1 } +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { - { .role = "dbck", .clk = "mmchsdb2_fck" }, +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { + &omap2430_l4_core__timer8, }; -static struct omap_hwmod omap2430_mmc2_hwmod = { - .name = "mmc2", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2430_mmc2_mpu_irqs, - .sdma_reqs = omap2430_mmc2_sdma_reqs, - .opt_clks = omap2430_mmc2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), - .main_clk = "mmchs2_fck", +/* timer8 hwmod */ +static struct omap_hwmod omap2430_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2_timer8_mpu_irqs, + .main_clk = "gpt8_fck", .prcm = { .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP2430_EN_MMCHS2_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, }, }, - .class = &omap2430_mmc_class, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap2430_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* - * interfaces - */ +/* timer9 */ +static struct omap_hwmod omap2430_timer9_hwmod; -/* L3 -> L4_CORE interface */ -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { - .master = &omap2430_usbhsotg_hwmod, - .slave = &omap2xxx_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU, +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { + &omap2430_l4_core__timer9, }; -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, +/* timer9 hwmod */ +static struct omap_hwmod omap2430_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2_timer9_mpu_irqs, + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap2430_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer10 */ +static struct omap_hwmod omap2430_timer10_hwmod; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { - { - .pa_start = OMAP243X_HS_BASE, - .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { + &omap2430_l4_core__timer10, }; -/* l4_core ->usbhsotg interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_usbhsotg_hwmod, - .clk = "usb_l4_ick", - .addr = omap2430_usbhsotg_addrs, - .user = OCP_USER_MPU, +/* timer10 hwmod */ +static struct omap_hwmod omap2430_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2_timer10_mpu_irqs, + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap2430_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* L4 CORE -> MMC1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, +/* timer11 */ +static struct omap_hwmod omap2430_timer11_hwmod; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 CORE -> MMC2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { + &omap2430_l4_core__timer11, }; -/* l4 core -> mcspi3 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_mcspi3_hwmod, - .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* timer11 hwmod */ +static struct omap_hwmod omap2430_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2_timer11_mpu_irqs, + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap2430_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), + .class = &omap2xxx_timer_hwmod_class, }; -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap2430_l3__iva = { - .master = &omap2xxx_l3_main_hwmod, - .slave = &omap2430_iva_hwmod, - .clk = "core_l3_ck", +/* timer12 */ +static struct omap_hwmod omap2430_timer12_hwmod; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2xxx_timer12_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { - { - .pa_start = 0x49018000, - .pa_end = 0x49018000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { + &omap2430_l4_core__timer12, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap2430_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* timer12 hwmod */ +static struct omap_hwmod omap2430_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2xxx_timer12_mpu_irqs, + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap2430_timer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), + .class = &omap2xxx_timer_hwmod_class, }; /* l4_wkup -> wd_timer2 */ @@ -641,146 +817,923 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { }; static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_wd_timer2_hwmod, + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_wd_timer2_hwmod, .clk = "mpu_wdt_ick", .addr = omap2430_wd_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { - { - .pa_start = 0x4900C000, - .pa_end = 0x4900C1ff, - .flags = ADDR_TYPE_RT +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { + &omap2430_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap2430_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2xxx_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, }, - { } + .slaves = omap2430_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), }; -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_gpio1_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* UART1 */ + +static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { + &omap2_l4_core__uart1, }; -/* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { - { - .pa_start = 0x4900E000, - .pa_end = 0x4900E1ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap2430_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = omap2_uart1_mpu_irqs, + .sdma_reqs = omap2_uart1_sdma_reqs, + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, }, - { } + .slaves = omap2430_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), + .class = &omap2_uart_class, }; -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_gpio2_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* UART2 */ + +static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { + &omap2_l4_core__uart2, }; -/* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { - { - .pa_start = 0x49010000, - .pa_end = 0x490101ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap2430_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = omap2_uart2_mpu_irqs, + .sdma_reqs = omap2_uart2_sdma_reqs, + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, }, - { } + .slaves = omap2430_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), + .class = &omap2_uart_class, }; -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_gpio3_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* UART3 */ + +static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { + &omap2_l4_core__uart3, }; -/* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { - { - .pa_start = 0x49012000, - .pa_end = 0x490121ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap2430_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = omap2_uart3_mpu_irqs, + .sdma_reqs = omap2_uart3_sdma_reqs, + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, }, - { } + .slaves = omap2430_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), + .class = &omap2_uart_class, }; -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_gpio4_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio4_addr_space, +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { + &omap2430_dss__l3, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_core -> gpio5 */ -static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { - { - .pa_start = 0x480B6000, - .pa_end = 0x480B61ff, - .flags = ADDR_TYPE_RT - }, - { } +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { + &omap2430_l4_core__dss, }; -static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_gpio5_hwmod, - .clk = "gpio5_ick", - .addr = omap2430_gpio5_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + /* + * The DSS HW needs all DSS clocks enabled during reset. The dss_core + * driver does not use these clocks. + */ + { .role = "tv_clk", .clk = "dss_54m_fck" }, + { .role = "sys_clk", .clk = "dss2_fck" }, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { - .master = &omap2430_dma_system_hwmod, - .slave = &omap2xxx_l3_main_hwmod, - .clk = "core_l3_ck", +static struct omap_hwmod omap2430_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2_dss_hwmod_class, + .main_clk = "dss1_fck", /* instead of dss_fck */ + .sdma_reqs = omap2xxx_dss_sdma_chs, + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap2430_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), + .masters = omap2430_dss_masters, + .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), + .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_core -> dma_system */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_dma_system_hwmod, - .clk = "sdma_ick", - .addr = omap2_dma_system_addrs, +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { + &omap2430_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap2430_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap2_dispc_hwmod_class, + .mpu_irqs = omap2_dispc_irqs, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .slaves = omap2430_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), + .flags = HWMOD_NO_IDLEST, + .dev_attr = &omap2_3_dss_dispc_dev_attr +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_mailbox_hwmod, - .addr = omap2_mailbox_addrs, +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { + &omap2430_l4_core__dss_rfbi, +}; + +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { + { .role = "ick", .clk = "dss_ick" }, +}; + +static struct omap_hwmod omap2430_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2_rfbi_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .opt_clks = dss_rfbi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), + .slaves = omap2430_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), + .flags = HWMOD_NO_IDLEST, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { + &omap2430_l4_core__dss_venc, +}; + +static struct omap_hwmod omap2430_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2_venc_hwmod_class, + .main_clk = "dss_54m_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2430_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), + .flags = HWMOD_NO_IDLEST, +}; + +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_1, + .reset = &omap_i2c_reset, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr = { + .fifo_depth = 8, /* bytes */ + .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | + OMAP_I2C_FLAG_BUS_SHIFT_2 | + OMAP_I2C_FLAG_FORCE_19200_INT_CLK, +}; + +/* I2C1 */ + +static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { + &omap2430_l4_core__i2c1, +}; + +static struct omap_hwmod omap2430_i2c1_hwmod = { + .name = "i2c1", + .flags = HWMOD_16BIT_REG, + .mpu_irqs = omap2_i2c1_mpu_irqs, + .sdma_reqs = omap2_i2c1_sdma_reqs, + .main_clk = "i2chs1_fck", + .prcm = { + .omap2 = { + /* + * NOTE: The CM_FCLKEN* and CM_ICLKEN* for + * I2CHS IP's do not follow the usual pattern. + * prcm_reg_id alone cannot be used to program + * the iclk and fclk. Needs to be handled using + * additional flags when clk handling is moved + * to hwmod framework. + */ + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, + }, + }, + .slaves = omap2430_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, +}; + +/* I2C2 */ + +static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { + &omap2430_l4_core__i2c2, +}; + +static struct omap_hwmod omap2430_i2c2_hwmod = { + .name = "i2c2", + .flags = HWMOD_16BIT_REG, + .mpu_irqs = omap2_i2c2_mpu_irqs, + .sdma_reqs = omap2_i2c2_sdma_reqs, + .main_clk = "i2chs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, + }, + }, + .slaves = omap2430_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { + { + .pa_start = 0x4900C000, + .pa_end = 0x4900C1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { + { + .pa_start = 0x4900E000, + .pa_end = 0x4900E1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { + { + .pa_start = 0x49010000, + .pa_end = 0x490101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { + { + .pa_start = 0x49012000, + .pa_end = 0x490121ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> gpio5 */ +static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { + { + .pa_start = 0x480B6000, + .pa_end = 0x480B61ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap2430_gpio5_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, +}; + +/* gpio1 */ +static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { + &omap2430_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap2430_gpio1_hwmod = { + .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio1_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* gpio2 */ +static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { + &omap2430_l4_wkup__gpio2, +}; + +static struct omap_hwmod omap2430_gpio2_hwmod = { + .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio2_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* gpio3 */ +static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { + &omap2430_l4_wkup__gpio3, +}; + +static struct omap_hwmod omap2430_gpio3_hwmod = { + .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio3_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* gpio4 */ +static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { + &omap2430_l4_wkup__gpio4, +}; + +static struct omap_hwmod omap2430_gpio4_hwmod = { + .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio4_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* gpio5 */ +static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { + { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ + { .irq = -1 } +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { + &omap2430_l4_core__gpio5, +}; + +static struct omap_hwmod omap2430_gpio5_hwmod = { + .name = "gpio5", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap243x_gpio5_irqs, + .main_clk = "gpio5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_GPIO5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, + }, + }, + .slaves = omap2430_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { + .master = &omap2430_dma_system_hwmod, + .slave = &omap2430_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { + &omap2430_dma_system__l3, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { + &omap2430_l4_core__dma_system, +}; + +static struct omap_hwmod omap2430_dma_system_hwmod = { + .name = "dma", + .class = &omap2xxx_dma_hwmod_class, + .mpu_irqs = omap2_dma_system_irqs, + .main_clk = "core_l3_ck", + .slaves = omap2430_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), + .masters = omap2430_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), + .dev_attr = &dma_dev_attr, + .flags = HWMOD_NO_IDLEST, +}; + +/* mailbox */ +static struct omap_hwmod omap2430_mailbox_hwmod; +static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { + { .irq = 26 }, + { .irq = -1 } +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mailbox_hwmod, + .addr = omap2_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { + &omap2430_l4_core__mailbox, +}; + +static struct omap_hwmod omap2430_mailbox_hwmod = { + .name = "mailbox", + .class = &omap2xxx_mailbox_hwmod_class, + .mpu_irqs = omap2430_mailbox_irqs, + .main_clk = "mailboxes_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, + }, + }, + .slaves = omap2430_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), +}; + +/* mcspi1 */ +static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { + &omap2430_l4_core__mcspi1, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap2430_mcspi1_hwmod = { + .name = "mcspi1_hwmod", + .mpu_irqs = omap2_mcspi1_mpu_irqs, + .sdma_reqs = omap2_mcspi1_sdma_reqs, + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, + }, + }, + .slaves = omap2430_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, +}; + +/* mcspi2 */ +static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { + &omap2430_l4_core__mcspi2, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2430_mcspi2_hwmod = { + .name = "mcspi2_hwmod", + .mpu_irqs = omap2_mcspi2_mpu_irqs, + .sdma_reqs = omap2_mcspi2_sdma_reqs, + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, + }, + }, + .slaves = omap2430_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, +}; + +/* mcspi3 */ +static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { + { .irq = 91 }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { + { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ + { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ + { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ + { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ + { .dma_req = -1 } +}; + +static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { + &omap2430_l4_core__mcspi3, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2430_mcspi3_hwmod = { + .name = "mcspi3_hwmod", + .mpu_irqs = omap2430_mcspi3_mpu_irqs, + .sdma_reqs = omap2430_mcspi3_sdma_reqs, + .main_clk = "mcspi3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MCSPI3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, + }, + }, + .slaves = omap2430_mcspi3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi3_dev_attr, +}; + +/* + * usbhsotg + */ +static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap2430_usbhsotg_sysc, +}; + +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { + + { .name = "mc", .irq = 92 }, + { .name = "dma", .irq = 93 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap2430_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .mpu_irqs = omap2430_usbhsotg_mpu_irqs, + .main_clk = "usbhs_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_USBHS_MASK, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, + }, + }, + .masters = omap2430_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), + .slaves = omap2430_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), + .class = &usbotg_class, + /* + * Erratum ID: i479 idle_req / idle_ack mechanism potentially + * broken when autoidle is enabled + * workaround is to disable the autoidle bit at module level. + */ + .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE + | HWMOD_SWSUP_MSTANDBY, +}; + +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { + .rev_offs = 0x007C, + .sysc_offs = 0x008C, + .sysc_flags = (SYSC_HAS_SOFTRESET), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap2430_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE2, +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .name = "ovr", .irq = 61 }, + { .name = "common", .irq = 64 }, + { .irq = -1 } +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { + &omap2430_l4_core__mcbsp1, +}; + +static struct omap_hwmod omap2430_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp1_irqs, + .sdma_reqs = omap2_mcbsp1_sdma_reqs, + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + }, + }, + .slaves = omap2430_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), +}; + +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, + { .name = "common", .irq = 16 }, + { .irq = -1 } }; /* l4_core -> mcbsp2 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { - .master = &omap2xxx_l4_core_hwmod, + .master = &omap2430_l4_core_hwmod, .slave = &omap2430_mcbsp2_hwmod, .clk = "mcbsp2_ick", .addr = omap2xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { + &omap2430_l4_core__mcbsp2, +}; + +static struct omap_hwmod omap2430_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp2_irqs, + .sdma_reqs = omap2_mcbsp2_sdma_reqs, + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap2430_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), +}; + +/* mcbsp3 */ +static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { + { .name = "tx", .irq = 89 }, + { .name = "rx", .irq = 90 }, + { .name = "common", .irq = 17 }, + { .irq = -1 } +}; + static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { { .name = "mpu", @@ -793,13 +1746,51 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { /* l4_core -> mcbsp3 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { - .master = &omap2xxx_l4_core_hwmod, + .master = &omap2430_l4_core_hwmod, .slave = &omap2430_mcbsp3_hwmod, .clk = "mcbsp3_ick", .addr = omap2430_mcbsp3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { + &omap2430_l4_core__mcbsp3, +}; + +static struct omap_hwmod omap2430_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp3_irqs, + .sdma_reqs = omap2_mcbsp3_sdma_reqs, + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap2430_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), +}; + +/* mcbsp4 */ +static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { + { .name = "tx", .irq = 54 }, + { .name = "rx", .irq = 55 }, + { .name = "common", .irq = 18 }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { + { .name = "rx", .dma_req = 20 }, + { .name = "tx", .dma_req = 19 }, + { .dma_req = -1 } +}; + static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { { .name = "mpu", @@ -812,13 +1803,51 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { /* l4_core -> mcbsp4 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { - .master = &omap2xxx_l4_core_hwmod, + .master = &omap2430_l4_core_hwmod, .slave = &omap2430_mcbsp4_hwmod, .clk = "mcbsp4_ick", .addr = omap2430_mcbsp4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { + &omap2430_l4_core__mcbsp4, +}; + +static struct omap_hwmod omap2430_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp4_irqs, + .sdma_reqs = omap2430_mcbsp4_sdma_chs, + .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, + }, + }, + .slaves = omap2430_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), +}; + +/* mcbsp5 */ +static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { + { .name = "tx", .irq = 81 }, + { .name = "rx", .irq = 82 }, + { .name = "common", .irq = 19 }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { + { .name = "rx", .dma_req = 22 }, + { .name = "tx", .dma_req = 21 }, + { .dma_req = -1 } +}; + static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { { .name = "mpu", @@ -831,65 +1860,213 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { /* l4_core -> mcbsp5 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { - .master = &omap2xxx_l4_core_hwmod, + .master = &omap2430_l4_core_hwmod, .slave = &omap2430_mcbsp5_hwmod, .clk = "mcbsp5_ick", .addr = omap2430_mcbsp5_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { - &omap2xxx_l3_main__l4_core, - &omap2xxx_mpu__l3_main, - &omap2xxx_dss__l3, - &omap2430_usbhsotg__l3, - &omap2430_l4_core__i2c1, - &omap2430_l4_core__i2c2, - &omap2xxx_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, - &omap2430_l4_core__usbhsotg, +/* mcbsp5 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { + &omap2430_l4_core__mcbsp5, +}; + +static struct omap_hwmod omap2430_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp5_irqs, + .sdma_reqs = omap2430_mcbsp5_sdma_chs, + .main_clk = "mcbsp5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, + }, + }, + .slaves = omap2430_mcbsp5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), +}; + +/* MMC/SD/SDIO common */ + +static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mmc_class = { + .name = "mmc", + .sysc = &omap2430_mmc_sysc, +}; + +/* MMC/SD/SDIO1 */ + +static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { + { .irq = 83 }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { + { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ + { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ + { .dma_req = -1 } +}; + +static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { + { .role = "dbck", .clk = "mmchsdb1_fck" }, +}; + +static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { &omap2430_l4_core__mmc1, +}; + +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod omap2430_mmc1_hwmod = { + .name = "mmc1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2430_mmc1_mpu_irqs, + .sdma_reqs = omap2430_mmc1_sdma_reqs, + .opt_clks = omap2430_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MMCHS1_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, + }, + }, + .dev_attr = &mmc1_dev_attr, + .slaves = omap2430_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), + .class = &omap2430_mmc_class, +}; + +/* MMC/SD/SDIO2 */ + +static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { + { .irq = 86 }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { + { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ + { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ + { .dma_req = -1 } +}; + +static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { + { .role = "dbck", .clk = "mmchsdb2_fck" }, +}; + +static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { &omap2430_l4_core__mmc2, - &omap2xxx_l4_core__mcspi1, - &omap2xxx_l4_core__mcspi2, - &omap2430_l4_core__mcspi3, - &omap2430_l3__iva, - &omap2430_l4_wkup__timer1, - &omap2xxx_l4_core__timer2, - &omap2xxx_l4_core__timer3, - &omap2xxx_l4_core__timer4, - &omap2xxx_l4_core__timer5, - &omap2xxx_l4_core__timer6, - &omap2xxx_l4_core__timer7, - &omap2xxx_l4_core__timer8, - &omap2xxx_l4_core__timer9, - &omap2xxx_l4_core__timer10, - &omap2xxx_l4_core__timer11, - &omap2xxx_l4_core__timer12, - &omap2430_l4_wkup__wd_timer2, - &omap2xxx_l4_core__dss, - &omap2xxx_l4_core__dss_dispc, - &omap2xxx_l4_core__dss_rfbi, - &omap2xxx_l4_core__dss_venc, - &omap2430_l4_wkup__gpio1, - &omap2430_l4_wkup__gpio2, - &omap2430_l4_wkup__gpio3, - &omap2430_l4_wkup__gpio4, - &omap2430_l4_core__gpio5, - &omap2430_dma_system__l3, - &omap2430_l4_core__dma_system, - &omap2430_l4_core__mailbox, - &omap2430_l4_core__mcbsp1, - &omap2430_l4_core__mcbsp2, - &omap2430_l4_core__mcbsp3, - &omap2430_l4_core__mcbsp4, - &omap2430_l4_core__mcbsp5, +}; + +static struct omap_hwmod omap2430_mmc2_hwmod = { + .name = "mmc2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2430_mmc2_mpu_irqs, + .sdma_reqs = omap2430_mmc2_sdma_reqs, + .opt_clks = omap2430_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MMCHS2_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, + }, + }, + .slaves = omap2430_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), + .class = &omap2430_mmc_class, +}; + +static __initdata struct omap_hwmod *omap2430_hwmods[] = { + &omap2430_l3_main_hwmod, + &omap2430_l4_core_hwmod, + &omap2430_l4_wkup_hwmod, + &omap2430_mpu_hwmod, + &omap2430_iva_hwmod, + + &omap2430_timer1_hwmod, + &omap2430_timer2_hwmod, + &omap2430_timer3_hwmod, + &omap2430_timer4_hwmod, + &omap2430_timer5_hwmod, + &omap2430_timer6_hwmod, + &omap2430_timer7_hwmod, + &omap2430_timer8_hwmod, + &omap2430_timer9_hwmod, + &omap2430_timer10_hwmod, + &omap2430_timer11_hwmod, + &omap2430_timer12_hwmod, + + &omap2430_wd_timer2_hwmod, + &omap2430_uart1_hwmod, + &omap2430_uart2_hwmod, + &omap2430_uart3_hwmod, + /* dss class */ + &omap2430_dss_core_hwmod, + &omap2430_dss_dispc_hwmod, + &omap2430_dss_rfbi_hwmod, + &omap2430_dss_venc_hwmod, + /* i2c class */ + &omap2430_i2c1_hwmod, + &omap2430_i2c2_hwmod, + &omap2430_mmc1_hwmod, + &omap2430_mmc2_hwmod, + + /* gpio class */ + &omap2430_gpio1_hwmod, + &omap2430_gpio2_hwmod, + &omap2430_gpio3_hwmod, + &omap2430_gpio4_hwmod, + &omap2430_gpio5_hwmod, + + /* dma_system class*/ + &omap2430_dma_system_hwmod, + + /* mcbsp class */ + &omap2430_mcbsp1_hwmod, + &omap2430_mcbsp2_hwmod, + &omap2430_mcbsp3_hwmod, + &omap2430_mcbsp4_hwmod, + &omap2430_mcbsp5_hwmod, + + /* mailbox class */ + &omap2430_mailbox_hwmod, + + /* mcspi class */ + &omap2430_mcspi1_hwmod, + &omap2430_mcspi2_hwmod, + &omap2430_mcspi3_hwmod, + + /* usbotg class*/ + &omap2430_usbhsotg_hwmod, + NULL, }; int __init omap2430_hwmod_init(void) { - return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); + return omap_hwmod_register(omap2430_hwmods); } diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 5178e40e84f9..4f3547c2a49e 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -15,12 +15,10 @@ #include #include -#include -#include #include "omap_hwmod_common_data.h" -static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { +struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { { .pa_start = OMAP2_UART1_BASE, .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, @@ -29,7 +27,7 @@ static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { +struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { { .pa_start = OMAP2_UART2_BASE, .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, @@ -38,7 +36,7 @@ static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { +struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { { .pa_start = OMAP2_UART3_BASE, .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, @@ -47,7 +45,7 @@ static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { +struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { { .pa_start = 0x4802a000, .pa_end = 0x4802a000 + SZ_1K - 1, @@ -56,7 +54,7 @@ static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { +struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { { .pa_start = 0x48078000, .pa_end = 0x48078000 + SZ_1K - 1, @@ -65,7 +63,7 @@ static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { +struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { { .pa_start = 0x4807a000, .pa_end = 0x4807a000 + SZ_1K - 1, @@ -74,7 +72,7 @@ static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { +struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { { .pa_start = 0x4807c000, .pa_end = 0x4807c000 + SZ_1K - 1, @@ -83,7 +81,7 @@ static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { +struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { { .pa_start = 0x4807e000, .pa_end = 0x4807e000 + SZ_1K - 1, @@ -92,7 +90,7 @@ static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { +struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { { .pa_start = 0x48080000, .pa_end = 0x48080000 + SZ_1K - 1, @@ -101,7 +99,7 @@ static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { +struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { { .pa_start = 0x48082000, .pa_end = 0x48082000 + SZ_1K - 1, @@ -110,7 +108,7 @@ static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { { } }; -static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { +struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { { .pa_start = 0x48084000, .pa_end = 0x48084000 + SZ_1K - 1, @@ -129,246 +127,4 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { { } }; -/* - * Common interconnect data - */ - -/* L3 -> L4_CORE interface */ -struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = { - .master = &omap2xxx_l3_main_hwmod, - .slave = &omap2xxx_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* MPU -> L3 interface */ -struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = { - .master = &omap2xxx_mpu_hwmod, - .slave = &omap2xxx_l3_main_hwmod, - .user = OCP_USER_MPU, -}; - -/* DSS -> l3 */ -struct omap_hwmod_ocp_if omap2xxx_dss__l3 = { - .master = &omap2xxx_dss_core_hwmod, - .slave = &omap2xxx_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4_CORE -> L4_WKUP interface */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART1 interface */ -struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi1 interface */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_mcspi1_hwmod, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_mcspi2_hwmod, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer2 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer3 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer4 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer5 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer6 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer7 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer8 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer9 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer10 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer11 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> timer12 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> dss */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> dss_dispc */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> dss_rfbi */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> dss_venc */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .flags = OCPIF_SWSUP_IDLE, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 45aaa07e3025..2a6729741b06 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -10,7 +10,6 @@ */ #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include "omap_hwmod_common_data.h" -#include "cm-regbits-24xx.h" -#include "prm-regbits-24xx.h" #include "wd_timer.h" struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { @@ -173,562 +170,3 @@ struct omap_hwmod_class omap2xxx_mcspi_class = { .sysc = &omap2xxx_mcspi_sysc, .rev = OMAP2_MCSPI_REV, }; - -/* - * IP blocks - */ - -/* L3 */ -struct omap_hwmod omap2xxx_l3_main_hwmod = { - .name = "l3_main", - .class = &l3_hwmod_class, - .flags = HWMOD_NO_IDLEST, -}; - -/* L4 CORE */ -struct omap_hwmod omap2xxx_l4_core_hwmod = { - .name = "l4_core", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, -}; - -/* L4 WKUP */ -struct omap_hwmod omap2xxx_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, -}; - -/* MPU */ -struct omap_hwmod omap2xxx_mpu_hwmod = { - .name = "mpu", - .class = &mpu_hwmod_class, - .main_clk = "mpu_ck", -}; - -/* IVA2 */ -struct omap_hwmod omap2xxx_iva_hwmod = { - .name = "iva", - .class = &iva_hwmod_class, -}; - -/* always-on timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, -}; - -/* pwm timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, -}; - -/* timer1 */ - -struct omap_hwmod omap2xxx_timer1_hwmod = { - .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer2 */ - -struct omap_hwmod omap2xxx_timer2_hwmod = { - .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, - .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT2_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer3 */ - -struct omap_hwmod omap2xxx_timer3_hwmod = { - .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, - .main_clk = "gpt3_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT3_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer4 */ - -struct omap_hwmod omap2xxx_timer4_hwmod = { - .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, - .main_clk = "gpt4_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT4_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer5 */ - -struct omap_hwmod omap2xxx_timer5_hwmod = { - .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, - .main_clk = "gpt5_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT5_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer6 */ - -struct omap_hwmod omap2xxx_timer6_hwmod = { - .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, - .main_clk = "gpt6_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT6_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer7 */ - -struct omap_hwmod omap2xxx_timer7_hwmod = { - .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, - .main_clk = "gpt7_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT7_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer8 */ - -struct omap_hwmod omap2xxx_timer8_hwmod = { - .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, - .main_clk = "gpt8_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT8_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer9 */ - -struct omap_hwmod omap2xxx_timer9_hwmod = { - .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, - .main_clk = "gpt9_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT9_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer10 */ - -struct omap_hwmod omap2xxx_timer10_hwmod = { - .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, - .main_clk = "gpt10_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT10_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer11 */ - -struct omap_hwmod omap2xxx_timer11_hwmod = { - .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, - .main_clk = "gpt11_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT11_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer12 */ - -struct omap_hwmod omap2xxx_timer12_hwmod = { - .name = "timer12", - .mpu_irqs = omap2xxx_timer12_mpu_irqs, - .main_clk = "gpt12_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT12_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap2xxx_timer_hwmod_class, -}; - -/* wd_timer2 */ -struct omap_hwmod omap2xxx_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap2xxx_wd_timer_hwmod_class, - .main_clk = "mpu_wdt_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, - }, - }, -}; - -/* UART1 */ - -struct omap_hwmod omap2xxx_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, - }, - }, - .class = &omap2_uart_class, -}; - -/* UART2 */ - -struct omap_hwmod omap2xxx_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, - }, - }, - .class = &omap2_uart_class, -}; - -/* UART3 */ - -struct omap_hwmod omap2xxx_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, - .class = &omap2_uart_class, -}; - -/* dss */ - -static struct omap_hwmod_opt_clk dss_opt_clks[] = { - /* - * The DSS HW needs all DSS clocks enabled during reset. The dss_core - * driver does not use these clocks. - */ - { .role = "tv_clk", .clk = "dss_54m_fck" }, - { .role = "sys_clk", .clk = "dss2_fck" }, -}; - -struct omap_hwmod omap2xxx_dss_core_hwmod = { - .name = "dss_core", - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_fck", /* instead of dss_fck */ - .sdma_reqs = omap2xxx_dss_sdma_chs, - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, -}; - -struct omap_hwmod omap2xxx_dss_dispc_hwmod = { - .name = "dss_dispc", - .class = &omap2_dispc_hwmod_class, - .mpu_irqs = omap2_dispc_irqs, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr -}; - -static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { - { .role = "ick", .clk = "dss_ick" }, -}; - -struct omap_hwmod omap2xxx_dss_rfbi_hwmod = { - .name = "dss_rfbi", - .class = &omap2_rfbi_hwmod_class, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .opt_clks = dss_rfbi_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .flags = HWMOD_NO_IDLEST, -}; - -struct omap_hwmod omap2xxx_dss_venc_hwmod = { - .name = "dss_venc", - .class = &omap2_venc_hwmod_class, - .main_clk = "dss_54m_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .flags = HWMOD_NO_IDLEST, -}; - -/* gpio dev_attr */ -struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = false, -}; - -/* gpio1 */ -struct omap_hwmod omap2xxx_gpio1_hwmod = { - .name = "gpio1", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, -}; - -/* gpio2 */ -struct omap_hwmod omap2xxx_gpio2_hwmod = { - .name = "gpio2", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, -}; - -/* gpio3 */ -struct omap_hwmod omap2xxx_gpio3_hwmod = { - .name = "gpio3", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, -}; - -/* gpio4 */ -struct omap_hwmod omap2xxx_gpio4_hwmod = { - .name = "gpio4", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, -}; - -/* mcspi1 */ -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - -struct omap_hwmod omap2xxx_mcspi1_hwmod = { - .name = "mcspi1", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, - .main_clk = "mcspi1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, - }, - }, - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, -}; - -/* mcspi2 */ -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - -struct omap_hwmod omap2xxx_mcspi2_hwmod = { - .name = "mcspi2", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, - .main_clk = "mcspi2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, - }, - }, - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, -}; diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 43d288066d06..db86ce90c69f 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -2,7 +2,6 @@ * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips * * Copyright (C) 2009-2011 Nokia Corporation - * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -39,2973 +38,3302 @@ /* * OMAP3xxx hardware module integration data * - * All of the data in this section should be autogeneratable from the + * ALl of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -/* - * IP blocks - */ +static struct omap_hwmod omap3xxx_mpu_hwmod; +static struct omap_hwmod omap3xxx_iva_hwmod; +static struct omap_hwmod omap3xxx_l3_main_hwmod; +static struct omap_hwmod omap3xxx_l4_core_hwmod; +static struct omap_hwmod omap3xxx_l4_per_hwmod; +static struct omap_hwmod omap3xxx_wd_timer2_hwmod; +static struct omap_hwmod omap3430es1_dss_core_hwmod; +static struct omap_hwmod omap3xxx_dss_core_hwmod; +static struct omap_hwmod omap3xxx_dss_dispc_hwmod; +static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; +static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; +static struct omap_hwmod omap3xxx_dss_venc_hwmod; +static struct omap_hwmod omap3xxx_i2c1_hwmod; +static struct omap_hwmod omap3xxx_i2c2_hwmod; +static struct omap_hwmod omap3xxx_i2c3_hwmod; +static struct omap_hwmod omap3xxx_gpio1_hwmod; +static struct omap_hwmod omap3xxx_gpio2_hwmod; +static struct omap_hwmod omap3xxx_gpio3_hwmod; +static struct omap_hwmod omap3xxx_gpio4_hwmod; +static struct omap_hwmod omap3xxx_gpio5_hwmod; +static struct omap_hwmod omap3xxx_gpio6_hwmod; +static struct omap_hwmod omap34xx_sr1_hwmod; +static struct omap_hwmod omap34xx_sr2_hwmod; +static struct omap_hwmod omap34xx_mcspi1; +static struct omap_hwmod omap34xx_mcspi2; +static struct omap_hwmod omap34xx_mcspi3; +static struct omap_hwmod omap34xx_mcspi4; +static struct omap_hwmod omap3xxx_mmc1_hwmod; +static struct omap_hwmod omap3xxx_mmc2_hwmod; +static struct omap_hwmod omap3xxx_mmc3_hwmod; +static struct omap_hwmod am35xx_usbhsotg_hwmod; + +static struct omap_hwmod omap3xxx_dma_system_hwmod; + +static struct omap_hwmod omap3xxx_mcbsp1_hwmod; +static struct omap_hwmod omap3xxx_mcbsp2_hwmod; +static struct omap_hwmod omap3xxx_mcbsp3_hwmod; +static struct omap_hwmod omap3xxx_mcbsp4_hwmod; +static struct omap_hwmod omap3xxx_mcbsp5_hwmod; +static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; +static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; +static struct omap_hwmod omap3xxx_usb_host_hs_hwmod; +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod; -/* L3 */ +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L3 -> L4_PER interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_l4_per_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L3 taret configuration and error log registers */ static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { { .irq = INT_34XX_L3_DBG_IRQ }, { .irq = INT_34XX_L3_APP_IRQ }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { + { + .pa_start = 0x68000000, + .pa_end = 0x6800ffff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { + .master = &omap3xxx_mpu_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .addr = omap3xxx_l3_main_addrs, + .user = OCP_USER_MPU, +}; + +/* Slave interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { + &omap3xxx_mpu__l3_main, +}; + +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { + .master = &omap3xxx_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* Master interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { + &omap3xxx_l3_main__l4_core, + &omap3xxx_l3_main__l4_per, +}; + +/* L3 */ static struct omap_hwmod omap3xxx_l3_main_hwmod = { .name = "l3_main", .class = &l3_hwmod_class, .mpu_irqs = omap3xxx_l3_main_irqs, + .masters = omap3xxx_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), + .slaves = omap3xxx_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), .flags = HWMOD_NO_IDLEST, }; -/* L4 CORE */ -static struct omap_hwmod omap3xxx_l4_core_hwmod = { - .name = "l4_core", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, +static struct omap_hwmod omap3xxx_l4_wkup_hwmod; +static struct omap_hwmod omap3xxx_uart1_hwmod; +static struct omap_hwmod omap3xxx_uart2_hwmod; +static struct omap_hwmod omap3xxx_uart3_hwmod; +static struct omap_hwmod omap3xxx_uart4_hwmod; +static struct omap_hwmod am35xx_uart4_hwmod; +static struct omap_hwmod omap3xxx_usbhsotg_hwmod; + +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { + .master = &omap3xxx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, }; -/* L4 PER */ -static struct omap_hwmod omap3xxx_l4_per_hwmod = { - .name = "l4_per", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, +/* l3_core -> am35xx_usbhsotg interface */ +static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { + .master = &am35xx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 WKUP */ -static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 }; -/* L4 SEC */ -static struct omap_hwmod omap3xxx_l4_sec_hwmod = { - .name = "l4_sec", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 }; -/* MPU */ -static struct omap_hwmod omap3xxx_mpu_hwmod = { - .name = "mpu", - .class = &mpu_hwmod_class, - .main_clk = "arm_fck", +/* L4 CORE -> MMC3 interface */ +static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad1ff, + .flags = ADDR_TYPE_RT, + }, + { } }; -/* IVA2 (IVA2) */ -static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { - { .name = "logic", .rst_shift = 0 }, - { .name = "seq0", .rst_shift = 1 }, - { .name = "seq1", .rst_shift = 2 }, +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc3_hwmod, + .clk = "mmchs3_ick", + .addr = omap3xxx_mmc3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 }; -static struct omap_hwmod omap3xxx_iva_hwmod = { - .name = "iva", - .class = &iva_hwmod_class, - .clkdm_name = "iva2_clkdm", - .rst_lines = omap3xxx_iva_resets, - .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), - .main_clk = "iva2_ck", +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { + { + .pa_start = OMAP3_UART1_BASE, + .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } }; -/* timer class */ -static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap3xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { - .name = "timer", - .sysc = &omap3xxx_timer_1ms_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { + { + .pa_start = OMAP3_UART2_BASE, + .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } }; -static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap3xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { - .name = "timer", - .sysc = &omap3xxx_timer_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { + { + .pa_start = OMAP3_UART3_BASE, + .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } }; -/* secure timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { - .timer_capability = OMAP_TIMER_SECURE, +static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap3xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* always-on timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, +/* L4 PER -> UART4 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_BASE, + .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } }; -/* pwm timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, +static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_uart4_hwmod, + .clk = "uart4_ick", + .addr = omap3xxx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer1 */ -static struct omap_hwmod omap3xxx_timer1_hwmod = { - .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, - }, +/* AM35xx: L4 CORE -> UART4 interface */ +static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_AM35XX_BASE, + .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_1ms_hwmod_class, }; -/* timer2 */ -static struct omap_hwmod omap3xxx_timer2_hwmod = { - .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, - .main_clk = "gpt2_fck", - .prcm = { +static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = am35xx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .fw = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT2_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, - }, + .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_1ms_hwmod_class, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer3 */ -static struct omap_hwmod omap3xxx_timer3_hwmod = { - .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, - .main_clk = "gpt3_fck", - .prcm = { +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .fw = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT3_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, - }, + .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer4 */ -static struct omap_hwmod omap3xxx_timer4_hwmod = { - .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, - .main_clk = "gpt4_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT4_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, - }, +/* L4 CORE -> I2C3 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x48060000 + SZ_128 - 1, + .flags = ADDR_TYPE_RT, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + { } }; -/* timer5 */ -static struct omap_hwmod omap3xxx_timer5_hwmod = { - .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, - .main_clk = "gpt5_fck", - .prcm = { +static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c3_hwmod, + .clk = "i2c3_ick", + .addr = omap3xxx_i2c3_addr_space, + .fw = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT5_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, - }, + .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer6 */ -static struct omap_hwmod omap3xxx_timer6_hwmod = { - .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, - .main_clk = "gpt6_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT6_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, +static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { + { .irq = 18}, + { .irq = -1 } }; -/* timer7 */ -static struct omap_hwmod omap3xxx_timer7_hwmod = { - .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, - .main_clk = "gpt7_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT7_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, +static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { + { .irq = 19}, + { .irq = -1 } }; -/* timer8 */ -static struct omap_hwmod omap3xxx_timer8_hwmod = { - .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, - .main_clk = "gpt8_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT8_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, - }, +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { + { + .pa_start = OMAP34XX_SR1_BASE, + .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + { } }; -/* timer9 */ -static struct omap_hwmod omap3xxx_timer9_hwmod = { - .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, - .main_clk = "gpt9_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT9_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_hwmod_class, +static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .user = OCP_USER_MPU, }; -/* timer10 */ -static struct omap_hwmod omap3xxx_timer10_hwmod = { - .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, - .main_clk = "gpt10_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT10_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, - }, +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { + { + .pa_start = OMAP34XX_SR2_BASE, + .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_1ms_hwmod_class, + { } }; -/* timer11 */ -static struct omap_hwmod omap3xxx_timer11_hwmod = { - .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, - .main_clk = "gpt11_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT11_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, - }, +static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .user = OCP_USER_MPU, +}; + +/* +* usbhsotg interface data +*/ + +static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { + { + .pa_start = OMAP34XX_HSUSB_OTG_BASE, + .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + { } }; -/* timer12 */ -static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { - { .irq = 95, }, - { .irq = -1 } +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = omap3xxx_usbhsotg_addrs, + .user = OCP_USER_MPU, }; -static struct omap_hwmod omap3xxx_timer12_hwmod = { - .name = "timer12", - .mpu_irqs = omap3xxx_timer12_mpu_irqs, - .main_clk = "gpt12_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT12_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, - }, +static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { + &omap3xxx_usbhsotg__l3, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { + &omap3xxx_l4_core__usbhsotg, +}; + +static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { + { + .pa_start = AM35XX_IPSS_USBOTGSS_BASE, + .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT }, - .dev_attr = &capability_secure_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + { } }; -/* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition - */ +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = am35xx_usbhsotg_addrs, + .user = OCP_USER_MPU, +}; -static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { + &am35xx_usbhsotg__l3, +}; + +static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { + &am35xx_l4_core__usbhsotg, +}; +/* Slave interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { + &omap3xxx_l3_main__l4_core, +}; + +/* L4 CORE */ +static struct omap_hwmod omap3xxx_l4_core_hwmod = { + .name = "l4_core", + .class = &l4_hwmod_class, + .slaves = omap3xxx_l4_core_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), + .flags = HWMOD_NO_IDLEST, }; -/* I2C common */ -static struct omap_hwmod_class_sysconfig i2c_sysc = { - .rev_offs = 0x00, - .sysc_offs = 0x20, - .syss_offs = 0x10, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .clockact = CLOCKACT_TEST_ICLK, - .sysc_fields = &omap_hwmod_sysc_type1, +/* Slave interfaces on the L4_PER interconnect */ +static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { + &omap3xxx_l3_main__l4_per, }; -static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap3xxx_wd_timer_sysc, - .pre_shutdown = &omap2_wd_timer_disable +/* L4 PER */ +static struct omap_hwmod omap3xxx_l4_per_hwmod = { + .name = "l4_per", + .class = &l4_hwmod_class, + .slaves = omap3xxx_l4_per_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), + .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap3xxx_wd_timer_hwmod_class, - .main_clk = "wdt2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_WDT2_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, - }, - }, - /* - * XXX: Use software supervised mode, HW supervised smartidle seems to - * block CORE power domain idle transitions. Maybe a HW bug in wdt2? - */ - .flags = HWMOD_SWSUP_SIDLE, +/* Slave interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { + &omap3xxx_l4_core__l4_wkup, }; -/* UART1 */ -static struct omap_hwmod omap3xxx_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, - }, - }, - .class = &omap2_uart_class, +/* L4 WKUP */ +static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &l4_hwmod_class, + .slaves = omap3xxx_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), + .flags = HWMOD_NO_IDLEST, }; -/* UART2 */ -static struct omap_hwmod omap3xxx_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, - }, - }, - .class = &omap2_uart_class, +/* Master interfaces on the MPU device */ +static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { + &omap3xxx_mpu__l3_main, }; -/* UART3 */ -static struct omap_hwmod omap3xxx_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = OMAP3430_PER_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART3_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, - }, - }, - .class = &omap2_uart_class, +/* MPU */ +static struct omap_hwmod omap3xxx_mpu_hwmod = { + .name = "mpu", + .class = &mpu_hwmod_class, + .main_clk = "arm_fck", + .masters = omap3xxx_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), }; -/* UART4 */ -static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { - { .irq = INT_36XX_UART4_IRQ, }, - { .irq = -1 } +/* + * IVA2_2 interface data + */ + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_iva_hwmod, + .clk = "iva2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, - { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, - { .dma_req = -1 } +static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { + &omap3xxx_l3__iva, }; -static struct omap_hwmod omap36xx_uart4_hwmod = { - .name = "uart4", - .mpu_irqs = uart4_mpu_irqs, - .sdma_reqs = uart4_sdma_reqs, - .main_clk = "uart4_fck", - .prcm = { - .omap2 = { - .module_offs = OMAP3430_PER_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3630_EN_UART4_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, - }, - }, - .class = &omap2_uart_class, +/* + * IVA2 (IVA2) + */ + +static struct omap_hwmod omap3xxx_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .masters = omap3xxx_iva_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), }; -static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { - { .irq = INT_35XX_UART4_IRQ, }, +/* timer class */ +static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { - { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, - { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, +static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { + .name = "timer", + .sysc = &omap3xxx_timer_1ms_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, }; -static struct omap_hwmod am35xx_uart4_hwmod = { - .name = "uart4", - .mpu_irqs = am35xx_uart4_mpu_irqs, - .sdma_reqs = am35xx_uart4_sdma_reqs, - .main_clk = "uart4_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART4_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, - }, - }, - .class = &omap2_uart_class, +static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class i2c_class = { - .name = "i2c", - .sysc = &i2c_sysc, - .rev = OMAP_I2C_IP_VERSION_1, - .reset = &omap_i2c_reset, +static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { + .name = "timer", + .sysc = &omap3xxx_timer_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, }; -static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { - { .name = "dispc", .dma_req = 5 }, - { .name = "dsi1", .dma_req = 74 }, - { .dma_req = -1 } +/* secure timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { + .timer_capability = OMAP_TIMER_SECURE, }; -/* dss */ -static struct omap_hwmod_opt_clk dss_opt_clks[] = { - /* - * The DSS HW needs all DSS clocks enabled during reset. The dss_core - * driver does not use these clocks. - */ - { .role = "sys_clk", .clk = "dss2_alwon_fck" }, - { .role = "tv_clk", .clk = "dss_tv_fck" }, - /* required only on OMAP3430 */ - { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, }; -static struct omap_hwmod omap3430es1_dss_core_hwmod = { - .name = "dss_core", - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .sdma_reqs = omap3xxx_dss_sdma_chs, - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, - }, +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, +}; + +/* timer1 */ +static struct omap_hwmod omap3xxx_timer1_hwmod; + +static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { + { + .pa_start = 0x48318000, + .pa_end = 0x48318000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, + { } }; -static struct omap_hwmod omap3xxx_dss_core_hwmod = { - .name = "dss_core", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .sdma_reqs = omap3xxx_dss_sdma_chs, +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap3xxx_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { + &omap3xxx_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap3xxx_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2_timer1_mpu_irqs, + .main_clk = "gpt1_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, }, }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap3xxx_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, }; -/* - * 'dispc' class - * display controller - */ +/* timer2 */ +static struct omap_hwmod omap3xxx_timer2_hwmod; -static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSC_HAS_ENAWAKEUP), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x49032000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_class omap3_dispc_hwmod_class = { - .name = "dispc", - .sysc = &omap3_dispc_sysc, +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap3xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { - .name = "dss_dispc", - .class = &omap3_dispc_hwmod_class, - .mpu_irqs = omap2_dispc_irqs, - .main_clk = "dss1_alwon_fck", +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { + &omap3xxx_l4_per__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap3xxx_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2_timer2_mpu_irqs, + .main_clk = "gpt2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_GPT2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, }, }, - .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap3xxx_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, }; -/* - * 'dsi' class - * display serial interface controller - */ +/* timer3 */ +static struct omap_hwmod omap3xxx_timer3_hwmod; -static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { - .name = "dsi", +static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { + { + .pa_start = 0x49034000, + .pa_end = 0x49034000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { - { .irq = 25 }, - { .irq = -1 } +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap3xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dss_dsi1 */ -static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { - { .role = "sys_clk", .clk = "dss2_alwon_fck" }, +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { + &omap3xxx_l4_per__timer3, }; -static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { - .name = "dss_dsi1", - .class = &omap3xxx_dsi_hwmod_class, - .mpu_irqs = omap3xxx_dsi1_irqs, - .main_clk = "dss1_alwon_fck", +/* timer3 hwmod */ +static struct omap_hwmod omap3xxx_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2_timer3_mpu_irqs, + .main_clk = "gpt3_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_GPT3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, }, }, - .opt_clks = dss_dsi1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), - .flags = HWMOD_NO_IDLEST, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap3xxx_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { - { .role = "ick", .clk = "dss_ick" }, -}; +/* timer4 */ +static struct omap_hwmod omap3xxx_timer4_hwmod; -static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { - .name = "dss_rfbi", - .class = &omap2_rfbi_hwmod_class, - .main_clk = "dss1_alwon_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, - }, +static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { + { + .pa_start = 0x49036000, + .pa_end = 0x49036000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, - .opt_clks = dss_rfbi_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .flags = HWMOD_NO_IDLEST, + { } }; -static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { - /* required only on OMAP3430 */ - { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap3xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_dss_venc_hwmod = { - .name = "dss_venc", - .class = &omap2_venc_hwmod_class, - .main_clk = "dss_tv_fck", +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { + &omap3xxx_l4_per__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap3xxx_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2_timer4_mpu_irqs, + .main_clk = "gpt4_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_GPT4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, }, }, - .opt_clks = dss_venc_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), - .flags = HWMOD_NO_IDLEST, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap3xxx_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -/* I2C1 */ -static struct omap_i2c_dev_attr i2c1_dev_attr = { - .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, -}; +/* timer5 */ +static struct omap_hwmod omap3xxx_timer5_hwmod; -static struct omap_hwmod omap3xxx_i2c1_hwmod = { - .name = "i2c1", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, - .main_clk = "i2c1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x49038000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, - .class = &i2c_class, - .dev_attr = &i2c1_dev_attr, + { } }; -/* I2C2 */ -static struct omap_i2c_dev_attr i2c2_dev_attr = { - .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, +/* l4_per -> timer5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap3xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_i2c2_hwmod = { - .name = "i2c2", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, - .main_clk = "i2c2_fck", +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { + &omap3xxx_l4_per__timer5, +}; + +/* timer5 hwmod */ +static struct omap_hwmod omap3xxx_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2_timer5_mpu_irqs, + .main_clk = "gpt5_fck", .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C2_SHIFT, + .module_bit = OMAP3430_EN_GPT5_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, }, }, - .class = &i2c_class, - .dev_attr = &i2c2_dev_attr, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap3xxx_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -/* I2C3 */ -static struct omap_i2c_dev_attr i2c3_dev_attr = { - .fifo_depth = 64, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, +/* timer6 */ +static struct omap_hwmod omap3xxx_timer6_hwmod; + +static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { + { + .pa_start = 0x4903A000, + .pa_end = 0x4903A000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { - { .irq = INT_34XX_I2C3_IRQ, }, - { .irq = -1 } +/* l4_per -> timer6 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap3xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, - { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, - { .dma_req = -1 } +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { + &omap3xxx_l4_per__timer6, }; -static struct omap_hwmod omap3xxx_i2c3_hwmod = { - .name = "i2c3", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = i2c3_mpu_irqs, - .sdma_reqs = i2c3_sdma_reqs, - .main_clk = "i2c3_fck", +/* timer6 hwmod */ +static struct omap_hwmod omap3xxx_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2_timer6_mpu_irqs, + .main_clk = "gpt6_fck", .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C3_SHIFT, + .module_bit = OMAP3430_EN_GPT6_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, }, }, - .class = &i2c_class, - .dev_attr = &i2c3_dev_attr, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap3xxx_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -/* - * 'gpio' class - * general purpose io module - */ - -static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; +/* timer7 */ +static struct omap_hwmod omap3xxx_timer7_hwmod; -static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { - .name = "gpio", - .sysc = &omap3xxx_gpio_sysc, - .rev = 1, +static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { + { + .pa_start = 0x4903C000, + .pa_end = 0x4903C000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -/* gpio_dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, +/* l4_per -> timer7 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap3xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* gpio1 */ -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { - { .role = "dbclk", .clk = "gpio1_dbck", }, +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { + &omap3xxx_l4_per__timer7, }; -static struct omap_hwmod omap3xxx_gpio1_hwmod = { - .name = "gpio1", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, - .main_clk = "gpio1_ick", - .opt_clks = gpio1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), +/* timer7 hwmod */ +static struct omap_hwmod omap3xxx_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2_timer7_mpu_irqs, + .main_clk = "gpt7_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO1_SHIFT, - .module_offs = WKUP_MOD, + .module_bit = OMAP3430_EN_GPT7_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, }, }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .dev_attr = &capability_alwon_dev_attr, + .slaves = omap3xxx_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -/* gpio2 */ -static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { - { .role = "dbclk", .clk = "gpio2_dbck", }, -}; +/* timer8 */ +static struct omap_hwmod omap3xxx_timer8_hwmod; -static struct omap_hwmod omap3xxx_gpio2_hwmod = { - .name = "gpio2", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, - .main_clk = "gpio2_ick", - .opt_clks = gpio2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO2_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { + { + .pa_start = 0x4903E000, + .pa_end = 0x4903E000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + { } }; -/* gpio3 */ -static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { - { .role = "dbclk", .clk = "gpio3_dbck", }, +/* l4_per -> timer8 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap3xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_gpio3_hwmod = { - .name = "gpio3", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, - .main_clk = "gpio3_ick", - .opt_clks = gpio3_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { + &omap3xxx_l4_per__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap3xxx_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2_timer8_mpu_irqs, + .main_clk = "gpt8_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO3_SHIFT, + .module_bit = OMAP3430_EN_GPT8_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, }, }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap3xxx_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -/* gpio4 */ -static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { - { .role = "dbclk", .clk = "gpio4_dbck", }, +/* timer9 */ +static struct omap_hwmod omap3xxx_timer9_hwmod; + +static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { + { + .pa_start = 0x49040000, + .pa_end = 0x49040000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap3xxx_gpio4_hwmod = { - .name = "gpio4", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, - .main_clk = "gpio4_ick", - .opt_clks = gpio4_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap3xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { + &omap3xxx_l4_per__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap3xxx_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2_timer9_mpu_irqs, + .main_clk = "gpt9_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO4_SHIFT, + .module_bit = OMAP3430_EN_GPT9_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, }, }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap3xxx_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -/* gpio5 */ -static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { - { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ - { .irq = -1 } +/* timer10 */ +static struct omap_hwmod omap3xxx_timer10_hwmod; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { - { .role = "dbclk", .clk = "gpio5_dbck", }, +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { + &omap3xxx_l4_core__timer10, }; -static struct omap_hwmod omap3xxx_gpio5_hwmod = { - .name = "gpio5", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap3xxx_gpio5_irqs, - .main_clk = "gpio5_ick", - .opt_clks = gpio5_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), +/* timer10 hwmod */ +static struct omap_hwmod omap3xxx_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2_timer10_mpu_irqs, + .main_clk = "gpt10_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO5_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, }, }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap3xxx_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, }; -/* gpio6 */ -static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { - { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ - { .irq = -1 } +/* timer11 */ +static struct omap_hwmod omap3xxx_timer11_hwmod; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { - { .role = "dbclk", .clk = "gpio6_dbck", }, +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { + &omap3xxx_l4_core__timer11, }; -static struct omap_hwmod omap3xxx_gpio6_hwmod = { - .name = "gpio6", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap3xxx_gpio6_irqs, - .main_clk = "gpio6_ick", - .opt_clks = gpio6_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), +/* timer11 hwmod */ +static struct omap_hwmod omap3xxx_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2_timer11_mpu_irqs, + .main_clk = "gpt11_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO6_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, }, }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .dev_attr = &capability_pwm_dev_attr, + .slaves = omap3xxx_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, +/* timer12*/ +static struct omap_hwmod omap3xxx_timer12_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { + { .irq = 95, }, + { .irq = -1 } }; -static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x002c, - .syss_offs = 0x0028, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { - .name = "dma", - .sysc = &omap3xxx_dma_sysc, +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap3xxx_timer12_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system */ -static struct omap_hwmod omap3xxx_dma_system_hwmod = { - .name = "dma", - .class = &omap3xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, - .main_clk = "core_l3_ick", - .prcm = { +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { + &omap3xxx_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap3xxx_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap3xxx_timer12_mpu_irqs, + .main_clk = "gpt12_fck", + .prcm = { .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_ST_SDMA_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT12_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, }, }, - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, + .dev_attr = &capability_secure_dev_attr, + .slaves = omap3xxx_timer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), + .class = &omap3xxx_timer_hwmod_class, }; -/* - * 'mcbsp' class - * multi channel buffered serial port controller - */ - -static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { - .sysc_offs = 0x008c, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, - .clockact = 0x2, +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { + { + .pa_start = 0x48314000, + .pa_end = 0x4831407f, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { - .name = "mcbsp", - .sysc = &omap3xxx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE3, +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_wd_timer2_hwmod, + .clk = "wdt2_ick", + .addr = omap3xxx_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp1 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { - { .name = "irq", .irq = 16 }, - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { - .name = "mcbsp1", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, - .main_clk = "mcbsp1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, - }, - }, +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* mcbsp2 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { - { .name = "irq", .irq = 17 }, - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } +static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap3xxx_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable }; -static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { - .sidetone = "mcbsp2_sidetone", +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { + &omap3xxx_l4_wkup__wd_timer2, }; -static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { - .name = "mcbsp2", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, - .main_clk = "mcbsp2_fck", +static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap3xxx_wd_timer_hwmod_class, + .main_clk = "wdt2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP2_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_WDT2_SHIFT, + .module_offs = WKUP_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, }, }, - .dev_attr = &omap34xx_mcbsp2_dev_attr, + .slaves = omap3xxx_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), + /* + * XXX: Use software supervised mode, HW supervised smartidle seems to + * block CORE power domain idle transitions. Maybe a HW bug in wdt2? + */ + .flags = HWMOD_SWSUP_SIDLE, }; -/* mcbsp3 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { - { .name = "irq", .irq = 22 }, - { .name = "tx", .irq = 89 }, - { .name = "rx", .irq = 90 }, - { .irq = -1 } -}; +/* UART1 */ -static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { - .sidetone = "mcbsp3_sidetone", +static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { + &omap3_l4_core__uart1, }; -static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { - .name = "mcbsp3", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp3_irqs, - .sdma_reqs = omap2_mcbsp3_sdma_reqs, - .main_clk = "mcbsp3_fck", +static struct omap_hwmod omap3xxx_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = omap2_uart1_mpu_irqs, + .sdma_reqs = omap2_uart1_sdma_reqs, + .main_clk = "uart1_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP3_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_UART1_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, }, }, - .dev_attr = &omap34xx_mcbsp3_dev_attr, + .slaves = omap3xxx_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), + .class = &omap2_uart_class, }; -/* mcbsp4 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { - { .name = "irq", .irq = 23 }, - { .name = "tx", .irq = 54 }, - { .name = "rx", .irq = 55 }, - { .irq = -1 } -}; +/* UART2 */ -static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { - { .name = "rx", .dma_req = 20 }, - { .name = "tx", .dma_req = 19 }, - { .dma_req = -1 } +static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { + &omap3_l4_core__uart2, }; -static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { - .name = "mcbsp4", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp4_irqs, - .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, - .main_clk = "mcbsp4_fck", +static struct omap_hwmod omap3xxx_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = omap2_uart2_mpu_irqs, + .sdma_reqs = omap2_uart2_sdma_reqs, + .main_clk = "uart2_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP4_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_UART2_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, + .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, }, }, + .slaves = omap3xxx_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), + .class = &omap2_uart_class, }; -/* mcbsp5 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { - { .name = "irq", .irq = 27 }, - { .name = "tx", .irq = 81 }, - { .name = "rx", .irq = 82 }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { - { .name = "rx", .dma_req = 22 }, - { .name = "tx", .dma_req = 21 }, - { .dma_req = -1 } +/* UART3 */ + +static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { + &omap3_l4_per__uart3, }; -static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { - .name = "mcbsp5", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp5_irqs, - .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, - .main_clk = "mcbsp5_fck", +static struct omap_hwmod omap3xxx_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = omap2_uart3_mpu_irqs, + .sdma_reqs = omap2_uart3_sdma_reqs, + .main_clk = "uart3_fck", .prcm = { .omap2 = { + .module_offs = OMAP3430_PER_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP5_SHIFT, - .module_offs = CORE_MOD, + .module_bit = OMAP3430_EN_UART3_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, + .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, }, }, + .slaves = omap3xxx_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), + .class = &omap2_uart_class, }; -/* 'mcbsp sidetone' class */ -static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_AUTOIDLE, - .sysc_fields = &omap_hwmod_sysc_type1, +/* UART4 */ + +static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { + { .irq = INT_36XX_UART4_IRQ, }, + { .irq = -1 } }; -static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { - .name = "mcbsp_sidetone", - .sysc = &omap3xxx_mcbsp_sidetone_sysc, +static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, + { .dma_req = -1 } }; -/* mcbsp2_sidetone */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { - { .name = "irq", .irq = 4 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { + &omap3_l4_per__uart4, }; -static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { - .name = "mcbsp2_sidetone", - .class = &omap3xxx_mcbsp_sidetone_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, - .main_clk = "mcbsp2_fck", +static struct omap_hwmod omap3xxx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = uart4_mpu_irqs, + .sdma_reqs = uart4_sdma_reqs, + .main_clk = "uart4_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP2_SHIFT, .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3630_EN_UART4_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, }, }, + .slaves = omap3xxx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), + .class = &omap2_uart_class, }; -/* mcbsp3_sidetone */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { - { .name = "irq", .irq = 5 }, - { .irq = -1 } +static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { + { .irq = INT_35XX_UART4_IRQ, }, }; -static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { - .name = "mcbsp3_sidetone", - .class = &omap3xxx_mcbsp_sidetone_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, - .main_clk = "mcbsp3_fck", - .prcm = { +static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, +}; + +static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = { + &am35xx_l4_core__uart4, +}; + +static struct omap_hwmod am35xx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = am35xx_uart4_mpu_irqs, + .sdma_reqs = am35xx_uart4_sdma_reqs, + .main_clk = "uart4_fck", + .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP3_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_UART4_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, }, }, + .slaves = am35xx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves), + .class = &omap2_uart_class, }; -/* SR common */ -static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { - .clkact_shift = 20, + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_1, + .reset = &omap_i2c_reset, }; -static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { - .sysc_offs = 0x24, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), - .clockact = CLOCKACT_TEST_ICLK, - .sysc_fields = &omap34xx_sr_sysc_fields, +static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, + { .name = "dsi1", .dma_req = 74 }, + { .dma_req = -1 } }; -static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { - .name = "smartreflex", - .sysc = &omap34xx_sr_sysc, - .rev = 1, +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { + &omap3xxx_dss__l3, }; -static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { - .sidle_shift = 24, - .enwkup_shift = 26, +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3430es1_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { - .sysc_offs = 0x38, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | - SYSC_NO_CACHE), - .sysc_fields = &omap36xx_sr_sysc_fields, +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { - .name = "smartreflex", - .sysc = &omap36xx_sr_sysc, - .rev = 2, +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { + &omap3430es1_l4_core__dss, }; -/* SR1 */ -static struct omap_smartreflex_dev_attr sr1_dev_attr = { - .sensor_voltdm_name = "mpu_iva", +static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { + &omap3xxx_l4_core__dss, }; -static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { - { .irq = 18 }, - { .irq = -1 } +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + /* + * The DSS HW needs all DSS clocks enabled during reset. The dss_core + * driver does not use these clocks. + */ + { .role = "sys_clk", .clk = "dss2_alwon_fck" }, + { .role = "tv_clk", .clk = "dss_tv_fck" }, + /* required only on OMAP3430 */ + { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, }; -static struct omap_hwmod omap34xx_sr1_hwmod = { - .name = "sr1", - .class = &omap34xx_smartreflex_hwmod_class, - .main_clk = "sr1_fck", +static struct omap_hwmod omap3430es1_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .sdma_reqs = omap3xxx_dss_sdma_chs, .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR1_SHIFT, - .module_offs = WKUP_MOD, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, }, }, - .dev_attr = &sr1_dev_attr, - .mpu_irqs = omap3_smartreflex_mpu_irqs, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap3430es1_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), + .masters = omap3xxx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), + .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, }; -static struct omap_hwmod omap36xx_sr1_hwmod = { - .name = "sr1", - .class = &omap36xx_smartreflex_hwmod_class, - .main_clk = "sr1_fck", +static struct omap_hwmod omap3xxx_dss_core_hwmod = { + .name = "dss_core", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .class = &omap2_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .sdma_reqs = omap3xxx_dss_sdma_chs, .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR1_SHIFT, - .module_offs = WKUP_MOD, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap3xxx_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), + .masters = omap3xxx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSC_HAS_ENAWAKEUP), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap3_dispc_sysc, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { + &omap3xxx_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap3_dispc_hwmod_class, + .mpu_irqs = omap2_dispc_irqs, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, }, }, - .dev_attr = &sr1_dev_attr, - .mpu_irqs = omap3_smartreflex_mpu_irqs, + .slaves = omap3xxx_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), + .flags = HWMOD_NO_IDLEST, + .dev_attr = &omap2_3_dss_dispc_dev_attr }; -/* SR2 */ -static struct omap_smartreflex_dev_attr sr2_dev_attr = { - .sensor_voltdm_name = "core", +/* + * 'dsi' class + * display serial interface controller + */ + +static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { + .name = "dsi", }; -static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { - { .irq = 19 }, +static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { + { .irq = 25 }, { .irq = -1 } }; -static struct omap_hwmod omap34xx_sr2_hwmod = { - .name = "sr2", - .class = &omap34xx_smartreflex_hwmod_class, - .main_clk = "sr2_fck", - .prcm = { +/* dss_dsi1 */ +static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { + { + .pa_start = 0x4804FC00, + .pa_end = 0x4804FFFF, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dsi1_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_dsi1_addrs, + .fw = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR2_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, - }, + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } }, - .dev_attr = &sr2_dev_attr, - .mpu_irqs = omap3_smartreflex_core_irqs, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap36xx_sr2_hwmod = { - .name = "sr2", - .class = &omap36xx_smartreflex_hwmod_class, - .main_clk = "sr2_fck", +/* dss_dsi1 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { + &omap3xxx_l4_core__dss_dsi1, +}; + +static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { + { .role = "sys_clk", .clk = "dss2_alwon_fck" }, +}; + +static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { + .name = "dss_dsi1", + .class = &omap3xxx_dsi_hwmod_class, + .mpu_irqs = omap3xxx_dsi1_irqs, + .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR2_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, }, }, - .dev_attr = &sr2_dev_attr, - .mpu_irqs = omap3_smartreflex_core_irqs, + .opt_clks = dss_dsi1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), + .slaves = omap3xxx_dss_dsi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), + .flags = HWMOD_NO_IDLEST, }; -/* - * 'mailbox' class - * mailbox module allowing communication between the on-chip processors - * using a queued mailbox-interrupt mechanism. - */ - -static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { - .rev_offs = 0x000, - .sysc_offs = 0x010, - .syss_offs = 0x014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { - .name = "mailbox", - .sysc = &omap3xxx_mailbox_sysc, +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { + &omap3xxx_l4_core__dss_rfbi, }; -static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { - { .irq = 26 }, - { .irq = -1 } +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { + { .role = "ick", .clk = "dss_ick" }, }; -static struct omap_hwmod omap3xxx_mailbox_hwmod = { - .name = "mailbox", - .class = &omap3xxx_mailbox_hwmod_class, - .mpu_irqs = omap3xxx_mailbox_irqs, - .main_clk = "mailboxes_ick", +static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2_rfbi_hwmod_class, + .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, }, }, + .opt_clks = dss_rfbi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), + .slaves = omap3xxx_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), + .flags = HWMOD_NO_IDLEST, }; -/* - * 'mcspi' class - * multichannel serial port interface (mcspi) / master/slave synchronous serial - * bus - */ - -static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap34xx_mcspi_class = { - .name = "mcspi", - .sysc = &omap34xx_mcspi_sysc, - .rev = OMAP3_MCSPI_REV, +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { + &omap3xxx_l4_core__dss_venc, }; -/* mcspi1 */ -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { + /* required only on OMAP3430 */ + { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, }; -static struct omap_hwmod omap34xx_mcspi1 = { - .name = "mcspi1", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, - .main_clk = "mcspi1_fck", +static struct omap_hwmod omap3xxx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2_venc_hwmod_class, + .main_clk = "dss_tv_fck", .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, }, }, - .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, + .opt_clks = dss_venc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), + .slaves = omap3xxx_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), + .flags = HWMOD_NO_IDLEST, }; -/* mcspi2 */ -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, +/* I2C1 */ + +static struct omap_i2c_dev_attr i2c1_dev_attr = { + .fifo_depth = 8, /* bytes */ + .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + OMAP_I2C_FLAG_BUS_SHIFT_2, }; -static struct omap_hwmod omap34xx_mcspi2 = { - .name = "mcspi2", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, - .main_clk = "mcspi2_fck", +static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { + &omap3_l4_core__i2c1, +}; + +static struct omap_hwmod omap3xxx_i2c1_hwmod = { + .name = "i2c1", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .mpu_irqs = omap2_i2c1_mpu_irqs, + .sdma_reqs = omap2_i2c1_sdma_reqs, + .main_clk = "i2c1_fck", .prcm = { .omap2 = { .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI2_SHIFT, + .module_bit = OMAP3430_EN_I2C1_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, + .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, }, }, - .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, + .slaves = omap3xxx_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c1_dev_attr, }; -/* mcspi3 */ -static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { - { .name = "irq", .irq = 91 }, /* 91 */ - { .irq = -1 } -}; +/* I2C2 */ -static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { - { .name = "tx0", .dma_req = 15 }, - { .name = "rx0", .dma_req = 16 }, - { .name = "tx1", .dma_req = 23 }, - { .name = "rx1", .dma_req = 24 }, - { .dma_req = -1 } +static struct omap_i2c_dev_attr i2c2_dev_attr = { + .fifo_depth = 8, /* bytes */ + .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + OMAP_I2C_FLAG_BUS_SHIFT_2, }; -static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { - .num_chipselect = 2, +static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { + &omap3_l4_core__i2c2, }; - -static struct omap_hwmod omap34xx_mcspi3 = { - .name = "mcspi3", - .mpu_irqs = omap34xx_mcspi3_mpu_irqs, - .sdma_reqs = omap34xx_mcspi3_sdma_reqs, - .main_clk = "mcspi3_fck", + +static struct omap_hwmod omap3xxx_i2c2_hwmod = { + .name = "i2c2", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .mpu_irqs = omap2_i2c2_mpu_irqs, + .sdma_reqs = omap2_i2c2_sdma_reqs, + .main_clk = "i2c2_fck", .prcm = { .omap2 = { .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI3_SHIFT, + .module_bit = OMAP3430_EN_I2C2_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, + .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, }, }, - .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi3_dev_attr, + .slaves = omap3xxx_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c2_dev_attr, }; -/* mcspi4 */ -static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { - { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ +/* I2C3 */ + +static struct omap_i2c_dev_attr i2c3_dev_attr = { + .fifo_depth = 64, /* bytes */ + .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + OMAP_I2C_FLAG_BUS_SHIFT_2, +}; + +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { + { .irq = INT_34XX_I2C3_IRQ, }, { .irq = -1 } }; -static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { - { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ - { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ +static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, + { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, { .dma_req = -1 } }; -static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { - .num_chipselect = 1, +static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { + &omap3_l4_core__i2c3, }; -static struct omap_hwmod omap34xx_mcspi4 = { - .name = "mcspi4", - .mpu_irqs = omap34xx_mcspi4_mpu_irqs, - .sdma_reqs = omap34xx_mcspi4_sdma_reqs, - .main_clk = "mcspi4_fck", +static struct omap_hwmod omap3xxx_i2c3_hwmod = { + .name = "i2c3", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .mpu_irqs = i2c3_mpu_irqs, + .sdma_reqs = i2c3_sdma_reqs, + .main_clk = "i2c3_fck", .prcm = { .omap2 = { .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI4_SHIFT, + .module_bit = OMAP3430_EN_I2C3_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, + .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, }, }, - .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi4_dev_attr, + .slaves = omap3xxx_i2c3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), + .class = &i2c_class, + .dev_attr = &i2c3_dev_attr, }; -/* usbhsotg */ -static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { - .rev_offs = 0x0400, - .sysc_offs = 0x0404, - .syss_offs = 0x0408, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { + { + .pa_start = 0x48310000, + .pa_end = 0x483101ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_class usbotg_class = { - .name = "usbotg", - .sysc = &omap3xxx_usbhsotg_sysc, +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gpio1_hwmod, + .addr = omap3xxx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* usb_otg_hs */ -static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { +/* l4_per -> gpio2 */ +static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { + { + .pa_start = 0x49050000, + .pa_end = 0x490501ff, + .flags = ADDR_TYPE_RT + }, + { } +}; - { .name = "mc", .irq = 92 }, - { .name = "dma", .irq = 93 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio2_hwmod, + .addr = omap3xxx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { - .name = "usb_otg_hs", - .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, - .main_clk = "hsotgusb_ick", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT - }, +/* l4_per -> gpio3 */ +static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { + { + .pa_start = 0x49052000, + .pa_end = 0x490521ff, + .flags = ADDR_TYPE_RT }, - .class = &usbotg_class, - - /* - * Erratum ID: i479 idle_req / idle_ack mechanism potentially - * broken when autoidle is enabled - * workaround is to disable the autoidle bit at module level. - */ - .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE - | HWMOD_SWSUP_MSTANDBY, + { } }; -/* usb_otg_hs */ -static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio3_hwmod, + .addr = omap3xxx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; - { .name = "mc", .irq = 71 }, - { .irq = -1 } +/* l4_per -> gpio4 */ +static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { + { + .pa_start = 0x49054000, + .pa_end = 0x490541ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_class am35xx_usbotg_class = { - .name = "am35xx_usbotg", - .sysc = NULL, +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio4_hwmod, + .addr = omap3xxx_gpio4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod am35xx_usbhsotg_hwmod = { - .name = "am35x_otg_hs", - .mpu_irqs = am35xx_usbhsotg_mpu_irqs, - .main_clk = NULL, - .prcm = { - .omap2 = { - }, +/* l4_per -> gpio5 */ +static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { + { + .pa_start = 0x49056000, + .pa_end = 0x490561ff, + .flags = ADDR_TYPE_RT }, - .class = &am35xx_usbotg_class, + { } }; -/* MMC/SD/SDIO common */ -static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { - .rev_offs = 0x1fc, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio5_hwmod, + .addr = omap3xxx_gpio5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap34xx_mmc_class = { - .name = "mmc", - .sysc = &omap34xx_mmc_sysc, +/* l4_per -> gpio6 */ +static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { + { + .pa_start = 0x49058000, + .pa_end = 0x490581ff, + .flags = ADDR_TYPE_RT + }, + { } }; -/* MMC/SD/SDIO1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio6_hwmod, + .addr = omap3xxx_gpio6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; -static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { - { .irq = 83, }, - { .irq = -1 } +/* + * 'gpio' class + * general purpose io module + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { - { .name = "tx", .dma_req = 61, }, - { .name = "rx", .dma_req = 62, }, - { .dma_req = -1 } +static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap3xxx_gpio_sysc, + .rev = 1, }; -static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { - { .role = "dbck", .clk = "omap_32k_fck", }, +/* gpio_dev_attr*/ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, }; -static struct omap_mmc_dev_attr mmc1_dev_attr = { - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +/* gpio1 */ +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbck", }, }; -/* See 35xx errata 2.1.1.128 in SPRZ278F */ -static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { - .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | - OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), +static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { + &omap3xxx_l4_wkup__gpio1, }; -static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { - .name = "mmc1", - .mpu_irqs = omap34xx_mmc1_mpu_irqs, - .sdma_reqs = omap34xx_mmc1_sdma_reqs, - .opt_clks = omap34xx_mmc1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), - .main_clk = "mmchs1_fck", +static struct omap_hwmod omap3xxx_gpio1_hwmod = { + .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio1_irqs, + .main_clk = "gpio1_ick", + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC1_SHIFT, + .module_bit = OMAP3430_EN_GPIO1_SHIFT, + .module_offs = WKUP_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, }, }, - .dev_attr = &mmc1_pre_es3_dev_attr, - .class = &omap34xx_mmc_class, + .slaves = omap3xxx_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { - .name = "mmc1", - .mpu_irqs = omap34xx_mmc1_mpu_irqs, - .sdma_reqs = omap34xx_mmc1_sdma_reqs, - .opt_clks = omap34xx_mmc1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), - .main_clk = "mmchs1_fck", +/* gpio2 */ +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { + &omap3xxx_l4_per__gpio2, +}; + +static struct omap_hwmod omap3xxx_gpio2_hwmod = { + .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio2_irqs, + .main_clk = "gpio2_ick", + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC1_SHIFT, + .module_bit = OMAP3430_EN_GPIO2_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, }, }, - .dev_attr = &mmc1_dev_attr, - .class = &omap34xx_mmc_class, -}; - -/* MMC/SD/SDIO2 */ - -static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { - { .irq = INT_24XX_MMC2_IRQ, }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { - { .name = "tx", .dma_req = 47, }, - { .name = "rx", .dma_req = 48, }, - { .dma_req = -1 } + .slaves = omap3xxx_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { - { .role = "dbck", .clk = "omap_32k_fck", }, +/* gpio3 */ +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbck", }, }; -/* See 35xx errata 2.1.1.128 in SPRZ278F */ -static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { - .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, +static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { + &omap3xxx_l4_per__gpio3, }; -static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { - .name = "mmc2", - .mpu_irqs = omap34xx_mmc2_mpu_irqs, - .sdma_reqs = omap34xx_mmc2_sdma_reqs, - .opt_clks = omap34xx_mmc2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), - .main_clk = "mmchs2_fck", +static struct omap_hwmod omap3xxx_gpio3_hwmod = { + .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio3_irqs, + .main_clk = "gpio3_ick", + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC2_SHIFT, + .module_bit = OMAP3430_EN_GPIO3_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, }, }, - .dev_attr = &mmc2_pre_es3_dev_attr, - .class = &omap34xx_mmc_class, + .slaves = omap3xxx_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { - .name = "mmc2", - .mpu_irqs = omap34xx_mmc2_mpu_irqs, - .sdma_reqs = omap34xx_mmc2_sdma_reqs, - .opt_clks = omap34xx_mmc2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), - .main_clk = "mmchs2_fck", +/* gpio4 */ +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { + &omap3xxx_l4_per__gpio4, +}; + +static struct omap_hwmod omap3xxx_gpio4_hwmod = { + .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio4_irqs, + .main_clk = "gpio4_ick", + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC2_SHIFT, + .module_bit = OMAP3430_EN_GPIO4_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, }, }, - .class = &omap34xx_mmc_class, + .slaves = omap3xxx_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -/* MMC/SD/SDIO3 */ - -static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { - { .irq = 94, }, +/* gpio5 */ +static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { + { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ { .irq = -1 } }; -static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { - { .name = "tx", .dma_req = 77, }, - { .name = "rx", .dma_req = 78, }, - { .dma_req = -1 } +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbck", }, }; -static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { - { .role = "dbck", .clk = "omap_32k_fck", }, +static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { + &omap3xxx_l4_per__gpio5, }; -static struct omap_hwmod omap3xxx_mmc3_hwmod = { - .name = "mmc3", - .mpu_irqs = omap34xx_mmc3_mpu_irqs, - .sdma_reqs = omap34xx_mmc3_sdma_reqs, - .opt_clks = omap34xx_mmc3_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), - .main_clk = "mmchs3_fck", +static struct omap_hwmod omap3xxx_gpio5_hwmod = { + .name = "gpio5", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap3xxx_gpio5_irqs, + .main_clk = "gpio5_ick", + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC3_SHIFT, + .module_bit = OMAP3430_EN_GPIO5_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, }, }, - .class = &omap34xx_mmc_class, -}; - -/* - * 'usb_host_hs' class - * high-speed multi-port usb host controller - */ - -static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, + .slaves = omap3xxx_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap3xxx_usb_host_hs_sysc, +/* gpio6 */ +static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { + { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ + { .irq = -1 } }; -static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { - { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbck", }, }; -static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 }, - { .name = "ehci-irq", .irq = 77 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { + &omap3xxx_l4_per__gpio6, }; -static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap3xxx_usb_host_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap3xxx_usb_host_hs_irqs, - .main_clk = "usbhost_48m_fck", - .prcm = { +static struct omap_hwmod omap3xxx_gpio6_hwmod = { + .name = "gpio6", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap3xxx_gpio6_irqs, + .main_clk = "gpio6_ick", + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .prcm = { .omap2 = { - .module_offs = OMAP3430ES2_USBHOST_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, - }, - }, - .opt_clks = omap3xxx_usb_host_hs_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), - - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ - - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ + .module_bit = OMAP3430_EN_GPIO6_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, + }, + }, + .slaves = omap3xxx_gpio6_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, +}; - /* - * During system boot; If the hwmod framework resets the module - * the module will have smart idle settings; which can lead to deadlock - * (above Errata Id:i660); so, dont reset the module during boot; - * Use HWMOD_INIT_NO_RESET. - */ +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { + .master = &omap3xxx_dma_system_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | - HWMOD_INIT_NO_RESET, +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, }; -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ -static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { +static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap3xxx_usb_tll_hs_sysc, +static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { + .name = "dma", + .sysc = &omap3xxx_dma_sysc, }; -static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 }, - { .irq = -1 } +/* dma_system */ +static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x48056fff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap3xxx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap3xxx_usb_tll_hs_irqs, - .main_clk = "usbtll_fck", +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { + &omap3xxx_dma_system__l3, +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dma_system_hwmod, + .clk = "core_l4_ick", + .addr = omap3xxx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { + &omap3xxx_l4_core__dma_system, +}; + +static struct omap_hwmod omap3xxx_dma_system_hwmod = { + .name = "dma", + .class = &omap3xxx_dma_hwmod_class, + .mpu_irqs = omap2_dma_system_irqs, + .main_clk = "core_l3_ick", .prcm = { .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 3, - .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .idlest_reg_id = 3, - .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_ST_SDMA_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, }, }, + .slaves = omap3xxx_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), + .masters = omap3xxx_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), + .dev_attr = &dma_dev_attr, + .flags = HWMOD_NO_IDLEST, }; /* - * interfaces + * 'mcbsp' class + * multi channel buffered serial port controller */ -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, + .clockact = 0x2, }; -/* L3 -> L4_PER interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_l4_per_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap3xxx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE3, }; -static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { + { .name = "irq", .irq = 16 }, + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { { - .pa_start = 0x68000000, - .pa_end = 0x6800ffff, - .flags = ADDR_TYPE_RT, + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT }, { } }; -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { - .master = &omap3xxx_mpu_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .addr = omap3xxx_l3_main_addrs, - .user = OCP_USER_MPU, +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap3xxx_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { - .master = &omap3430es1_dss_core_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { + &omap3xxx_l4_core__mcbsp1, }; -static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { - .master = &omap3xxx_dss_core_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .fw = { +static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp1_irqs, + .sdma_reqs = omap2_mcbsp1_sdma_reqs, + .main_clk = "mcbsp1_fck", + .prcm = { .omap2 = { - .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, - .flags = OMAP_FIREWALL_L3, - } + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .slaves = omap3xxx_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), }; -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { - .master = &omap3xxx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { + { .name = "irq", .irq = 17 }, + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, + { .irq = -1 } }; -/* l3_core -> am35xx_usbhsotg interface */ -static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { - .master = &am35xx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, -}; -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, + { } }; -/* L4 CORE -> MMC1 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_pre_es3_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, +/* l4_per -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 }; -static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_es3plus_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { + &omap3xxx_l4_per__mcbsp2, }; -/* L4 CORE -> MMC2 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_pre_es3_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 +static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { + .sidetone = "mcbsp2_sidetone", }; -static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_es3plus_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 +static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_irqs, + .sdma_reqs = omap2_mcbsp2_sdma_reqs, + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), + .dev_attr = &omap34xx_mcbsp2_dev_attr, }; -/* L4 CORE -> MMC3 interface */ -static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { +/* mcbsp3 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { + { .name = "irq", .irq = 22 }, + { .name = "tx", .irq = 89 }, + { .name = "rx", .irq = 90 }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { { - .pa_start = 0x480ad000, - .pa_end = 0x480ad1ff, - .flags = ADDR_TYPE_RT, + .name = "mpu", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT }, { } }; -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mmc3_hwmod, - .clk = "mmchs3_ick", - .addr = omap3xxx_mmc3_addr_space, +/* l4_per -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 }; -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { - { - .pa_start = OMAP3_UART1_BASE, - .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { + &omap3xxx_l4_per__mcbsp3, }; -static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap3xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { + .sidetone = "mcbsp3_sidetone", }; -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { - { - .pa_start = OMAP3_UART2_BASE, - .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, +static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_irqs, + .sdma_reqs = omap2_mcbsp3_sdma_reqs, + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + }, }, - { } + .slaves = omap3xxx_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), + .dev_attr = &omap34xx_mcbsp3_dev_attr, }; -static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap3xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* mcbsp4 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { + { .name = "irq", .irq = 23 }, + { .name = "tx", .irq = 54 }, + { .name = "rx", .irq = 55 }, + { .irq = -1 } }; -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { +static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { + { .name = "rx", .dma_req = 20 }, + { .name = "tx", .dma_req = 19 }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { { - .pa_start = OMAP3_UART3_BASE, - .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + .name = "mpu", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT }, { } }; -static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap3xxx_uart3_addr_space, + .slave = &omap3xxx_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap3xxx_mcbsp4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 PER -> UART4 interface */ -static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { - { - .pa_start = OMAP3_UART4_BASE, - .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { + &omap3xxx_l4_per__mcbsp4, +}; + +static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp4_irqs, + .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, + .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, + }, }, - { } + .slaves = omap3xxx_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), }; -static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap36xx_uart4_hwmod, - .clk = "uart4_ick", - .addr = omap36xx_uart4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* mcbsp5 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { + { .name = "irq", .irq = 27 }, + { .name = "tx", .irq = 81 }, + { .name = "rx", .irq = 82 }, + { .irq = -1 } }; -/* AM35xx: L4 CORE -> UART4 interface */ -static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { +static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { + { .name = "rx", .dma_req = 22 }, + { .name = "tx", .dma_req = 21 }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { { - .pa_start = OMAP3_UART4_AM35XX_BASE, - .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT }, + { } }; -static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_uart4_hwmod, - .clk = "uart4_ick", - .addr = am35xx_uart4_addr_space, + .slave = &omap3xxx_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap3xxx_mcbsp5_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* mcbsp5 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { + &omap3xxx_l4_core__mcbsp5, }; -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .fw = { +static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp5_irqs, + .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, + .main_clk = "mcbsp5_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .slaves = omap3xxx_mcbsp5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), +}; +/* 'mcbsp sidetone' class */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_AUTOIDLE, + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* L4 CORE -> I2C3 interface */ -static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { +static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { + .name = "mcbsp_sidetone", + .sysc = &omap3xxx_mcbsp_sidetone_sysc, +}; + +/* mcbsp2_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { + { .name = "irq", .irq = 4 }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { { - .pa_start = 0x48060000, - .pa_end = 0x48060000 + SZ_128 - 1, - .flags = ADDR_TYPE_RT, + .name = "sidetone", + .pa_start = 0x49028000, + .pa_end = 0x490280ff, + .flags = ADDR_TYPE_RT }, { } }; -static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c3_hwmod, - .clk = "i2c3_ick", - .addr = omap3xxx_i2c3_addr_space, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } +/* l4_per -> mcbsp2_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_sidetone_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_sidetone_addrs, + .user = OCP_USER_MPU, +}; + +/* mcbsp2_sidetone slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { + &omap3xxx_l4_per__mcbsp2_sidetone, +}; + +static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { + .name = "mcbsp2_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .slaves = omap3xxx_mcbsp2_sidetone_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), }; -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { +/* mcbsp3_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { + { .name = "irq", .irq = 5 }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { { - .pa_start = OMAP34XX_SR1_BASE, - .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, + .name = "sidetone", + .pa_start = 0x4902A000, + .pa_end = 0x4902A0ff, + .flags = ADDR_TYPE_RT }, { } }; -static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_sr1_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr1_addr_space, +/* l4_per -> mcbsp3_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_sidetone_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_sidetone_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap36xx_sr1_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr1_addr_space, - .user = OCP_USER_MPU, +/* mcbsp3_sidetone slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { + &omap3xxx_l4_per__mcbsp3_sidetone, }; -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { - { - .pa_start = OMAP34XX_SR2_BASE, - .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, +static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { + .name = "mcbsp3_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + }, }, - { } + .slaves = omap3xxx_mcbsp3_sidetone_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), }; -static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_sr2_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr2_addr_space, - .user = OCP_USER_MPU, -}; -static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap36xx_sr2_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr2_addr_space, - .user = OCP_USER_MPU, +/* SR common */ +static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { + .clkact_shift = 20, }; -static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { - { - .pa_start = OMAP34XX_HSUSB_OTG_BASE, - .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { + .sysc_offs = 0x24, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap34xx_sr_sysc_fields, }; -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_usbhsotg_hwmod, - .clk = "l4_ick", - .addr = omap3xxx_usbhsotg_addrs, - .user = OCP_USER_MPU, +static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap34xx_sr_sysc, + .rev = 1, }; -static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { - { - .pa_start = AM35XX_IPSS_USBOTGSS_BASE, - .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { + .sidle_shift = 24, + .enwkup_shift = 26 }; -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_usbhsotg_hwmod, - .clk = "l4_ick", - .addr = am35xx_usbhsotg_addrs, - .user = OCP_USER_MPU, +static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { + .sysc_offs = 0x38, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_NO_CACHE), + .sysc_fields = &omap36xx_sr_sysc_fields, }; -/* L4_WKUP -> L4_SEC interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_l4_sec_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap36xx_sr_sysc, + .rev = 2, }; -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_iva_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* SR1 */ +static struct omap_smartreflex_dev_attr sr1_dev_attr = { + .sensor_voltdm_name = "mpu_iva", }; -static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { - { - .pa_start = 0x48318000, - .pa_end = 0x48318000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { + &omap3_l4_core__sr1, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap3xxx_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap34xx_sr1_hwmod = { + .name = "sr1_hwmod", + .class = &omap34xx_smartreflex_hwmod_class, + .main_clk = "sr1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + }, + }, + .slaves = omap3_sr1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), + .dev_attr = &sr1_dev_attr, + .mpu_irqs = omap3_smartreflex_mpu_irqs, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; -static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { - { - .pa_start = 0x49032000, - .pa_end = 0x49032000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap36xx_sr1_hwmod = { + .name = "sr1_hwmod", + .class = &omap36xx_smartreflex_hwmod_class, + .main_clk = "sr1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + }, }, - { } + .slaves = omap3_sr1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), + .dev_attr = &sr1_dev_attr, + .mpu_irqs = omap3_smartreflex_mpu_irqs, }; -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap3xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* SR2 */ +static struct omap_smartreflex_dev_attr sr2_dev_attr = { + .sensor_voltdm_name = "core", }; -static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { - { - .pa_start = 0x49034000, - .pa_end = 0x49034000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { + &omap3_l4_core__sr2, }; -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap3xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap34xx_sr2_hwmod = { + .name = "sr2_hwmod", + .class = &omap34xx_smartreflex_hwmod_class, + .main_clk = "sr2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR2_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, + }, + }, + .slaves = omap3_sr2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), + .dev_attr = &sr2_dev_attr, + .mpu_irqs = omap3_smartreflex_core_irqs, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; -static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { - { - .pa_start = 0x49036000, - .pa_end = 0x49036000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap36xx_sr2_hwmod = { + .name = "sr2_hwmod", + .class = &omap36xx_smartreflex_hwmod_class, + .main_clk = "sr2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR2_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, + }, }, - { } + .slaves = omap3_sr2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), + .dev_attr = &sr2_dev_attr, + .mpu_irqs = omap3_smartreflex_core_irqs, }; -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap3xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors + * using a queued mailbox-interrupt mechanism. + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x49038000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &omap3xxx_mailbox_sysc, }; -/* l4_per -> timer5 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap3xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap3xxx_mailbox_hwmod; +static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { + { .irq = 26 }, + { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { +static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { { - .pa_start = 0x4903A000, - .pa_end = 0x4903A000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT + .pa_start = 0x48094000, + .pa_end = 0x480941ff, + .flags = ADDR_TYPE_RT, }, { } }; -/* l4_per -> timer6 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap3xxx_timer6_addrs, +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mailbox_hwmod, + .addr = omap3xxx_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { - { - .pa_start = 0x4903C000, - .pa_end = 0x4903C000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { + &omap3xxx_l4_core__mailbox, +}; + +static struct omap_hwmod omap3xxx_mailbox_hwmod = { + .name = "mailbox", + .class = &omap3xxx_mailbox_hwmod_class, + .mpu_irqs = omap3xxx_mailbox_irqs, + .main_clk = "mailboxes_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, + }, }, - { } + .slaves = omap3xxx_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), }; -/* l4_per -> timer7 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap3xxx_timer7_addrs, +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi1, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { - { - .pa_start = 0x4903E000, - .pa_end = 0x4903E000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi2, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per -> timer8 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap3xxx_timer8_addrs, +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi3, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { +/* l4 core -> mcspi4 interface */ +static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { { - .pa_start = 0x49040000, - .pa_end = 0x49040000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT + .pa_start = 0x480ba000, + .pa_end = 0x480ba0ff, + .flags = ADDR_TYPE_RT, }, { } }; -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap3xxx_timer9_addrs, +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi4, + .clk = "mcspi4_ick", + .addr = omap34xx_mcspi4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap34xx_mcspi_class = { + .name = "mcspi", + .sysc = &omap34xx_mcspi_sysc, + .rev = OMAP3_MCSPI_REV, }; -static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { - { - .pa_start = 0x48304000, - .pa_end = 0x48304000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +/* mcspi1 */ +static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { + &omap34xx_l4_core__mcspi1, }; -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { - .master = &omap3xxx_l4_sec_hwmod, - .slave = &omap3xxx_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap3xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { - { - .pa_start = 0x48314000, - .pa_end = 0x4831407f, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap34xx_mcspi1 = { + .name = "mcspi1", + .mpu_irqs = omap2_mcspi1_mpu_irqs, + .sdma_reqs = omap2_mcspi1_sdma_reqs, + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, + }, }, - { } + .slaves = omap34xx_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_wd_timer2_hwmod, - .clk = "wdt2_ick", - .addr = omap3xxx_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* mcspi2 */ +static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { + &omap34xx_l4_core__mcspi2, }; -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3430es1_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { +static struct omap_hwmod omap34xx_mcspi2 = { + .name = "mcspi2", + .mpu_irqs = omap2_mcspi2_mpu_irqs, + .sdma_reqs = omap2_mcspi2_sdma_reqs, + .main_clk = "mcspi2_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .slaves = omap34xx_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, }; -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* mcspi3 */ +static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { + { .name = "irq", .irq = 91 }, /* 91 */ + { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { - { - .pa_start = 0x4804FC00, - .pa_end = 0x4804FFFF, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { + { .name = "tx0", .dma_req = 15 }, + { .name = "rx0", .dma_req = 16 }, + { .name = "tx1", .dma_req = 23 }, + { .name = "rx1", .dma_req = 24 }, + { .dma_req = -1 } }; -/* l4_core -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_dsi1_hwmod, - .clk = "dss_ick", - .addr = omap3xxx_dss_dsi1_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { + &omap34xx_l4_core__mcspi3, }; -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { + .num_chipselect = 2, }; -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .fw = { +static struct omap_hwmod omap34xx_mcspi3 = { + .name = "mcspi3", + .mpu_irqs = omap34xx_mcspi3_mpu_irqs, + .sdma_reqs = omap34xx_mcspi3_sdma_reqs, + .main_clk = "mcspi3_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, + }, }, - .flags = OCPIF_SWSUP_IDLE, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .slaves = omap34xx_mcspi3_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi3_dev_attr, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { - { - .pa_start = 0x48310000, - .pa_end = 0x483101ff, - .flags = ADDR_TYPE_RT - }, - { } +/* SPI4 */ +static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { + { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ + { .irq = -1 } }; -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_gpio1_hwmod, - .addr = omap3xxx_gpio1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { + { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ + { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ + { .dma_req = -1 } }; -/* l4_per -> gpio2 */ -static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { - { - .pa_start = 0x49050000, - .pa_end = 0x490501ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { + &omap34xx_l4_core__mcspi4, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio2_hwmod, - .addr = omap3xxx_gpio2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { + .num_chipselect = 1, }; -/* l4_per -> gpio3 */ -static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { - { - .pa_start = 0x49052000, - .pa_end = 0x490521ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap34xx_mcspi4 = { + .name = "mcspi4", + .mpu_irqs = omap34xx_mcspi4_mpu_irqs, + .sdma_reqs = omap34xx_mcspi4_sdma_reqs, + .main_clk = "mcspi4_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, + }, }, - { } + .slaves = omap34xx_mcspi4_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi4_dev_attr, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio3_hwmod, - .addr = omap3xxx_gpio3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* + * usbhsotg + */ +static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* l4_per -> gpio4 */ -static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { - { - .pa_start = 0x49054000, - .pa_end = 0x490541ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap3xxx_usbhsotg_sysc, }; +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio4_hwmod, - .addr = omap3xxx_gpio4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, + { .name = "mc", .irq = 92 }, + { .name = "dma", .irq = 93 }, + { .irq = -1 } }; -/* l4_per -> gpio5 */ -static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { - { - .pa_start = 0x49056000, - .pa_end = 0x490561ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, + .main_clk = "hsotgusb_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT + }, }, - { } -}; + .masters = omap3xxx_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), + .slaves = omap3xxx_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), + .class = &usbotg_class, -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio5_hwmod, - .addr = omap3xxx_gpio5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, + /* + * Erratum ID: i479 idle_req / idle_ack mechanism potentially + * broken when autoidle is enabled + * workaround is to disable the autoidle bit at module level. + */ + .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE + | HWMOD_SWSUP_MSTANDBY, }; -/* l4_per -> gpio6 */ -static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { - { - .pa_start = 0x49058000, - .pa_end = 0x490581ff, - .flags = ADDR_TYPE_RT - }, - { } -}; +/* usb_otg_hs */ +static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio6_hwmod, - .addr = omap3xxx_gpio6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, + { .name = "mc", .irq = 71 }, + { .irq = -1 } }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { - .master = &omap3xxx_dma_system_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class am35xx_usbotg_class = { + .name = "am35xx_usbotg", + .sysc = NULL, }; -static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { - { - .pa_start = 0x48056000, - .pa_end = 0x48056fff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod am35xx_usbhsotg_hwmod = { + .name = "am35x_otg_hs", + .mpu_irqs = am35xx_usbhsotg_mpu_irqs, + .main_clk = NULL, + .prcm = { + .omap2 = { + }, }, - { } + .masters = am35xx_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), + .slaves = am35xx_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), + .class = &am35xx_usbotg_class, }; -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dma_system_hwmod, - .clk = "core_l4_ick", - .addr = omap3xxx_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* MMC/SD/SDIO common */ + +static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48074000, - .pa_end = 0x480740ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_class omap34xx_mmc_class = { + .name = "mmc", + .sysc = &omap34xx_mmc_sysc, }; -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap3xxx_mcbsp1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* MMC/SD/SDIO1 */ + +static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { + { .irq = 83, }, + { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { + { .name = "tx", .dma_req = 61, }, + { .name = "rx", .dma_req = 62, }, + { .dma_req = -1 } }; -/* l4_per -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp2_hwmod, - .clk = "mcbsp2_ick", - .addr = omap3xxx_mcbsp2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { + &omap3xxx_l4_core__mmc1, }; -/* l4_per -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp3_hwmod, - .clk = "mcbsp3_ick", - .addr = omap3xxx_mcbsp3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT - }, - { } +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { + .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | + OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), }; -/* l4_per -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp4_hwmod, - .clk = "mcbsp4_ick", - .addr = omap3xxx_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { + .name = "mmc1", + .mpu_irqs = omap34xx_mmc1_mpu_irqs, + .sdma_reqs = omap34xx_mmc1_sdma_reqs, + .opt_clks = omap34xx_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + }, + }, + .dev_attr = &mmc1_pre_es3_dev_attr, + .slaves = omap3xxx_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), + .class = &omap34xx_mmc_class, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { + .name = "mmc1", + .mpu_irqs = omap34xx_mmc1_mpu_irqs, + .sdma_reqs = omap34xx_mmc1_sdma_reqs, + .opt_clks = omap34xx_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + }, }, - { } + .dev_attr = &mmc1_dev_attr, + .slaves = omap3xxx_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), + .class = &omap34xx_mmc_class, }; -/* l4_core -> mcbsp5 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mcbsp5_hwmod, - .clk = "mcbsp5_ick", - .addr = omap3xxx_mcbsp5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* MMC/SD/SDIO2 */ + +static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { + { .irq = INT_24XX_MMC2_IRQ, }, + { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { - { - .name = "sidetone", - .pa_start = 0x49028000, - .pa_end = 0x490280ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { + { .name = "tx", .dma_req = 47, }, + { .name = "rx", .dma_req = 48, }, + { .dma_req = -1 } }; -/* l4_per -> mcbsp2_sidetone */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp2_sidetone_hwmod, - .clk = "mcbsp2_ick", - .addr = omap3xxx_mcbsp2_sidetone_addrs, - .user = OCP_USER_MPU, +static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { - { - .name = "sidetone", - .pa_start = 0x4902A000, - .pa_end = 0x4902A0ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { + &omap3xxx_l4_core__mmc2, }; -/* l4_per -> mcbsp3_sidetone */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp3_sidetone_hwmod, - .clk = "mcbsp3_ick", - .addr = omap3xxx_mcbsp3_sidetone_addrs, - .user = OCP_USER_MPU, +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { + .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, }; -static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { - { - .pa_start = 0x48094000, - .pa_end = 0x480941ff, - .flags = ADDR_TYPE_RT, +static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { + .name = "mmc2", + .mpu_irqs = omap34xx_mmc2_mpu_irqs, + .sdma_reqs = omap34xx_mmc2_sdma_reqs, + .opt_clks = omap34xx_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + }, }, - { } + .dev_attr = &mmc2_pre_es3_dev_attr, + .slaves = omap3xxx_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), + .class = &omap34xx_mmc_class, }; -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mailbox_hwmod, - .addr = omap3xxx_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { + .name = "mmc2", + .mpu_irqs = omap34xx_mmc2_mpu_irqs, + .sdma_reqs = omap34xx_mmc2_sdma_reqs, + .opt_clks = omap34xx_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + }, + }, + .slaves = omap3xxx_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), + .class = &omap34xx_mmc_class, }; -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi1, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* MMC/SD/SDIO3 */ -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi2, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { + { .irq = 94, }, + { .irq = -1 } }; -/* l4 core -> mcspi3 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi3, - .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { + { .name = "tx", .dma_req = 77, }, + { .name = "rx", .dma_req = 78, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, }; -/* l4 core -> mcspi4 interface */ -static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { - { - .pa_start = 0x480ba000, - .pa_end = 0x480ba0ff, - .flags = ADDR_TYPE_RT, - }, - { } +static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { + &omap3xxx_l4_core__mmc3, }; -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi4, - .clk = "mcspi4_ick", - .addr = omap34xx_mcspi4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap3xxx_mmc3_hwmod = { + .name = "mmc3", + .mpu_irqs = omap34xx_mmc3_mpu_irqs, + .sdma_reqs = omap34xx_mmc3_sdma_reqs, + .opt_clks = omap34xx_mmc3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), + .main_clk = "mmchs3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, + }, + }, + .slaves = omap3xxx_mmc3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), + .class = &omap34xx_mmc_class, }; +/* + * 'usb_host_hs' class + * high-speed multi-port usb host controller + */ static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { .master = &omap3xxx_usb_host_hs_hwmod, .slave = &omap3xxx_l3_main_hwmod, @@ -3013,6 +3341,27 @@ static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap3xxx_usb_host_hs_sysc, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = { + &omap3xxx_usb_host_hs__l3_main_2, +}; + static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { { .name = "uhh", @@ -3041,6 +3390,117 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = { + &omap3xxx_l4_core__usb_host_hs, +}; + +static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { + { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, +}; + +static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 }, + { .name = "ehci-irq", .irq = 77 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap3xxx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_host_hs_irqs, + .main_clk = "usbhost_48m_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430ES2_USBHOST_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, + }, + }, + .opt_clks = omap3xxx_usb_host_hs_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), + .slaves = omap3xxx_usb_host_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves), + .masters = omap3xxx_usb_host_hs_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters), + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, +}; + +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ +static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap3xxx_usb_tll_hs_sysc, +}; + +static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 }, + { .irq = -1 } +}; + static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { { .name = "tll", @@ -3059,156 +3519,183 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l3_main__l4_core, - &omap3xxx_l3_main__l4_per, - &omap3xxx_mpu__l3_main, - &omap3xxx_l4_core__l4_wkup, - &omap3xxx_l4_core__mmc3, - &omap3_l4_core__uart1, - &omap3_l4_core__uart2, - &omap3_l4_per__uart3, - &omap3_l4_core__i2c1, - &omap3_l4_core__i2c2, - &omap3_l4_core__i2c3, - &omap3xxx_l4_wkup__l4_sec, - &omap3xxx_l4_wkup__timer1, - &omap3xxx_l4_per__timer2, - &omap3xxx_l4_per__timer3, - &omap3xxx_l4_per__timer4, - &omap3xxx_l4_per__timer5, - &omap3xxx_l4_per__timer6, - &omap3xxx_l4_per__timer7, - &omap3xxx_l4_per__timer8, - &omap3xxx_l4_per__timer9, - &omap3xxx_l4_core__timer10, - &omap3xxx_l4_core__timer11, - &omap3xxx_l4_wkup__wd_timer2, - &omap3xxx_l4_wkup__gpio1, - &omap3xxx_l4_per__gpio2, - &omap3xxx_l4_per__gpio3, - &omap3xxx_l4_per__gpio4, - &omap3xxx_l4_per__gpio5, - &omap3xxx_l4_per__gpio6, - &omap3xxx_dma_system__l3, - &omap3xxx_l4_core__dma_system, - &omap3xxx_l4_core__mcbsp1, - &omap3xxx_l4_per__mcbsp2, - &omap3xxx_l4_per__mcbsp3, - &omap3xxx_l4_per__mcbsp4, - &omap3xxx_l4_core__mcbsp5, - &omap3xxx_l4_per__mcbsp2_sidetone, - &omap3xxx_l4_per__mcbsp3_sidetone, - &omap34xx_l4_core__mcspi1, - &omap34xx_l4_core__mcspi2, - &omap34xx_l4_core__mcspi3, - &omap34xx_l4_core__mcspi4, +static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { + &omap3xxx_l4_core__usb_tll_hs, +}; + +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap3xxx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_tll_hs_irqs, + .main_clk = "usbtll_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 3, + .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .idlest_reg_id = 3, + .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, + }, + }, + .slaves = omap3xxx_usb_tll_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), +}; + +static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { + &omap3xxx_l3_main_hwmod, + &omap3xxx_l4_core_hwmod, + &omap3xxx_l4_per_hwmod, + &omap3xxx_l4_wkup_hwmod, + &omap3xxx_mmc3_hwmod, + &omap3xxx_mpu_hwmod, + + &omap3xxx_timer1_hwmod, + &omap3xxx_timer2_hwmod, + &omap3xxx_timer3_hwmod, + &omap3xxx_timer4_hwmod, + &omap3xxx_timer5_hwmod, + &omap3xxx_timer6_hwmod, + &omap3xxx_timer7_hwmod, + &omap3xxx_timer8_hwmod, + &omap3xxx_timer9_hwmod, + &omap3xxx_timer10_hwmod, + &omap3xxx_timer11_hwmod, + + &omap3xxx_wd_timer2_hwmod, + &omap3xxx_uart1_hwmod, + &omap3xxx_uart2_hwmod, + &omap3xxx_uart3_hwmod, + + /* i2c class */ + &omap3xxx_i2c1_hwmod, + &omap3xxx_i2c2_hwmod, + &omap3xxx_i2c3_hwmod, + + /* gpio class */ + &omap3xxx_gpio1_hwmod, + &omap3xxx_gpio2_hwmod, + &omap3xxx_gpio3_hwmod, + &omap3xxx_gpio4_hwmod, + &omap3xxx_gpio5_hwmod, + &omap3xxx_gpio6_hwmod, + + /* dma_system class*/ + &omap3xxx_dma_system_hwmod, + + /* mcbsp class */ + &omap3xxx_mcbsp1_hwmod, + &omap3xxx_mcbsp2_hwmod, + &omap3xxx_mcbsp3_hwmod, + &omap3xxx_mcbsp4_hwmod, + &omap3xxx_mcbsp5_hwmod, + &omap3xxx_mcbsp2_sidetone_hwmod, + &omap3xxx_mcbsp3_sidetone_hwmod, + + + /* mcspi class */ + &omap34xx_mcspi1, + &omap34xx_mcspi2, + &omap34xx_mcspi3, + &omap34xx_mcspi4, + NULL, }; -/* GP-only hwmod links */ -static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_sec__timer12, +/* GP-only hwmods */ +static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { + &omap3xxx_timer12_hwmod, NULL }; -/* 3430ES1-only hwmod links */ -static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { - &omap3430es1_dss__l3, - &omap3430es1_l4_core__dss, +/* 3430ES1-only hwmods */ +static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { + &omap3430es1_dss_core_hwmod, NULL }; -/* 3430ES2+-only hwmod links */ -static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_dss__l3, - &omap3xxx_l4_core__dss, - &omap3xxx_usbhsotg__l3, - &omap3xxx_l4_core__usbhsotg, - &omap3xxx_usb_host_hs__l3_main_2, - &omap3xxx_l4_core__usb_host_hs, - &omap3xxx_l4_core__usb_tll_hs, +/* 3430ES2+-only hwmods */ +static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { + &omap3xxx_dss_core_hwmod, + &omap3xxx_usbhsotg_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, NULL }; -/* <= 3430ES3-only hwmod links */ -static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_core__pre_es3_mmc1, - &omap3xxx_l4_core__pre_es3_mmc2, +/* <= 3430ES3-only hwmods */ +static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { + &omap3xxx_pre_es3_mmc1_hwmod, + &omap3xxx_pre_es3_mmc2_hwmod, NULL }; -/* 3430ES3+-only hwmod links */ -static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_core__es3plus_mmc1, - &omap3xxx_l4_core__es3plus_mmc2, +/* 3430ES3+-only hwmods */ +static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; -/* 34xx-only hwmod links (all ES revisions) */ -static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l3__iva, - &omap34xx_l4_core__sr1, - &omap34xx_l4_core__sr2, - &omap3xxx_l4_core__mailbox, +/* 34xx-only hwmods (all ES revisions) */ +static __initdata struct omap_hwmod *omap34xx_hwmods[] = { + &omap3xxx_iva_hwmod, + &omap34xx_sr1_hwmod, + &omap34xx_sr2_hwmod, + &omap3xxx_mailbox_hwmod, NULL }; -/* 36xx-only hwmod links (all ES revisions) */ -static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l3__iva, - &omap36xx_l4_per__uart4, - &omap3xxx_dss__l3, - &omap3xxx_l4_core__dss, - &omap36xx_l4_core__sr1, - &omap36xx_l4_core__sr2, - &omap3xxx_usbhsotg__l3, - &omap3xxx_l4_core__usbhsotg, - &omap3xxx_l4_core__mailbox, - &omap3xxx_usb_host_hs__l3_main_2, - &omap3xxx_l4_core__usb_host_hs, - &omap3xxx_l4_core__usb_tll_hs, - &omap3xxx_l4_core__es3plus_mmc1, - &omap3xxx_l4_core__es3plus_mmc2, +/* 36xx-only hwmods (all ES revisions) */ +static __initdata struct omap_hwmod *omap36xx_hwmods[] = { + &omap3xxx_iva_hwmod, + &omap3xxx_uart4_hwmod, + &omap3xxx_dss_core_hwmod, + &omap36xx_sr1_hwmod, + &omap36xx_sr2_hwmod, + &omap3xxx_usbhsotg_hwmod, + &omap3xxx_mailbox_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; -static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_dss__l3, - &omap3xxx_l4_core__dss, - &am35xx_usbhsotg__l3, - &am35xx_l4_core__usbhsotg, - &am35xx_l4_core__uart4, - &omap3xxx_usb_host_hs__l3_main_2, - &omap3xxx_l4_core__usb_host_hs, - &omap3xxx_l4_core__usb_tll_hs, - &omap3xxx_l4_core__es3plus_mmc1, - &omap3xxx_l4_core__es3plus_mmc2, +static __initdata struct omap_hwmod *am35xx_hwmods[] = { + &omap3xxx_dss_core_hwmod, /* XXX ??? */ + &am35xx_usbhsotg_hwmod, + &am35xx_uart4_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; -static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_core__dss_dispc, - &omap3xxx_l4_core__dss_dsi1, - &omap3xxx_l4_core__dss_rfbi, - &omap3xxx_l4_core__dss_venc, +static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { + /* dss class */ + &omap3xxx_dss_dispc_hwmod, + &omap3xxx_dss_dsi1_hwmod, + &omap3xxx_dss_rfbi_hwmod, + &omap3xxx_dss_venc_hwmod, NULL }; int __init omap3xxx_hwmod_init(void) { int r; - struct omap_hwmod_ocp_if **h = NULL; + struct omap_hwmod **h = NULL; unsigned int rev; - /* Register hwmod links common to all OMAP3 */ - r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); + /* Register hwmods common to all OMAP3 */ + r = omap_hwmod_register(omap3xxx_hwmods); if (r < 0) return r; - /* Register GP-only hwmod links. */ + /* Register GP-only hwmods. */ if (omap_type() == OMAP2_DEVICE_TYPE_GP) { - r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); + r = omap_hwmod_register(omap3xxx_gp_hwmods); if (r < 0) return r; } @@ -3216,43 +3703,43 @@ int __init omap3xxx_hwmod_init(void) rev = omap_rev(); /* - * Register hwmod links common to individual OMAP3 families, all + * Register hwmods common to individual OMAP3 families, all * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) * All possible revisions should be included in this conditional. */ if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap34xx_hwmod_ocp_ifs; - } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { - h = am35xx_hwmod_ocp_ifs; + h = omap34xx_hwmods; + } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { + h = am35xx_hwmods; } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) { - h = omap36xx_hwmod_ocp_ifs; + h = omap36xx_hwmods; } else { WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); return -EINVAL; }; - r = omap_hwmod_register_links(h); + r = omap_hwmod_register(h); if (r < 0) return r; /* - * Register hwmod links specific to certain ES levels of a + * Register hwmods specific to certain ES levels of a * particular family of silicon (e.g., 34xx ES1.0) */ h = NULL; if (rev == OMAP3430_REV_ES1_0) { - h = omap3430es1_hwmod_ocp_ifs; + h = omap3430es1_hwmods; } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap3430es2plus_hwmod_ocp_ifs; + h = omap3430es2plus_hwmods; }; if (h) { - r = omap_hwmod_register_links(h); + r = omap_hwmod_register(h); if (r < 0) return r; } @@ -3260,29 +3747,29 @@ int __init omap3xxx_hwmod_init(void) h = NULL; if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1) { - h = omap3430_pre_es3_hwmod_ocp_ifs; + h = omap3430_pre_es3_hwmods; } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap3430_es3plus_hwmod_ocp_ifs; + h = omap3430_es3plus_hwmods; }; if (h) - r = omap_hwmod_register_links(h); + r = omap_hwmod_register(h); if (r < 0) return r; /* * DSS code presumes that dss_core hwmod is handled first, * _before_ any other DSS related hwmods so register common - * DSS hwmod links last to ensure that dss_core is already - * registered. Otherwise some change things may happen, for - * ex. if dispc is handled before dss_core and DSS is enabled - * in bootloader DISPC will be reset with outputs enabled - * which sometimes leads to unrecoverable L3 error. XXX The - * long-term fix to this is to ensure hwmods are set up in - * dependency order in the hwmod core code. + * DSS hwmods last to ensure that dss_core is already registered. + * Otherwise some change things may happen, for ex. if dispc + * is handled before dss_core and DSS is enabled in bootloader + * DIPSC will be reset with outputs enabled which sometimes leads + * to unrecoverable L3 error. + * XXX The long-term fix to this is to ensure modules are set up + * in dependency order in the hwmod core code. */ - r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); + r = omap_hwmod_register(omap3xxx_dss_hwmods); return r; } diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 49061295475c..6abc75753e42 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1,7 +1,7 @@ /* * Hardware modules present on the OMAP44xx chips * - * Copyright (C) 2009-2012 Texas Instruments, Inc. + * Copyright (C) 2009-2011 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley @@ -44,33 +44,40 @@ #define OMAP44XX_IRQ_GIC_START 32 /* Base offset for all OMAP4 dma requests */ -#define OMAP44XX_DMA_REQ_START 1 +#define OMAP44XX_DMA_REQ_START 1 + +/* Backward references (IPs with Bus Master capability) */ +static struct omap_hwmod omap44xx_aess_hwmod; +static struct omap_hwmod omap44xx_dma_system_hwmod; +static struct omap_hwmod omap44xx_dmm_hwmod; +static struct omap_hwmod omap44xx_dsp_hwmod; +static struct omap_hwmod omap44xx_dss_hwmod; +static struct omap_hwmod omap44xx_emif_fw_hwmod; +static struct omap_hwmod omap44xx_hsi_hwmod; +static struct omap_hwmod omap44xx_ipu_hwmod; +static struct omap_hwmod omap44xx_iss_hwmod; +static struct omap_hwmod omap44xx_iva_hwmod; +static struct omap_hwmod omap44xx_l3_instr_hwmod; +static struct omap_hwmod omap44xx_l3_main_1_hwmod; +static struct omap_hwmod omap44xx_l3_main_2_hwmod; +static struct omap_hwmod omap44xx_l3_main_3_hwmod; +static struct omap_hwmod omap44xx_l4_abe_hwmod; +static struct omap_hwmod omap44xx_l4_cfg_hwmod; +static struct omap_hwmod omap44xx_l4_per_hwmod; +static struct omap_hwmod omap44xx_l4_wkup_hwmod; +static struct omap_hwmod omap44xx_mmc1_hwmod; +static struct omap_hwmod omap44xx_mmc2_hwmod; +static struct omap_hwmod omap44xx_mpu_hwmod; +static struct omap_hwmod omap44xx_mpu_private_hwmod; +static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; +static struct omap_hwmod omap44xx_usb_host_hs_hwmod; +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; /* - * IP blocks + * Interconnects omap_hwmod structures + * hwmods that compose the global OMAP interconnect */ -/* - * 'c2c_target_fw' class - * instance(s): c2c_target_fw - */ -static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { - .name = "c2c_target_fw", -}; - -/* c2c_target_fw */ -static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { - .name = "c2c_target_fw", - .class = &omap44xx_c2c_target_fw_hwmod_class, - .clkdm_name = "d2d_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, - }, - }, -}; - /* * 'dmm' class * instance(s): dmm @@ -85,17 +92,51 @@ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { { .irq = -1 } }; +/* l3_main_1 -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { + { + .pa_start = 0x4e000000, + .pa_end = 0x4e0007ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* mpu -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dmm_addrs, + .user = OCP_USER_MPU, +}; + +/* dmm slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { + &omap44xx_l3_main_1__dmm, + &omap44xx_mpu__dmm, +}; + static struct omap_hwmod omap44xx_dmm_hwmod = { .name = "dmm", .class = &omap44xx_dmm_hwmod_class, .clkdm_name = "l3_emif_clkdm", - .mpu_irqs = omap44xx_dmm_irqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_dmm_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), + .mpu_irqs = omap44xx_dmm_irqs, }; /* @@ -107,6 +148,38 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { }; /* emif_fw */ +/* dmm -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { + .master = &omap44xx_dmm_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { + { + .pa_start = 0x4a20c000, + .pa_end = 0x4a20c0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_emif_fw_addrs, + .user = OCP_USER_MPU, +}; + +/* emif_fw slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { + &omap44xx_dmm__emif_fw, + &omap44xx_l4_cfg__emif_fw, +}; + static struct omap_hwmod omap44xx_emif_fw_hwmod = { .name = "emif_fw", .class = &omap44xx_emif_fw_hwmod_class, @@ -117,6 +190,8 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = { .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_emif_fw_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), }; /* @@ -128,6 +203,28 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = { }; /* l3_instr */ +/* iva -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_3 -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { + .master = &omap44xx_l3_main_3_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_instr slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { + &omap44xx_iva__l3_instr, + &omap44xx_l3_main_3__l3_instr, +}; + static struct omap_hwmod omap44xx_l3_instr_hwmod = { .name = "l3_instr", .class = &omap44xx_l3_hwmod_class, @@ -139,6 +236,8 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, + .slaves = omap44xx_l3_instr_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), }; /* l3_main_1 */ @@ -148,6 +247,83 @@ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { { .irq = -1 } }; +/* dsp -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { + .master = &omap44xx_dss_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { + .master = &omap44xx_mmc1_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { + .master = &omap44xx_mmc2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { + { + .pa_start = 0x44000000, + .pa_end = 0x44000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_1_addrs, + .user = OCP_USER_MPU, +}; + +/* l3_main_1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { + &omap44xx_dsp__l3_main_1, + &omap44xx_dss__l3_main_1, + &omap44xx_l3_main_2__l3_main_1, + &omap44xx_l4_cfg__l3_main_1, + &omap44xx_mmc1__l3_main_1, + &omap44xx_mmc2__l3_main_1, + &omap44xx_mpu__l3_main_1, +}; + static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .name = "l3_main_1", .class = &omap44xx_l3_hwmod_class, @@ -159,9 +335,97 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_l3_main_1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), }; /* l3_main_2 */ +/* dma_system -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { + .master = &omap44xx_dma_system_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* hsi -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { + .master = &omap44xx_hsi_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { + .master = &omap44xx_ipu_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iss -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { + .master = &omap44xx_iss_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iva -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { + { + .pa_start = 0x44800000, + .pa_end = 0x44801fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_2_addrs, + .user = OCP_USER_MPU, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_otg_hs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { + .master = &omap44xx_usb_otg_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { + &omap44xx_dma_system__l3_main_2, + &omap44xx_hsi__l3_main_2, + &omap44xx_ipu__l3_main_2, + &omap44xx_iss__l3_main_2, + &omap44xx_iva__l3_main_2, + &omap44xx_l3_main_1__l3_main_2, + &omap44xx_l4_cfg__l3_main_2, + &omap44xx_usb_otg_hs__l3_main_2, +}; + static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .name = "l3_main_2", .class = &omap44xx_l3_hwmod_class, @@ -172,20 +436,65 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_l3_main_2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), }; /* l3_main_3 */ -static struct omap_hwmod omap44xx_l3_main_3_hwmod = { - .name = "l3_main_3", - .class = &omap44xx_l3_hwmod_class, - .clkdm_name = "l3_instr_clkdm", - .prcm = { +static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { + { + .pa_start = 0x45000000, + .pa_end = 0x45000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_3_addrs, + .user = OCP_USER_MPU, +}; + +/* l3_main_2 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { + &omap44xx_l3_main_1__l3_main_3, + &omap44xx_l3_main_2__l3_main_3, + &omap44xx_l4_cfg__l3_main_3, +}; + +static struct omap_hwmod omap44xx_l3_main_3_hwmod = { + .name = "l3_main_3", + .class = &omap44xx_l3_hwmod_class, + .clkdm_name = "l3_instr_clkdm", + .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, .modulemode = MODULEMODE_HWCTRL, }, }, + .slaves = omap44xx_l3_main_3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), }; /* @@ -197,6 +506,46 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = { }; /* l4_abe */ +/* aess -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { + .master = &omap44xx_aess_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { + &omap44xx_aess__l4_abe, + &omap44xx_dsp__l4_abe, + &omap44xx_l3_main_1__l4_abe, + &omap44xx_mpu__l4_abe, +}; + static struct omap_hwmod omap44xx_l4_abe_hwmod = { .name = "l4_abe", .class = &omap44xx_l4_hwmod_class, @@ -206,9 +555,24 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, }, }, + .slaves = omap44xx_l4_abe_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), }; /* l4_cfg */ +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_cfg_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { + &omap44xx_l3_main_1__l4_cfg, +}; + static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .name = "l4_cfg", .class = &omap44xx_l4_hwmod_class, @@ -219,9 +583,24 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_l4_cfg_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), }; /* l4_per */ +/* l3_main_2 -> l4_per */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l4_per_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { + &omap44xx_l3_main_2__l4_per, +}; + static struct omap_hwmod omap44xx_l4_per_hwmod = { .name = "l4_per", .class = &omap44xx_l4_hwmod_class, @@ -232,9 +611,24 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_l4_per_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), }; /* l4_wkup */ +/* l4_cfg -> l4_wkup */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l4_wkup_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { + &omap44xx_l4_cfg__l4_wkup, +}; + static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .name = "l4_wkup", .class = &omap44xx_l4_hwmod_class, @@ -245,6 +639,8 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), }; /* @@ -256,32 +652,25 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { }; /* mpu_private */ -static struct omap_hwmod omap44xx_mpu_private_hwmod = { - .name = "mpu_private", - .class = &omap44xx_mpu_bus_hwmod_class, - .clkdm_name = "mpuss_clkdm", +/* mpu -> mpu_private */ +static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_mpu_private_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* - * 'ocp_wp_noc' class - * instance(s): ocp_wp_noc - */ -static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { - .name = "ocp_wp_noc", +/* mpu_private slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { + &omap44xx_mpu__mpu_private, }; -/* ocp_wp_noc */ -static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { - .name = "ocp_wp_noc", - .class = &omap44xx_ocp_wp_noc_hwmod_class, - .clkdm_name = "l3_instr_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, +static struct omap_hwmod omap44xx_mpu_private_hwmod = { + .name = "mpu_private", + .class = &omap44xx_mpu_bus_hwmod_class, + .clkdm_name = "mpuss_clkdm", + .slaves = omap44xx_mpu_private_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), }; /* @@ -292,7 +681,41 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { * - They still need to be validated with the driver * properly adapted to omap_hwmod / omap_device * - * usim + * c2c + * c2c_target_fw + * cm_core + * cm_core_aon + * ctrl_module_core + * ctrl_module_pad_core + * ctrl_module_pad_wkup + * ctrl_module_wkup + * debugss + * efuse_ctrl_cust + * efuse_ctrl_std + * elm + * emif1 + * emif2 + * fdif + * gpmc + * gpu + * hdq1w + * mcasp + * mpu_c0 + * mpu_c1 + * ocmc_ram + * ocp2scp_usb_phy + * ocp_wp_noc + * prcm_mpu + * prm + * scrm + * sl2if + * slimbus1 + * slimbus2 + * usb_host_fs + * usb_host_hs + * usb_phy_cm + * usb_tll_hs + * usim */ /* @@ -333,6 +756,53 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { { .dma_req = -1 } }; +/* aess master ports */ +static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { + &omap44xx_aess__l4_abe, +}; + +static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { + { + .pa_start = 0x401f1000, + .pa_end = 0x401f13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> aess */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_aess_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_aess_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { + { + .pa_start = 0x490f1000, + .pa_end = 0x490f13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> aess (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_aess_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_aess_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* aess slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { + &omap44xx_l4_abe__aess, + &omap44xx_l4_abe__aess_dma, +}; + static struct omap_hwmod omap44xx_aess_hwmod = { .name = "aess", .class = &omap44xx_aess_hwmod_class, @@ -347,41 +817,37 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_aess_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), + .masters = omap44xx_aess_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), }; /* - * 'c2c' class - * chip 2 chip interface used to plug the ape soc (omap) with an external modem - * soc + * 'bandgap' class + * bangap reference for ldo regulators */ -static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { - .name = "c2c", -}; - -/* c2c */ -static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { - { .irq = 88 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { + .name = "bandgap", }; -static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { - { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } +/* bandgap */ +static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { + { .role = "fclk", .clk = "bandgap_fclk" }, }; -static struct omap_hwmod omap44xx_c2c_hwmod = { - .name = "c2c", - .class = &omap44xx_c2c_hwmod_class, - .clkdm_name = "d2d_clkdm", - .mpu_irqs = omap44xx_c2c_irqs, - .sdma_reqs = omap44xx_c2c_sdma_reqs, +static struct omap_hwmod omap44xx_bandgap_hwmod = { + .name = "bandgap", + .class = &omap44xx_bandgap_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, + .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, }, }, + .opt_clks = bandgap_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), }; /* @@ -404,95 +870,44 @@ static struct omap_hwmod_class omap44xx_counter_hwmod_class = { }; /* counter_32k */ -static struct omap_hwmod omap44xx_counter_32k_hwmod = { - .name = "counter_32k", - .class = &omap44xx_counter_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "sys_32k_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, - }, +static struct omap_hwmod omap44xx_counter_32k_hwmod; +static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { + { + .pa_start = 0x4a304000, + .pa_end = 0x4a30401f, + .flags = ADDR_TYPE_RT }, + { } }; -/* - * 'ctrl_module' class - * attila core control module + core pad control module + wkup pad control - * module + attila wkup control module - */ - -static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { - .name = "ctrl_module", - .sysc = &omap44xx_ctrl_module_sysc, -}; - -/* ctrl_module_core */ -static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { - { .irq = 8 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { - .name = "ctrl_module_core", - .class = &omap44xx_ctrl_module_hwmod_class, - .clkdm_name = "l4_cfg_clkdm", - .mpu_irqs = omap44xx_ctrl_module_core_irqs, -}; - -/* ctrl_module_pad_core */ -static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { - .name = "ctrl_module_pad_core", - .class = &omap44xx_ctrl_module_hwmod_class, - .clkdm_name = "l4_cfg_clkdm", +/* l4_wkup -> counter_32k */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_counter_32k_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_counter_32k_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* ctrl_module_wkup */ -static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { - .name = "ctrl_module_wkup", - .class = &omap44xx_ctrl_module_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", +/* counter_32k slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { + &omap44xx_l4_wkup__counter_32k, }; -/* ctrl_module_pad_wkup */ -static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { - .name = "ctrl_module_pad_wkup", - .class = &omap44xx_ctrl_module_hwmod_class, +static struct omap_hwmod omap44xx_counter_32k_hwmod = { + .name = "counter_32k", + .class = &omap44xx_counter_hwmod_class, .clkdm_name = "l4_wkup_clkdm", -}; - -/* - * 'debugss' class - * debug and emulation sub system - */ - -static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { - .name = "debugss", -}; - -/* debugss */ -static struct omap_hwmod omap44xx_debugss_hwmod = { - .name = "debugss", - .class = &omap44xx_debugss_hwmod_class, - .clkdm_name = "emu_sys_clkdm", - .main_clk = "trace_clk_div_ck", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "sys_32k_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, + .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_counter_32k_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), }; /* @@ -535,19 +950,51 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod omap44xx_dma_system_hwmod = { - .name = "dma_system", - .class = &omap44xx_dma_hwmod_class, - .clkdm_name = "l3_dma_clkdm", - .mpu_irqs = omap44xx_dma_system_irqs, - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { + &omap44xx_dma_system__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { + { + .pa_start = 0x4a056000, + .pa_end = 0x4a056fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dma_system_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { + &omap44xx_l4_cfg__dma_system, +}; + +static struct omap_hwmod omap44xx_dma_system_hwmod = { + .name = "dma_system", + .class = &omap44xx_dma_hwmod_class, + .clkdm_name = "l3_dma_clkdm", + .mpu_irqs = omap44xx_dma_system_irqs, + .main_clk = "l3_div_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, }, }, .dev_attr = &dma_dev_attr, + .slaves = omap44xx_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), + .masters = omap44xx_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), }; /* @@ -571,6 +1018,7 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { }; /* dmic */ +static struct omap_hwmod omap44xx_dmic_hwmod; static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { { .irq = 114 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -581,6 +1029,50 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4012e000, + .pa_end = 0x4012e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> dmic */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x4902e000, + .pa_end = 0x4902e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> dmic (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* dmic slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { + &omap44xx_l4_abe__dmic, + &omap44xx_l4_abe__dmic_dma, +}; + static struct omap_hwmod omap44xx_dmic_hwmod = { .name = "dmic", .class = &omap44xx_dmic_hwmod_class, @@ -595,6 +1087,8 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_dmic_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), }; /* @@ -613,10 +1107,55 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { }; static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { - { .name = "dsp", .rst_shift = 0 }, { .name = "mmu_cache", .rst_shift = 1 }, }; +static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { + { .name = "dsp", .rst_shift = 0 }, +}; + +/* dsp -> iva */ +static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "dpll_iva_m5x2_ck", +}; + +/* dsp master ports */ +static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { + &omap44xx_dsp__l3_main_1, + &omap44xx_dsp__l4_abe, + &omap44xx_dsp__iva, +}; + +/* l4_cfg -> dsp */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dsp_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { + &omap44xx_l4_cfg__dsp, +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_dsp_c0_hwmod = { + .name = "dsp_c0", + .class = &omap44xx_dsp_hwmod_class, + .clkdm_name = "tesla_clkdm", + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_dsp_c0_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), + .prcm = { + .omap4 = { + .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, + }, + }, +}; + static struct omap_hwmod omap44xx_dsp_hwmod = { .name = "dsp", .class = &omap44xx_dsp_hwmod_class, @@ -633,6 +1172,10 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, + .slaves = omap44xx_dsp_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), + .masters = omap44xx_dsp_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), }; /* @@ -653,6 +1196,53 @@ static struct omap_hwmod_class omap44xx_dss_hwmod_class = { }; /* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { + &omap44xx_dss__l3_main_1, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { + { + .pa_start = 0x58000000, + .pa_end = 0x5800007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { + { + .pa_start = 0x48040000, + .pa_end = 0x4804007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_addrs, + .user = OCP_USER_MPU, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { + &omap44xx_l3_main_2__dss, + &omap44xx_l4_per__dss, +}; + static struct omap_hwmod_opt_clk dss_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, { .role = "tv_clk", .clk = "dss_tv_clk" }, @@ -673,6 +1263,10 @@ static struct omap_hwmod omap44xx_dss_hwmod = { }, .opt_clks = dss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap44xx_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), + .masters = omap44xx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), }; /* @@ -699,6 +1293,7 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { }; /* dss_dispc */ +static struct omap_hwmod omap44xx_dss_dispc_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { { .irq = 25 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -709,11 +1304,53 @@ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { + { + .pa_start = 0x58001000, + .pa_end = 0x58001fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dispc_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { + { + .pa_start = 0x48041000, + .pa_end = 0x48041fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { .manager_count = 3, .has_framedonetv_irq = 1 }; +/* l4_per -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dispc_addrs, + .user = OCP_USER_MPU, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { + &omap44xx_l3_main_2__dss_dispc, + &omap44xx_l4_per__dss_dispc, +}; + static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap44xx_dispc_hwmod_class, @@ -727,6 +1364,8 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), .dev_attr = &omap44xx_dss_dispc_dev_attr }; @@ -752,6 +1391,7 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { }; /* dss_dsi1 */ +static struct omap_hwmod omap44xx_dss_dsi1_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { { .irq = 53 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -762,6 +1402,48 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { + { + .pa_start = 0x58004000, + .pa_end = 0x580041ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dsi1_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { + { + .pa_start = 0x48044000, + .pa_end = 0x480441ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi1_addrs, + .user = OCP_USER_MPU, +}; + +/* dss_dsi1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { + &omap44xx_l3_main_2__dss_dsi1, + &omap44xx_l4_per__dss_dsi1, +}; + static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -781,9 +1463,12 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { }, .opt_clks = dss_dsi1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), + .slaves = omap44xx_dss_dsi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), }; /* dss_dsi2 */ +static struct omap_hwmod omap44xx_dss_dsi2_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { { .irq = 84 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -794,25 +1479,69 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { - { .role = "sys_clk", .clk = "dss_sys_clk" }, +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { + { + .pa_start = 0x58005000, + .pa_end = 0x580051ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { - .name = "dss_dsi2", - .class = &omap44xx_dsi_hwmod_class, - .clkdm_name = "l3_dss_clkdm", - .mpu_irqs = omap44xx_dss_dsi2_irqs, - .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, - .main_clk = "dss_dss_clk", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, - }, +/* l3_main_2 -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dsi2_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { + { + .pa_start = 0x48045000, + .pa_end = 0x480451ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi2_addrs, + .user = OCP_USER_MPU, +}; + +/* dss_dsi2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { + &omap44xx_l3_main_2__dss_dsi2, + &omap44xx_l4_per__dss_dsi2, +}; + +static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, +}; + +static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { + .name = "dss_dsi2", + .class = &omap44xx_dsi_hwmod_class, + .clkdm_name = "l3_dss_clkdm", + .mpu_irqs = omap44xx_dss_dsi2_irqs, + .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, + .main_clk = "dss_dss_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, + }, }, .opt_clks = dss_dsi2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), + .slaves = omap44xx_dss_dsi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), }; /* @@ -836,6 +1565,7 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { }; /* dss_hdmi */ +static struct omap_hwmod omap44xx_dss_hdmi_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { { .irq = 101 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -846,6 +1576,48 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { + { + .pa_start = 0x58006000, + .pa_end = 0x58006fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_hdmi_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { + { + .pa_start = 0x48046000, + .pa_end = 0x48046fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_hdmi_addrs, + .user = OCP_USER_MPU, +}; + +/* dss_hdmi slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { + &omap44xx_l3_main_2__dss_hdmi, + &omap44xx_l4_per__dss_hdmi, +}; + static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -865,6 +1637,8 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { }, .opt_clks = dss_hdmi_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), + .slaves = omap44xx_dss_hdmi_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), }; /* @@ -888,11 +1662,54 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { }; /* dss_rfbi */ +static struct omap_hwmod omap44xx_dss_rfbi_hwmod; static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { + { + .pa_start = 0x58002000, + .pa_end = 0x580020ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_rfbi_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { + { + .pa_start = 0x48042000, + .pa_end = 0x480420ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_rfbi_addrs, + .user = OCP_USER_MPU, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { + &omap44xx_l3_main_2__dss_rfbi, + &omap44xx_l4_per__dss_rfbi, +}; + static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "dss_fck" }, }; @@ -911,6 +1728,8 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { }, .opt_clks = dss_rfbi_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), + .slaves = omap44xx_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), }; /* @@ -923,165 +1742,62 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = { }; /* dss_venc */ -static struct omap_hwmod omap44xx_dss_venc_hwmod = { - .name = "dss_venc", - .class = &omap44xx_venc_hwmod_class, - .clkdm_name = "l3_dss_clkdm", - .main_clk = "dss_tv_clk", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, - }, - }, -}; - -/* - * 'elm' class - * bch error location module - */ - -static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_elm_hwmod_class = { - .name = "elm", - .sysc = &omap44xx_elm_sysc, -}; - -/* elm */ -static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { - { .irq = 4 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_elm_hwmod = { - .name = "elm", - .class = &omap44xx_elm_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_elm_irqs, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, - }, - }, -}; - -/* - * 'emif' class - * external memory interface no1 - */ - -static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { - .rev_offs = 0x0000, -}; - -static struct omap_hwmod_class omap44xx_emif_hwmod_class = { - .name = "emif", - .sysc = &omap44xx_emif_sysc, -}; - -/* emif1 */ -static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { - { .irq = 110 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_emif1_hwmod = { - .name = "emif1", - .class = &omap44xx_emif_hwmod_class, - .clkdm_name = "l3_emif_clkdm", - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, - .mpu_irqs = omap44xx_emif1_irqs, - .main_clk = "ddrphy_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, +static struct omap_hwmod omap44xx_dss_venc_hwmod; +static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { + { + .pa_start = 0x58003000, + .pa_end = 0x580030ff, + .flags = ADDR_TYPE_RT }, + { } }; -/* emif2 */ -static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { - { .irq = 111 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +/* l3_main_2 -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_venc_dma_addrs, + .user = OCP_USER_SDMA, }; -static struct omap_hwmod omap44xx_emif2_hwmod = { - .name = "emif2", - .class = &omap44xx_emif_hwmod_class, - .clkdm_name = "l3_emif_clkdm", - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, - .mpu_irqs = omap44xx_emif2_irqs, - .main_clk = "ddrphy_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, +static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { + { + .pa_start = 0x48043000, + .pa_end = 0x480430ff, + .flags = ADDR_TYPE_RT }, + { } }; -/* - * 'fdif' class - * face detection hw accelerator module - */ - -static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - /* - * FDIF needs 100 OCP clk cycles delay after a softreset before - * accessing sysconfig again. - * The lowest frequency at the moment for L3 bus is 100 MHz, so - * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). - * - * TODO: Indicate errata when available. - */ - .srst_udelay = 2, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { - .name = "fdif", - .sysc = &omap44xx_fdif_sysc, +/* l4_per -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_venc_addrs, + .user = OCP_USER_MPU, }; -/* fdif */ -static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { - { .irq = 69 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { + &omap44xx_l3_main_2__dss_venc, + &omap44xx_l4_per__dss_venc, }; -static struct omap_hwmod omap44xx_fdif_hwmod = { - .name = "fdif", - .class = &omap44xx_fdif_hwmod_class, - .clkdm_name = "iss_clkdm", - .mpu_irqs = omap44xx_fdif_irqs, - .main_clk = "fdif_fck", +static struct omap_hwmod omap44xx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap44xx_venc_hwmod_class, + .clkdm_name = "l3_dss_clkdm", + .main_clk = "dss_tv_clk", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), }; /* @@ -1114,13 +1830,37 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { }; /* gpio1 */ +static struct omap_hwmod omap44xx_gpio1_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { { .irq = 29 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { - { .role = "dbclk", .clk = "gpio1_dbclk" }, +static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { + { + .pa_start = 0x4a310000, + .pa_end = 0x4a3101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_gpio1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { + &omap44xx_l4_wkup__gpio1, +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbclk" }, }; static struct omap_hwmod omap44xx_gpio1_hwmod = { @@ -1139,14 +1879,40 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .opt_clks = gpio1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), }; /* gpio2 */ +static struct omap_hwmod omap44xx_gpio2_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { { .irq = 30 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { + { + .pa_start = 0x48055000, + .pa_end = 0x480551ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { + &omap44xx_l4_per__gpio2, +}; + static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbclk" }, }; @@ -1168,14 +1934,40 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { .opt_clks = gpio2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), }; /* gpio3 */ +static struct omap_hwmod omap44xx_gpio3_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { { .irq = 31 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { + { + .pa_start = 0x48057000, + .pa_end = 0x480571ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { + &omap44xx_l4_per__gpio3, +}; + static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbclk" }, }; @@ -1197,14 +1989,40 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { .opt_clks = gpio3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), }; /* gpio4 */ +static struct omap_hwmod omap44xx_gpio4_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { { .irq = 32 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { + { + .pa_start = 0x48059000, + .pa_end = 0x480591ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { + &omap44xx_l4_per__gpio4, +}; + static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { { .role = "dbclk", .clk = "gpio4_dbclk" }, }; @@ -1226,14 +2044,40 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { .opt_clks = gpio4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), }; /* gpio5 */ +static struct omap_hwmod omap44xx_gpio5_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { { .irq = 33 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { + { + .pa_start = 0x4805b000, + .pa_end = 0x4805b1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio5 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { + &omap44xx_l4_per__gpio5, +}; + static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { { .role = "dbclk", .clk = "gpio5_dbclk" }, }; @@ -1255,14 +2099,40 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { .opt_clks = gpio5_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), }; /* gpio6 */ +static struct omap_hwmod omap44xx_gpio6_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { { .irq = 34 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { + { + .pa_start = 0x4805d000, + .pa_end = 0x4805d1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio6_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio6 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { + &omap44xx_l4_per__gpio6, +}; + static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { { .role = "dbclk", .clk = "gpio6_dbclk" }, }; @@ -1284,135 +2154,8 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .opt_clks = gpio6_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), .dev_attr = &gpio_dev_attr, -}; - -/* - * 'gpmc' class - * general purpose memory controller - */ - -static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { - .name = "gpmc", - .sysc = &omap44xx_gpmc_sysc, -}; - -/* gpmc */ -static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { - { .irq = 20 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { - { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - -static struct omap_hwmod omap44xx_gpmc_hwmod = { - .name = "gpmc", - .class = &omap44xx_gpmc_hwmod_class, - .clkdm_name = "l3_2_clkdm", - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, - .mpu_irqs = omap44xx_gpmc_irqs, - .sdma_reqs = omap44xx_gpmc_sdma_reqs, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* - * 'gpu' class - * 2d/3d graphics accelerator - */ - -static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { - .rev_offs = 0x1fc00, - .sysc_offs = 0x1fc10, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { - .name = "gpu", - .sysc = &omap44xx_gpu_sysc, -}; - -/* gpu */ -static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { - { .irq = 21 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_gpu_hwmod = { - .name = "gpu", - .class = &omap44xx_gpu_hwmod_class, - .clkdm_name = "l3_gfx_clkdm", - .mpu_irqs = omap44xx_gpu_irqs, - .main_clk = "gpu_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'hdq1w' class - * hdq / 1-wire serial interface controller - */ - -static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0014, - .syss_offs = 0x0018, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { - .name = "hdq1w", - .sysc = &omap44xx_hdq1w_sysc, -}; - -/* hdq1w */ -static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { - { .irq = 58 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_hdq1w_hwmod = { - .name = "hdq1w", - .class = &omap44xx_hdq1w_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ - .mpu_irqs = omap44xx_hdq1w_irqs, - .main_clk = "hdq1w_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, + .slaves = omap44xx_gpio6_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), }; /* @@ -1447,6 +2190,34 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { { .irq = -1 } }; +/* hsi master ports */ +static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { + &omap44xx_hsi__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { + { + .pa_start = 0x4a058000, + .pa_end = 0x4a05bfff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> hsi */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_hsi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_hsi_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* hsi slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { + &omap44xx_l4_cfg__hsi, +}; + static struct omap_hwmod omap44xx_hsi_hwmod = { .name = "hsi", .class = &omap44xx_hsi_hwmod_class, @@ -1460,6 +2231,10 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, + .slaves = omap44xx_hsi_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), + .masters = omap44xx_hsi_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), }; /* @@ -1491,6 +2266,7 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* i2c1 */ +static struct omap_hwmod omap44xx_i2c1_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { { .irq = 56 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1502,6 +2278,29 @@ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x480700ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { + &omap44xx_l4_per__i2c1, +}; + static struct omap_hwmod omap44xx_i2c1_hwmod = { .name = "i2c1", .class = &omap44xx_i2c_hwmod_class, @@ -1517,10 +2316,13 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), .dev_attr = &i2c_dev_attr, }; /* i2c2 */ +static struct omap_hwmod omap44xx_i2c2_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { { .irq = 57 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1532,25 +2334,51 @@ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod omap44xx_i2c2_hwmod = { - .name = "i2c2", - .class = &omap44xx_i2c_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap44xx_i2c2_irqs, - .sdma_reqs = omap44xx_i2c2_sdma_reqs, - .main_clk = "i2c2_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &i2c_dev_attr, -}; - +static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x480720ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { + &omap44xx_l4_per__i2c2, +}; + +static struct omap_hwmod omap44xx_i2c2_hwmod = { + .name = "i2c2", + .class = &omap44xx_i2c_hwmod_class, + .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .mpu_irqs = omap44xx_i2c2_irqs, + .sdma_reqs = omap44xx_i2c2_sdma_reqs, + .main_clk = "i2c2_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .slaves = omap44xx_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), + .dev_attr = &i2c_dev_attr, +}; + /* i2c3 */ +static struct omap_hwmod omap44xx_i2c3_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { { .irq = 61 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1562,6 +2390,29 @@ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x480600ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { + &omap44xx_l4_per__i2c3, +}; + static struct omap_hwmod omap44xx_i2c3_hwmod = { .name = "i2c3", .class = &omap44xx_i2c_hwmod_class, @@ -1577,10 +2428,13 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_i2c3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), .dev_attr = &i2c_dev_attr, }; /* i2c4 */ +static struct omap_hwmod omap44xx_i2c4_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { { .irq = 62 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1592,6 +2446,29 @@ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { + { + .pa_start = 0x48350000, + .pa_end = 0x483500ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { + &omap44xx_l4_per__i2c4, +}; + static struct omap_hwmod omap44xx_i2c4_hwmod = { .name = "i2c4", .class = &omap44xx_i2c_hwmod_class, @@ -1607,6 +2484,8 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_i2c4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), .dev_attr = &i2c_dev_attr, }; @@ -1625,12 +2504,66 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { +static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { { .name = "cpu0", .rst_shift = 0 }, +}; + +static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { { .name = "cpu1", .rst_shift = 1 }, +}; + +static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "mmu_cache", .rst_shift = 2 }, }; +/* ipu master ports */ +static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { + &omap44xx_ipu__l3_main_2, +}; + +/* l3_main_2 -> ipu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_ipu_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { + &omap44xx_l3_main_2__ipu, +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_ipu_c0_hwmod = { + .name = "ipu_c0", + .class = &omap44xx_ipu_hwmod_class, + .clkdm_name = "ducati_clkdm", + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_ipu_c0_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), + .prcm = { + .omap4 = { + .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, + }, + }, +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_ipu_c1_hwmod = { + .name = "ipu_c1", + .class = &omap44xx_ipu_hwmod_class, + .clkdm_name = "ducati_clkdm", + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_ipu_c1_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), + .prcm = { + .omap4 = { + .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, + }, + }, +}; + static struct omap_hwmod omap44xx_ipu_hwmod = { .name = "ipu", .class = &omap44xx_ipu_hwmod_class, @@ -1647,6 +2580,10 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, + .slaves = omap44xx_ipu_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), + .masters = omap44xx_ipu_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), }; /* @@ -1693,6 +2630,34 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { { .dma_req = -1 } }; +/* iss master ports */ +static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { + &omap44xx_iss__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { + { + .pa_start = 0x52000000, + .pa_end = 0x520000ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> iss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iss_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iss slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { + &omap44xx_l3_main_2__iss, +}; + static struct omap_hwmod_opt_clk iss_opt_clks[] = { { .role = "ctrlclk", .clk = "iss_ctrlclk" }, }; @@ -1713,6 +2678,10 @@ static struct omap_hwmod omap44xx_iss_hwmod = { }, .opt_clks = iss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), + .slaves = omap44xx_iss_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), + .masters = omap44xx_iss_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), }; /* @@ -1733,9 +2702,75 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { }; static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { + { .name = "logic", .rst_shift = 2 }, +}; + +static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { { .name = "seq0", .rst_shift = 0 }, +}; + +static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { { .name = "seq1", .rst_shift = 1 }, - { .name = "logic", .rst_shift = 2 }, +}; + +/* iva master ports */ +static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { + &omap44xx_iva__l3_main_2, + &omap44xx_iva__l3_instr, +}; + +static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { + { + .pa_start = 0x5a000000, + .pa_end = 0x5a07ffff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> iva */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iva_addrs, + .user = OCP_USER_MPU, +}; + +/* iva slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { + &omap44xx_dsp__iva, + &omap44xx_l3_main_2__iva, +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_iva_seq0_hwmod = { + .name = "iva_seq0", + .class = &omap44xx_iva_hwmod_class, + .clkdm_name = "ivahd_clkdm", + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_iva_seq0_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), + .prcm = { + .omap4 = { + .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, + }, + }, +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_iva_seq1_hwmod = { + .name = "iva_seq1", + .class = &omap44xx_iva_hwmod_class, + .clkdm_name = "ivahd_clkdm", + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_iva_seq1_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), + .prcm = { + .omap4 = { + .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, + }, + }, }; static struct omap_hwmod omap44xx_iva_hwmod = { @@ -1754,6 +2789,10 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, + .slaves = omap44xx_iva_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), + .masters = omap44xx_iva_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), }; /* @@ -1779,11 +2818,35 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { }; /* kbd */ +static struct omap_hwmod omap44xx_kbd_hwmod; static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { { .irq = 120 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { + { + .pa_start = 0x4a31c000, + .pa_end = 0x4a31c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> kbd */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_kbd_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_kbd_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* kbd slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { + &omap44xx_l4_wkup__kbd, +}; + static struct omap_hwmod omap44xx_kbd_hwmod = { .name = "kbd", .class = &omap44xx_kbd_hwmod_class, @@ -1797,6 +2860,8 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_kbd_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), }; /* @@ -1820,11 +2885,35 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { }; /* mailbox */ +static struct omap_hwmod omap44xx_mailbox_hwmod; static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { { .irq = 26 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { + { + .pa_start = 0x4a0f4000, + .pa_end = 0x4a0f41ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> mailbox */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_mailbox_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { + &omap44xx_l4_cfg__mailbox, +}; + static struct omap_hwmod omap44xx_mailbox_hwmod = { .name = "mailbox", .class = &omap44xx_mailbox_hwmod_class, @@ -1836,89 +2925,84 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), }; /* - * 'mcasp' class - * multi-channel audio serial port controller + * 'mcbsp' class + * multi channel buffered serial port controller */ -/* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { - .sidle_shift = 0, +static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { - .sysc_offs = 0x0004, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type_mcasp, +static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap44xx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE4, }; -static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { - .name = "mcasp", - .sysc = &omap44xx_mcasp_sysc, +/* mcbsp1 */ +static struct omap_hwmod omap44xx_mcbsp1_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { + { .irq = 17 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } }; -/* mcasp */ -static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { - { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, - { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { - { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, - { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, +static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { + { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, { .dma_req = -1 } }; -static struct omap_hwmod omap44xx_mcasp_hwmod = { - .name = "mcasp", - .class = &omap44xx_mcasp_hwmod_class, - .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_mcasp_irqs, - .sdma_reqs = omap44xx_mcasp_sdma_reqs, - .main_clk = "mcasp_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, +static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40122000, + .pa_end = 0x401220ff, + .flags = ADDR_TYPE_RT }, + { } }; -/* - * 'mcbsp' class - * multi channel buffered serial port controller - */ - -static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { - .sysc_offs = 0x008c, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_abe -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_addrs, + .user = OCP_USER_MPU, }; -static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { - .name = "mcbsp", - .sysc = &omap44xx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE4, +static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, + { } }; -/* mcbsp1 */ -static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { - { .irq = 17 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +/* l4_abe -> mcbsp1 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_dma_addrs, + .user = OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { - { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { + &omap44xx_l4_abe__mcbsp1, + &omap44xx_l4_abe__mcbsp1_dma, }; static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { @@ -1940,11 +3024,14 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), .opt_clks = mcbsp1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), }; /* mcbsp2 */ +static struct omap_hwmod omap44xx_mcbsp2_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { { .irq = 22 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1956,6 +3043,50 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40124000, + .pa_end = 0x401240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp2 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { + &omap44xx_l4_abe__mcbsp2, + &omap44xx_l4_abe__mcbsp2_dma, +}; + static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, @@ -1975,11 +3106,14 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), .opt_clks = mcbsp2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), }; /* mcbsp3 */ +static struct omap_hwmod omap44xx_mcbsp3_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { { .irq = 23 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1991,6 +3125,50 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40126000, + .pa_end = 0x401260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { + &omap44xx_l4_abe__mcbsp3, + &omap44xx_l4_abe__mcbsp3_dma, +}; + static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, @@ -2010,11 +3188,14 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), .opt_clks = mcbsp3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), }; /* mcbsp4 */ +static struct omap_hwmod omap44xx_mcbsp4_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { { .irq = 16 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2026,6 +3207,29 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { + { + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcbsp4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { + &omap44xx_l4_per__mcbsp4, +}; + static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, @@ -2045,6 +3249,8 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), .opt_clks = mcbsp4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), }; @@ -2071,6 +3277,7 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { }; /* mcpdm */ +static struct omap_hwmod omap44xx_mcpdm_hwmod; static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { { .irq = 112 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2082,6 +3289,48 @@ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { + { + .pa_start = 0x40132000, + .pa_end = 0x4013207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcpdm */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x4903207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcpdm (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* mcpdm slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { + &omap44xx_l4_abe__mcpdm, + &omap44xx_l4_abe__mcpdm_dma, +}; + static struct omap_hwmod omap44xx_mcpdm_hwmod = { .name = "mcpdm", .class = &omap44xx_mcpdm_hwmod_class, @@ -2096,6 +3345,8 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mcpdm_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), }; /* @@ -2121,6 +3372,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { }; /* mcspi1 */ +static struct omap_hwmod omap44xx_mcspi1_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { { .irq = 65 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2138,6 +3390,29 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480981ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcspi1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { + &omap44xx_l4_per__mcspi1, +}; + /* mcspi1 dev_attr */ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { .num_chipselect = 4, @@ -2158,9 +3433,12 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { }, }, .dev_attr = &mcspi1_dev_attr, + .slaves = omap44xx_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), }; /* mcspi2 */ +static struct omap_hwmod omap44xx_mcspi2_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { { .irq = 66 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2174,6 +3452,29 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcspi2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { + &omap44xx_l4_per__mcspi2, +}; + /* mcspi2 dev_attr */ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { .num_chipselect = 2, @@ -2194,9 +3495,12 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { }, }, .dev_attr = &mcspi2_dev_attr, + .slaves = omap44xx_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), }; /* mcspi3 */ +static struct omap_hwmod omap44xx_mcspi3_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { { .irq = 91 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2210,10 +3514,33 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { { .dma_req = -1 } }; -/* mcspi3 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { - .num_chipselect = 2, -}; +static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { + { + .pa_start = 0x480b8000, + .pa_end = 0x480b81ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcspi3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { + &omap44xx_l4_per__mcspi3, +}; + +/* mcspi3 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { + .num_chipselect = 2, +}; static struct omap_hwmod omap44xx_mcspi3_hwmod = { .name = "mcspi3", @@ -2230,9 +3557,12 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { }, }, .dev_attr = &mcspi3_dev_attr, + .slaves = omap44xx_mcspi3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), }; /* mcspi4 */ +static struct omap_hwmod omap44xx_mcspi4_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { { .irq = 48 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2244,6 +3574,29 @@ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcspi4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { + &omap44xx_l4_per__mcspi4, +}; + /* mcspi4 dev_attr */ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { .num_chipselect = 1, @@ -2264,6 +3617,8 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { }, }, .dev_attr = &mcspi4_dev_attr, + .slaves = omap44xx_mcspi4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), }; /* @@ -2300,6 +3655,34 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { { .dma_req = -1 } }; +/* mmc1 master ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { + &omap44xx_mmc1__l3_main_1, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { + &omap44xx_l4_per__mmc1, +}; + /* mmc1 dev_attr */ static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, @@ -2320,6 +3703,10 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { }, }, .dev_attr = &mmc1_dev_attr, + .slaves = omap44xx_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), + .masters = omap44xx_mmc1_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), }; /* mmc2 */ @@ -2334,6 +3721,34 @@ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { { .dma_req = -1 } }; +/* mmc2 master ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { + &omap44xx_mmc2__l3_main_1, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { + { + .pa_start = 0x480b4000, + .pa_end = 0x480b43ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { + &omap44xx_l4_per__mmc2, +}; + static struct omap_hwmod omap44xx_mmc2_hwmod = { .name = "mmc2", .class = &omap44xx_mmc_hwmod_class, @@ -2348,9 +3763,14 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), + .masters = omap44xx_mmc2_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), }; /* mmc3 */ +static struct omap_hwmod omap44xx_mmc3_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { { .irq = 94 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2362,6 +3782,29 @@ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { + &omap44xx_l4_per__mmc3, +}; + static struct omap_hwmod omap44xx_mmc3_hwmod = { .name = "mmc3", .class = &omap44xx_mmc_hwmod_class, @@ -2376,9 +3819,12 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mmc3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), }; /* mmc4 */ +static struct omap_hwmod omap44xx_mmc4_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { { .irq = 96 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2390,11 +3836,35 @@ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { + { + .pa_start = 0x480d1000, + .pa_end = 0x480d13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { + &omap44xx_l4_per__mmc4, +}; + static struct omap_hwmod omap44xx_mmc4_hwmod = { .name = "mmc4", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mmc4_irqs, + .sdma_reqs = omap44xx_mmc4_sdma_reqs, .main_clk = "mmc4_fck", .prcm = { @@ -2404,9 +3874,12 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mmc4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), }; /* mmc5 */ +static struct omap_hwmod omap44xx_mmc5_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { { .irq = 59 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2418,6 +3891,29 @@ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { + { + .pa_start = 0x480d5000, + .pa_end = 0x480d53ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc5 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { + &omap44xx_l4_per__mmc5, +}; + static struct omap_hwmod omap44xx_mmc5_hwmod = { .name = "mmc5", .class = &omap44xx_mmc_hwmod_class, @@ -2432,6 +3928,8 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_mmc5_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), }; /* @@ -2451,6 +3949,13 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { { .irq = -1 } }; +/* mpu master ports */ +static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { + &omap44xx_mpu__l3_main_1, + &omap44xx_mpu__l4_abe, + &omap44xx_mpu__dmm, +}; + static struct omap_hwmod omap44xx_mpu_hwmod = { .name = "mpu", .class = &omap44xx_mpu_hwmod_class, @@ -2464,315 +3969,121 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, }, }, + .masters = omap44xx_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), }; /* - * 'ocmc_ram' class - * top-level core on-chip ram + * 'smartreflex' class + * smartreflex module (monitor silicon performance and outputs a measure of + * performance error) */ -static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { - .name = "ocmc_ram", +/* The IP is not compliant to type1 / type2 scheme */ +static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { + .sidle_shift = 24, + .enwkup_shift = 26, }; -/* ocmc_ram */ -static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { - .name = "ocmc_ram", - .class = &omap44xx_ocmc_ram_hwmod_class, - .clkdm_name = "l3_2_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, - }, - }, +static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { + .sysc_offs = 0x0038, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type_smartreflex, }; -/* - * 'ocp2scp' class - * bridge to transform ocp interface protocol to scp (serial control port) - * protocol - */ +static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap44xx_smartreflex_sysc, + .rev = 2, +}; -static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { - .name = "ocp2scp", +/* smartreflex_core */ +static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { + .sensor_voltdm_name = "core", }; -/* ocp2scp_usb_phy */ -static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { - { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, +static struct omap_hwmod omap44xx_smartreflex_core_hwmod; +static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { + { .irq = 19 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } }; -static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { - .name = "ocp2scp_usb_phy", - .class = &omap44xx_ocp2scp_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, +static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { + { + .pa_start = 0x4a0dd000, + .pa_end = 0x4a0dd03f, + .flags = ADDR_TYPE_RT }, - .opt_clks = ocp2scp_usb_phy_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), + { } }; -/* - * 'prcm' class - * power and reset manager (part of the prcm infrastructure) + clock manager 2 - * + clock manager 1 (in always on power domain) + local prm in mpu - */ - -static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { - .name = "prcm", +/* l4_cfg -> smartreflex_core */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_core_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_core_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* prcm_mpu */ -static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { - .name = "prcm_mpu", - .class = &omap44xx_prcm_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", +/* smartreflex_core slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { + &omap44xx_l4_cfg__smartreflex_core, }; -/* cm_core_aon */ -static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { - .name = "cm_core_aon", - .class = &omap44xx_prcm_hwmod_class, - .clkdm_name = "cm_clkdm", +static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { + .name = "smartreflex_core", + .class = &omap44xx_smartreflex_hwmod_class, + .clkdm_name = "l4_ao_clkdm", + .mpu_irqs = omap44xx_smartreflex_core_irqs, + + .main_clk = "smartreflex_core_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .slaves = omap44xx_smartreflex_core_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), + .dev_attr = &smartreflex_core_dev_attr, }; -/* cm_core */ -static struct omap_hwmod omap44xx_cm_core_hwmod = { - .name = "cm_core", - .class = &omap44xx_prcm_hwmod_class, - .clkdm_name = "cm_clkdm", +/* smartreflex_iva */ +static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { + .sensor_voltdm_name = "iva", }; -/* prm */ -static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { - { .irq = 11 + OMAP44XX_IRQ_GIC_START }, +static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; +static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { + { .irq = 102 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { - { .name = "rst_global_warm_sw", .rst_shift = 0 }, - { .name = "rst_global_cold_sw", .rst_shift = 1 }, +static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { + { + .pa_start = 0x4a0db000, + .pa_end = 0x4a0db03f, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap44xx_prm_hwmod = { - .name = "prm", - .class = &omap44xx_prcm_hwmod_class, - .clkdm_name = "prm_clkdm", - .mpu_irqs = omap44xx_prm_irqs, - .rst_lines = omap44xx_prm_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), +/* l4_cfg -> smartreflex_iva */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_iva_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_iva_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* - * 'scrm' class - * system clock and reset manager - */ - -static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { - .name = "scrm", -}; - -/* scrm */ -static struct omap_hwmod omap44xx_scrm_hwmod = { - .name = "scrm", - .class = &omap44xx_scrm_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* - * 'sl2if' class - * shared level 2 memory interface - */ - -static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { - .name = "sl2if", -}; - -/* sl2if */ -static struct omap_hwmod omap44xx_sl2if_hwmod = { - .name = "sl2if", - .class = &omap44xx_sl2if_hwmod_class, - .clkdm_name = "ivahd_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* - * 'slimbus' class - * bidirectional, multi-drop, multi-channel two-line serial interface between - * the device and external components - */ - -static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { - .name = "slimbus", - .sysc = &omap44xx_slimbus_sysc, -}; - -/* slimbus1 */ -static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { - { .irq = 97 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { - { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, - { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, - { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, - { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, - { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, - { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, - { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, - { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - -static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { - { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, - { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, - { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, - { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, -}; - -static struct omap_hwmod omap44xx_slimbus1_hwmod = { - .name = "slimbus1", - .class = &omap44xx_slimbus_hwmod_class, - .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_slimbus1_irqs, - .sdma_reqs = omap44xx_slimbus1_sdma_reqs, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = slimbus1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), -}; - -/* slimbus2 */ -static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { - { .irq = 98 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { - { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, - { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, - { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, - { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, - { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, - { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, - { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, - { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - -static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { - { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, - { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, - { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, -}; - -static struct omap_hwmod omap44xx_slimbus2_hwmod = { - .name = "slimbus2", - .class = &omap44xx_slimbus_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_slimbus2_irqs, - .sdma_reqs = omap44xx_slimbus2_sdma_reqs, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = slimbus2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), -}; - -/* - * 'smartreflex' class - * smartreflex module (monitor silicon performance and outputs a measure of - * performance error) - */ - -/* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { - .sidle_shift = 24, - .enwkup_shift = 26, -}; - -static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { - .sysc_offs = 0x0038, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type_smartreflex, -}; - -static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { - .name = "smartreflex", - .sysc = &omap44xx_smartreflex_sysc, - .rev = 2, -}; - -/* smartreflex_core */ -static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { - .sensor_voltdm_name = "core", -}; - -static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { - { .irq = 19 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { - .name = "smartreflex_core", - .class = &omap44xx_smartreflex_hwmod_class, - .clkdm_name = "l4_ao_clkdm", - .mpu_irqs = omap44xx_smartreflex_core_irqs, - - .main_clk = "smartreflex_core_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &smartreflex_core_dev_attr, -}; - -/* smartreflex_iva */ -static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { - .sensor_voltdm_name = "iva", -}; - -static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { - { .irq = 102 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +/* smartreflex_iva slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { + &omap44xx_l4_cfg__smartreflex_iva, }; static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { @@ -2788,6 +4099,8 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_smartreflex_iva_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), .dev_attr = &smartreflex_iva_dev_attr, }; @@ -2796,11 +4109,35 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { .sensor_voltdm_name = "mpu", }; +static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { { .irq = 18 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { + { + .pa_start = 0x4a0d9000, + .pa_end = 0x4a0d903f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_mpu */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_mpu_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_mpu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* smartreflex_mpu slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { + &omap44xx_l4_cfg__smartreflex_mpu, +}; + static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .name = "smartreflex_mpu", .class = &omap44xx_smartreflex_hwmod_class, @@ -2814,6 +4151,8 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_smartreflex_mpu_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), .dev_attr = &smartreflex_mpu_dev_attr, }; @@ -2841,6 +4180,30 @@ static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { }; /* spinlock */ +static struct omap_hwmod omap44xx_spinlock_hwmod; +static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { + { + .pa_start = 0x4a0f6000, + .pa_end = 0x4a0f6fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> spinlock */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_spinlock_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_spinlock_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* spinlock slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { + &omap44xx_l4_cfg__spinlock, +}; + static struct omap_hwmod omap44xx_spinlock_hwmod = { .name = "spinlock", .class = &omap44xx_spinlock_hwmod_class, @@ -2851,6 +4214,8 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = { .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, }, }, + .slaves = omap44xx_spinlock_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), }; /* @@ -2902,11 +4267,35 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { }; /* timer1 */ +static struct omap_hwmod omap44xx_timer1_hwmod; static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { { .irq = 37 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { + { + .pa_start = 0x4a318000, + .pa_end = 0x4a31807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_timer1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { + &omap44xx_l4_wkup__timer1, +}; + static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", .class = &omap44xx_timer_1ms_hwmod_class, @@ -2921,14 +4310,40 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, + .slaves = omap44xx_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), }; /* timer2 */ +static struct omap_hwmod omap44xx_timer2_hwmod; static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { { .irq = 38 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { + { + .pa_start = 0x48032000, + .pa_end = 0x4803207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { + &omap44xx_l4_per__timer2, +}; + static struct omap_hwmod omap44xx_timer2_hwmod = { .name = "timer2", .class = &omap44xx_timer_1ms_hwmod_class, @@ -2943,14 +4358,40 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, + .slaves = omap44xx_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), }; /* timer3 */ +static struct omap_hwmod omap44xx_timer3_hwmod; static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { { .irq = 39 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { + { + .pa_start = 0x48034000, + .pa_end = 0x4803407f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { + &omap44xx_l4_per__timer3, +}; + static struct omap_hwmod omap44xx_timer3_hwmod = { .name = "timer3", .class = &omap44xx_timer_hwmod_class, @@ -2965,14 +4406,40 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, + .slaves = omap44xx_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), }; /* timer4 */ +static struct omap_hwmod omap44xx_timer4_hwmod; static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { { .irq = 40 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { + { + .pa_start = 0x48036000, + .pa_end = 0x4803607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { + &omap44xx_l4_per__timer4, +}; + static struct omap_hwmod omap44xx_timer4_hwmod = { .name = "timer4", .class = &omap44xx_timer_hwmod_class, @@ -2987,20 +4454,65 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, + .slaves = omap44xx_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), }; /* timer5 */ +static struct omap_hwmod omap44xx_timer5_hwmod; static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { { .irq = 41 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod omap44xx_timer5_hwmod = { - .name = "timer5", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_timer5_irqs, - .main_clk = "timer5_fck", +static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { + { + .pa_start = 0x40138000, + .pa_end = 0x4013807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x4903807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer5 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* timer5 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { + &omap44xx_l4_abe__timer5, + &omap44xx_l4_abe__timer5_dma, +}; + +static struct omap_hwmod omap44xx_timer5_hwmod = { + .name = "timer5", + .class = &omap44xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .mpu_irqs = omap44xx_timer5_irqs, + .main_clk = "timer5_fck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, @@ -3009,14 +4521,59 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, + .slaves = omap44xx_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), }; /* timer6 */ +static struct omap_hwmod omap44xx_timer6_hwmod; static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { { .irq = 42 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { + { + .pa_start = 0x4013a000, + .pa_end = 0x4013a07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { + { + .pa_start = 0x4903a000, + .pa_end = 0x4903a07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer6 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* timer6 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { + &omap44xx_l4_abe__timer6, + &omap44xx_l4_abe__timer6_dma, +}; + static struct omap_hwmod omap44xx_timer6_hwmod = { .name = "timer6", .class = &omap44xx_timer_hwmod_class, @@ -3032,14 +4589,59 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, + .slaves = omap44xx_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), }; /* timer7 */ +static struct omap_hwmod omap44xx_timer7_hwmod; static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { { .irq = 43 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { + { + .pa_start = 0x4013c000, + .pa_end = 0x4013c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer7 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { + { + .pa_start = 0x4903c000, + .pa_end = 0x4903c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer7 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* timer7 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { + &omap44xx_l4_abe__timer7, + &omap44xx_l4_abe__timer7_dma, +}; + static struct omap_hwmod omap44xx_timer7_hwmod = { .name = "timer7", .class = &omap44xx_timer_hwmod_class, @@ -3054,14 +4656,59 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, + .slaves = omap44xx_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), }; /* timer8 */ +static struct omap_hwmod omap44xx_timer8_hwmod; static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { { .irq = 44 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { + { + .pa_start = 0x4013e000, + .pa_end = 0x4013e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer8 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { + { + .pa_start = 0x4903e000, + .pa_end = 0x4903e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer8 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* timer8 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { + &omap44xx_l4_abe__timer8, + &omap44xx_l4_abe__timer8_dma, +}; + static struct omap_hwmod omap44xx_timer8_hwmod = { .name = "timer8", .class = &omap44xx_timer_hwmod_class, @@ -3076,14 +4723,40 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, + .slaves = omap44xx_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), }; /* timer9 */ +static struct omap_hwmod omap44xx_timer9_hwmod; static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { { .irq = 45 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { + { + .pa_start = 0x4803e000, + .pa_end = 0x4803e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer9_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer9 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { + &omap44xx_l4_per__timer9, +}; + static struct omap_hwmod omap44xx_timer9_hwmod = { .name = "timer9", .class = &omap44xx_timer_hwmod_class, @@ -3098,14 +4771,40 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, + .slaves = omap44xx_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), }; /* timer10 */ +static struct omap_hwmod omap44xx_timer10_hwmod; static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { { .irq = 46 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x4808607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer10 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer10_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer10 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { + &omap44xx_l4_per__timer10, +}; + static struct omap_hwmod omap44xx_timer10_hwmod = { .name = "timer10", .class = &omap44xx_timer_1ms_hwmod_class, @@ -3120,14 +4819,40 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, + .slaves = omap44xx_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), }; /* timer11 */ +static struct omap_hwmod omap44xx_timer11_hwmod; static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { { .irq = 47 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x4808807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer11 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer11_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer11 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { + &omap44xx_l4_per__timer11, +}; + static struct omap_hwmod omap44xx_timer11_hwmod = { .name = "timer11", .class = &omap44xx_timer_hwmod_class, @@ -3142,6 +4867,8 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, + .slaves = omap44xx_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), }; /* @@ -3167,6 +4894,7 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = { }; /* uart1 */ +static struct omap_hwmod omap44xx_uart1_hwmod; static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { { .irq = 72 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3178,6 +4906,29 @@ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { + { + .pa_start = 0x4806a000, + .pa_end = 0x4806a0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { + &omap44xx_l4_per__uart1, +}; + static struct omap_hwmod omap44xx_uart1_hwmod = { .name = "uart1", .class = &omap44xx_uart_hwmod_class, @@ -3192,9 +4943,12 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), }; /* uart2 */ +static struct omap_hwmod omap44xx_uart2_hwmod; static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { { .irq = 73 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3206,12 +4960,35 @@ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod omap44xx_uart2_hwmod = { - .name = "uart2", - .class = &omap44xx_uart_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_uart2_irqs, - .sdma_reqs = omap44xx_uart2_sdma_reqs, +static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { + { + .pa_start = 0x4806c000, + .pa_end = 0x4806c0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { + &omap44xx_l4_per__uart2, +}; + +static struct omap_hwmod omap44xx_uart2_hwmod = { + .name = "uart2", + .class = &omap44xx_uart_hwmod_class, + .clkdm_name = "l4_per_clkdm", + .mpu_irqs = omap44xx_uart2_irqs, + .sdma_reqs = omap44xx_uart2_sdma_reqs, .main_clk = "uart2_fck", .prcm = { .omap4 = { @@ -3220,9 +4997,12 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), }; /* uart3 */ +static struct omap_hwmod omap44xx_uart3_hwmod; static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { { .irq = 74 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3234,6 +5014,29 @@ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { + { + .pa_start = 0x48020000, + .pa_end = 0x480200ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { + &omap44xx_l4_per__uart3, +}; + static struct omap_hwmod omap44xx_uart3_hwmod = { .name = "uart3", .class = &omap44xx_uart_hwmod_class, @@ -3249,9 +5052,12 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), }; /* uart4 */ +static struct omap_hwmod omap44xx_uart4_hwmod; static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { { .irq = 70 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3263,6 +5069,29 @@ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { { .dma_req = -1 } }; +static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { + { + .pa_start = 0x4806e000, + .pa_end = 0x4806e0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { + &omap44xx_l4_per__uart4, +}; + static struct omap_hwmod omap44xx_uart4_hwmod = { .name = "uart4", .class = &omap44xx_uart_hwmod_class, @@ -3277,147 +5106,8 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, -}; - -/* - * 'usb_host_fs' class - * full-speed usb host controller - */ - -/* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { - .midle_shift = 4, - .sidle_shift = 2, - .srst_shift = 1, -}; - -static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0210, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, -}; - -static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { - .name = "usb_host_fs", - .sysc = &omap44xx_usb_host_fs_sysc, -}; - -/* usb_host_fs */ -static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { - { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, - { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { - .name = "usb_host_fs", - .class = &omap44xx_usb_host_fs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap44xx_usb_host_fs_irqs, - .main_clk = "usb_host_fs_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'usb_host_hs' class - * high-speed multi-port usb host controller - */ - -static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap44xx_usb_host_hs_sysc, -}; - -/* usb_host_hs */ -static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, - { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap44xx_usb_host_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_host_hs_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .mpu_irqs = omap44xx_usb_host_hs_irqs, - - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ - - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ - - /* - * During system boot; If the hwmod framework resets the module - * the module will have smart idle settings; which can lead to deadlock - * (above Errata Id:i660); so, dont reset the module during boot; - * Use HWMOD_INIT_NO_RESET. - */ - - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | - HWMOD_INIT_NO_RESET, + .slaves = omap44xx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), }; /* @@ -3450,6 +5140,34 @@ static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { { .irq = -1 } }; +/* usb_otg_hs master ports */ +static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { + &omap44xx_usb_otg_hs__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { + { + .pa_start = 0x4a0ab000, + .pa_end = 0x4a0ab003, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> usb_otg_hs */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_otg_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_otg_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_otg_hs slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { + &omap44xx_l4_cfg__usb_otg_hs, +}; + static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { { .role = "xclk", .clk = "usb_otg_hs_xclk" }, }; @@ -3470,47 +5188,10 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { }, .opt_clks = usb_otg_hs_opt_clks, .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), -}; - -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ - -static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap44xx_usb_tll_hs_sysc, -}; - -static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap44xx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap44xx_usb_tll_hs_irqs, - .main_clk = "usb_tll_hs_ick", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, + .slaves = omap44xx_usb_otg_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), + .masters = omap44xx_usb_otg_hs_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), }; /* @@ -3537,32 +5218,101 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { }; /* wd_timer2 */ +static struct omap_hwmod omap44xx_wd_timer2_hwmod; static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { { .irq = 80 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod omap44xx_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap44xx_wd_timer_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = omap44xx_wd_timer2_irqs, - .main_clk = "wd_timer2_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, +static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { + { + .pa_start = 0x4a314000, + .pa_end = 0x4a31407f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_wd_timer2_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* wd_timer2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { + &omap44xx_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap44xx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap44xx_wd_timer_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = omap44xx_wd_timer2_irqs, + .main_clk = "wd_timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), }; /* wd_timer3 */ +static struct omap_hwmod omap44xx_wd_timer3_hwmod; static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { { .irq = 36 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; +static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { + { + .pa_start = 0x40130000, + .pa_end = 0x4013007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> wd_timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { + { + .pa_start = 0x49030000, + .pa_end = 0x4903007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> wd_timer3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* wd_timer3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { + &omap44xx_l4_abe__wd_timer3, + &omap44xx_l4_abe__wd_timer3_dma, +}; + static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .name = "wd_timer3", .class = &omap44xx_wd_timer_hwmod_class, @@ -3576,2572 +5326,365 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .slaves = omap44xx_wd_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), }; - /* - * interfaces + * 'usb_host_hs' class + * high-speed multi-port usb host controller */ +static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { + .master = &omap44xx_usb_host_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap44xx_usb_host_hs_sysc, +}; + +static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { + &omap44xx_usb_host_hs__l3_main_2, +}; -static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { +static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { { - .pa_start = 0x4a204000, - .pa_end = 0x4a2040ff, + .name = "uhh", + .pa_start = 0x4a064000, + .pa_end = 0x4a0647ff, .flags = ADDR_TYPE_RT }, - { } + { + .name = "ohci", + .pa_start = 0x4a064800, + .pa_end = 0x4a064bff, + }, + { + .name = "ehci", + .pa_start = 0x4a064c00, + .pa_end = 0x4a064fff, + }, + {} }; -/* c2c -> c2c_target_fw */ -static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { - .master = &omap44xx_c2c_hwmod, - .slave = &omap44xx_c2c_target_fw_hwmod, - .clk = "div_core_ck", - .addr = omap44xx_c2c_target_fw_addrs, - .user = OCP_USER_MPU, +static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, + { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } }; -/* l4_cfg -> c2c_target_fw */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_c2c_target_fw_hwmod, + .slave = &omap44xx_usb_host_hs_hwmod, .clk = "l4_div_ck", + .addr = omap44xx_usb_host_hs_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_1 -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_SDMA, +static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { + &omap44xx_l4_cfg__usb_host_hs, }; -static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { - { - .pa_start = 0x4e000000, - .pa_end = 0x4e0007ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap44xx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .main_clk = "usb_host_hs_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, }, - { } + .mpu_irqs = omap44xx_usb_host_hs_irqs, + .slaves = omap44xx_usb_host_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), + .masters = omap44xx_usb_host_hs_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, }; -/* mpu -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_dmm_addrs, - .user = OCP_USER_MPU, +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ +static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* c2c -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { - .master = &omap44xx_c2c_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "div_core_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap44xx_usb_tll_hs_sysc, }; -/* dmm -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { - .master = &omap44xx_dmm_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { +static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { { - .pa_start = 0x4a20c000, - .pa_end = 0x4a20c0ff, + .name = "tll", + .pa_start = 0x4a062000, + .pa_end = 0x4a063fff, .flags = ADDR_TYPE_RT }, - { } + {} }; -/* l4_cfg -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_emif_fw_hwmod, + .slave = &omap44xx_usb_tll_hs_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_emif_fw_addrs, - .user = OCP_USER_MPU, + .addr = omap44xx_usb_tll_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* iva -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { + &omap44xx_l4_cfg__usb_tll_hs, }; -/* l3_main_3 -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { - .master = &omap44xx_l3_main_3_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* ocp_wp_noc -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { - .master = &omap44xx_ocp_wp_noc_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dsp -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { - .master = &omap44xx_dss_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc1 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { - .master = &omap44xx_mmc1_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { - .master = &omap44xx_mmc2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { - { - .pa_start = 0x44000000, - .pa_end = 0x44000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* mpu -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_1_addrs, - .user = OCP_USER_MPU, -}; - -/* c2c_target_fw -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { - .master = &omap44xx_c2c_target_fw_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* debugss -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { - .master = &omap44xx_debugss_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "dbgclk_mux_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { - .master = &omap44xx_dma_system_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* fdif -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { - .master = &omap44xx_fdif_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpu -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { - .master = &omap44xx_gpu_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* hsi -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { - .master = &omap44xx_hsi_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* ipu -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { - .master = &omap44xx_ipu_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iss -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { - .master = &omap44xx_iss_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iva -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { - { - .pa_start = 0x44800000, - .pa_end = 0x44801fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_1 -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_2_addrs, - .user = OCP_USER_MPU, -}; - -/* l4_cfg -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_host_fs -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = { - .master = &omap44xx_usb_host_fs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_host_hs -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { - .master = &omap44xx_usb_host_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_otg_hs -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { - .master = &omap44xx_usb_otg_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { - { - .pa_start = 0x45000000, - .pa_end = 0x45000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_1 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_3_addrs, - .user = OCP_USER_MPU, -}; - -/* l3_main_2 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* aess -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { - .master = &omap44xx_aess_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dsp -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_1 -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_1 -> l4_cfg */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_cfg_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> l4_per */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l4_per_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l4_wkup */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l4_wkup_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> mpu_private */ -static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_mpu_private_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { - { - .pa_start = 0x4a102000, - .pa_end = 0x4a10207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> ocp_wp_noc */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_ocp_wp_noc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_ocp_wp_noc_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { - { - .pa_start = 0x401f1000, - .pa_end = 0x401f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> aess */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { - { - .pa_start = 0x490f1000, - .pa_end = 0x490f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> aess (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* l3_main_2 -> c2c */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_c2c_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { - { - .pa_start = 0x4a304000, - .pa_end = 0x4a30401f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_counter_32k_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_counter_32k_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { - { - .pa_start = 0x4a002000, - .pa_end = 0x4a0027ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> ctrl_module_core */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_ctrl_module_core_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_ctrl_module_core_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { - { - .pa_start = 0x4a100000, - .pa_end = 0x4a1007ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> ctrl_module_pad_core */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_ctrl_module_pad_core_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_ctrl_module_pad_core_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { - { - .pa_start = 0x4a30c000, - .pa_end = 0x4a30c7ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> ctrl_module_wkup */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_ctrl_module_wkup_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_ctrl_module_wkup_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { - { - .pa_start = 0x4a31e000, - .pa_end = 0x4a31e7ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> ctrl_module_pad_wkup */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_ctrl_module_pad_wkup_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = { - { - .pa_start = 0x54160000, - .pa_end = 0x54167fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_instr -> debugss */ -static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { - .master = &omap44xx_l3_instr_hwmod, - .slave = &omap44xx_debugss_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_debugss_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { - { - .pa_start = 0x4a056000, - .pa_end = 0x4a056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dma_system_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4012e000, - .pa_end = 0x4012e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> dmic */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x4902e000, - .pa_end = 0x4902e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> dmic (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* dsp -> iva */ -static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "dpll_iva_m5x2_ck", - .user = OCP_USER_DSP, -}; - -/* dsp -> sl2if */ -static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_sl2if_hwmod, - .clk = "dpll_iva_m5x2_ck", - .user = OCP_USER_DSP, -}; - -/* l4_cfg -> dsp */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dsp_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { - { - .pa_start = 0x58000000, - .pa_end = 0x5800007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { - { - .pa_start = 0x48040000, - .pa_end = 0x4804007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { - { - .pa_start = 0x58001000, - .pa_end = 0x58001fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dispc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dispc_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dispc_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { - { - .pa_start = 0x48041000, - .pa_end = 0x48041fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dispc */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dispc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dispc_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { - { - .pa_start = 0x58004000, - .pa_end = 0x580041ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dsi1_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { - { - .pa_start = 0x48044000, - .pa_end = 0x480441ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi1_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { - { - .pa_start = 0x58005000, - .pa_end = 0x580051ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dsi2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dsi2_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { - { - .pa_start = 0x48045000, - .pa_end = 0x480451ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dsi2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi2_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { - { - .pa_start = 0x58006000, - .pa_end = 0x58006fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_hdmi */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_hdmi_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { - { - .pa_start = 0x48046000, - .pa_end = 0x48046fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_hdmi */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_hdmi_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { - { - .pa_start = 0x58002000, - .pa_end = 0x580020ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_rfbi_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { - { - .pa_start = 0x48042000, - .pa_end = 0x480420ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_rfbi_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { - { - .pa_start = 0x58003000, - .pa_end = 0x580030ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_venc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_venc_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_venc_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { - { - .pa_start = 0x48043000, - .pa_end = 0x480430ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_venc */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_venc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_venc_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { - { - .pa_start = 0x48078000, - .pa_end = 0x48078fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> elm */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_elm_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_elm_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { - { - .pa_start = 0x4c000000, - .pa_end = 0x4c0000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* emif_fw -> emif1 */ -static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { - .master = &omap44xx_emif_fw_hwmod, - .slave = &omap44xx_emif1_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_emif1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { - { - .pa_start = 0x4d000000, - .pa_end = 0x4d0000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* emif_fw -> emif2 */ -static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { - .master = &omap44xx_emif_fw_hwmod, - .slave = &omap44xx_emif2_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_emif2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { - { - .pa_start = 0x4a10a000, - .pa_end = 0x4a10a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> fdif */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_fdif_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_fdif_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { - { - .pa_start = 0x4a310000, - .pa_end = 0x4a3101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_gpio1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_gpio1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { - { - .pa_start = 0x48055000, - .pa_end = 0x480551ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { - { - .pa_start = 0x48057000, - .pa_end = 0x480571ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { - { - .pa_start = 0x48059000, - .pa_end = 0x480591ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { - { - .pa_start = 0x4805b000, - .pa_end = 0x4805b1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio5_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { - { - .pa_start = 0x4805d000, - .pa_end = 0x4805d1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio6_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { - { - .pa_start = 0x50000000, - .pa_end = 0x500003ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> gpmc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_gpmc_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_gpmc_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { - { - .pa_start = 0x56000000, - .pa_end = 0x5600ffff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> gpu */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_gpu_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_gpu_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { - { - .pa_start = 0x480b2000, - .pa_end = 0x480b201f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> hdq1w */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_hdq1w_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_hdq1w_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { - { - .pa_start = 0x4a058000, - .pa_end = 0x4a05bfff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> hsi */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_hsi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_hsi_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { - { - .pa_start = 0x48070000, - .pa_end = 0x480700ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { - { - .pa_start = 0x48072000, - .pa_end = 0x480720ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { - { - .pa_start = 0x48060000, - .pa_end = 0x480600ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { - { - .pa_start = 0x48350000, - .pa_end = 0x483500ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> ipu */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_ipu_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { - { - .pa_start = 0x52000000, - .pa_end = 0x520000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> iss */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iss_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_iss_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iva -> sl2if */ -static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_sl2if_hwmod, - .clk = "dpll_iva_m5x2_ck", - .user = OCP_USER_IVA, -}; - -static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { - { - .pa_start = 0x5a000000, - .pa_end = 0x5a07ffff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> iva */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_iva_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { - { - .pa_start = 0x4a31c000, - .pa_end = 0x4a31c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> kbd */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_kbd_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_kbd_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { - { - .pa_start = 0x4a0f4000, - .pa_end = 0x4a0f41ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> mailbox */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_mailbox_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { - { - .pa_start = 0x40128000, - .pa_end = 0x401283ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcasp */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcasp_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcasp_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { - { - .pa_start = 0x49028000, - .pa_end = 0x490283ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcasp (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcasp_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcasp_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40122000, - .pa_end = 0x401220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp1 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40124000, - .pa_end = 0x401240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp2 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40126000, - .pa_end = 0x401260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { - { - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcbsp4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { - { - .pa_start = 0x40132000, - .pa_end = 0x4013207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcpdm */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { - { - .pa_start = 0x49032000, - .pa_end = 0x4903207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcpdm (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { - { - .pa_start = 0x48098000, - .pa_end = 0x480981ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { - { - .pa_start = 0x4809a000, - .pa_end = 0x4809a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { - { - .pa_start = 0x480b8000, - .pa_end = 0x480b81ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { - { - .pa_start = 0x480ba000, - .pa_end = 0x480ba1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { - { - .pa_start = 0x4809c000, - .pa_end = 0x4809c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { - { - .pa_start = 0x480b4000, - .pa_end = 0x480b43ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { - { - .pa_start = 0x480ad000, - .pa_end = 0x480ad3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { - { - .pa_start = 0x480d1000, - .pa_end = 0x480d13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { - { - .pa_start = 0x480d5000, - .pa_end = 0x480d53ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc5_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> ocmc_ram */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_ocmc_ram_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> ocp2scp_usb_phy */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_ocp2scp_usb_phy_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { - { - .pa_start = 0x48243000, - .pa_end = 0x48243fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* mpu_private -> prcm_mpu */ -static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { - .master = &omap44xx_mpu_private_hwmod, - .slave = &omap44xx_prcm_mpu_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_prcm_mpu_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { - { - .pa_start = 0x4a004000, - .pa_end = 0x4a004fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> cm_core_aon */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_cm_core_aon_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_cm_core_aon_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { - { - .pa_start = 0x4a008000, - .pa_end = 0x4a009fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> cm_core */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_cm_core_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_cm_core_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { - { - .pa_start = 0x4a306000, - .pa_end = 0x4a307fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> prm */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_prm_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_prm_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { - { - .pa_start = 0x4a30a000, - .pa_end = 0x4a30a7ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> scrm */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_scrm_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_scrm_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> sl2if */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_sl2if_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { - { - .pa_start = 0x4012c000, - .pa_end = 0x4012c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> slimbus1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_slimbus1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_slimbus1_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { - { - .pa_start = 0x4902c000, - .pa_end = 0x4902c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> slimbus1 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_slimbus1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_slimbus1_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { - { - .pa_start = 0x48076000, - .pa_end = 0x480763ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> slimbus2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_slimbus2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_slimbus2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { - { - .pa_start = 0x4a0dd000, - .pa_end = 0x4a0dd03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_core */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_core_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_core_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { - { - .pa_start = 0x4a0db000, - .pa_end = 0x4a0db03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_iva */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_iva_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_iva_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { - { - .pa_start = 0x4a0d9000, - .pa_end = 0x4a0d903f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_mpu */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_mpu_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_mpu_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { - { - .pa_start = 0x4a0f6000, - .pa_end = 0x4a0f6fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> spinlock */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_spinlock_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_spinlock_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { - { - .pa_start = 0x4a318000, - .pa_end = 0x4a31807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_timer1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { - { - .pa_start = 0x48032000, - .pa_end = 0x4803207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { - { - .pa_start = 0x48034000, - .pa_end = 0x4803407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { - { - .pa_start = 0x48036000, - .pa_end = 0x4803607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { - { - .pa_start = 0x40138000, - .pa_end = 0x4013807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x4903807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer5 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { - { - .pa_start = 0x4013a000, - .pa_end = 0x4013a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { - { - .pa_start = 0x4903a000, - .pa_end = 0x4903a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer6 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { - { - .pa_start = 0x4013c000, - .pa_end = 0x4013c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer7 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { - { - .pa_start = 0x4903c000, - .pa_end = 0x4903c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer7 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { - { - .pa_start = 0x4013e000, - .pa_end = 0x4013e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer8 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { - { - .pa_start = 0x4903e000, - .pa_end = 0x4903e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer8 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { - { - .pa_start = 0x4803e000, - .pa_end = 0x4803e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer9_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { - { - .pa_start = 0x48086000, - .pa_end = 0x4808607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer10 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer10_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { - { - .pa_start = 0x48088000, - .pa_end = 0x4808807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer11 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer11_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { - { - .pa_start = 0x4806a000, - .pa_end = 0x4806a0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { - { - .pa_start = 0x4806c000, - .pa_end = 0x4806c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { - { - .pa_start = 0x48020000, - .pa_end = 0x480200ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { - { - .pa_start = 0x4806e000, - .pa_end = 0x4806e0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { - { - .pa_start = 0x4a0a9000, - .pa_end = 0x4a0a93ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> usb_host_fs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_host_fs_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_usb_host_fs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { - { - .name = "uhh", - .pa_start = 0x4a064000, - .pa_end = 0x4a0647ff, - .flags = ADDR_TYPE_RT - }, - { - .name = "ohci", - .pa_start = 0x4a064800, - .pa_end = 0x4a064bff, - }, - { - .name = "ehci", - .pa_start = 0x4a064c00, - .pa_end = 0x4a064fff, - }, - {} -}; - -/* l4_cfg -> usb_host_hs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_host_hs_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_usb_host_hs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { - { - .pa_start = 0x4a0ab000, - .pa_end = 0x4a0ab003, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> usb_otg_hs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_otg_hs_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_usb_otg_hs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { - { - .name = "tll", - .pa_start = 0x4a062000, - .pa_end = 0x4a063fff, - .flags = ADDR_TYPE_RT - }, - {} -}; - -/* l4_cfg -> usb_tll_hs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_tll_hs_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_usb_tll_hs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { - { - .pa_start = 0x4a314000, - .pa_end = 0x4a31407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_wd_timer2_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { - { - .pa_start = 0x40130000, - .pa_end = 0x4013007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> wd_timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { - { - .pa_start = 0x49030000, - .pa_end = 0x4903007f, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap44xx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .main_clk = "usb_tll_hs_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, }, - { } -}; - -/* l4_abe -> wd_timer3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_dma_addrs, - .user = OCP_USER_SDMA, + .mpu_irqs = omap44xx_usb_tll_hs_irqs, + .slaves = omap44xx_usb_tll_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), }; -static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { - &omap44xx_c2c__c2c_target_fw, - &omap44xx_l4_cfg__c2c_target_fw, - &omap44xx_l3_main_1__dmm, - &omap44xx_mpu__dmm, - &omap44xx_c2c__emif_fw, - &omap44xx_dmm__emif_fw, - &omap44xx_l4_cfg__emif_fw, - &omap44xx_iva__l3_instr, - &omap44xx_l3_main_3__l3_instr, - &omap44xx_ocp_wp_noc__l3_instr, - &omap44xx_dsp__l3_main_1, - &omap44xx_dss__l3_main_1, - &omap44xx_l3_main_2__l3_main_1, - &omap44xx_l4_cfg__l3_main_1, - &omap44xx_mmc1__l3_main_1, - &omap44xx_mmc2__l3_main_1, - &omap44xx_mpu__l3_main_1, - &omap44xx_c2c_target_fw__l3_main_2, - &omap44xx_debugss__l3_main_2, - &omap44xx_dma_system__l3_main_2, - &omap44xx_fdif__l3_main_2, - &omap44xx_gpu__l3_main_2, - &omap44xx_hsi__l3_main_2, - &omap44xx_ipu__l3_main_2, - &omap44xx_iss__l3_main_2, - &omap44xx_iva__l3_main_2, - &omap44xx_l3_main_1__l3_main_2, - &omap44xx_l4_cfg__l3_main_2, - &omap44xx_usb_host_fs__l3_main_2, - &omap44xx_usb_host_hs__l3_main_2, - &omap44xx_usb_otg_hs__l3_main_2, - &omap44xx_l3_main_1__l3_main_3, - &omap44xx_l3_main_2__l3_main_3, - &omap44xx_l4_cfg__l3_main_3, - &omap44xx_aess__l4_abe, - &omap44xx_dsp__l4_abe, - &omap44xx_l3_main_1__l4_abe, - &omap44xx_mpu__l4_abe, - &omap44xx_l3_main_1__l4_cfg, - &omap44xx_l3_main_2__l4_per, - &omap44xx_l4_cfg__l4_wkup, - &omap44xx_mpu__mpu_private, - &omap44xx_l4_cfg__ocp_wp_noc, - &omap44xx_l4_abe__aess, - &omap44xx_l4_abe__aess_dma, - &omap44xx_l3_main_2__c2c, - &omap44xx_l4_wkup__counter_32k, - &omap44xx_l4_cfg__ctrl_module_core, - &omap44xx_l4_cfg__ctrl_module_pad_core, - &omap44xx_l4_wkup__ctrl_module_wkup, - &omap44xx_l4_wkup__ctrl_module_pad_wkup, - &omap44xx_l3_instr__debugss, - &omap44xx_l4_cfg__dma_system, - &omap44xx_l4_abe__dmic, - &omap44xx_l4_abe__dmic_dma, - &omap44xx_dsp__iva, - &omap44xx_dsp__sl2if, - &omap44xx_l4_cfg__dsp, - &omap44xx_l3_main_2__dss, - &omap44xx_l4_per__dss, - &omap44xx_l3_main_2__dss_dispc, - &omap44xx_l4_per__dss_dispc, - &omap44xx_l3_main_2__dss_dsi1, - &omap44xx_l4_per__dss_dsi1, - &omap44xx_l3_main_2__dss_dsi2, - &omap44xx_l4_per__dss_dsi2, - &omap44xx_l3_main_2__dss_hdmi, - &omap44xx_l4_per__dss_hdmi, - &omap44xx_l3_main_2__dss_rfbi, - &omap44xx_l4_per__dss_rfbi, - &omap44xx_l3_main_2__dss_venc, - &omap44xx_l4_per__dss_venc, - &omap44xx_l4_per__elm, - &omap44xx_emif_fw__emif1, - &omap44xx_emif_fw__emif2, - &omap44xx_l4_cfg__fdif, - &omap44xx_l4_wkup__gpio1, - &omap44xx_l4_per__gpio2, - &omap44xx_l4_per__gpio3, - &omap44xx_l4_per__gpio4, - &omap44xx_l4_per__gpio5, - &omap44xx_l4_per__gpio6, - &omap44xx_l3_main_2__gpmc, - &omap44xx_l3_main_2__gpu, - &omap44xx_l4_per__hdq1w, - &omap44xx_l4_cfg__hsi, - &omap44xx_l4_per__i2c1, - &omap44xx_l4_per__i2c2, - &omap44xx_l4_per__i2c3, - &omap44xx_l4_per__i2c4, - &omap44xx_l3_main_2__ipu, - &omap44xx_l3_main_2__iss, - &omap44xx_iva__sl2if, - &omap44xx_l3_main_2__iva, - &omap44xx_l4_wkup__kbd, - &omap44xx_l4_cfg__mailbox, - &omap44xx_l4_abe__mcasp, - &omap44xx_l4_abe__mcasp_dma, - &omap44xx_l4_abe__mcbsp1, - &omap44xx_l4_abe__mcbsp1_dma, - &omap44xx_l4_abe__mcbsp2, - &omap44xx_l4_abe__mcbsp2_dma, - &omap44xx_l4_abe__mcbsp3, - &omap44xx_l4_abe__mcbsp3_dma, - &omap44xx_l4_per__mcbsp4, - &omap44xx_l4_abe__mcpdm, - &omap44xx_l4_abe__mcpdm_dma, - &omap44xx_l4_per__mcspi1, - &omap44xx_l4_per__mcspi2, - &omap44xx_l4_per__mcspi3, - &omap44xx_l4_per__mcspi4, - &omap44xx_l4_per__mmc1, - &omap44xx_l4_per__mmc2, - &omap44xx_l4_per__mmc3, - &omap44xx_l4_per__mmc4, - &omap44xx_l4_per__mmc5, - &omap44xx_l3_main_2__ocmc_ram, - &omap44xx_l4_cfg__ocp2scp_usb_phy, - &omap44xx_mpu_private__prcm_mpu, - &omap44xx_l4_wkup__cm_core_aon, - &omap44xx_l4_cfg__cm_core, - &omap44xx_l4_wkup__prm, - &omap44xx_l4_wkup__scrm, - &omap44xx_l3_main_2__sl2if, - &omap44xx_l4_abe__slimbus1, - &omap44xx_l4_abe__slimbus1_dma, - &omap44xx_l4_per__slimbus2, - &omap44xx_l4_cfg__smartreflex_core, - &omap44xx_l4_cfg__smartreflex_iva, - &omap44xx_l4_cfg__smartreflex_mpu, - &omap44xx_l4_cfg__spinlock, - &omap44xx_l4_wkup__timer1, - &omap44xx_l4_per__timer2, - &omap44xx_l4_per__timer3, - &omap44xx_l4_per__timer4, - &omap44xx_l4_abe__timer5, - &omap44xx_l4_abe__timer5_dma, - &omap44xx_l4_abe__timer6, - &omap44xx_l4_abe__timer6_dma, - &omap44xx_l4_abe__timer7, - &omap44xx_l4_abe__timer7_dma, - &omap44xx_l4_abe__timer8, - &omap44xx_l4_abe__timer8_dma, - &omap44xx_l4_per__timer9, - &omap44xx_l4_per__timer10, - &omap44xx_l4_per__timer11, - &omap44xx_l4_per__uart1, - &omap44xx_l4_per__uart2, - &omap44xx_l4_per__uart3, - &omap44xx_l4_per__uart4, - &omap44xx_l4_cfg__usb_host_fs, - &omap44xx_l4_cfg__usb_host_hs, - &omap44xx_l4_cfg__usb_otg_hs, - &omap44xx_l4_cfg__usb_tll_hs, - &omap44xx_l4_wkup__wd_timer2, - &omap44xx_l4_abe__wd_timer3, - &omap44xx_l4_abe__wd_timer3_dma, +static __initdata struct omap_hwmod *omap44xx_hwmods[] = { + + /* dmm class */ + &omap44xx_dmm_hwmod, + + /* emif_fw class */ + &omap44xx_emif_fw_hwmod, + + /* l3 class */ + &omap44xx_l3_instr_hwmod, + &omap44xx_l3_main_1_hwmod, + &omap44xx_l3_main_2_hwmod, + &omap44xx_l3_main_3_hwmod, + + /* l4 class */ + &omap44xx_l4_abe_hwmod, + &omap44xx_l4_cfg_hwmod, + &omap44xx_l4_per_hwmod, + &omap44xx_l4_wkup_hwmod, + + /* mpu_bus class */ + &omap44xx_mpu_private_hwmod, + + /* aess class */ +/* &omap44xx_aess_hwmod, */ + + /* bandgap class */ + &omap44xx_bandgap_hwmod, + + /* counter class */ +/* &omap44xx_counter_32k_hwmod, */ + + /* dma class */ + &omap44xx_dma_system_hwmod, + + /* dmic class */ + &omap44xx_dmic_hwmod, + + /* dsp class */ + &omap44xx_dsp_hwmod, + &omap44xx_dsp_c0_hwmod, + + /* dss class */ + &omap44xx_dss_hwmod, + &omap44xx_dss_dispc_hwmod, + &omap44xx_dss_dsi1_hwmod, + &omap44xx_dss_dsi2_hwmod, + &omap44xx_dss_hdmi_hwmod, + &omap44xx_dss_rfbi_hwmod, + &omap44xx_dss_venc_hwmod, + + /* gpio class */ + &omap44xx_gpio1_hwmod, + &omap44xx_gpio2_hwmod, + &omap44xx_gpio3_hwmod, + &omap44xx_gpio4_hwmod, + &omap44xx_gpio5_hwmod, + &omap44xx_gpio6_hwmod, + + /* hsi class */ +/* &omap44xx_hsi_hwmod, */ + + /* i2c class */ + &omap44xx_i2c1_hwmod, + &omap44xx_i2c2_hwmod, + &omap44xx_i2c3_hwmod, + &omap44xx_i2c4_hwmod, + + /* ipu class */ + &omap44xx_ipu_hwmod, + &omap44xx_ipu_c0_hwmod, + &omap44xx_ipu_c1_hwmod, + + /* iss class */ +/* &omap44xx_iss_hwmod, */ + + /* iva class */ + &omap44xx_iva_hwmod, + &omap44xx_iva_seq0_hwmod, + &omap44xx_iva_seq1_hwmod, + + /* kbd class */ + &omap44xx_kbd_hwmod, + + /* mailbox class */ + &omap44xx_mailbox_hwmod, + + /* mcbsp class */ + &omap44xx_mcbsp1_hwmod, + &omap44xx_mcbsp2_hwmod, + &omap44xx_mcbsp3_hwmod, + &omap44xx_mcbsp4_hwmod, + + /* mcpdm class */ + &omap44xx_mcpdm_hwmod, + + /* mcspi class */ + &omap44xx_mcspi1_hwmod, + &omap44xx_mcspi2_hwmod, + &omap44xx_mcspi3_hwmod, + &omap44xx_mcspi4_hwmod, + + /* mmc class */ + &omap44xx_mmc1_hwmod, + &omap44xx_mmc2_hwmod, + &omap44xx_mmc3_hwmod, + &omap44xx_mmc4_hwmod, + &omap44xx_mmc5_hwmod, + + /* mpu class */ + &omap44xx_mpu_hwmod, + + /* smartreflex class */ + &omap44xx_smartreflex_core_hwmod, + &omap44xx_smartreflex_iva_hwmod, + &omap44xx_smartreflex_mpu_hwmod, + + /* spinlock class */ + &omap44xx_spinlock_hwmod, + + /* timer class */ + &omap44xx_timer1_hwmod, + &omap44xx_timer2_hwmod, + &omap44xx_timer3_hwmod, + &omap44xx_timer4_hwmod, + &omap44xx_timer5_hwmod, + &omap44xx_timer6_hwmod, + &omap44xx_timer7_hwmod, + &omap44xx_timer8_hwmod, + &omap44xx_timer9_hwmod, + &omap44xx_timer10_hwmod, + &omap44xx_timer11_hwmod, + + /* uart class */ + &omap44xx_uart1_hwmod, + &omap44xx_uart2_hwmod, + &omap44xx_uart3_hwmod, + &omap44xx_uart4_hwmod, + + /* usb host class */ + &omap44xx_usb_host_hs_hwmod, + &omap44xx_usb_tll_hs_hwmod, + + /* usb_otg_hs class */ + &omap44xx_usb_otg_hs_hwmod, + + /* wd_timer class */ + &omap44xx_wd_timer2_hwmod, + &omap44xx_wd_timer3_hwmod, NULL, }; int __init omap44xx_hwmod_init(void) { - return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); + return omap_hwmod_register(omap44xx_hwmods); } diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_common_data.h b/trunk/arch/arm/mach-omap2/omap_hwmod_common_data.h index 7aa9156d50ab..ad5d8f04c0b8 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -19,6 +19,18 @@ #include "display.h" /* Common address space across OMAP2xxx */ +extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[]; +extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[]; +extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[]; +extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[]; /* Common address space across OMAP2xxx/3xxx */ @@ -42,64 +54,6 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; /* Common IP block data across OMAP2xxx */ extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[]; -extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; -extern struct omap_hwmod omap2xxx_l3_main_hwmod; -extern struct omap_hwmod omap2xxx_l4_core_hwmod; -extern struct omap_hwmod omap2xxx_l4_wkup_hwmod; -extern struct omap_hwmod omap2xxx_mpu_hwmod; -extern struct omap_hwmod omap2xxx_iva_hwmod; -extern struct omap_hwmod omap2xxx_timer1_hwmod; -extern struct omap_hwmod omap2xxx_timer2_hwmod; -extern struct omap_hwmod omap2xxx_timer3_hwmod; -extern struct omap_hwmod omap2xxx_timer4_hwmod; -extern struct omap_hwmod omap2xxx_timer5_hwmod; -extern struct omap_hwmod omap2xxx_timer6_hwmod; -extern struct omap_hwmod omap2xxx_timer7_hwmod; -extern struct omap_hwmod omap2xxx_timer8_hwmod; -extern struct omap_hwmod omap2xxx_timer9_hwmod; -extern struct omap_hwmod omap2xxx_timer10_hwmod; -extern struct omap_hwmod omap2xxx_timer11_hwmod; -extern struct omap_hwmod omap2xxx_timer12_hwmod; -extern struct omap_hwmod omap2xxx_wd_timer2_hwmod; -extern struct omap_hwmod omap2xxx_uart1_hwmod; -extern struct omap_hwmod omap2xxx_uart2_hwmod; -extern struct omap_hwmod omap2xxx_uart3_hwmod; -extern struct omap_hwmod omap2xxx_dss_core_hwmod; -extern struct omap_hwmod omap2xxx_dss_dispc_hwmod; -extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod; -extern struct omap_hwmod omap2xxx_dss_venc_hwmod; -extern struct omap_hwmod omap2xxx_gpio1_hwmod; -extern struct omap_hwmod omap2xxx_gpio2_hwmod; -extern struct omap_hwmod omap2xxx_gpio3_hwmod; -extern struct omap_hwmod omap2xxx_gpio4_hwmod; -extern struct omap_hwmod omap2xxx_mcspi1_hwmod; -extern struct omap_hwmod omap2xxx_mcspi2_hwmod; - -/* Common interface data across OMAP2xxx */ -extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; -extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main; -extern struct omap_hwmod_ocp_if omap2xxx_dss__l3; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup; -extern struct omap_hwmod_ocp_if omap2_l4_core__uart1; -extern struct omap_hwmod_ocp_if omap2_l4_core__uart2; -extern struct omap_hwmod_ocp_if omap2_l4_core__uart3; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; -extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; /* Common IP block data */ extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; @@ -140,7 +94,6 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[]; extern struct omap_hwmod_irq_info omap2_dma_system_irqs[]; extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[]; extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; /* OMAP hwmod classes - forward declarations */ extern struct omap_hwmod_class l3_hwmod_class; diff --git a/trunk/arch/arm/mach-omap2/powerdomains3xxx_data.c b/trunk/arch/arm/mach-omap2/powerdomains3xxx_data.c index fb0a0a6869d1..b7ea468eea32 100644 --- a/trunk/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -311,7 +311,7 @@ void __init omap3xxx_powerdomains_init(void) rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0) pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 || - rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 || + rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 || rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); else diff --git a/trunk/arch/arm/mach-omap2/timer.c b/trunk/arch/arm/mach-omap2/timer.c index ecec873e78cd..c512bac69ec5 100644 --- a/trunk/arch/arm/mach-omap2/timer.c +++ b/trunk/arch/arm/mach-omap2/timer.c @@ -145,10 +145,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ struct omap_hwmod *oh; - struct resource irq_rsrc, mem_rsrc; size_t size; int res = 0; - int r; sprintf(name, "timer%d", gptimer_id); omap_hwmod_setup_one(name); @@ -156,16 +154,9 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, if (!oh) return -ENODEV; - r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); - if (r) - return -ENXIO; - timer->irq = irq_rsrc.start; - - r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); - if (r) - return -ENXIO; - timer->phys_base = mem_rsrc.start; - size = mem_rsrc.end - mem_rsrc.start; + timer->irq = oh->mpu_irqs[0].irq; + timer->phys_base = oh->slaves[0]->addr->pa_start; + size = oh->slaves[0]->addr->pa_end - timer->phys_base; /* Static mapping, never released */ timer->io_base = ioremap(timer->phys_base, size); diff --git a/trunk/arch/arm/mach-omap2/usb-musb.c b/trunk/arch/arm/mach-omap2/usb-musb.c index b19d1b43c12e..8d5ed775dd56 100644 --- a/trunk/arch/arm/mach-omap2/usb-musb.c +++ b/trunk/arch/arm/mach-omap2/usb-musb.c @@ -90,7 +90,7 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) musb_plat.mode = board_data->mode; musb_plat.extvbus = board_data->extvbus; - if (soc_is_am35xx()) { + if (cpu_is_omap3517() || cpu_is_omap3505()) { oh_name = "am35x_otg_hs"; name = "musb-am35x"; } else if (cpu_is_ti81xx()) { diff --git a/trunk/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/trunk/arch/arm/mach-omap2/voltagedomains3xxx_data.c index d0103c80d040..57db2038b23c 100644 --- a/trunk/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -118,7 +118,7 @@ void __init omap3xxx_voltagedomains_init(void) } #endif - if (soc_is_am35xx()) + if (cpu_is_omap3517() || cpu_is_omap3505()) voltdms = voltagedomains_am35xx; else voltdms = voltagedomains_omap3; diff --git a/trunk/arch/arm/plat-omap/devices.c b/trunk/arch/arm/plat-omap/devices.c index 60278f47c0bd..09b07d252892 100644 --- a/trunk/arch/arm/plat-omap/devices.c +++ b/trunk/arch/arm/plat-omap/devices.c @@ -167,8 +167,8 @@ void __init omap_dsp_reserve_sdram_memblock(void) paddr = arm_memblock_steal(size, SZ_1M); if (!paddr) { - pr_err("%s: failed to reserve %x bytes\n", - __func__, size); + pr_err("%s: failed to reserve %llx bytes\n", + __func__, (unsigned long long)size); return; } diff --git a/trunk/arch/arm/plat-omap/dma.c b/trunk/arch/arm/plat-omap/dma.c index 807ce4c45ef3..c58d896cd5c3 100644 --- a/trunk/arch/arm/plat-omap/dma.c +++ b/trunk/arch/arm/plat-omap/dma.c @@ -843,7 +843,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio, } l = p->dma_read(CCR, lch); l &= ~((1 << 6) | (1 << 26)); - if (cpu_class_is_omap2() && !cpu_is_omap242x()) + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); else l |= ((read_prio & 0x1) << 6); @@ -2071,7 +2071,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) } } - if (cpu_class_is_omap2() && !cpu_is_omap242x()) + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0); diff --git a/trunk/arch/arm/plat-omap/dmtimer.c b/trunk/arch/arm/plat-omap/dmtimer.c index 15e7882f371c..652139c0339e 100644 --- a/trunk/arch/arm/plat-omap/dmtimer.c +++ b/trunk/arch/arm/plat-omap/dmtimer.c @@ -82,6 +82,8 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, static void omap_timer_restore_context(struct omap_dm_timer *timer) { + __raw_writel(timer->context.tiocp_cfg, + timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); if (timer->revision == 1) __raw_writel(timer->context.tistat, timer->sys_stat); diff --git a/trunk/arch/arm/plat-omap/include/plat/cpu.h b/trunk/arch/arm/plat-omap/include/plat/cpu.h index bf90212cc9c7..4bdf14ec6747 100644 --- a/trunk/arch/arm/plat-omap/include/plat/cpu.h +++ b/trunk/arch/arm/plat-omap/include/plat/cpu.h @@ -121,7 +121,6 @@ IS_OMAP_CLASS(16xx, 0x16) IS_OMAP_CLASS(24xx, 0x24) IS_OMAP_CLASS(34xx, 0x34) IS_OMAP_CLASS(44xx, 0x44) -IS_AM_CLASS(35xx, 0x35) IS_AM_CLASS(33xx, 0x33) IS_TI_CLASS(81xx, 0x81) @@ -149,7 +148,6 @@ IS_AM_SUBCLASS(335x, 0x335) #define cpu_is_ti81xx() 0 #define cpu_is_ti816x() 0 #define cpu_is_ti814x() 0 -#define soc_is_am35xx() 0 #define cpu_is_am33xx() 0 #define cpu_is_am335x() 0 #define cpu_is_omap44xx() 0 @@ -359,7 +357,6 @@ IS_OMAP_TYPE(3517, 0x3517) # undef cpu_is_ti81xx # undef cpu_is_ti816x # undef cpu_is_ti814x -# undef soc_is_am35xx # undef cpu_is_am33xx # undef cpu_is_am335x # define cpu_is_omap3430() is_omap3430() @@ -381,7 +378,6 @@ IS_OMAP_TYPE(3517, 0x3517) # define cpu_is_ti81xx() is_ti81xx() # define cpu_is_ti816x() is_ti816x() # define cpu_is_ti814x() is_ti814x() -# define soc_is_am35xx() is_am35xx() # define cpu_is_am33xx() is_am33xx() # define cpu_is_am335x() is_am335x() #endif @@ -437,10 +433,6 @@ IS_OMAP_TYPE(3517, 0x3517) #define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8)) #define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8)) -#define AM35XX_CLASS 0x35170034 -#define AM35XX_REV_ES1_0 AM35XX_CLASS -#define AM35XX_REV_ES1_1 (AM35XX_CLASS | (0x1 << 8)) - #define AM335X_CLASS 0x33500034 #define AM335X_REV_ES1_0 AM335X_CLASS @@ -453,6 +445,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP446X_CLASS 0x44600044 #define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) +#define OMAP4460_REV_ES1_1 (OMAP446X_CLASS | (0x11 << 8)) #define OMAP447X_CLASS 0x44700044 #define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) diff --git a/trunk/arch/arm/plat-omap/include/plat/dma.h b/trunk/arch/arm/plat-omap/include/plat/dma.h index 77422041e7be..dc562a5c0a8a 100644 --- a/trunk/arch/arm/plat-omap/include/plat/dma.h +++ b/trunk/arch/arm/plat-omap/include/plat/dma.h @@ -312,11 +312,6 @@ #define CLEAR_CSR_ON_READ BIT(0xC) #define IS_WORD_16 BIT(0xD) -/* Defines for DMA Capabilities */ -#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) -#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19) -#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20) - enum omap_reg_offsets { GCR, GSCR, GRST1, HW_ID, diff --git a/trunk/arch/arm/plat-omap/include/plat/dmtimer.h b/trunk/arch/arm/plat-omap/include/plat/dmtimer.h index a4c08d04e284..9418f00b6c38 100644 --- a/trunk/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/trunk/arch/arm/plat-omap/include/plat/dmtimer.h @@ -75,6 +75,7 @@ struct clk; struct timer_regs { u32 tidr; + u32 tiocp_cfg; u32 tistat; u32 tisr; u32 tier; diff --git a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h index c835b7194ff5..3f26db4ee8e6 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -213,17 +213,11 @@ struct omap_hwmod_addr_space { */ #define OCP_USER_MPU (1 << 0) #define OCP_USER_SDMA (1 << 1) -#define OCP_USER_DSP (1 << 2) -#define OCP_USER_IVA (1 << 3) /* omap_hwmod_ocp_if.flags bits */ #define OCPIF_SWSUP_IDLE (1 << 0) #define OCPIF_CAN_BURST (1 << 1) -/* omap_hwmod_ocp_if._int_flags possibilities */ -#define _OCPIF_INT_FLAGS_REGISTERED (1 << 0) - - /** * struct omap_hwmod_ocp_if - OCP interface data * @master: struct omap_hwmod that initiates OCP transactions on this link @@ -235,7 +229,6 @@ struct omap_hwmod_addr_space { * @width: OCP data width * @user: initiators using this interface (see OCP_USER_* macros above) * @flags: OCP interface flags (see OCPIF_* macros above) - * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above) * * It may also be useful to add a tag_cnt field for OCP2.x devices. * @@ -254,7 +247,6 @@ struct omap_hwmod_ocp_if { u8 width; u8 user; u8 flags; - u8 _int_flags; }; @@ -335,9 +327,9 @@ struct omap_hwmod_sysc_fields { * then this field has to be populated with the correct offset structure. */ struct omap_hwmod_class_sysconfig { - u32 rev_offs; - u32 sysc_offs; - u32 syss_offs; + u16 rev_offs; + u16 sysc_offs; + u16 syss_offs; u16 sysc_flags; struct omap_hwmod_sysc_fields *sysc_fields; u8 srst_udelay; @@ -483,16 +475,6 @@ struct omap_hwmod_class { int (*reset)(struct omap_hwmod *oh); }; -/** - * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs - * @ocp_if: OCP interface structure record pointer - * @node: list_head pointing to next struct omap_hwmod_link in a list - */ -struct omap_hwmod_link { - struct omap_hwmod_ocp_if *ocp_if; - struct list_head node; -}; - /** * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) * @name: name of the hwmod @@ -505,10 +487,12 @@ struct omap_hwmod_link { * @_clk: pointer to the main struct clk (filled in at runtime) * @opt_clks: other device clocks that drivers can request (0..*) * @voltdm: pointer to voltage domain (filled in at runtime) + * @masters: ptr to array of OCP ifs that this hwmod can initiate on + * @slaves: ptr to array of OCP ifs that this hwmod can respond on * @dev_attr: arbitrary device attributes that can be passed to the driver * @_sysc_cache: internal-use hwmod flags * @_mpu_rt_va: cached register target start address (internal use) - * @_mpu_port: cached MPU register target slave (internal use) + * @_mpu_port_index: cached MPU register target slave ID (internal use) * @opt_clks_cnt: number of @opt_clks * @master_cnt: number of @master entries * @slaves_cnt: number of @slave entries @@ -527,8 +511,6 @@ struct omap_hwmod_link { * * Parameter names beginning with an underscore are managed internally by * the omap_hwmod code and should not be set during initialization. - * - * @masters and @slaves are now deprecated. */ struct omap_hwmod { const char *name; @@ -547,15 +529,15 @@ struct omap_hwmod { struct omap_hwmod_opt_clk *opt_clks; char *clkdm_name; struct clockdomain *clkdm; - struct list_head master_ports; /* connect to *_IA */ - struct list_head slave_ports; /* connect to *_TA */ + struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ + struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ void *dev_attr; u32 _sysc_cache; void __iomem *_mpu_rt_va; spinlock_t _lock; struct list_head node; - struct omap_hwmod_ocp_if *_mpu_port; u16 flags; + u8 _mpu_port_index; u8 response_lat; u8 rst_lines_cnt; u8 opt_clks_cnt; @@ -567,6 +549,7 @@ struct omap_hwmod { u8 _postsetup_state; }; +int omap_hwmod_register(struct omap_hwmod **ohs); struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); @@ -598,8 +581,6 @@ int omap_hwmod_softreset(struct omap_hwmod *oh); int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); -int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, - const char *name, struct resource *res); struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); @@ -638,6 +619,4 @@ extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); -extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); - #endif