From 972bb084fe8309e3b060964dc2fdaa12fac9d8c4 Mon Sep 17 00:00:00 2001 From: Robert Tivy Date: Thu, 10 Jan 2013 16:23:20 -0800 Subject: [PATCH] --- yaml --- r: 355510 b: refs/heads/master c: d2e0c18a9751229b31bf9bc7a5c1b9ab4a7a9651 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-davinci/devices-da8xx.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index c20ddd0d769b..c96117855695 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0273612cb845932f3086ceb7f6c7b43a8a338ae7 +refs/heads/master: d2e0c18a9751229b31bf9bc7a5c1b9ab4a7a9651 diff --git a/trunk/arch/arm/mach-davinci/devices-da8xx.c b/trunk/arch/arm/mach-davinci/devices-da8xx.c index 30da05f22ef4..aa402bc160c8 100644 --- a/trunk/arch/arm/mach-davinci/devices-da8xx.c +++ b/trunk/arch/arm/mach-davinci/devices-da8xx.c @@ -751,7 +751,7 @@ void __iomem * __init da8xx_get_mem_ctlr(void) da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); if (!da8xx_ddr2_ctlr_base) - pr_warning("%s: Unable to map DDR2 controller", __func__); + pr_warn("%s: Unable to map DDR2 controller", __func__); return da8xx_ddr2_ctlr_base; }