From 982f116099bc11ad91d38eaab3d34c22cf026edd Mon Sep 17 00:00:00 2001 From: Davide Rizzo Date: Thu, 13 Aug 2009 11:53:53 +0200 Subject: [PATCH] --- yaml --- r: 156834 b: refs/heads/master c: 48ec45e725aa385d72bced73b267dfaf13351876 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-s3c24xx/clock-dclk.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 5be6482bb962..4eaf175d9059 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a219dc4d4463809b1be473038e7d9f3437ca452d +refs/heads/master: 48ec45e725aa385d72bced73b267dfaf13351876 diff --git a/trunk/arch/arm/plat-s3c24xx/clock-dclk.c b/trunk/arch/arm/plat-s3c24xx/clock-dclk.c index 5b75a797b5ab..0afb217a775e 100644 --- a/trunk/arch/arm/plat-s3c24xx/clock-dclk.c +++ b/trunk/arch/arm/plat-s3c24xx/clock-dclk.c @@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) /* calculate the MISCCR setting for the clock */ - if (parent == &clk_xtal) + if (parent == &clk_mpll) source = S3C2410_MISCCR_CLK0_MPLL; else if (parent == &clk_upll) source = S3C2410_MISCCR_CLK0_UPLL;