From 98a0d0f631353d1d9511036c1b6c6a191af14023 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 19 May 2012 21:06:13 +0800 Subject: [PATCH] --- yaml --- r: 303351 b: refs/heads/master c: 3e48b1baa042a4d5e92f373fc945a4aa0081178b h: refs/heads/master i: 303349: c989c9f17f985a6db49d8c982a4d723191f899ca 303347: f8c158feb2639b2c78a19d8ec0b6bbb2335c4c0d 303343: f8a10ff91e86484e9295ca1ffec35e90fcc3f1a2 v: v3 --- [refs] | 2 +- trunk/Documentation/arm/SPEAr/overview.txt | 13 +- .../devicetree/bindings/arm/spear.txt | 18 - .../bindings/pinctrl/fsl,imx-pinctrl.txt | 95 - .../bindings/pinctrl/fsl,imx6q-pinctrl.txt | 1628 -------- .../bindings/pinctrl/fsl,mxs-pinctrl.txt | 918 ----- .../pinctrl/nvidia,tegra20-pinmux.txt | 132 - .../pinctrl/nvidia,tegra30-pinmux.txt | 132 - .../bindings/pinctrl/pinctrl-bindings.txt | 128 - .../bindings/pinctrl/pinctrl_spear.txt | 108 - .../bindings/pinmux/pinmux_nvidia.txt | 5 + trunk/Documentation/driver-model/devres.txt | 8 - trunk/Documentation/pinctrl.txt | 94 +- trunk/MAINTAINERS | 23 +- trunk/arch/arm/Kconfig | 3 - trunk/arch/arm/boot/dts/spear300-evb.dts | 221 -- trunk/arch/arm/boot/dts/spear300.dtsi | 77 - trunk/arch/arm/boot/dts/spear310-evb.dts | 172 - trunk/arch/arm/boot/dts/spear310.dtsi | 80 - trunk/arch/arm/boot/dts/spear320-evb.dts | 173 - trunk/arch/arm/boot/dts/spear320.dtsi | 95 - trunk/arch/arm/boot/dts/spear3xx.dtsi | 144 - trunk/arch/arm/boot/dts/spear600-evb.dts | 4 - trunk/arch/arm/boot/dts/spear600.dtsi | 8 - trunk/arch/arm/boot/dts/tegra-cardhu.dts | 44 - trunk/arch/arm/boot/dts/tegra-harmony.dts | 224 -- trunk/arch/arm/boot/dts/tegra-paz00.dts | 220 -- trunk/arch/arm/boot/dts/tegra-seaboard.dts | 243 -- trunk/arch/arm/boot/dts/tegra-trimslice.dts | 230 -- trunk/arch/arm/boot/dts/tegra-ventana.dts | 230 -- trunk/arch/arm/configs/nhk8815_defconfig | 1 - trunk/arch/arm/configs/spear3xx_defconfig | 52 +- trunk/arch/arm/configs/spear6xx_defconfig | 41 +- trunk/arch/arm/mach-nomadik/Kconfig | 1 - trunk/arch/arm/mach-spear3xx/Kconfig | 37 +- trunk/arch/arm/mach-spear3xx/Makefile | 13 +- trunk/arch/arm/mach-spear3xx/Makefile.boot | 4 - trunk/arch/arm/mach-spear3xx/clock.c | 182 +- .../arm/mach-spear3xx/include/mach/generic.h | 153 +- .../arm/mach-spear3xx/include/mach/hardware.h | 3 + .../arm/mach-spear3xx/include/mach/spear.h | 9 +- trunk/arch/arm/mach-spear3xx/spear300.c | 613 +-- trunk/arch/arm/mach-spear3xx/spear300_evb.c | 75 + trunk/arch/arm/mach-spear3xx/spear310.c | 416 +- trunk/arch/arm/mach-spear3xx/spear310_evb.c | 81 + trunk/arch/arm/mach-spear3xx/spear320.c | 663 ++-- trunk/arch/arm/mach-spear3xx/spear320_evb.c | 79 + trunk/arch/arm/mach-spear3xx/spear3xx.c | 541 ++- trunk/arch/arm/mach-spear6xx/Makefile.boot | 2 - trunk/arch/arm/mach-spear6xx/clock.c | 80 +- trunk/arch/arm/mach-spear6xx/spear6xx.c | 372 +- trunk/arch/arm/mach-tegra/Makefile | 3 + trunk/arch/arm/mach-tegra/board-dt-tegra20.c | 31 + .../arm/mach-tegra/board-harmony-pinmux.c | 266 +- .../arch/arm/mach-tegra/board-paz00-pinmux.c | 263 +- trunk/arch/arm/mach-tegra/board-pinmux.c | 105 +- trunk/arch/arm/mach-tegra/board-pinmux.h | 40 +- .../arm/mach-tegra/board-seaboard-pinmux.c | 346 +- trunk/arch/arm/mach-tegra/board-seaboard.c | 21 +- .../arm/mach-tegra/board-trimslice-pinmux.c | 264 +- trunk/arch/arm/mach-tegra/board-trimslice.c | 15 +- trunk/arch/arm/mach-tegra/devices.c | 5 +- .../arm/mach-tegra/include/mach/gpio-tegra.h | 9 + .../mach-tegra/include/mach/pinmux-tegra20.h | 184 + .../mach-tegra/include/mach/pinmux-tegra30.h | 320 ++ .../arch/arm/mach-tegra/include/mach/pinmux.h | 302 ++ .../arm/mach-tegra/pinmux-tegra20-tables.c | 244 ++ .../arm/mach-tegra/pinmux-tegra30-tables.c | 376 ++ trunk/arch/arm/mach-tegra/pinmux.c | 987 +++++ trunk/arch/arm/mach-tegra/usb_phy.c | 1 + trunk/arch/arm/mach-ux500/Kconfig | 3 - trunk/arch/arm/mach-ux500/Makefile | 3 +- trunk/arch/arm/mach-ux500/board-mop500-msp.c | 267 -- trunk/arch/arm/mach-ux500/board-mop500-msp.h | 14 - trunk/arch/arm/mach-ux500/board-mop500-pins.c | 733 ++-- trunk/arch/arm/mach-ux500/board-mop500.c | 99 +- trunk/arch/arm/mach-ux500/board-mop500.h | 10 +- trunk/arch/arm/mach-ux500/clock.c | 8 +- trunk/arch/arm/mach-ux500/cpu-db8500.c | 1 - trunk/arch/arm/mach-ux500/cpu.c | 12 - trunk/arch/arm/mach-ux500/devices-common.h | 12 - trunk/arch/arm/mach-ux500/devices-db8500.h | 10 + trunk/arch/arm/mach-ux500/include/mach/msp.h | 29 - trunk/arch/arm/mach-ux500/pins-db8500.h | 72 +- .../plat-nomadik/include/plat/gpio-nomadik.h | 8 - .../arm/plat-nomadik/include/plat/pincfg.h | 32 - trunk/arch/arm/plat-spear/Kconfig | 4 +- trunk/arch/arm/plat-spear/Makefile | 4 +- .../arch/arm/plat-spear/include/plat/padmux.h | 92 + .../arch/arm/plat-spear/include/plat/pl080.h | 21 - trunk/arch/arm/plat-spear/padmux.c | 164 + trunk/arch/arm/plat-spear/pl080.c | 79 - trunk/drivers/clk/clkdev.c | 142 +- trunk/drivers/gpio/Makefile | 1 + .../pinctrl-nomadik.c => gpio/gpio-nomadik.c} | 857 +--- trunk/drivers/gpio/gpio-tegra.c | 39 +- trunk/drivers/mmc/host/sdhci-tegra.c | 24 +- trunk/drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 2 +- trunk/drivers/of/base.c | 41 - trunk/drivers/pinctrl/Kconfig | 41 +- trunk/drivers/pinctrl/Makefile | 12 - trunk/drivers/pinctrl/core.c | 244 +- trunk/drivers/pinctrl/core.h | 12 +- trunk/drivers/pinctrl/devicetree.c | 249 -- trunk/drivers/pinctrl/devicetree.h | 35 - trunk/drivers/pinctrl/pinconf.c | 52 +- trunk/drivers/pinctrl/pinconf.h | 17 +- trunk/drivers/pinctrl/pinctrl-coh901.c | 4 +- trunk/drivers/pinctrl/pinctrl-imx.c | 627 --- trunk/drivers/pinctrl/pinctrl-imx.h | 106 - trunk/drivers/pinctrl/pinctrl-imx23.c | 305 -- trunk/drivers/pinctrl/pinctrl-imx28.c | 421 -- trunk/drivers/pinctrl/pinctrl-imx6q.c | 2331 ----------- trunk/drivers/pinctrl/pinctrl-mxs.c | 508 --- trunk/drivers/pinctrl/pinctrl-mxs.h | 91 - .../drivers/pinctrl/pinctrl-nomadik-db8500.c | 857 ---- trunk/drivers/pinctrl/pinctrl-nomadik.h | 77 - trunk/drivers/pinctrl/pinctrl-pxa3xx.c | 24 +- trunk/drivers/pinctrl/pinctrl-sirf.c | 20 +- trunk/drivers/pinctrl/pinctrl-tegra.c | 439 +-- trunk/drivers/pinctrl/pinctrl-tegra.h | 23 +- trunk/drivers/pinctrl/pinctrl-tegra20.c | 40 +- trunk/drivers/pinctrl/pinctrl-tegra30.c | 40 +- trunk/drivers/pinctrl/pinctrl-u300.c | 20 +- trunk/drivers/pinctrl/pinmux.c | 93 +- trunk/drivers/pinctrl/pinmux.h | 18 +- trunk/drivers/pinctrl/spear/Kconfig | 34 - trunk/drivers/pinctrl/spear/Makefile | 7 - trunk/drivers/pinctrl/spear/pinctrl-spear.c | 354 -- trunk/drivers/pinctrl/spear/pinctrl-spear.h | 142 - .../drivers/pinctrl/spear/pinctrl-spear300.c | 708 ---- .../drivers/pinctrl/spear/pinctrl-spear310.c | 431 -- .../drivers/pinctrl/spear/pinctrl-spear320.c | 3468 ----------------- .../drivers/pinctrl/spear/pinctrl-spear3xx.c | 588 --- .../drivers/pinctrl/spear/pinctrl-spear3xx.h | 92 - trunk/drivers/usb/host/ehci-tegra.c | 13 +- trunk/include/linux/clk.h | 32 - trunk/include/linux/clkdev.h | 3 - trunk/include/linux/of.h | 51 - trunk/include/linux/pinctrl/consumer.h | 44 - trunk/include/linux/pinctrl/machine.h | 7 +- trunk/include/linux/pinctrl/pinconf.h | 6 +- trunk/include/linux/pinctrl/pinctrl-state.h | 13 - trunk/include/linux/pinctrl/pinctrl.h | 22 +- trunk/include/linux/pinctrl/pinmux.h | 9 +- trunk/include/linux/platform_data/tegra_usb.h | 1 - 146 files changed, 6276 insertions(+), 21910 deletions(-) delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt create mode 100644 trunk/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt delete mode 100644 trunk/arch/arm/boot/dts/spear300-evb.dts delete mode 100644 trunk/arch/arm/boot/dts/spear300.dtsi delete mode 100644 trunk/arch/arm/boot/dts/spear310-evb.dts delete mode 100644 trunk/arch/arm/boot/dts/spear310.dtsi delete mode 100644 trunk/arch/arm/boot/dts/spear320-evb.dts delete mode 100644 trunk/arch/arm/boot/dts/spear320.dtsi delete mode 100644 trunk/arch/arm/boot/dts/spear3xx.dtsi create mode 100644 trunk/arch/arm/mach-spear3xx/spear300_evb.c create mode 100644 trunk/arch/arm/mach-spear3xx/spear310_evb.c create mode 100644 trunk/arch/arm/mach-spear3xx/spear320_evb.c create mode 100644 trunk/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h create mode 100644 trunk/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h create mode 100644 trunk/arch/arm/mach-tegra/include/mach/pinmux.h create mode 100644 trunk/arch/arm/mach-tegra/pinmux-tegra20-tables.c create mode 100644 trunk/arch/arm/mach-tegra/pinmux-tegra30-tables.c create mode 100644 trunk/arch/arm/mach-tegra/pinmux.c delete mode 100644 trunk/arch/arm/mach-ux500/board-mop500-msp.c delete mode 100644 trunk/arch/arm/mach-ux500/board-mop500-msp.h delete mode 100644 trunk/arch/arm/mach-ux500/include/mach/msp.h create mode 100644 trunk/arch/arm/plat-spear/include/plat/padmux.h delete mode 100644 trunk/arch/arm/plat-spear/include/plat/pl080.h create mode 100644 trunk/arch/arm/plat-spear/padmux.c delete mode 100644 trunk/arch/arm/plat-spear/pl080.c rename trunk/drivers/{pinctrl/pinctrl-nomadik.c => gpio/gpio-nomadik.c} (56%) delete mode 100644 trunk/drivers/pinctrl/devicetree.c delete mode 100644 trunk/drivers/pinctrl/devicetree.h delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx.h delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx23.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx28.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx6q.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-mxs.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-mxs.h delete mode 100644 trunk/drivers/pinctrl/pinctrl-nomadik-db8500.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-nomadik.h delete mode 100644 trunk/drivers/pinctrl/spear/Kconfig delete mode 100644 trunk/drivers/pinctrl/spear/Makefile delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear.h delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear300.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear310.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear320.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear3xx.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear3xx.h diff --git a/[refs] b/[refs] index 6718e5168dcf..972c1f197ea9 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: cbd8d842319c8084c050292e7d167be2a4cf1ad9 +refs/heads/master: 3e48b1baa042a4d5e92f373fc945a4aa0081178b diff --git a/trunk/Documentation/arm/SPEAr/overview.txt b/trunk/Documentation/arm/SPEAr/overview.txt index 28a9af953b9d..253a35c6f782 100644 --- a/trunk/Documentation/arm/SPEAr/overview.txt +++ b/trunk/Documentation/arm/SPEAr/overview.txt @@ -17,14 +17,14 @@ Introduction SPEAr (Platform) - SPEAr3XX (3XX SOC series, based on ARM9) - SPEAr300 (SOC) - - SPEAr300 Evaluation Board + - SPEAr300_EVB (Evaluation Board) - SPEAr310 (SOC) - - SPEAr310 Evaluation Board + - SPEAr310_EVB (Evaluation Board) - SPEAr320 (SOC) - - SPEAr320 Evaluation Board + - SPEAr320_EVB (Evaluation Board) - SPEAr6XX (6XX SOC series, based on ARM9) - SPEAr600 (SOC) - - SPEAr600 Evaluation Board + - SPEAr600_EVB (Evaluation Board) - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9) - SPEAr1300 (SOC) @@ -51,11 +51,10 @@ Introduction Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine specific files, like spear300.c, spear310.c, spear320.c and spear600.c. - mach-spear* doesn't contains board specific files as they fully support - Flattened Device Tree. + mach-spear* also contains board specific files for each machine type. Document Author --------------- - Viresh Kumar , (c) 2010-2012 ST Microelectronics + Viresh Kumar, (c) 2010 ST Microelectronics diff --git a/trunk/Documentation/devicetree/bindings/arm/spear.txt b/trunk/Documentation/devicetree/bindings/arm/spear.txt index aa5f355cc947..f8e54f092328 100644 --- a/trunk/Documentation/devicetree/bindings/arm/spear.txt +++ b/trunk/Documentation/devicetree/bindings/arm/spear.txt @@ -6,21 +6,3 @@ Boards with the ST SPEAr600 SoC shall have the following properties: Required root node property: compatible = "st,spear600"; - -Boards with the ST SPEAr300 SoC shall have the following properties: - -Required root node property: - -compatible = "st,spear300"; - -Boards with the ST SPEAr310 SoC shall have the following properties: - -Required root node property: - -compatible = "st,spear310"; - -Boards with the ST SPEAr320 SoC shall have the following properties: - -Required root node property: - -compatible = "st,spear320"; diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt deleted file mode 100644 index ab19e6bc7d3b..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +++ /dev/null @@ -1,95 +0,0 @@ -* Freescale IOMUX Controller (IOMUXC) for i.MX - -The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are up to -8 muxing options (called ALT modes). Since different modules require -different PAD settings (like pull up, keeper, etc) the IOMUXC controls -also the PAD settings parameters. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Freescale IMX pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and config -of the pins in that group. The 'mux' selects the function mode(also named mux -mode) this pin can work on and the 'config' configures various pad settings -such as pull-up, open drain, drive strength, etc. - -Required properties for iomux controller: -- compatible: "fsl,-iomuxc" - Please refer to each fsl,-pinctrl.txt binding doc for supported SoCs. - -Required properties for pin configuration node: -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up on this pin. Please refer to fsl,-pinctrl.txt for the valid - pins and functions of each SoC. - -Bits used for CONFIG: -NO_PAD_CTL(1 << 31): indicate this pin does not need config. - -SION(1 << 30): Software Input On Field. -Force the selected mux mode input path no matter of MUX_MODE functionality. -By default the input path is determined by functionality of the selected -mux mode (regular). - -Other bits are used for PAD setting. -Please refer to each fsl,-pinctrl,txt binding doc for SoC specific part -of bits definitions. - -NOTE: -Some requirements for using fsl,imx-pinctrl binding: -1. We have pin function node defined under iomux controller node to represent - what pinmux functions this SoC supports. -2. The pin configuration node intends to work on a specific function should - to be defined under that specific function node. - The function node's name should represent well about what function - this group of pins in this pin configuration node are working on. -3. The driver can use the function node's name and pin configuration node's - name describe the pin function and group hierarchy. - For example, Linux IMX pinctrl driver takes the function node's name - as the function name and pin configuration node's name as group name to - create the map table. -4. Each pin configuration node should have a phandle, devices can set pins - configurations by referring to the phandle of that pin configuration node. - -Examples: -usdhc@0219c000 { /* uSDHC4 */ - fsl,card-wired; - vmmc-supply = <®_3p3v>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4_1>; -}; - -iomuxc@020e0000 { - compatible = "fsl,imx6q-iomuxc"; - reg = <0x020e0000 0x4000>; - - /* shared pinctrl settings */ - usdhc4 { - pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ - }; - }; - .... -}; -Refer to the IOMUXC controller chapter in imx6q datasheet, -0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, -80Ohm driver strength and Fast Slew Rate. -User should refer to each SoC spec to set the correct value. - -TODO: when dtc macro support is available, we can change above raw data -to dt macro which can get better readability in dts file. diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt deleted file mode 100644 index 82b43f915857..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt +++ /dev/null @@ -1,1628 +0,0 @@ -* Freescale IMX6Q IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6q-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6q datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -See below for available PIN_FUNC_ID for imx6q: -MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0 -MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1 -MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2 -MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3 -MX6Q_PAD_SD2_DAT1__KPP_COL_7 4 -MX6Q_PAD_SD2_DAT1__GPIO_1_14 5 -MX6Q_PAD_SD2_DAT1__CCM_WAIT 6 -MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7 -MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8 -MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9 -MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10 -MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11 -MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12 -MX6Q_PAD_SD2_DAT2__GPIO_1_13 13 -MX6Q_PAD_SD2_DAT2__CCM_STOP 14 -MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15 -MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16 -MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17 -MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18 -MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19 -MX6Q_PAD_SD2_DAT0__GPIO_1_15 20 -MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21 -MX6Q_PAD_SD2_DAT0__TESTO_2 22 -MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23 -MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24 -MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25 -MX6Q_PAD_RGMII_TXC__GPIO_6_19 26 -MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27 -MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28 -MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29 -MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30 -MX6Q_PAD_RGMII_TD0__GPIO_6_20 31 -MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32 -MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33 -MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34 -MX6Q_PAD_RGMII_TD1__GPIO_6_21 35 -MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36 -MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37 -MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38 -MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39 -MX6Q_PAD_RGMII_TD2__GPIO_6_22 40 -MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41 -MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42 -MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43 -MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44 -MX6Q_PAD_RGMII_TD3__GPIO_6_23 45 -MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46 -MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47 -MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48 -MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49 -MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50 -MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51 -MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52 -MX6Q_PAD_RGMII_RD0__GPIO_6_25 53 -MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54 -MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55 -MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56 -MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57 -MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58 -MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59 -MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60 -MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61 -MX6Q_PAD_RGMII_RD1__GPIO_6_27 62 -MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63 -MX6Q_PAD_RGMII_RD1__SJC_FAIL 64 -MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65 -MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66 -MX6Q_PAD_RGMII_RD2__GPIO_6_28 67 -MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68 -MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69 -MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70 -MX6Q_PAD_RGMII_RD3__GPIO_6_29 71 -MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72 -MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73 -MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74 -MX6Q_PAD_RGMII_RXC__GPIO_6_30 75 -MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76 -MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77 -MX6Q_PAD_EIM_A25__ECSPI4_SS1 78 -MX6Q_PAD_EIM_A25__ECSPI2_RDY 79 -MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80 -MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81 -MX6Q_PAD_EIM_A25__GPIO_5_2 82 -MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83 -MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84 -MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85 -MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86 -MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87 -MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88 -MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89 -MX6Q_PAD_EIM_EB2__GPIO_2_30 90 -MX6Q_PAD_EIM_EB2__I2C2_SCL 91 -MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92 -MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93 -MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94 -MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95 -MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96 -MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97 -MX6Q_PAD_EIM_D16__GPIO_3_16 98 -MX6Q_PAD_EIM_D16__I2C2_SDA 99 -MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100 -MX6Q_PAD_EIM_D17__ECSPI1_MISO 101 -MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102 -MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103 -MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104 -MX6Q_PAD_EIM_D17__GPIO_3_17 105 -MX6Q_PAD_EIM_D17__I2C3_SCL 106 -MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107 -MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108 -MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109 -MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110 -MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111 -MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112 -MX6Q_PAD_EIM_D18__GPIO_3_18 113 -MX6Q_PAD_EIM_D18__I2C3_SDA 114 -MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115 -MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116 -MX6Q_PAD_EIM_D19__ECSPI1_SS1 117 -MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118 -MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119 -MX6Q_PAD_EIM_D19__UART1_CTS 120 -MX6Q_PAD_EIM_D19__GPIO_3_19 121 -MX6Q_PAD_EIM_D19__EPIT1_EPITO 122 -MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123 -MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124 -MX6Q_PAD_EIM_D20__ECSPI4_SS0 125 -MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126 -MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127 -MX6Q_PAD_EIM_D20__UART1_RTS 128 -MX6Q_PAD_EIM_D20__GPIO_3_20 129 -MX6Q_PAD_EIM_D20__EPIT2_EPITO 130 -MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131 -MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132 -MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133 -MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134 -MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135 -MX6Q_PAD_EIM_D21__GPIO_3_21 136 -MX6Q_PAD_EIM_D21__I2C1_SCL 137 -MX6Q_PAD_EIM_D21__SPDIF_IN1 138 -MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139 -MX6Q_PAD_EIM_D22__ECSPI4_MISO 140 -MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141 -MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142 -MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143 -MX6Q_PAD_EIM_D22__GPIO_3_22 144 -MX6Q_PAD_EIM_D22__SPDIF_OUT1 145 -MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146 -MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147 -MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148 -MX6Q_PAD_EIM_D23__UART3_CTS 149 -MX6Q_PAD_EIM_D23__UART1_DCD 150 -MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151 -MX6Q_PAD_EIM_D23__GPIO_3_23 152 -MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153 -MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154 -MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155 -MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156 -MX6Q_PAD_EIM_EB3__UART3_RTS 157 -MX6Q_PAD_EIM_EB3__UART1_RI 158 -MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159 -MX6Q_PAD_EIM_EB3__GPIO_2_31 160 -MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161 -MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162 -MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163 -MX6Q_PAD_EIM_D24__ECSPI4_SS2 164 -MX6Q_PAD_EIM_D24__UART3_TXD 165 -MX6Q_PAD_EIM_D24__ECSPI1_SS2 166 -MX6Q_PAD_EIM_D24__ECSPI2_SS2 167 -MX6Q_PAD_EIM_D24__GPIO_3_24 168 -MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169 -MX6Q_PAD_EIM_D24__UART1_DTR 170 -MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171 -MX6Q_PAD_EIM_D25__ECSPI4_SS3 172 -MX6Q_PAD_EIM_D25__UART3_RXD 173 -MX6Q_PAD_EIM_D25__ECSPI1_SS3 174 -MX6Q_PAD_EIM_D25__ECSPI2_SS3 175 -MX6Q_PAD_EIM_D25__GPIO_3_25 176 -MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177 -MX6Q_PAD_EIM_D25__UART1_DSR 178 -MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179 -MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180 -MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181 -MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182 -MX6Q_PAD_EIM_D26__UART2_TXD 183 -MX6Q_PAD_EIM_D26__GPIO_3_26 184 -MX6Q_PAD_EIM_D26__IPU1_SISG_2 185 -MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186 -MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187 -MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188 -MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189 -MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190 -MX6Q_PAD_EIM_D27__UART2_RXD 191 -MX6Q_PAD_EIM_D27__GPIO_3_27 192 -MX6Q_PAD_EIM_D27__IPU1_SISG_3 193 -MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194 -MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195 -MX6Q_PAD_EIM_D28__I2C1_SDA 196 -MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197 -MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198 -MX6Q_PAD_EIM_D28__UART2_CTS 199 -MX6Q_PAD_EIM_D28__GPIO_3_28 200 -MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201 -MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202 -MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203 -MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204 -MX6Q_PAD_EIM_D29__ECSPI4_SS0 205 -MX6Q_PAD_EIM_D29__UART2_RTS 206 -MX6Q_PAD_EIM_D29__GPIO_3_29 207 -MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208 -MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209 -MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210 -MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211 -MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212 -MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213 -MX6Q_PAD_EIM_D30__UART3_CTS 214 -MX6Q_PAD_EIM_D30__GPIO_3_30 215 -MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216 -MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217 -MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218 -MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219 -MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220 -MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221 -MX6Q_PAD_EIM_D31__UART3_RTS 222 -MX6Q_PAD_EIM_D31__GPIO_3_31 223 -MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224 -MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225 -MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226 -MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227 -MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228 -MX6Q_PAD_EIM_A24__IPU2_SISG_2 229 -MX6Q_PAD_EIM_A24__IPU1_SISG_2 230 -MX6Q_PAD_EIM_A24__GPIO_5_4 231 -MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232 -MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233 -MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234 -MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235 -MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236 -MX6Q_PAD_EIM_A23__IPU2_SISG_3 237 -MX6Q_PAD_EIM_A23__IPU1_SISG_3 238 -MX6Q_PAD_EIM_A23__GPIO_6_6 239 -MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240 -MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241 -MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242 -MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243 -MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244 -MX6Q_PAD_EIM_A22__GPIO_2_16 245 -MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246 -MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247 -MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248 -MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249 -MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250 -MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251 -MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252 -MX6Q_PAD_EIM_A21__GPIO_2_17 253 -MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254 -MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255 -MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256 -MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257 -MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258 -MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259 -MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260 -MX6Q_PAD_EIM_A20__GPIO_2_18 261 -MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262 -MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263 -MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264 -MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265 -MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266 -MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267 -MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268 -MX6Q_PAD_EIM_A19__GPIO_2_19 269 -MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270 -MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271 -MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272 -MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273 -MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274 -MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275 -MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276 -MX6Q_PAD_EIM_A18__GPIO_2_20 277 -MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278 -MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279 -MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280 -MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281 -MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282 -MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283 -MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284 -MX6Q_PAD_EIM_A17__GPIO_2_21 285 -MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286 -MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287 -MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288 -MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289 -MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290 -MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291 -MX6Q_PAD_EIM_A16__GPIO_2_22 292 -MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293 -MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294 -MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295 -MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296 -MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297 -MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298 -MX6Q_PAD_EIM_CS0__GPIO_2_23 299 -MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300 -MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301 -MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302 -MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303 -MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304 -MX6Q_PAD_EIM_CS1__GPIO_2_24 305 -MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306 -MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307 -MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308 -MX6Q_PAD_EIM_OE__ECSPI2_MISO 309 -MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310 -MX6Q_PAD_EIM_OE__GPIO_2_25 311 -MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312 -MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313 -MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314 -MX6Q_PAD_EIM_RW__ECSPI2_SS0 315 -MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316 -MX6Q_PAD_EIM_RW__GPIO_2_26 317 -MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318 -MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319 -MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320 -MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321 -MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322 -MX6Q_PAD_EIM_LBA__GPIO_2_27 323 -MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324 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-MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489 -MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490 -MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491 -MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492 -MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493 -MX6Q_PAD_SD4_DAT4__UART2_RXD 1494 -MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495 -MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496 -MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497 -MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498 -MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499 -MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500 -MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501 -MX6Q_PAD_SD4_DAT5__UART2_RTS 1502 -MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503 -MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504 -MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505 -MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506 -MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507 -MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508 -MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509 -MX6Q_PAD_SD4_DAT6__UART2_CTS 1510 -MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511 -MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512 -MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513 -MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514 -MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515 -MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516 -MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517 -MX6Q_PAD_SD4_DAT7__UART2_TXD 1518 -MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519 -MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520 -MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521 -MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522 -MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523 -MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524 -MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525 -MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526 -MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527 -MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528 -MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529 -MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530 -MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531 -MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532 -MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533 -MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534 -MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535 -MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536 -MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537 -MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538 -MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539 -MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540 -MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541 -MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542 -MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543 -MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544 -MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545 -MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546 -MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547 -MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548 -MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549 -MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550 -MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551 -MX6Q_PAD_SD1_CMD__GPIO_1_18 1552 -MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553 -MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554 -MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555 -MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556 -MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557 -MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558 -MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559 -MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560 -MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561 -MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562 -MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563 -MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564 -MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565 -MX6Q_PAD_SD1_CLK__GPIO_1_20 1566 -MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567 -MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568 -MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569 -MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570 -MX6Q_PAD_SD2_CLK__KPP_COL_5 1571 -MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572 -MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573 -MX6Q_PAD_SD2_CLK__GPIO_1_10 1574 -MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575 -MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576 -MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577 -MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578 -MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579 -MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580 -MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581 -MX6Q_PAD_SD2_CMD__GPIO_1_11 1582 -MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583 -MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584 -MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585 -MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586 -MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587 -MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588 -MX6Q_PAD_SD2_DAT3__SJC_DONE 1589 -MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590 diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt deleted file mode 100644 index f7e8e8f4d9a3..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ /dev/null @@ -1,918 +0,0 @@ -* Freescale MXS Pin Controller - -The pins controlled by mxs pin controller are organized in banks, each bank -has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th -function is GPIO. The configuration on the pins includes drive strength, -voltage and pull-up. - -Required properties: -- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" -- reg: Should contain the register physical address and length for the - pin controller. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -The node of mxs pin controller acts as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for -a group of pins, and only affects those parameters that are explicitly listed. -In other words, a subnode that describes a drive strength parameter implies no -information about pull-up. For this reason, even seemingly boolean values are -actually tristates in this binding: unspecified, off, or on. Unspecified is -represented as an absent property, and off/on are represented as integer -values 0 and 1. - -Those subnodes under mxs pin controller node will fall into two categories. -One is to set up a group of pins for a function, both mux selection and pin -configurations, and it's called group node in the binding document. The other -one is to adjust the pin configuration for some particular pins that need a -different configuration than what is defined in group node. The binding -document calls this type of node config node. - -On mxs, there is no hardware pin group. The pin group in this binding only -means a group of pins put together for particular peripheral to work in -particular function, like SSP0 functioning as mmc0-8bit. That said, the -group node should include all the pins needed for one function rather than -having these pins defined in several group nodes. It also means each of -"pinctrl-*" phandle in client device node should only have one group node -pointed in there, while the phandle can have multiple config node referenced -there to adjust configurations for some pins in the group. - -Required subnode-properties: -- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin - with given mux function, with bank, pin and mux packed as below. - - [15..12] : bank number - [11..4] : pin number - [3..0] : mux selection - - This integer with mux selection packed is used as an entity by both group - and config nodes to identify a pin. The mux selection in the integer takes - effects only on group node, and will get ignored by driver with config node, - since config node is only meant to set up pin configurations. - - Valid values for these integers are listed below. - -- reg: Should be the index of the group nodes for same function. This property - is required only for group nodes, and should not be present in any config - nodes. - -Optional subnode-properties: -- fsl,drive-strength: Integer. - 0: 4 mA - 1: 8 mA - 2: 12 mA - 3: 16 mA -- fsl,voltage: Integer. - 0: 1.8 V - 1: 3.3 V -- fsl,pull-up: Integer. - 0: Disable the internal pull-up - 1: Enable the internal pull-up - -Examples: - -pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-pinctrl"; - reg = <0x80018000 2000>; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x2000 0x2010 0x2020 0x2030 - 0x2040 0x2050 0x2060 0x2070 - 0x2080 0x2090 0x20a0>; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; - }; - - mmc_cd_cfg: mmc-cd-cfg { - fsl,pinmux-ids = <0x2090>; - fsl,pull-up = <0>; - }; - - mmc_sck_cfg: mmc-sck-cfg { - fsl,pinmux-ids = <0x20a0>; - fsl,drive-strength = <2>; - fsl,pull-up = <0>; - }; -}; - -In this example, group node mmc0-8bit defines a group of pins for mxs SSP0 -to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations -applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are -adjusting the configuration for pins card-detection and clock from what group -node mmc0-8bit defines. Only the configuration properties to be adjusted need -to be listed in the config nodes. - -Valid values for i.MX28 pinmux-id: - -pinmux id ------- -- -MX28_PAD_GPMI_D00__GPMI_D0 0x0000 -MX28_PAD_GPMI_D01__GPMI_D1 0x0010 -MX28_PAD_GPMI_D02__GPMI_D2 0x0020 -MX28_PAD_GPMI_D03__GPMI_D3 0x0030 -MX28_PAD_GPMI_D04__GPMI_D4 0x0040 -MX28_PAD_GPMI_D05__GPMI_D5 0x0050 -MX28_PAD_GPMI_D06__GPMI_D6 0x0060 -MX28_PAD_GPMI_D07__GPMI_D7 0x0070 -MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 -MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 -MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 -MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 -MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 -MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 -MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 -MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 -MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 -MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 -MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 -MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 -MX28_PAD_LCD_D00__LCD_D0 0x1000 -MX28_PAD_LCD_D01__LCD_D1 0x1010 -MX28_PAD_LCD_D02__LCD_D2 0x1020 -MX28_PAD_LCD_D03__LCD_D3 0x1030 -MX28_PAD_LCD_D04__LCD_D4 0x1040 -MX28_PAD_LCD_D05__LCD_D5 0x1050 -MX28_PAD_LCD_D06__LCD_D6 0x1060 -MX28_PAD_LCD_D07__LCD_D7 0x1070 -MX28_PAD_LCD_D08__LCD_D8 0x1080 -MX28_PAD_LCD_D09__LCD_D9 0x1090 -MX28_PAD_LCD_D10__LCD_D10 0x10a0 -MX28_PAD_LCD_D11__LCD_D11 0x10b0 -MX28_PAD_LCD_D12__LCD_D12 0x10c0 -MX28_PAD_LCD_D13__LCD_D13 0x10d0 -MX28_PAD_LCD_D14__LCD_D14 0x10e0 -MX28_PAD_LCD_D15__LCD_D15 0x10f0 -MX28_PAD_LCD_D16__LCD_D16 0x1100 -MX28_PAD_LCD_D17__LCD_D17 0x1110 -MX28_PAD_LCD_D18__LCD_D18 0x1120 -MX28_PAD_LCD_D19__LCD_D19 0x1130 -MX28_PAD_LCD_D20__LCD_D20 0x1140 -MX28_PAD_LCD_D21__LCD_D21 0x1150 -MX28_PAD_LCD_D22__LCD_D22 0x1160 -MX28_PAD_LCD_D23__LCD_D23 0x1170 -MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 -MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 -MX28_PAD_LCD_RS__LCD_RS 0x11a0 -MX28_PAD_LCD_CS__LCD_CS 0x11b0 -MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 -MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 -MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 -MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 -MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 -MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 -MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 -MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 -MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 -MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 -MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 -MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 -MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 -MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 -MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 -MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 -MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 -MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 -MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 -MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 -MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 -MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 -MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 -MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 -MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 -MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 -MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 -MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 -MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 -MX28_PAD_AUART0_RX__AUART0_RX 0x3000 -MX28_PAD_AUART0_TX__AUART0_TX 0x3010 -MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 -MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 -MX28_PAD_AUART1_RX__AUART1_RX 0x3040 -MX28_PAD_AUART1_TX__AUART1_TX 0x3050 -MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 -MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 -MX28_PAD_AUART2_RX__AUART2_RX 0x3080 -MX28_PAD_AUART2_TX__AUART2_TX 0x3090 -MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 -MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 -MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 -MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 -MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 -MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 -MX28_PAD_PWM0__PWM_0 0x3100 -MX28_PAD_PWM1__PWM_1 0x3110 -MX28_PAD_PWM2__PWM_2 0x3120 -MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 -MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 -MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 -MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 -MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 -MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 -MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 -MX28_PAD_SPDIF__SPDIF_TX 0x31b0 -MX28_PAD_PWM3__PWM_3 0x31c0 -MX28_PAD_PWM4__PWM_4 0x31d0 -MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 -MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 -MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 -MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 -MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 -MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 -MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 -MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 -MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 -MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 -MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 -MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 -MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 -MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 -MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 -MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 -MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 -MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 -MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 -MX28_PAD_EMI_D00__EMI_DATA0 0x5000 -MX28_PAD_EMI_D01__EMI_DATA1 0x5010 -MX28_PAD_EMI_D02__EMI_DATA2 0x5020 -MX28_PAD_EMI_D03__EMI_DATA3 0x5030 -MX28_PAD_EMI_D04__EMI_DATA4 0x5040 -MX28_PAD_EMI_D05__EMI_DATA5 0x5050 -MX28_PAD_EMI_D06__EMI_DATA6 0x5060 -MX28_PAD_EMI_D07__EMI_DATA7 0x5070 -MX28_PAD_EMI_D08__EMI_DATA8 0x5080 -MX28_PAD_EMI_D09__EMI_DATA9 0x5090 -MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 -MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 -MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 -MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 -MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 -MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 -MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 -MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 -MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 -MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 -MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 -MX28_PAD_EMI_CLK__EMI_CLK 0x5150 -MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 -MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 -MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 -MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 -MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 -MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 -MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 -MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 -MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 -MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 -MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 -MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 -MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 -MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 -MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 -MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 -MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 -MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 -MX28_PAD_EMI_BA0__EMI_BA0 0x6100 -MX28_PAD_EMI_BA1__EMI_BA1 0x6110 -MX28_PAD_EMI_BA2__EMI_BA2 0x6120 -MX28_PAD_EMI_CASN__EMI_CASN 0x6130 -MX28_PAD_EMI_RASN__EMI_RASN 0x6140 -MX28_PAD_EMI_WEN__EMI_WEN 0x6150 -MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 -MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 -MX28_PAD_EMI_CKE__EMI_CKE 0x6180 -MX28_PAD_GPMI_D00__SSP1_D0 0x0001 -MX28_PAD_GPMI_D01__SSP1_D1 0x0011 -MX28_PAD_GPMI_D02__SSP1_D2 0x0021 -MX28_PAD_GPMI_D03__SSP1_D3 0x0031 -MX28_PAD_GPMI_D04__SSP1_D4 0x0041 -MX28_PAD_GPMI_D05__SSP1_D5 0x0051 -MX28_PAD_GPMI_D06__SSP1_D6 0x0061 -MX28_PAD_GPMI_D07__SSP1_D7 0x0071 -MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 -MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 -MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 -MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 -MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 -MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 -MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 -MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 -MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 -MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 -MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 -MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 -MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 -MX28_PAD_LCD_D03__ETM_DA8 0x1031 -MX28_PAD_LCD_D04__ETM_DA9 0x1041 -MX28_PAD_LCD_D08__ETM_DA3 0x1081 -MX28_PAD_LCD_D09__ETM_DA4 0x1091 -MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 -MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 -MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 -MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 -MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 -MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 -MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 -MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 -MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 -MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 -MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 -MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 -MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 -MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 -MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 -MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 -MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 -MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 -MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 -MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 -MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 -MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 -MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 -MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 -MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 -MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 -MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 -MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 -MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 -MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 -MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 -MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 -MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 -MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 -MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 -MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 -MX28_PAD_AUART1_RTS__USB0_ID 0x3071 -MX28_PAD_AUART2_RX__SSP3_D1 0x3081 -MX28_PAD_AUART2_TX__SSP3_D2 0x3091 -MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 -MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 -MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 -MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 -MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 -MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 -MX28_PAD_PWM0__I2C1_SCL 0x3101 -MX28_PAD_PWM1__I2C1_SDA 0x3111 -MX28_PAD_PWM2__USB0_ID 0x3121 -MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 -MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 -MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 -MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 -MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 -MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 -MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 -MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 -MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 -MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 -MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 -MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 -MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 -MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 -MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 -MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 -MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 -MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 -MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 -MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 -MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 -MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 -MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 -MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 -MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 -MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 -MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 -MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 -MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 -MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 -MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 -MX28_PAD_LCD_D00__ETM_DA0 0x1002 -MX28_PAD_LCD_D01__ETM_DA1 0x1012 -MX28_PAD_LCD_D02__ETM_DA2 0x1022 -MX28_PAD_LCD_D03__ETM_DA3 0x1032 -MX28_PAD_LCD_D04__ETM_DA4 0x1042 -MX28_PAD_LCD_D05__ETM_DA5 0x1052 -MX28_PAD_LCD_D06__ETM_DA6 0x1062 -MX28_PAD_LCD_D07__ETM_DA7 0x1072 -MX28_PAD_LCD_D08__ETM_DA8 0x1082 -MX28_PAD_LCD_D09__ETM_DA9 0x1092 -MX28_PAD_LCD_D10__ETM_DA10 0x10a2 -MX28_PAD_LCD_D11__ETM_DA11 0x10b2 -MX28_PAD_LCD_D12__ETM_DA12 0x10c2 -MX28_PAD_LCD_D13__ETM_DA13 0x10d2 -MX28_PAD_LCD_D14__ETM_DA14 0x10e2 -MX28_PAD_LCD_D15__ETM_DA15 0x10f2 -MX28_PAD_LCD_D16__ETM_DA7 0x1102 -MX28_PAD_LCD_D17__ETM_DA6 0x1112 -MX28_PAD_LCD_D18__ETM_DA5 0x1122 -MX28_PAD_LCD_D19__ETM_DA4 0x1132 -MX28_PAD_LCD_D20__ETM_DA3 0x1142 -MX28_PAD_LCD_D21__ETM_DA2 0x1152 -MX28_PAD_LCD_D22__ETM_DA1 0x1162 -MX28_PAD_LCD_D23__ETM_DA0 0x1172 -MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 -MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 -MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 -MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 -MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 -MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 -MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 -MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 -MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 -MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 -MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 -MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 -MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 -MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 -MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 -MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 -MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 -MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 -MX28_PAD_AUART0_RX__DUART_CTS 0x3002 -MX28_PAD_AUART0_TX__DUART_RTS 0x3012 -MX28_PAD_AUART0_CTS__DUART_RX 0x3022 -MX28_PAD_AUART0_RTS__DUART_TX 0x3032 -MX28_PAD_AUART1_RX__PWM_0 0x3042 -MX28_PAD_AUART1_TX__PWM_1 0x3052 -MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 -MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 -MX28_PAD_AUART2_RX__SSP3_D4 0x3082 -MX28_PAD_AUART2_TX__SSP3_D5 0x3092 -MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 -MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 -MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 -MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 -MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 -MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 -MX28_PAD_PWM0__DUART_RX 0x3102 -MX28_PAD_PWM1__DUART_TX 0x3112 -MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 -MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 -MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 -MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 -MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 -MX28_PAD_I2C0_SCL__DUART_RX 0x3182 -MX28_PAD_I2C0_SDA__DUART_TX 0x3192 -MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 -MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 -MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 -MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 -MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 -MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 -MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 -MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 -MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 -MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 -MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 -MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 -MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 -MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 -MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 -MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 -MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 -MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 -MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 -MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 -MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 -MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 -MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 -MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 -MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 -MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 -MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 -MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 -MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 -MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 -MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 -MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 -MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 -MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 -MX28_PAD_LCD_D00__GPIO_1_0 0x1003 -MX28_PAD_LCD_D01__GPIO_1_1 0x1013 -MX28_PAD_LCD_D02__GPIO_1_2 0x1023 -MX28_PAD_LCD_D03__GPIO_1_3 0x1033 -MX28_PAD_LCD_D04__GPIO_1_4 0x1043 -MX28_PAD_LCD_D05__GPIO_1_5 0x1053 -MX28_PAD_LCD_D06__GPIO_1_6 0x1063 -MX28_PAD_LCD_D07__GPIO_1_7 0x1073 -MX28_PAD_LCD_D08__GPIO_1_8 0x1083 -MX28_PAD_LCD_D09__GPIO_1_9 0x1093 -MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 -MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 -MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 -MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 -MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 -MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 -MX28_PAD_LCD_D16__GPIO_1_16 0x1103 -MX28_PAD_LCD_D17__GPIO_1_17 0x1113 -MX28_PAD_LCD_D18__GPIO_1_18 0x1123 -MX28_PAD_LCD_D19__GPIO_1_19 0x1133 -MX28_PAD_LCD_D20__GPIO_1_20 0x1143 -MX28_PAD_LCD_D21__GPIO_1_21 0x1153 -MX28_PAD_LCD_D22__GPIO_1_22 0x1163 -MX28_PAD_LCD_D23__GPIO_1_23 0x1173 -MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 -MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 -MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 -MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 -MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 -MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 -MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 -MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 -MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 -MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 -MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 -MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 -MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 -MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 -MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 -MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 -MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 -MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 -MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 -MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 -MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 -MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 -MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 -MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 -MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 -MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 -MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 -MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 -MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 -MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 -MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 -MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 -MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 -MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 -MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 -MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 -MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 -MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 -MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 -MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 -MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 -MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 -MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 -MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 -MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 -MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 -MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 -MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 -MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 -MX28_PAD_PWM0__GPIO_3_16 0x3103 -MX28_PAD_PWM1__GPIO_3_17 0x3113 -MX28_PAD_PWM2__GPIO_3_18 0x3123 -MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 -MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 -MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 -MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 -MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 -MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 -MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 -MX28_PAD_SPDIF__GPIO_3_27 0x31b3 -MX28_PAD_PWM3__GPIO_3_28 0x31c3 -MX28_PAD_PWM4__GPIO_3_29 0x31d3 -MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 -MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 -MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 -MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 -MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 -MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 -MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 -MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 -MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 -MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 -MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 -MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 -MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 -MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 -MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 -MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 -MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 -MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 -MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 - -Valid values for i.MX23 pinmux-id: - -pinmux id ------- -- -MX23_PAD_GPMI_D00__GPMI_D00 0x0000 -MX23_PAD_GPMI_D01__GPMI_D01 0x0010 -MX23_PAD_GPMI_D02__GPMI_D02 0x0020 -MX23_PAD_GPMI_D03__GPMI_D03 0x0030 -MX23_PAD_GPMI_D04__GPMI_D04 0x0040 -MX23_PAD_GPMI_D05__GPMI_D05 0x0050 -MX23_PAD_GPMI_D06__GPMI_D06 0x0060 -MX23_PAD_GPMI_D07__GPMI_D07 0x0070 -MX23_PAD_GPMI_D08__GPMI_D08 0x0080 -MX23_PAD_GPMI_D09__GPMI_D09 0x0090 -MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 -MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 -MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 -MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 -MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 -MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 -MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 -MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 -MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 -MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 -MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 -MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 -MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 -MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 -MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 -MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 -MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 -MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 -MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 -MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 -MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 -MX23_PAD_LCD_D00__LCD_D00 0x1000 -MX23_PAD_LCD_D01__LCD_D01 0x1010 -MX23_PAD_LCD_D02__LCD_D02 0x1020 -MX23_PAD_LCD_D03__LCD_D03 0x1030 -MX23_PAD_LCD_D04__LCD_D04 0x1040 -MX23_PAD_LCD_D05__LCD_D05 0x1050 -MX23_PAD_LCD_D06__LCD_D06 0x1060 -MX23_PAD_LCD_D07__LCD_D07 0x1070 -MX23_PAD_LCD_D08__LCD_D08 0x1080 -MX23_PAD_LCD_D09__LCD_D09 0x1090 -MX23_PAD_LCD_D10__LCD_D10 0x10a0 -MX23_PAD_LCD_D11__LCD_D11 0x10b0 -MX23_PAD_LCD_D12__LCD_D12 0x10c0 -MX23_PAD_LCD_D13__LCD_D13 0x10d0 -MX23_PAD_LCD_D14__LCD_D14 0x10e0 -MX23_PAD_LCD_D15__LCD_D15 0x10f0 -MX23_PAD_LCD_D16__LCD_D16 0x1100 -MX23_PAD_LCD_D17__LCD_D17 0x1110 -MX23_PAD_LCD_RESET__LCD_RESET 0x1120 -MX23_PAD_LCD_RS__LCD_RS 0x1130 -MX23_PAD_LCD_WR__LCD_WR 0x1140 -MX23_PAD_LCD_CS__LCD_CS 0x1150 -MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 -MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 -MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 -MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 -MX23_PAD_PWM0__PWM0 0x11a0 -MX23_PAD_PWM1__PWM1 0x11b0 -MX23_PAD_PWM2__PWM2 0x11c0 -MX23_PAD_PWM3__PWM3 0x11d0 -MX23_PAD_PWM4__PWM4 0x11e0 -MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 -MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 -MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 -MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 -MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 -MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 -MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 -MX23_PAD_ROTARYA__ROTARYA 0x2070 -MX23_PAD_ROTARYB__ROTARYB 0x2080 -MX23_PAD_EMI_A00__EMI_A00 0x2090 -MX23_PAD_EMI_A01__EMI_A01 0x20a0 -MX23_PAD_EMI_A02__EMI_A02 0x20b0 -MX23_PAD_EMI_A03__EMI_A03 0x20c0 -MX23_PAD_EMI_A04__EMI_A04 0x20d0 -MX23_PAD_EMI_A05__EMI_A05 0x20e0 -MX23_PAD_EMI_A06__EMI_A06 0x20f0 -MX23_PAD_EMI_A07__EMI_A07 0x2100 -MX23_PAD_EMI_A08__EMI_A08 0x2110 -MX23_PAD_EMI_A09__EMI_A09 0x2120 -MX23_PAD_EMI_A10__EMI_A10 0x2130 -MX23_PAD_EMI_A11__EMI_A11 0x2140 -MX23_PAD_EMI_A12__EMI_A12 0x2150 -MX23_PAD_EMI_BA0__EMI_BA0 0x2160 -MX23_PAD_EMI_BA1__EMI_BA1 0x2170 -MX23_PAD_EMI_CASN__EMI_CASN 0x2180 -MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 -MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 -MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 -MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 -MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 -MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 -MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 -MX23_PAD_EMI_D00__EMI_D00 0x3000 -MX23_PAD_EMI_D01__EMI_D01 0x3010 -MX23_PAD_EMI_D02__EMI_D02 0x3020 -MX23_PAD_EMI_D03__EMI_D03 0x3030 -MX23_PAD_EMI_D04__EMI_D04 0x3040 -MX23_PAD_EMI_D05__EMI_D05 0x3050 -MX23_PAD_EMI_D06__EMI_D06 0x3060 -MX23_PAD_EMI_D07__EMI_D07 0x3070 -MX23_PAD_EMI_D08__EMI_D08 0x3080 -MX23_PAD_EMI_D09__EMI_D09 0x3090 -MX23_PAD_EMI_D10__EMI_D10 0x30a0 -MX23_PAD_EMI_D11__EMI_D11 0x30b0 -MX23_PAD_EMI_D12__EMI_D12 0x30c0 -MX23_PAD_EMI_D13__EMI_D13 0x30d0 -MX23_PAD_EMI_D14__EMI_D14 0x30e0 -MX23_PAD_EMI_D15__EMI_D15 0x30f0 -MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 -MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 -MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 -MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 -MX23_PAD_EMI_CLK__EMI_CLK 0x3140 -MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 -MX23_PAD_GPMI_D00__LCD_D8 0x0001 -MX23_PAD_GPMI_D01__LCD_D9 0x0011 -MX23_PAD_GPMI_D02__LCD_D10 0x0021 -MX23_PAD_GPMI_D03__LCD_D11 0x0031 -MX23_PAD_GPMI_D04__LCD_D12 0x0041 -MX23_PAD_GPMI_D05__LCD_D13 0x0051 -MX23_PAD_GPMI_D06__LCD_D14 0x0061 -MX23_PAD_GPMI_D07__LCD_D15 0x0071 -MX23_PAD_GPMI_D08__LCD_D18 0x0081 -MX23_PAD_GPMI_D09__LCD_D19 0x0091 -MX23_PAD_GPMI_D10__LCD_D20 0x00a1 -MX23_PAD_GPMI_D11__LCD_D21 0x00b1 -MX23_PAD_GPMI_D12__LCD_D22 0x00c1 -MX23_PAD_GPMI_D13__LCD_D23 0x00d1 -MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 -MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 -MX23_PAD_GPMI_CLE__LCD_D16 0x0101 -MX23_PAD_GPMI_ALE__LCD_D17 0x0111 -MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 -MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 -MX23_PAD_AUART1_RX__IR_RX 0x01c1 -MX23_PAD_AUART1_TX__IR_TX 0x01d1 -MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 -MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 -MX23_PAD_LCD_D00__ETM_DA8 0x1001 -MX23_PAD_LCD_D01__ETM_DA9 0x1011 -MX23_PAD_LCD_D02__ETM_DA10 0x1021 -MX23_PAD_LCD_D03__ETM_DA11 0x1031 -MX23_PAD_LCD_D04__ETM_DA12 0x1041 -MX23_PAD_LCD_D05__ETM_DA13 0x1051 -MX23_PAD_LCD_D06__ETM_DA14 0x1061 -MX23_PAD_LCD_D07__ETM_DA15 0x1071 -MX23_PAD_LCD_D08__ETM_DA0 0x1081 -MX23_PAD_LCD_D09__ETM_DA1 0x1091 -MX23_PAD_LCD_D10__ETM_DA2 0x10a1 -MX23_PAD_LCD_D11__ETM_DA3 0x10b1 -MX23_PAD_LCD_D12__ETM_DA4 0x10c1 -MX23_PAD_LCD_D13__ETM_DA5 0x10d1 -MX23_PAD_LCD_D14__ETM_DA6 0x10e1 -MX23_PAD_LCD_D15__ETM_DA7 0x10f1 -MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 -MX23_PAD_LCD_RS__ETM_TCLK 0x1131 -MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 -MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 -MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 -MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 -MX23_PAD_PWM0__ROTARYA 0x11a1 -MX23_PAD_PWM1__ROTARYB 0x11b1 -MX23_PAD_PWM2__GPMI_RDY3 0x11c1 -MX23_PAD_PWM3__ETM_TCTL 0x11d1 -MX23_PAD_PWM4__ETM_TCLK 0x11e1 -MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 -MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 -MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 -MX23_PAD_ROTARYA__AUART2_RTS 0x2071 -MX23_PAD_ROTARYB__AUART2_CTS 0x2081 -MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 -MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 -MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 -MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 -MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 -MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 -MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 -MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 -MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 -MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 -MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 -MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 -MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 -MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 -MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 -MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 -MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 -MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 -MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 -MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 -MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 -MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 -MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 -MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 -MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 -MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 -MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 -MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 -MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 -MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 -MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 -MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 -MX23_PAD_PWM0__DUART_RX 0x11a2 -MX23_PAD_PWM1__DUART_TX 0x11b2 -MX23_PAD_PWM3__AUART1_CTS 0x11d2 -MX23_PAD_PWM4__AUART1_RTS 0x11e2 -MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 -MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 -MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 -MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 -MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 -MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 -MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 -MX23_PAD_ROTARYA__SPDIF 0x2072 -MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 -MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 -MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 -MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 -MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 -MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 -MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 -MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 -MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 -MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 -MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 -MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 -MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 -MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 -MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 -MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 -MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 -MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 -MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 -MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 -MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 -MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 -MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 -MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 -MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 -MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 -MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 -MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 -MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 -MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 -MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 -MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 -MX23_PAD_LCD_D00__GPIO_1_0 0x1003 -MX23_PAD_LCD_D01__GPIO_1_1 0x1013 -MX23_PAD_LCD_D02__GPIO_1_2 0x1023 -MX23_PAD_LCD_D03__GPIO_1_3 0x1033 -MX23_PAD_LCD_D04__GPIO_1_4 0x1043 -MX23_PAD_LCD_D05__GPIO_1_5 0x1053 -MX23_PAD_LCD_D06__GPIO_1_6 0x1063 -MX23_PAD_LCD_D07__GPIO_1_7 0x1073 -MX23_PAD_LCD_D08__GPIO_1_8 0x1083 -MX23_PAD_LCD_D09__GPIO_1_9 0x1093 -MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 -MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 -MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 -MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 -MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 -MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 -MX23_PAD_LCD_D16__GPIO_1_16 0x1103 -MX23_PAD_LCD_D17__GPIO_1_17 0x1113 -MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 -MX23_PAD_LCD_RS__GPIO_1_19 0x1133 -MX23_PAD_LCD_WR__GPIO_1_20 0x1143 -MX23_PAD_LCD_CS__GPIO_1_21 0x1153 -MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 -MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 -MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 -MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 -MX23_PAD_PWM0__GPIO_1_26 0x11a3 -MX23_PAD_PWM1__GPIO_1_27 0x11b3 -MX23_PAD_PWM2__GPIO_1_28 0x11c3 -MX23_PAD_PWM3__GPIO_1_29 0x11d3 -MX23_PAD_PWM4__GPIO_1_30 0x11e3 -MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 -MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 -MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 -MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 -MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 -MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 -MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 -MX23_PAD_ROTARYA__GPIO_2_7 0x2073 -MX23_PAD_ROTARYB__GPIO_2_8 0x2083 -MX23_PAD_EMI_A00__GPIO_2_9 0x2093 -MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 -MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 -MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 -MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 -MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 -MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 -MX23_PAD_EMI_A07__GPIO_2_16 0x2103 -MX23_PAD_EMI_A08__GPIO_2_17 0x2113 -MX23_PAD_EMI_A09__GPIO_2_18 0x2123 -MX23_PAD_EMI_A10__GPIO_2_19 0x2133 -MX23_PAD_EMI_A11__GPIO_2_20 0x2143 -MX23_PAD_EMI_A12__GPIO_2_21 0x2153 -MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 -MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 -MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 -MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 -MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 -MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 -MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 -MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 -MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 -MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt deleted file mode 100644 index c8e578263ce2..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt +++ /dev/null @@ -1,132 +0,0 @@ -NVIDIA Tegra20 pinmux controller - -Required properties: -- compatible: "nvidia,tegra20-pinmux" -- reg: Should contain the register physical address and length for each of - the tri-state, mux, pull-up/down, and pad control register sets. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Tegra's pin configuration nodes act as a container for an abitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, tristate, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function or tristate parameter. For this -reason, even seemingly boolean values are actually tristates in this binding: -unspecified, off, or on. Unspecified is represented as an absent property, -and off/on are represented as integer values 0 and 1. - -Required subnode-properties: -- nvidia,pins : An array of strings. Each string contains the name of a pin or - group. Valid values for these names are listed below. - -Optional subnode-properties: -- nvidia,function: A string containing the name of the function to mux to the - pin or group. Valid values for function names are listed below. See the Tegra - TRM to determine which are valid for each pin or group. -- nvidia,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down, 2: up. -- nvidia,tristate: Integer. - 0: drive, 1: tristate. -- nvidia,high-speed-mode: Integer. Enable high speed mode the pins. - 0: no, 1: yes. -- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input. - 0: no, 1: yes. -- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is - most power. Controls the drive power or current. See "Low Power Mode" - or "LPMD1" and "LPMD0" in the Tegra TRM. -- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest. - The range of valid values depends on the pingroup. See "CAL_DRVDN" in the - Tegra TRM. -- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest. - The range of valid values depends on the pingroup. See "CAL_DRVUP" in the - Tegra TRM. -- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is - fastest. The range of valid values depends on the pingroup. See - "DRVDN_SLWR" in the Tegra TRM. -- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is - fastest. The range of valid values depends on the pingroup. See - "DRVUP_SLWF" in the Tegra TRM. - -Note that many of these properties are only valid for certain specific pins -or groups. See the Tegra TRM and various pinmux spreadsheets for complete -details regarding which groups support which functionality. The Linux pinctrl -driver may also be a useful reference, since it consolidates, disambiguates, -and corrects data from all those sources. - -Valid values for pin and group names are: - - mux groups: - - These all support nvidia,function, nvidia,tristate, and many support - nvidia,pull. - - ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4, - ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7, - gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, - ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13, - ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp, - lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs, - owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, - spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad, - uca, ucb, uda. - - tristate groups: - - These only support nvidia,pull. - - ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0, - ld19_18, ld21_20, ld23_22. - - drive groups: - - With some exceptions, these support nvidia,high-speed-mode, - nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength, - nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling. - - drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2, - drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg, - drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa, - drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a, - drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc, - drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr, - drive_uda. - -Example: - - pinctrl@70000000 { - compatible = "nvidia,tegra20-pinmux"; - reg = < 0x70000014 0x10 /* Tri-state registers */ - 0x70000080 0x20 /* Mux registers */ - 0x700000a0 0x14 /* Pull-up/down registers */ - 0x70000868 0xa8 >; /* Pad control registers */ - }; - -Example board file extract: - - pinctrl@70000000 { - sdio4_default: sdio4_default { - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - }; - }; - - sdhci@c8000600 { - pinctrl-names = "default"; - pinctrl-0 = <&sdio4_default>; - }; diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt deleted file mode 100644 index c275b70349c1..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt +++ /dev/null @@ -1,132 +0,0 @@ -NVIDIA Tegra30 pinmux controller - -The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding, -as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes -that binding as a baseline, and only documents the differences between the -two bindings. - -Required properties: -- compatible: "nvidia,tegra30-pinmux" -- reg: Should contain the register physical address and length for each of - the pad control and mux registers. - -Tegra30 adds the following optional properties for pin configuration subnodes: -- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes. -- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes. -- nvidia,lock: Integer. Lock the pin configuration against further changes - until reset. 0: no, 1: yes. -- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes. - -As with Tegra20, see the Tegra TRM for complete details regarding which groups -support which functionality. - -Valid values for pin and group names are: - - per-pin mux groups: - - These all support nvidia,function, nvidia,tristate, nvidia,pull, - nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain, - nvidia,io-reset. - - clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3, - dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0, - gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5, - sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1, - uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, - lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2, - sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7, - lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, - lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3, - lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0, - gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, - gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2, - gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7, - gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4, - gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, - gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5, - uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2, - gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7, - vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, - vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3, - lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0, - dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5, - lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2, - ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, - ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, - dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, - kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, - kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, - kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, - kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, - kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1, - vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, - sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0, - pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, - lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4, - clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1, - spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6, - spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, - sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7, - sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4, - sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, - sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, - sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0, - cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, - cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4, - clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7, - pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, - pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5, - pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1, - clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr, - pwr_int_n. - - drive groups: - - These all support nvidia,pull-down-strength, nvidia,pull-up-strength, - nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all - support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode. - - ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1, - dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg, - gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2, - uart3, uda, vi1. - -Example: - - pinctrl@70000000 { - compatible = "nvidia,tegra30-pinmux"; - reg = < 0x70000868 0xd0 /* Pad control registers */ - 0x70003000 0x3e0 >; /* Mux registers */ - }; - -Example board file extract: - - pinctrl@70000000 { - sdmmc4_default: pinmux { - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - }; - }; - - sdhci@78000400 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc4_default>; - }; diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt deleted file mode 100644 index c95ea8278f87..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ /dev/null @@ -1,128 +0,0 @@ -== Introduction == - -Hardware modules that control pin multiplexing or configuration parameters -such as pull-up/down, tri-state, drive-strength etc are designated as pin -controllers. Each pin controller must be represented as a node in device tree, -just like any other hardware module. - -Hardware modules whose signals are affected by pin configuration are -designated client devices. Again, each client device must be represented as a -node in device tree, just like any other hardware module. - -For a client device to operate correctly, certain pin controllers must -set up certain specific pin configurations. Some client devices need a -single static pin configuration, e.g. set up during initialization. Others -need to reconfigure pins at run-time, for example to tri-state pins when the -device is inactive. Hence, each client device can define a set of named -states. The number and names of those states is defined by the client device's -own binding. - -The common pinctrl bindings defined in this file provide an infrastructure -for client device device tree nodes to map those state names to the pin -configuration used by those states. - -Note that pin controllers themselves may also be client devices of themselves. -For example, a pin controller may set up its own "active" state when the -driver loads. This would allow representing a board's static pin configuration -in a single place, rather than splitting it across multiple client device -nodes. The decision to do this or not somewhat rests with the author of -individual board device tree files, and any requirements imposed by the -bindings for the individual client devices in use by that board, i.e. whether -they require certain specific named states for dynamic pin configuration. - -== Pinctrl client devices == - -For each client device individually, every pin state is assigned an integer -ID. These numbers start at 0, and are contiguous. For each state ID, a unique -property exists to define the pin configuration. Each state may also be -assigned a name. When names are used, another property exists to map from -those names to the integer IDs. - -Each client device's own binding determines the set of states the must be -defined in its device tree node, and whether to define the set of state -IDs that must be provided, or whether to define the set of state names that -must be provided. - -Required properties: -pinctrl-0: List of phandles, each pointing at a pin configuration - node. These referenced pin configuration nodes must be child - nodes of the pin controller that they configure. Multiple - entries may exist in this list so that multiple pin - controllers may be configured, or so that a state may be built - from multiple nodes for a single pin controller, each - contributing part of the overall configuration. See the next - section of this document for details of the format of these - pin configuration nodes. - - In some cases, it may be useful to define a state, but for it - to be empty. This may be required when a common IP block is - used in an SoC either without a pin controller, or where the - pin controller does not affect the HW module in question. If - the binding for that IP block requires certain pin states to - exist, they must still be defined, but may be left empty. - -Optional properties: -pinctrl-1: List of phandles, each pointing at a pin configuration - node within a pin controller. -... -pinctrl-n: List of phandles, each pointing at a pin configuration - node within a pin controller. -pinctrl-names: The list of names to assign states. List entry 0 defines the - name for integer state ID 0, list entry 1 for state ID 1, and - so on. - -For example: - - /* For a client device requiring named states */ - device { - pinctrl-names = "active", "idle"; - pinctrl-0 = <&state_0_node_a>; - pinctrl-1 = <&state_1_node_a &state_1_node_b>; - }; - - /* For the same device if using state IDs */ - device { - pinctrl-0 = <&state_0_node_a>; - pinctrl-1 = <&state_1_node_a &state_1_node_b>; - }; - - /* - * For an IP block whose binding supports pin configuration, - * but in use on an SoC that doesn't have any pin control hardware - */ - device { - pinctrl-names = "active", "idle"; - pinctrl-0 = <>; - pinctrl-1 = <>; - }; - -== Pin controller devices == - -Pin controller devices should contain the pin configuration nodes that client -devices reference. - -For example: - - pincontroller { - ... /* Standard DT properties for the device itself elided */ - - state_0_node_a { - ... - }; - state_1_node_a { - ... - }; - state_1_node_b { - ... - }; - } - -The contents of each of those pin configuration child nodes is defined -entirely by the binding for the individual pin controller device. There -exists no common standard for this content. - -The pin configuration nodes need not be direct children of the pin controller -device; they may be grandchildren, for example. Whether this is legal, and -whether there is any interaction between the child and intermediate parent -nodes, is again defined entirely by the binding for the individual pin -controller device. diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt deleted file mode 100644 index 3664d37e6799..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt +++ /dev/null @@ -1,108 +0,0 @@ -ST Microelectronics, SPEAr pinmux controller - -Required properties: -- compatible : "st,spear300-pinmux" - : "st,spear310-pinmux" - : "st,spear320-pinmux" -- reg : Address range of the pinctrl registers -- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others. - - Its values for SPEAr300: - - NAND_MODE : <0> - - NOR_MODE : <1> - - PHOTO_FRAME_MODE : <2> - - LEND_IP_PHONE_MODE : <3> - - HEND_IP_PHONE_MODE : <4> - - LEND_WIFI_PHONE_MODE : <5> - - HEND_WIFI_PHONE_MODE : <6> - - ATA_PABX_WI2S_MODE : <7> - - ATA_PABX_I2S_MODE : <8> - - CAML_LCDW_MODE : <9> - - CAMU_LCD_MODE : <10> - - CAMU_WLCD_MODE : <11> - - CAML_LCD_MODE : <12> - - Its values for SPEAr320: - - AUTO_NET_SMII_MODE : <0> - - AUTO_NET_MII_MODE : <1> - - AUTO_EXP_MODE : <2> - - SMALL_PRINTERS_MODE : <3> - - EXTENDED_MODE : <4> - -Please refer to pinctrl-bindings.txt in this directory for details of the common -pinctrl bindings used by client devices. - -SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each -of these subnodes represents muxing for a pin, a group, or a list of pins or -groups. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Required subnode-properties: -- st,pins : An array of strings. Each string contains the name of a pin or - group. -- st,function: A string containing the name of the function to mux to the pin or - group. See the SPEAr's TRM to determine which are valid for each pin or group. - - Valid values for group and function names can be found from looking at the - group and function arrays in driver files: - drivers/pinctrl/spear/pinctrl-spear3*0.c - -Valid values for group names are: -For All SPEAr3xx machines: - "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp", - "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp", - "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp", - "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp" - -For SPEAr300 machines: - "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp", - "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp", - "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp", - "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" - -For SPEAr310 machines: - "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp", - "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp" - -For SPEAr320 machines: - "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp", - "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp", - "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp", - "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp", - "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp", - "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp", - "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp", - "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", - "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp", - "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp", - "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp", - "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp", - "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp", - "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp", - "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp", - "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp", - "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp", - "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp", - "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp", - "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp", - "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp", - "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp", - "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" - -Valid values for function names are: -For All SPEAr3xx machines: - "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext", - "uart0", "timer_0_1", "timer_2_3" - -For SPEAr300 machines: - "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1" - -For SPEAr310 machines: - "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0", - "rs485_1", "tdm" - -For SPEAr320 machines: - "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem", - "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen", - "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2", - "mii0_1", "i2c1", "i2c2" diff --git a/trunk/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/trunk/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt new file mode 100644 index 000000000000..36f82dbdd14d --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt @@ -0,0 +1,5 @@ +NVIDIA Tegra 2 pinmux controller + +Required properties: +- compatible : "nvidia,tegra20-pinmux" + diff --git a/trunk/Documentation/driver-model/devres.txt b/trunk/Documentation/driver-model/devres.txt index 950856bd2e39..2a596a4fc23e 100644 --- a/trunk/Documentation/driver-model/devres.txt +++ b/trunk/Documentation/driver-model/devres.txt @@ -276,11 +276,3 @@ REGULATOR devm_regulator_get() devm_regulator_put() devm_regulator_bulk_get() - -CLOCK - devm_clk_get() - devm_clk_put() - -PINCTRL - devm_pinctrl_get() - devm_pinctrl_put() diff --git a/trunk/Documentation/pinctrl.txt b/trunk/Documentation/pinctrl.txt index e40f4b4e1977..d97bccf46147 100644 --- a/trunk/Documentation/pinctrl.txt +++ b/trunk/Documentation/pinctrl.txt @@ -152,9 +152,11 @@ static const struct foo_group foo_groups[] = { }; -static int foo_get_groups_count(struct pinctrl_dev *pctldev) +static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(foo_groups); + if (selector >= ARRAY_SIZE(foo_groups)) + return -EINVAL; + return 0; } static const char *foo_get_group_name(struct pinctrl_dev *pctldev, @@ -173,7 +175,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, } static struct pinctrl_ops foo_pctrl_ops = { - .get_groups_count = foo_get_groups_count, + .list_groups = foo_list_groups, .get_group_name = foo_get_group_name, .get_group_pins = foo_get_group_pins, }; @@ -184,12 +186,13 @@ static struct pinctrl_desc foo_desc = { .pctlops = &foo_pctrl_ops, }; -The pin control subsystem will call the .get_groups_count() function to -determine total number of legal selectors, then it will call the other functions -to retrieve the name and pins of the group. Maintaining the data structure of -the groups is up to the driver, this is just a simple example - in practice you -may need more entries in your group structure, for example specific register -ranges associated with each group and so on. +The pin control subsystem will call the .list_groups() function repeatedly +beginning on 0 until it returns non-zero to determine legal selectors, then +it will call the other functions to retrieve the name and pins of the group. +Maintaining the data structure of the groups is up to the driver, this is +just a simple example - in practice you may need more entries in your group +structure, for example specific register ranges associated with each group +and so on. Pin configuration @@ -603,9 +606,11 @@ static const struct foo_group foo_groups[] = { }; -static int foo_get_groups_count(struct pinctrl_dev *pctldev) +static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(foo_groups); + if (selector >= ARRAY_SIZE(foo_groups)) + return -EINVAL; + return 0; } static const char *foo_get_group_name(struct pinctrl_dev *pctldev, @@ -624,7 +629,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, } static struct pinctrl_ops foo_pctrl_ops = { - .get_groups_count = foo_get_groups_count, + .list_groups = foo_list_groups, .get_group_name = foo_get_group_name, .get_group_pins = foo_get_group_pins, }; @@ -635,7 +640,7 @@ struct foo_pmx_func { const unsigned num_groups; }; -static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" }; +static const char * const spi0_groups[] = { "spi0_1_grp" }; static const char * const i2c0_groups[] = { "i2c0_grp" }; static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", "mmc0_3_grp" }; @@ -658,9 +663,11 @@ static const struct foo_pmx_func foo_functions[] = { }, }; -int foo_get_functions_count(struct pinctrl_dev *pctldev) +int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(foo_functions); + if (selector >= ARRAY_SIZE(foo_functions)) + return -EINVAL; + return 0; } const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) @@ -696,7 +703,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector, } struct pinmux_ops foo_pmxops = { - .get_functions_count = foo_get_functions_count, + .list_functions = foo_list_funcs, .get_function_name = foo_get_fname, .get_function_groups = foo_get_groups, .enable = foo_enable, @@ -779,7 +786,7 @@ and spi on the second function mapping: #include -static const struct pinctrl_map mapping[] __initconst = { +static const struct pinctrl_map __initdata mapping[] = { { .dev_name = "foo-spi.0", .name = PINCTRL_STATE_DEFAULT, @@ -945,13 +952,13 @@ case), we define a mapping like this: The result of grabbing this mapping from the device with something like this (see next paragraph): - p = devm_pinctrl_get(dev); + p = pinctrl_get(dev); s = pinctrl_lookup_state(p, "8bit"); ret = pinctrl_select_state(p, s); or more simply: - p = devm_pinctrl_get_select(dev, "8bit"); + p = pinctrl_get_select(dev, "8bit"); Will be that you activate all the three bottom records in the mapping at once. Since they share the same name, pin controller device, function and @@ -985,7 +992,7 @@ foo_probe() /* Allocate a state holder named "foo" etc */ struct foo_state *foo = ...; - foo->p = devm_pinctrl_get(&device); + foo->p = pinctrl_get(&device); if (IS_ERR(foo->p)) { /* FIXME: clean up "foo" here */ return PTR_ERR(foo->p); @@ -993,17 +1000,24 @@ foo_probe() foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT); if (IS_ERR(foo->s)) { + pinctrl_put(foo->p); /* FIXME: clean up "foo" here */ return PTR_ERR(s); } ret = pinctrl_select_state(foo->s); if (ret < 0) { + pinctrl_put(foo->p); /* FIXME: clean up "foo" here */ return ret; } } +foo_remove() +{ + pinctrl_put(state->p); +} + This get/lookup/select/put sequence can just as well be handled by bus drivers if you don't want each and every driver to handle it and you know the arrangement on your bus. @@ -1015,11 +1029,6 @@ The semantics of the pinctrl APIs are: kernel memory to hold the pinmux state. All mapping table parsing or similar slow operations take place within this API. -- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put() - to be called automatically on the retrieved pointer when the associated - device is removed. It is recommended to use this function over plain - pinctrl_get(). - - pinctrl_lookup_state() is called in process context to obtain a handle to a specific state for a the client device. This operation may be slow too. @@ -1032,30 +1041,14 @@ The semantics of the pinctrl APIs are: - pinctrl_put() frees all information associated with a pinctrl handle. -- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to - explicitly destroy a pinctrl object returned by devm_pinctrl_get(). - However, use of this function will be rare, due to the automatic cleanup - that will occur even without calling it. - - pinctrl_get() must be paired with a plain pinctrl_put(). - pinctrl_get() may not be paired with devm_pinctrl_put(). - devm_pinctrl_get() can optionally be paired with devm_pinctrl_put(). - devm_pinctrl_get() may not be paired with plain pinctrl_put(). - Usually the pin control core handled the get/put pair and call out to the device drivers bookkeeping operations, like checking available functions and the associated pins, whereas the enable/disable pass on to the pin controller driver which takes care of activating and/or deactivating the mux setting by quickly poking some registers. -The pins are allocated for your device when you issue the devm_pinctrl_get() -call, after this you should be able to see this in the debugfs listing of all -pins. - -NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the -requested pinctrl handles, for example if the pinctrl driver has not yet -registered. Thus make sure that the error path in your driver gracefully -cleans up and is ready to retry the probing later in the startup process. +The pins are allocated for your device when you issue the pinctrl_get() call, +after this you should be able to see this in the debugfs listing of all pins. System pin control hogging @@ -1101,13 +1094,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B: #include -struct pinctrl *p; -struct pinctrl_state *s1, *s2; - -foo_probe() +foo_switch() { + struct pinctrl *p; + struct pinctrl_state *s1, *s2; + /* Setup */ - p = devm_pinctrl_get(&device); + p = pinctrl_get(&device); if (IS_ERR(p)) ... @@ -1118,10 +1111,7 @@ foo_probe() s2 = pinctrl_lookup_state(foo->p, "pos-B"); if (IS_ERR(s2)) ... -} -foo_switch() -{ /* Enable on position A */ ret = pinctrl_select_state(s1); if (ret < 0) @@ -1135,6 +1125,8 @@ foo_switch() ... ... + + pinctrl_put(p); } The above has to be done from process context. diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 35d2339dbc0b..bb76fc42fc42 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -5235,14 +5235,6 @@ M: Linus Walleij S: Maintained F: drivers/pinctrl/ -PIN CONTROLLER - ST SPEAR -M: Viresh Kumar -L: spear-devel@list.st.com -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -W: http://www.st.com/spear -S: Maintained -F: driver/pinctrl/spear/ - PKTCDVD DRIVER M: Peter Osterlund S: Maintained @@ -6339,6 +6331,21 @@ F: arch/arm/mach-spear*/clock.c F: arch/arm/plat-spear/clock.c F: arch/arm/plat-spear/include/plat/clock.h +SPEAR PAD MULTIPLEXING SUPPORT +M: Viresh Kumar +L: spear-devel@list.st.com +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +W: http://www.st.com/spear +S: Maintained +F: arch/arm/plat-spear/include/plat/padmux.h +F: arch/arm/plat-spear/padmux.c +F: arch/arm/mach-spear*/spear*xx.c +F: arch/arm/mach-spear*/include/mach/generic.h +F: arch/arm/mach-spear3xx/spear3*0.c +F: arch/arm/mach-spear3xx/spear3*0_evb.c +F: arch/arm/mach-spear6xx/spear600.c +F: arch/arm/mach-spear6xx/spear600_evb.c + SPI SUBSYSTEM M: Grant Likely L: spi-devel-general@lists.sourceforge.net diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 10c9abdc8e04..c67494fc05a7 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -407,8 +407,6 @@ config ARCH_PRIMA2 select CLKDEV_LOOKUP select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 - select PINCTRL - select PINCTRL_SIRF select USE_OF select ZONE_DMA help @@ -949,7 +947,6 @@ config ARCH_NOMADIK select CPU_ARM926T select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS - select PINCTRL select MIGHT_HAVE_CACHE_L2X0 select ARCH_REQUIRE_GPIOLIB help diff --git a/trunk/arch/arm/boot/dts/spear300-evb.dts b/trunk/arch/arm/boot/dts/spear300-evb.dts deleted file mode 100644 index 402ca0d55011..000000000000 --- a/trunk/arch/arm/boot/dts/spear300-evb.dts +++ /dev/null @@ -1,221 +0,0 @@ -/* - * DTS file for SPEAr300 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear300.dtsi" - -/ { - model = "ST SPEAr300 Evaluation Board"; - compatible = "st,spear300-evb", "st,spear300"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@99000000 { - st,pinmux-mode = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - clcd { - st,pins = "clcd_pfmode_grp"; - st,function = "clcd"; - }; - sdhci { - st,pins = "sdhci_4bit_grp"; - st,function = "sdhci"; - }; - gpio1 { - st,pins = "gpio1_4_to_7_grp", - "gpio1_0_to_3_grp"; - st,function = "gpio1"; - }; - }; - }; - - clcd@60000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@94000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - int-gpio = <&gpio1 0 0>; - power-gpio = <&gpio1 2 1>; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio1: gpio@a9000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - kbd@a0000000 { - linux,keymap = < 0x00010000 - 0x00020100 - 0x00030200 - 0x00040300 - 0x00050400 - 0x00060500 - 0x00070600 - 0x00080700 - 0x00090800 - 0x000a0001 - 0x000c0101 - 0x000d0201 - 0x000e0301 - 0x000f0401 - 0x00100501 - 0x00110601 - 0x00120701 - 0x00130801 - 0x00140002 - 0x00150102 - 0x00160202 - 0x00170302 - 0x00180402 - 0x00190502 - 0x001a0602 - 0x001b0702 - 0x001c0802 - 0x001d0003 - 0x001e0103 - 0x001f0203 - 0x00200303 - 0x00210403 - 0x00220503 - 0x00230603 - 0x00240703 - 0x00250803 - 0x00260004 - 0x00270104 - 0x00280204 - 0x00290304 - 0x002a0404 - 0x002b0504 - 0x002c0604 - 0x002d0704 - 0x002e0804 - 0x002f0005 - 0x00300105 - 0x00310205 - 0x00320305 - 0x00330405 - 0x00340505 - 0x00350605 - 0x00360705 - 0x00370805 - 0x00380006 - 0x00390106 - 0x003a0206 - 0x003b0306 - 0x003c0406 - 0x003d0506 - 0x003e0606 - 0x003f0706 - 0x00400806 - 0x00410007 - 0x00420107 - 0x00430207 - 0x00440307 - 0x00450407 - 0x00460507 - 0x00470607 - 0x00480707 - 0x00490807 - 0x004a0008 - 0x004b0108 - 0x004c0208 - 0x004d0308 - 0x004e0408 - 0x004f0508 - 0x00500608 - 0x00510708 - 0x00520808 >; - autorepeat; - st,mode = <0>; - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear300.dtsi b/trunk/arch/arm/boot/dts/spear300.dtsi deleted file mode 100644 index 01c5e358fdb2..000000000000 --- a/trunk/arch/arm/boot/dts/spear300.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* - * DTS file for SPEAr300 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x60000000 0x60000000 0x50000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux@99000000 { - compatible = "st,spear300-pinmux"; - reg = <0x99000000 0x1000>; - }; - - clcd@60000000 { - compatible = "arm,clcd-pl110", "arm,primecell"; - reg = <0x60000000 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - - fsmc: flash@94000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x94000000 0x1000 /* FSMC Register */ - 0x80000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <1>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - gpio1: gpio@a9000000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xa9000000 0x1000>; - status = "disabled"; - }; - - kbd@a0000000 { - compatible = "st,spear300-kbd"; - reg = <0xa0000000 0x1000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear310-evb.dts b/trunk/arch/arm/boot/dts/spear310-evb.dts deleted file mode 100644 index 6d95317100ad..000000000000 --- a/trunk/arch/arm/boot/dts/spear310-evb.dts +++ /dev/null @@ -1,172 +0,0 @@ -/* - * DTS file for SPEAr310 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear310.dtsi" - -/ { - model = "ST SPEAr310 Evaluation Board"; - compatible = "st,spear310-evb", "st,spear310"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b4000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - gpio0 { - st,pins = "gpio0_pin0_grp", - "gpio0_pin1_grp", - "gpio0_pin2_grp", - "gpio0_pin3_grp", - "gpio0_pin4_grp", - "gpio0_pin5_grp"; - st,function = "gpio0"; - }; - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - emi { - st,pins = "emi_cs_0_to_5_grp"; - st,function = "emi"; - }; - fsmc { - st,pins = "fsmc_grp"; - st,function = "fsmc"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - uart3 { - st,pins = "uart3_grp"; - st,function = "uart3"; - }; - uart4 { - st,pins = "uart4_grp"; - st,function = "uart4"; - }; - uart5 { - st,pins = "uart5_grp"; - st,function = "uart5"; - }; - }; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@44000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - label = "m25p64"; - reg = <0xf8000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - st,smi-fast-mode; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - }; - - serial@b2000000 { - status = "okay"; - }; - - serial@b2080000 { - status = "okay"; - }; - - serial@b2100000 { - status = "okay"; - }; - - serial@b2180000 { - status = "okay"; - }; - - serial@b2200000 { - status = "okay"; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear310.dtsi b/trunk/arch/arm/boot/dts/spear310.dtsi deleted file mode 100644 index e47081c494d9..000000000000 --- a/trunk/arch/arm/boot/dts/spear310.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -/* - * DTS file for SPEAr310 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux@b4000000 { - compatible = "st,spear310-pinmux"; - reg = <0xb4000000 0x1000>; - }; - - fsmc: flash@44000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x44000000 0x1000 /* FSMC Register */ - 0x40000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x10000>; - st,cle-off = <0x20000>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - serial@b2000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2000000 0x1000>; - status = "disabled"; - }; - - serial@b2080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2080000 0x1000>; - status = "disabled"; - }; - - serial@b2100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2100000 0x1000>; - status = "disabled"; - }; - - serial@b2180000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2180000 0x1000>; - status = "disabled"; - }; - - serial@b2200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2200000 0x1000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear320-evb.dts b/trunk/arch/arm/boot/dts/spear320-evb.dts deleted file mode 100644 index 0c6463b71a37..000000000000 --- a/trunk/arch/arm/boot/dts/spear320-evb.dts +++ /dev/null @@ -1,173 +0,0 @@ -/* - * DTS file for SPEAr320 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear320.dtsi" - -/ { - model = "ST SPEAr300 Evaluation Board"; - compatible = "st,spear300-evb", "st,spear300"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b3000000 { - st,pinmux-mode = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - sdhci { - st,pins = "sdhci_cd_51_grp"; - st,function = "sdhci"; - }; - i2s { - st,pins = "i2s_grp"; - st,function = "i2s"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - can0 { - st,pins = "can0_grp"; - st,function = "can0"; - }; - can1 { - st,pins = "can1_grp"; - st,function = "can1"; - }; - mii2 { - st,pins = "mii2_grp"; - st,function = "mii2"; - }; - pwm0_1 { - st,pins = "pwm0_1_pin_14_15_grp"; - st,function = "pwm0_1"; - }; - pwm2 { - st,pins = "pwm2_pin_13_grp"; - st,function = "pwm2"; - }; - }; - }; - - clcd@90000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@4c000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - power-gpio = <&gpio0 2 1>; - power_always_enb; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - spi1: spi@a5000000 { - status = "okay"; - }; - - spi2: spi@a6000000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - i2c1: i2c@a7000000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - }; - - serial@a3000000 { - status = "okay"; - }; - - serial@a4000000 { - status = "okay"; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear320.dtsi b/trunk/arch/arm/boot/dts/spear320.dtsi deleted file mode 100644 index 5372ca399b1f..000000000000 --- a/trunk/arch/arm/boot/dts/spear320.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -/* - * DTS file for SPEAr320 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x80000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux@b3000000 { - compatible = "st,spear320-pinmux"; - reg = <0xb3000000 0x1000>; - }; - - clcd@90000000 { - compatible = "arm,clcd-pl110", "arm,primecell"; - reg = <0x90000000 0x1000>; - interrupts = <33>; - status = "disabled"; - }; - - fsmc: flash@4c000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4c000000 0x1000 /* FSMC Register */ - 0x50000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <29>; - status = "disabled"; - }; - - spi1: spi@a5000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa5000000 0x1000>; - status = "disabled"; - }; - - spi2: spi@a6000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa6000000 0x1000>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - i2c1: i2c@a7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xa7000000 0x1000>; - status = "disabled"; - }; - - serial@a3000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa3000000 0x1000>; - status = "disabled"; - }; - - serial@a4000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa4000000 0x1000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear3xx.dtsi b/trunk/arch/arm/boot/dts/spear3xx.dtsi deleted file mode 100644 index 0ae7c8e86311..000000000000 --- a/trunk/arch/arm/boot/dts/spear3xx.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * DTS file for all SPEAr3xx SoCs - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "skeleton.dtsi" - -/ { - interrupt-parent = <&vic>; - - cpus { - cpu@0 { - compatible = "arm,arm926ejs"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - vic: interrupt-controller@f1100000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1100000 0x1000>; - #interrupt-cells = <1>; - }; - - dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <8>; - status = "disabled"; - }; - - gmac: eth@e0800000 { - compatible = "st,spear600-gmac"; - reg = <0xe0800000 0x8000>; - interrupts = <23 22>; - interrupt-names = "macirq", "eth_wake_irq"; - status = "disabled"; - }; - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupts = <9>; - status = "disabled"; - }; - - spi0: spi@d0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xd0100000 0x1000>; - interrupts = <20>; - status = "disabled"; - }; - - ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupts = <26>; - status = "disabled"; - }; - - ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1900000 0x1000>; - interrupts = <25>; - status = "disabled"; - }; - - ohci@e2100000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe2100000 0x1000>; - interrupts = <27>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - gpio0: gpio@fc980000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xfc980000 0x1000>; - interrupts = <11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - i2c0: i2c@d0180000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xd0180000 0x1000>; - interrupts = <21>; - status = "disabled"; - }; - - rtc@fc900000 { - compatible = "st,spear-rtc"; - reg = <0xfc900000 0x1000>; - interrupts = <10>; - status = "disabled"; - }; - - serial@d0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0000000 0x1000>; - interrupts = <19>; - status = "disabled"; - }; - - wdt@fc880000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0xfc880000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear600-evb.dts b/trunk/arch/arm/boot/dts/spear600-evb.dts index 790a7a8a5ccd..636292e18c90 100644 --- a/trunk/arch/arm/boot/dts/spear600-evb.dts +++ b/trunk/arch/arm/boot/dts/spear600-evb.dts @@ -24,10 +24,6 @@ }; ahb { - dma@fc400000 { - status = "okay"; - }; - gmac: ethernet@e0800000 { phy-mode = "gmii"; status = "okay"; diff --git a/trunk/arch/arm/boot/dts/spear600.dtsi b/trunk/arch/arm/boot/dts/spear600.dtsi index d777e3a6f178..ebe0885a2b98 100644 --- a/trunk/arch/arm/boot/dts/spear600.dtsi +++ b/trunk/arch/arm/boot/dts/spear600.dtsi @@ -45,14 +45,6 @@ #interrupt-cells = <1>; }; - dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - status = "disabled"; - }; - gmac: ethernet@e0800000 { compatible = "st,spear600-gmac"; reg = <0xe0800000 0x8000>; diff --git a/trunk/arch/arm/boot/dts/tegra-cardhu.dts b/trunk/arch/arm/boot/dts/tegra-cardhu.dts index 0a9f34a2c3aa..ac3fb7558459 100644 --- a/trunk/arch/arm/boot/dts/tegra-cardhu.dts +++ b/trunk/arch/arm/boot/dts/tegra-cardhu.dts @@ -10,50 +10,6 @@ reg = < 0x80000000 0x40000000 >; }; - pinmux@70000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - }; - }; - serial@70006000 { clock-frequency = < 408000000 >; }; diff --git a/trunk/arch/arm/boot/dts/tegra-harmony.dts b/trunk/arch/arm/boot/dts/tegra-harmony.dts index 1a0b1f182944..6e8447dc0202 100644 --- a/trunk/arch/arm/boot/dts/tegra-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra-harmony.dts @@ -10,230 +10,6 @@ reg = < 0x00000000 0x40000000 >; }; - pinmux@70000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", - "spia", "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtd"; - nvidia,function = "sdio2"; - }; - dtb { - nvidia,pins = "dtb", "dtc", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "dap1", "dtb", "gma", "gmb", - "gmc", "gmd", "gme", "gpu7", "gpv", - "i2cp", "pta", "rm", "slxa", "slxk", - "spia", "spib"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - conf_cdev2 { - nvidia,pins = "cdev2", "csus", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; - }; - conf_crtp { - nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "dtf", "gpu", "sdio1", - "slxc", "slxd", "spdi", "spdo", "spig", - "uac", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - }; - conf_ddc { - nvidia,pins = "ddc", "dta", "dtd", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "sdc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "owc", "sdb"; - nvidia,tristate = <1>; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "sdd", "spic", - "spie", "spih", "uaa", "uab", "uad", - "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc"; - nvidia,tristate = <0>; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = <1>; - }; - }; - }; - pmc@7000f400 { nvidia,invert-interrupt; }; diff --git a/trunk/arch/arm/boot/dts/tegra-paz00.dts b/trunk/arch/arm/boot/dts/tegra-paz00.dts index 10943fb2561c..6c02abb469d4 100644 --- a/trunk/arch/arm/boot/dts/tegra-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra-paz00.dts @@ -10,226 +10,6 @@ reg = <0x00000000 0x20000000>; }; - pinmux@70000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap2", "gmb", "gmc", "gmd", "spia", - "spib", "spic", "spid", "spie"; - nvidia,function = "gmi"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "pllc_out1"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gpu { - nvidia,pins = "gpu", "sdb", "sdd"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - kbcb { - nvidia,pins = "kbcb", "kbcd"; - nvidia,function = "sdio2"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc"; - nvidia,function = "owr"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdc { - nvidia,pins = "sdc"; - nvidia,function = "twc"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spi4"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "rsvd2"; - }; - spif { - nvidia,pins = "spif", "uac"; - nvidia,function = "rsvd4"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "spdif"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "dap1", "dap2", "dtf", "gma", - "gmb", "gmc", "gmd", "gme", "gpu", - "gpu7", "gpv", "i2cp", "pta", "rm", - "sdio1", "slxk", "spdo", "uac", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - conf_cdev2 { - nvidia,pins = "cdev2"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; - }; - conf_crtp { - nvidia,pins = "crtp", "dap3", "dap4", "dtb", - "dtc", "dte", "slxa", "slxc", "slxd", - "spdi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - }; - conf_csus { - nvidia,pins = "csus", "spia", "spib", "spid", - "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - }; - conf_ddc { - nvidia,pins = "ddc", "irrx", "irtx", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "spic", "spig", "uaa", "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - conf_dta { - nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", - "spie", "spih", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; - }; - conf_hdint { - nvidia,pins = "hdint", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhs", "lsc0", "lspi", - "lvs", "pmc"; - nvidia,tristate = <0>; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; - }; - conf_lcsn { - nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", - "lm0", "lm1", "lpp", "lpw0", "lpw1", - "lpw2", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "lvp1", "sdb"; - nvidia,tristate = <1>; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = <1>; - }; - }; - }; - i2c@7000c000 { clock-frequency = <400000>; diff --git a/trunk/arch/arm/boot/dts/tegra-seaboard.dts b/trunk/arch/arm/boot/dts/tegra-seaboard.dts index ec33116f5df9..dbf1c5a171c2 100644 --- a/trunk/arch/arm/boot/dts/tegra-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra-seaboard.dts @@ -11,249 +11,6 @@ reg = < 0x00000000 0x40000000 >; }; - pinmux@70000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc", "owc", "spdi", "spdo", - "uac"; - nvidia,function = "rsvd2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", - "lsck", "lsda", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lsc0", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap2", - "dap4", "dtf", "gma", "gmc", "gmd", - "gme", "gpu", "gpu7", "i2cp", "irrx", - "irtx", "pta", "rm", "sdc", "sdd", - "slxd", "slxk", "spdi", "spdo", "uac", - "uad", "uca", "ucb", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - conf_ate { - nvidia,pins = "ate", "csus", "dap3", "ddc", - "gpv", "owc", "slxc", "spib", "spid", - "spie"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spia", - "spig", "spih"; - nvidia,pull = <2>; - nvidia,tristate = <1>; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - }; - conf_dte { - nvidia,pins = "dte", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0"; - nvidia,tristate = <1>; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "spic", "uaa", - "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc", "sdb"; - nvidia,tristate = <0>; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = <1>; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = <3>; - nvidia,slew-rate-falling = <3>; - }; - }; - }; - i2c@7000c000 { clock-frequency = <400000>; diff --git a/trunk/arch/arm/boot/dts/tegra-trimslice.dts b/trunk/arch/arm/boot/dts/tegra-trimslice.dts index 98efd5b0d7f9..252476867b54 100644 --- a/trunk/arch/arm/boot/dts/tegra-trimslice.dts +++ b/trunk/arch/arm/boot/dts/tegra-trimslice.dts @@ -10,236 +10,6 @@ reg = < 0x00000000 0x40000000 >; }; - pinmux@70000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc", "gmb"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gme", "pta"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc", "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "uarta"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "sdio3"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "spdif"; - }; - spia { - nvidia,pins = "spia", "spib", "spic"; - nvidia,function = "spi2"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "crtp", "dap2", "dap3", "dap4", "dta", - "dtb", "dtc", "dtd", "dte", "gmb", - "gme", "i2cp", "pta", "slxc", "slxd", - "spdi", "spdo", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - }; - conf_atb { - nvidia,pins = "atb", "cdev1", "dap1", "gma", - "gmc", "gmd", "gpu", "gpu7", "gpv", - "sdio1", "slxa", "slxk", "uac"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - conf_cdev2 { - nvidia,pins = "cdev2", "csus", "spia", "spib", - "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; - }; - conf_ddc { - nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "pmc"; - nvidia,tristate = <1>; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "kbca", "kbcb", - "kbcc", "kbcd", "kbce", "kbcf", "owc", - "spic", "spie", "spig", "spih", "uaa", - "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "sdb"; - nvidia,tristate = <0>; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = <1>; - }; - }; - }; - i2c@7000c000 { clock-frequency = <400000>; }; diff --git a/trunk/arch/arm/boot/dts/tegra-ventana.dts b/trunk/arch/arm/boot/dts/tegra-ventana.dts index 71eb2e50a668..2dcff8728e90 100644 --- a/trunk/arch/arm/boot/dts/tegra-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra-ventana.dts @@ -10,236 +10,6 @@ reg = < 0x00000000 0x40000000 >; }; - pinmux@70000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc", "owc", "spdi", "spdo", - "uac"; - nvidia,function = "rsvd2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lpw0", - "lpw2", "lsc0", "lsc1", "lsck", "lsda", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxc"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxd { - nvidia,pins = "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap2", - "dap4", "ddc", "dtf", "gma", "gmc", - "gme", "gpu", "gpu7", "i2cp", "irrx", - "irtx", "pta", "rm", "sdc", "sdd", - "slxc", "slxd", "slxk", "spdi", "spdo", - "uac", "uad", "uca", "ucb", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - conf_ate { - nvidia,pins = "ate", "csus", "dap3", "gmd", - "gpv", "owc", "spia", "spib", "spic", - "spid", "spie", "spig"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spih"; - nvidia,pull = <2>; - nvidia,tristate = <1>; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - }; - conf_dte { - nvidia,pins = "dte", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = <1>; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "uaa", "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lsc1", "lspi", - "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = <0>; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = <1>; - }; - }; - }; - i2c@7000c000 { clock-frequency = <400000>; diff --git a/trunk/arch/arm/configs/nhk8815_defconfig b/trunk/arch/arm/configs/nhk8815_defconfig index bf123c5384d4..37207d1bf44b 100644 --- a/trunk/arch/arm/configs/nhk8815_defconfig +++ b/trunk/arch/arm/configs/nhk8815_defconfig @@ -97,7 +97,6 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y CONFIG_DEBUG_GPIO=y -CONFIG_PINCTRL_NOMADIK=y # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set CONFIG_RTC_CLASS=y diff --git a/trunk/arch/arm/configs/spear3xx_defconfig b/trunk/arch/arm/configs/spear3xx_defconfig index 7ed42912d69a..fea7e1f026a3 100644 --- a/trunk/arch/arm/configs/spear3xx_defconfig +++ b/trunk/arch/arm/configs/spear3xx_defconfig @@ -2,67 +2,33 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_PARTITION_ADVANCED=y CONFIG_PLAT_SPEAR=y -CONFIG_MACH_SPEAR300=y -CONFIG_MACH_SPEAR310=y -CONFIG_MACH_SPEAR320=y +CONFIG_BOARD_SPEAR300_EVB=y +CONFIG_BOARD_SPEAR310_EVB=y +CONFIG_BOARD_SPEAR320_EVB=y CONFIG_BINFMT_MISC=y -CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -CONFIG_STMMAC_ETH=y -# CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_SPEAR=y +# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set -# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y CONFIG_MAX_RAW_DEVS=8192 -CONFIG_I2C=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_SPI=y -CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_FB=y -CONFIG_FB_ARMCLCD=y # CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SPEAR=y -CONFIG_RTC_CLASS=y -CONFIG_DMADEVICES=y -CONFIG_AMBA_PL08X=y -CONFIG_DMATEST=m +# CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_SECURITY=y @@ -73,6 +39,8 @@ CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m @@ -80,4 +48,6 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y +# CONFIG_CRC32 is not set diff --git a/trunk/arch/arm/configs/spear6xx_defconfig b/trunk/arch/arm/configs/spear6xx_defconfig index cf94bc73a0e0..cef2e836afd2 100644 --- a/trunk/arch/arm/configs/spear6xx_defconfig +++ b/trunk/arch/arm/configs/spear6xx_defconfig @@ -2,58 +2,29 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_PARTITION_ADVANCED=y CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y -CONFIG_BOARD_SPEAR600_DT=y +CONFIG_BOARD_SPEAR600_EVB=y CONFIG_BINFMT_MISC=y -CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -CONFIG_STMMAC_ETH=y -# CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set CONFIG_RAW_DRIVER=y CONFIG_MAX_RAW_DEVS=8192 -CONFIG_I2C=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_SPI=y -CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_ARM_SP805_WATCHDOG=y # CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_DMADEVICES=y -CONFIG_AMBA_PL08X=y -CONFIG_DMATEST=m +# CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_SECURITY=y @@ -64,6 +35,8 @@ CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m @@ -71,4 +44,6 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y +# CONFIG_CRC32 is not set diff --git a/trunk/arch/arm/mach-nomadik/Kconfig b/trunk/arch/arm/mach-nomadik/Kconfig index 365879b47c0e..3c5e0f522e9c 100644 --- a/trunk/arch/arm/mach-nomadik/Kconfig +++ b/trunk/arch/arm/mach-nomadik/Kconfig @@ -15,7 +15,6 @@ config NOMADIK_8815 config I2C_BITBANG_8815NHK tristate "Driver for bit-bang busses found on the 8815 NHK" depends on I2C && MACH_NOMADIK_8815NHK - depends on PINCTRL_NOMADIK select I2C_ALGOBIT default y diff --git a/trunk/arch/arm/mach-spear3xx/Kconfig b/trunk/arch/arm/mach-spear3xx/Kconfig index 8bd37291fa4f..2cee6b0de371 100644 --- a/trunk/arch/arm/mach-spear3xx/Kconfig +++ b/trunk/arch/arm/mach-spear3xx/Kconfig @@ -5,22 +5,39 @@ if ARCH_SPEAR3XX menu "SPEAr3xx Implementations" +config BOARD_SPEAR300_EVB + bool "SPEAr300 Evaluation Board" + select MACH_SPEAR300 + help + Supports ST SPEAr300 Evaluation Board + +config BOARD_SPEAR310_EVB + bool "SPEAr310 Evaluation Board" + select MACH_SPEAR310 + help + Supports ST SPEAr310 Evaluation Board + +config BOARD_SPEAR320_EVB + bool "SPEAr320 Evaluation Board" + select MACH_SPEAR320 + help + Supports ST SPEAr320 Evaluation Board + +endmenu + config MACH_SPEAR300 - bool "SPEAr300 Machine support with Device Tree" - select PINCTRL_SPEAR300 + bool "SPEAr300" help - Supports ST SPEAr300 machine configured via the device-tree + Supports ST SPEAr300 Machine config MACH_SPEAR310 - bool "SPEAr310 Machine support with Device Tree" - select PINCTRL_SPEAR310 + bool "SPEAr310" help - Supports ST SPEAr310 machine configured via the device-tree + Supports ST SPEAr310 Machine config MACH_SPEAR320 - bool "SPEAr320 Machine support with Device Tree" - select PINCTRL_SPEAR320 + bool "SPEAr320" help - Supports ST SPEAr320 machine configured via the device-tree -endmenu + Supports ST SPEAr320 Machine + endif #ARCH_SPEAR3XX diff --git a/trunk/arch/arm/mach-spear3xx/Makefile b/trunk/arch/arm/mach-spear3xx/Makefile index 17b5d83cf2d5..b24862489704 100644 --- a/trunk/arch/arm/mach-spear3xx/Makefile +++ b/trunk/arch/arm/mach-spear3xx/Makefile @@ -3,13 +3,24 @@ # # common files -obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o clock.o +obj-y += spear3xx.o clock.o # spear300 specific files obj-$(CONFIG_MACH_SPEAR300) += spear300.o +# spear300 boards files +obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o + + # spear310 specific files obj-$(CONFIG_MACH_SPEAR310) += spear310.o +# spear310 boards files +obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o + + # spear320 specific files obj-$(CONFIG_MACH_SPEAR320) += spear320.o + +# spear320 boards files +obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o diff --git a/trunk/arch/arm/mach-spear3xx/Makefile.boot b/trunk/arch/arm/mach-spear3xx/Makefile.boot index d93e2177e6ec..4674a4c221db 100644 --- a/trunk/arch/arm/mach-spear3xx/Makefile.boot +++ b/trunk/arch/arm/mach-spear3xx/Makefile.boot @@ -1,7 +1,3 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 - -dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb -dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb -dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb diff --git a/trunk/arch/arm/mach-spear3xx/clock.c b/trunk/arch/arm/mach-spear3xx/clock.c index eeafe38eab25..6c4841f55223 100644 --- a/trunk/arch/arm/mach-spear3xx/clock.c +++ b/trunk/arch/arm/mach-spear3xx/clock.c @@ -11,11 +11,9 @@ * warranty of any kind, whether express or implied. */ -#include #include #include #include -#include #include #include #include @@ -413,21 +411,6 @@ static struct clk usbd_clk = { .recalc = &follow_parent, }; -/* clock derived from usbh clk */ -/* usbh0 clock */ -static struct clk usbh0_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &usbh_clk, - .recalc = &follow_parent, -}; - -/* usbh1 clock */ -static struct clk usbh1_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &usbh_clk, - .recalc = &follow_parent, -}; - /* clock derived from ahb clk */ /* apb masks structure */ static struct bus_clk_masks apb_masks = { @@ -669,126 +652,109 @@ static struct clk pwm_clk = { /* array of all spear 3xx clock lookups */ static struct clk_lookup spear_clk_lookups[] = { - CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk), + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, /* root clks */ - CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk), - CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk), + { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, + { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, /* clock derived from 32 KHz osc clk */ - CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk), + { .dev_id = "rtc-spear", .clk = &rtc_clk}, /* clock derived from 24 MHz osc clk */ - CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk), - CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk), - CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk), + { .con_id = "pll1_clk", .clk = &pll1_clk}, + { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, + { .dev_id = "wdt", .clk = &wdt_clk}, /* clock derived from pll1 clk */ - CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk), - CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk), - CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk), - CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk), - CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk), - CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk), - CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk), - CLKDEV_INIT("d0000000.serial", NULL, &uart_clk), - CLKDEV_INIT("firda", NULL, &firda_clk), - CLKDEV_INIT("gpt0", NULL, &gpt0_clk), - CLKDEV_INIT("gpt1", NULL, &gpt1_clk), - CLKDEV_INIT("gpt2", NULL, &gpt2_clk), + { .con_id = "cpu_clk", .clk = &cpu_clk}, + { .con_id = "ahb_clk", .clk = &ahb_clk}, + { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, + { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, + { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, + { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk}, + { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, + { .dev_id = "uart", .clk = &uart_clk}, + { .dev_id = "firda", .clk = &firda_clk}, + { .dev_id = "gpt0", .clk = &gpt0_clk}, + { .dev_id = "gpt1", .clk = &gpt1_clk}, + { .dev_id = "gpt2", .clk = &gpt2_clk}, /* clock derived from pll3 clk */ - CLKDEV_INIT("designware_udc", NULL, &usbd_clk), - CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk), - /* clock derived from usbh clk */ - CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk), - CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk), + { .dev_id = "designware_udc", .clk = &usbd_clk}, + { .con_id = "usbh_clk", .clk = &usbh_clk}, /* clock derived from ahb clk */ - CLKDEV_INIT(NULL, "apb_clk", &apb_clk), - CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk), - CLKDEV_INIT("fc400000.dma", NULL, &dma_clk), - CLKDEV_INIT("jpeg", NULL, &jpeg_clk), - CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk), - CLKDEV_INIT("fc000000.flash", NULL, &smi_clk), - CLKDEV_INIT("c3", NULL, &c3_clk), + { .con_id = "apb_clk", .clk = &apb_clk}, + { .dev_id = "i2c_designware.0", .clk = &i2c_clk}, + { .dev_id = "dma", .clk = &dma_clk}, + { .dev_id = "jpeg", .clk = &jpeg_clk}, + { .dev_id = "gmac", .clk = &gmac_clk}, + { .dev_id = "smi", .clk = &smi_clk}, + { .dev_id = "c3", .clk = &c3_clk}, /* clock derived from apb clk */ - CLKDEV_INIT("adc", NULL, &adc_clk), - CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk), - CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk), + { .dev_id = "adc", .clk = &adc_clk}, + { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, + { .dev_id = "gpio", .clk = &gpio_clk}, }; /* array of all spear 300 clock lookups */ #ifdef CONFIG_MACH_SPEAR300 static struct clk_lookup spear300_clk_lookups[] = { - CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk), - CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk), - CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk), - CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk), - CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk), + { .dev_id = "clcd", .clk = &clcd_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .dev_id = "gpio1", .clk = &gpio1_clk}, + { .dev_id = "keyboard", .clk = &kbd_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, }; - -void __init spear300_clk_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) - clk_register(&spear_clk_lookups[i]); - - for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++) - clk_register(&spear300_clk_lookups[i]); - - clk_init(); -} #endif /* array of all spear 310 clock lookups */ #ifdef CONFIG_MACH_SPEAR310 static struct clk_lookup spear310_clk_lookups[] = { - CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk), - CLKDEV_INIT(NULL, "emi", &emi_clk), - CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk), - CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk), - CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk), - CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk), - CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk), + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .con_id = "emi", .clk = &emi_clk}, + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, + { .dev_id = "uart3", .clk = &uart3_clk}, + { .dev_id = "uart4", .clk = &uart4_clk}, + { .dev_id = "uart5", .clk = &uart5_clk}, }; - -void __init spear310_clk_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) - clk_register(&spear_clk_lookups[i]); - - for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++) - clk_register(&spear310_clk_lookups[i]); - - clk_init(); -} #endif /* array of all spear 320 clock lookups */ #ifdef CONFIG_MACH_SPEAR320 static struct clk_lookup spear320_clk_lookups[] = { - CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk), - CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk), - CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk), - CLKDEV_INIT(NULL, "emi", &emi_clk), - CLKDEV_INIT("pwm", NULL, &pwm_clk), - CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk), - CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk), - CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk), - CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk), - CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk), - CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk), - CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk), -}; - -void __init spear320_clk_init(void) + { .dev_id = "clcd", .clk = &clcd_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, + { .con_id = "emi", .clk = &emi_clk}, + { .dev_id = "pwm", .clk = &pwm_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, + { .dev_id = "c_can_platform.0", .clk = &can0_clk}, + { .dev_id = "c_can_platform.1", .clk = &can1_clk}, + { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, + { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, +}; +#endif + +void __init spear3xx_clk_init(void) { - int i; + int i, cnt; + struct clk_lookup *lookups; + + if (machine_is_spear300()) { + cnt = ARRAY_SIZE(spear300_clk_lookups); + lookups = spear300_clk_lookups; + } else if (machine_is_spear310()) { + cnt = ARRAY_SIZE(spear310_clk_lookups); + lookups = spear310_clk_lookups; + } else { + cnt = ARRAY_SIZE(spear320_clk_lookups); + lookups = spear320_clk_lookups; + } for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) clk_register(&spear_clk_lookups[i]); - for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++) - clk_register(&spear320_clk_lookups[i]); + for (i = 0; i < cnt; i++) + clk_register(&lookups[i]); clk_init(); } -#endif diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/generic.h b/trunk/arch/arm/mach-spear3xx/include/mach/generic.h index 9603bf4d5119..14276e5a98d2 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/generic.h @@ -14,12 +14,12 @@ #ifndef __MACH_GENERIC_H #define __MACH_GENERIC_H -#include #include #include #include #include #include +#include /* spear3xx declarations */ /* @@ -31,32 +31,171 @@ #define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 /* Add spear3xx family device structure declarations here */ +extern struct amba_device spear3xx_gpio_device; +extern struct amba_device spear3xx_uart_device; extern struct sys_timer spear3xx_timer; -extern struct pl022_ssp_controller pl022_plat_data; -extern struct pl08x_platform_data pl080_plat_data; /* Add spear3xx family function declarations here */ +void __init spear3xx_clk_init(void); void __init spear_setup_timer(void); void __init spear3xx_map_io(void); -void __init spear3xx_dt_init_irq(void); +void __init spear3xx_init_irq(void); +void __init spear3xx_init(void); void spear_restart(char, const char *); +/* pad mux declarations */ +#define PMX_FIRDA_MASK (1 << 14) +#define PMX_I2C_MASK (1 << 13) +#define PMX_SSP_CS_MASK (1 << 12) +#define PMX_SSP_MASK (1 << 11) +#define PMX_MII_MASK (1 << 10) +#define PMX_GPIO_PIN0_MASK (1 << 9) +#define PMX_GPIO_PIN1_MASK (1 << 8) +#define PMX_GPIO_PIN2_MASK (1 << 7) +#define PMX_GPIO_PIN3_MASK (1 << 6) +#define PMX_GPIO_PIN4_MASK (1 << 5) +#define PMX_GPIO_PIN5_MASK (1 << 4) +#define PMX_UART0_MODEM_MASK (1 << 3) +#define PMX_UART0_MASK (1 << 2) +#define PMX_TIMER_3_4_MASK (1 << 1) +#define PMX_TIMER_1_2_MASK (1 << 0) + +/* pad mux devices */ +extern struct pmx_dev spear3xx_pmx_firda; +extern struct pmx_dev spear3xx_pmx_i2c; +extern struct pmx_dev spear3xx_pmx_ssp_cs; +extern struct pmx_dev spear3xx_pmx_ssp; +extern struct pmx_dev spear3xx_pmx_mii; +extern struct pmx_dev spear3xx_pmx_gpio_pin0; +extern struct pmx_dev spear3xx_pmx_gpio_pin1; +extern struct pmx_dev spear3xx_pmx_gpio_pin2; +extern struct pmx_dev spear3xx_pmx_gpio_pin3; +extern struct pmx_dev spear3xx_pmx_gpio_pin4; +extern struct pmx_dev spear3xx_pmx_gpio_pin5; +extern struct pmx_dev spear3xx_pmx_uart0_modem; +extern struct pmx_dev spear3xx_pmx_uart0; +extern struct pmx_dev spear3xx_pmx_timer_3_4; +extern struct pmx_dev spear3xx_pmx_timer_1_2; + +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* padmux plgpio devices */ +extern struct pmx_dev spear3xx_pmx_plgpio_0_1; +extern struct pmx_dev spear3xx_pmx_plgpio_2_3; +extern struct pmx_dev spear3xx_pmx_plgpio_4_5; +extern struct pmx_dev spear3xx_pmx_plgpio_6_9; +extern struct pmx_dev spear3xx_pmx_plgpio_10_27; +extern struct pmx_dev spear3xx_pmx_plgpio_28; +extern struct pmx_dev spear3xx_pmx_plgpio_29; +extern struct pmx_dev spear3xx_pmx_plgpio_30; +extern struct pmx_dev spear3xx_pmx_plgpio_31; +extern struct pmx_dev spear3xx_pmx_plgpio_32; +extern struct pmx_dev spear3xx_pmx_plgpio_33; +extern struct pmx_dev spear3xx_pmx_plgpio_34_36; +extern struct pmx_dev spear3xx_pmx_plgpio_37_42; +extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48; +extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50; +#endif + /* spear300 declarations */ #ifdef CONFIG_MACH_SPEAR300 -void __init spear300_clk_init(void); +/* Add spear300 machine device structure declarations here */ +extern struct amba_device spear300_gpio1_device; + +/* pad mux modes */ +extern struct pmx_mode spear300_nand_mode; +extern struct pmx_mode spear300_nor_mode; +extern struct pmx_mode spear300_photo_frame_mode; +extern struct pmx_mode spear300_lend_ip_phone_mode; +extern struct pmx_mode spear300_hend_ip_phone_mode; +extern struct pmx_mode spear300_lend_wifi_phone_mode; +extern struct pmx_mode spear300_hend_wifi_phone_mode; +extern struct pmx_mode spear300_ata_pabx_wi2s_mode; +extern struct pmx_mode spear300_ata_pabx_i2s_mode; +extern struct pmx_mode spear300_caml_lcdw_mode; +extern struct pmx_mode spear300_camu_lcd_mode; +extern struct pmx_mode spear300_camu_wlcd_mode; +extern struct pmx_mode spear300_caml_lcd_mode; + +/* pad mux devices */ +extern struct pmx_dev spear300_pmx_fsmc_2_chips; +extern struct pmx_dev spear300_pmx_fsmc_4_chips; +extern struct pmx_dev spear300_pmx_keyboard; +extern struct pmx_dev spear300_pmx_clcd; +extern struct pmx_dev spear300_pmx_telecom_gpio; +extern struct pmx_dev spear300_pmx_telecom_tdm; +extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk; +extern struct pmx_dev spear300_pmx_telecom_camera; +extern struct pmx_dev spear300_pmx_telecom_dac; +extern struct pmx_dev spear300_pmx_telecom_i2s; +extern struct pmx_dev spear300_pmx_telecom_boot_pins; +extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit; +extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit; +extern struct pmx_dev spear300_pmx_gpio1; + +/* Add spear300 machine function declarations here */ +void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR300 */ /* spear310 declarations */ #ifdef CONFIG_MACH_SPEAR310 -void __init spear310_clk_init(void); +/* Add spear310 machine device structure declarations here */ + +/* pad mux devices */ +extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5; +extern struct pmx_dev spear310_pmx_emi_cs_2_3; +extern struct pmx_dev spear310_pmx_uart1; +extern struct pmx_dev spear310_pmx_uart2; +extern struct pmx_dev spear310_pmx_uart3_4_5; +extern struct pmx_dev spear310_pmx_fsmc; +extern struct pmx_dev spear310_pmx_rs485_0_1; +extern struct pmx_dev spear310_pmx_tdm0; + +/* Add spear310 machine function declarations here */ +void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR310 */ /* spear320 declarations */ #ifdef CONFIG_MACH_SPEAR320 -void __init spear320_clk_init(void); +/* Add spear320 machine device structure declarations here */ + +/* pad mux modes */ +extern struct pmx_mode spear320_auto_net_smii_mode; +extern struct pmx_mode spear320_auto_net_mii_mode; +extern struct pmx_mode spear320_auto_exp_mode; +extern struct pmx_mode spear320_small_printers_mode; + +/* pad mux devices */ +extern struct pmx_dev spear320_pmx_clcd; +extern struct pmx_dev spear320_pmx_emi; +extern struct pmx_dev spear320_pmx_fsmc; +extern struct pmx_dev spear320_pmx_spp; +extern struct pmx_dev spear320_pmx_sdhci; +extern struct pmx_dev spear320_pmx_i2s; +extern struct pmx_dev spear320_pmx_uart1; +extern struct pmx_dev spear320_pmx_uart1_modem; +extern struct pmx_dev spear320_pmx_uart2; +extern struct pmx_dev spear320_pmx_touchscreen; +extern struct pmx_dev spear320_pmx_can; +extern struct pmx_dev spear320_pmx_sdhci_led; +extern struct pmx_dev spear320_pmx_pwm0; +extern struct pmx_dev spear320_pmx_pwm1; +extern struct pmx_dev spear320_pmx_pwm2; +extern struct pmx_dev spear320_pmx_pwm3; +extern struct pmx_dev spear320_pmx_ssp1; +extern struct pmx_dev spear320_pmx_ssp2; +extern struct pmx_dev spear320_pmx_mii1; +extern struct pmx_dev spear320_pmx_smii0; +extern struct pmx_dev spear320_pmx_smii1; +extern struct pmx_dev spear320_pmx_i2c1; + +/* Add spear320 machine function declarations here */ +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR320 */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h b/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h index defa374f5bee..4660c0d8ec0d 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -17,4 +17,7 @@ #include #include +/* Vitual to physical translation of statically mapped space */ +#define IO_ADDRESS(x) (x | 0xF0000000) + #endif /* __MACH_HARDWARE_H */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear.h index 8e3900aa0d45..63fd98356919 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/spear.h @@ -25,9 +25,8 @@ /* ICM1 - Low speed connection */ #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) -#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) -#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) +#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) #define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) #define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) @@ -54,11 +53,11 @@ #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) #define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) #define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) +#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) /* ICM3 - Basic Subsystem */ #define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) #define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) #define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) @@ -66,9 +65,9 @@ #define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) #define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) +#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) +#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) #define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) /* Debug uart for linux, will be used for debug and uncompress messages */ diff --git a/trunk/arch/arm/mach-spear3xx/spear300.c b/trunk/arch/arm/mach-spear3xx/spear300.c index 2db0bd14e481..f7db66812abb 100644 --- a/trunk/arch/arm/mach-spear3xx/spear300.c +++ b/trunk/arch/arm/mach-spear3xx/spear300.c @@ -3,24 +3,373 @@ * * SPEAr300 machine source file * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#define pr_fmt(fmt) "SPEAr300: " fmt - -#include -#include -#include -#include +#include +#include +#include +#include #include #include #include +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x00 +#define MODE_CONFIG_REG 0x04 + +/* modes */ +#define NAND_MODE (1 << 0) +#define NOR_MODE (1 << 1) +#define PHOTO_FRAME_MODE (1 << 2) +#define LEND_IP_PHONE_MODE (1 << 3) +#define HEND_IP_PHONE_MODE (1 << 4) +#define LEND_WIFI_PHONE_MODE (1 << 5) +#define HEND_WIFI_PHONE_MODE (1 << 6) +#define ATA_PABX_WI2S_MODE (1 << 7) +#define ATA_PABX_I2S_MODE (1 << 8) +#define CAML_LCDW_MODE (1 << 9) +#define CAMU_LCD_MODE (1 << 10) +#define CAMU_WLCD_MODE (1 << 11) +#define CAML_LCD_MODE (1 << 12) +#define ALL_MODES 0x1FFF + +struct pmx_mode spear300_nand_mode = { + .id = NAND_MODE, + .name = "nand mode", + .mask = 0x00, +}; + +struct pmx_mode spear300_nor_mode = { + .id = NOR_MODE, + .name = "nor mode", + .mask = 0x01, +}; + +struct pmx_mode spear300_photo_frame_mode = { + .id = PHOTO_FRAME_MODE, + .name = "photo frame mode", + .mask = 0x02, +}; + +struct pmx_mode spear300_lend_ip_phone_mode = { + .id = LEND_IP_PHONE_MODE, + .name = "lend ip phone mode", + .mask = 0x03, +}; + +struct pmx_mode spear300_hend_ip_phone_mode = { + .id = HEND_IP_PHONE_MODE, + .name = "hend ip phone mode", + .mask = 0x04, +}; + +struct pmx_mode spear300_lend_wifi_phone_mode = { + .id = LEND_WIFI_PHONE_MODE, + .name = "lend wifi phone mode", + .mask = 0x05, +}; + +struct pmx_mode spear300_hend_wifi_phone_mode = { + .id = HEND_WIFI_PHONE_MODE, + .name = "hend wifi phone mode", + .mask = 0x06, +}; + +struct pmx_mode spear300_ata_pabx_wi2s_mode = { + .id = ATA_PABX_WI2S_MODE, + .name = "ata pabx wi2s mode", + .mask = 0x07, +}; + +struct pmx_mode spear300_ata_pabx_i2s_mode = { + .id = ATA_PABX_I2S_MODE, + .name = "ata pabx i2s mode", + .mask = 0x08, +}; + +struct pmx_mode spear300_caml_lcdw_mode = { + .id = CAML_LCDW_MODE, + .name = "caml lcdw mode", + .mask = 0x0C, +}; + +struct pmx_mode spear300_camu_lcd_mode = { + .id = CAMU_LCD_MODE, + .name = "camu lcd mode", + .mask = 0x0D, +}; + +struct pmx_mode spear300_camu_wlcd_mode = { + .id = CAMU_WLCD_MODE, + .name = "camu wlcd mode", + .mask = 0x0E, +}; + +struct pmx_mode spear300_caml_lcd_mode = { + .id = CAML_LCD_MODE, + .name = "caml lcd mode", + .mask = 0x0F, +}; + +/* devices */ +static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { + { + .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear300_pmx_fsmc_2_chips = { + .name = "fsmc_2_chips", + .modes = pmx_fsmc_2_chips_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { + { + .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, + }, +}; + +struct pmx_dev spear300_pmx_fsmc_4_chips = { + .name = "fsmc_4_chips", + .modes = pmx_fsmc_4_chips_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_keyboard_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE | + CAML_LCD_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear300_pmx_keyboard = { + .name = "keyboard", + .modes = pmx_keyboard_modes, + .mode_count = ARRAY_SIZE(pmx_keyboard_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_clcd_modes[] = { + { + .ids = PHOTO_FRAME_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , + }, { + .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | + CAMU_LCD_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear300_pmx_clcd = { + .name = "clcd", + .modes = pmx_clcd_modes, + .mode_count = ARRAY_SIZE(pmx_clcd_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_gpio_modes[] = { + { + .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, + .mask = PMX_MII_MASK, + }, { + .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, { + .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK, + }, { + .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK, + }, { + .ids = ATA_PABX_WI2S_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK + | PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_gpio = { + .name = "telecom_gpio", + .modes = pmx_telecom_gpio_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_tdm_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE + | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE + | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_tdm = { + .name = "telecom_tdm", + .modes = pmx_telecom_tdm_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE + | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | + CAML_LCDW_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = { + .name = "telecom_spi_cs_i2c_clk", + .modes = pmx_telecom_spi_cs_i2c_clk_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_camera_modes[] = { + { + .ids = CAML_LCDW_MODE | CAML_LCD_MODE, + .mask = PMX_MII_MASK, + }, { + .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_camera = { + .name = "telecom_camera", + .modes = pmx_telecom_camera_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_dac_modes[] = { + { + .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_dac = { + .name = "telecom_dac", + .modes = pmx_telecom_dac_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_i2s_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE + | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_i2s = { + .name = "telecom_i2s", + .modes = pmx_telecom_i2s_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { + { + .ids = NAND_MODE | NOR_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | + PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_boot_pins = { + .name = "telecom_boot_pins", + .modes = pmx_telecom_boot_pins_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE | + ATA_PABX_I2S_MODE, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_sdhci_4bit = { + .name = "telecom_sdhci_4bit", + .modes = pmx_telecom_sdhci_4bit_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_sdhci_8bit = { + .name = "telecom_sdhci_8bit", + .modes = pmx_telecom_sdhci_8bit_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_gpio1_modes[] = { + { + .ids = PHOTO_FRAME_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | + PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear300_pmx_gpio1 = { + .name = "arm gpio1", + .modes = pmx_gpio1_modes, + .mode_count = ARRAY_SIZE(pmx_gpio1_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +static struct pmx_driver pmx_driver = { + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; + /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { { @@ -74,239 +423,45 @@ static struct spear_shirq shirq_ras1 = { }, }; -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear300_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, +/* Add spear300 specific devices here */ +/* arm gpio1 device registration */ +static struct pl061_platform_data gpio1_plat_data = { + .gpio_base = 8, + .irq_base = SPEAR300_GPIO1_INT_BASE, }; -/* Add SPEAr300 auxdata to pass platform data */ -static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - {} -}; +AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE, + {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data); -static void __init spear300_dt_init(void) +/* spear300 routines */ +void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { - int ret; - - pl080_plat_data.slave_channels = spear300_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); + int ret = 0; - of_platform_populate(NULL, of_default_bus_match_table, - spear300_auxdata_lookup, NULL); + /* call spear3xx family common init function */ + spear3xx_init(); /* shared irq registration */ shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); if (shirq_ras1.regs.base) { ret = spear_shirq_register(&shirq_ras1); if (ret) - pr_err("Error registering Shared IRQ\n"); + printk(KERN_ERR "Error registering Shared IRQ\n"); } -} -static const char * const spear300_dt_board_compat[] = { - "st,spear300", - "st,spear300-evb", - NULL, -}; + /* pmx initialization */ + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; -static void __init spear300_map_io(void) -{ - spear3xx_map_io(); - spear300_clk_init(); + pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); + if (pmx_driver.base) { + ret = pmx_register(&pmx_driver); + if (ret) + printk(KERN_ERR "padmux: registration failed. err no" + ": %d\n", ret); + /* Free Mapping, device selection already done */ + iounmap(pmx_driver.base); + } } - -DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") - .map_io = spear300_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear300_dt_init, - .restart = spear_restart, - .dt_compat = spear300_dt_board_compat, -MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear300_evb.c b/trunk/arch/arm/mach-spear3xx/spear300_evb.c new file mode 100644 index 000000000000..3462ab9d6122 --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/spear300_evb.c @@ -0,0 +1,75 @@ +/* + * arch/arm/mach-spear3xx/spear300_evb.c + * + * SPEAr300 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp_cs, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, + + /* spear300 specific devices */ + &spear300_pmx_fsmc_2_chips, + &spear300_pmx_clcd, + &spear300_pmx_telecom_sdhci_4bit, + &spear300_pmx_gpio1, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &spear3xx_gpio_device, + &spear3xx_uart_device, + + /* spear300 specific devices */ + &spear300_gpio1_device, +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear300 specific devices */ +}; + +static void __init spear300_evb_init(void) +{ + unsigned int i; + + /* call spear300 machine init function */ + spear300_init(&spear300_photo_frame_mode, pmx_devs, + ARRAY_SIZE(pmx_devs)); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR300, "ST-SPEAR300-EVB") + .atag_offset = 0x100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear300_evb_init, + .restart = spear_restart, +MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear310.c b/trunk/arch/arm/mach-spear3xx/spear310.c index aec07c951205..febaa6fcfb6a 100644 --- a/trunk/arch/arm/mach-spear3xx/spear310.c +++ b/trunk/arch/arm/mach-spear3xx/spear310.c @@ -3,25 +3,142 @@ * * SPEAr310 machine source file * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#define pr_fmt(fmt) "SPEAr310: " fmt - -#include -#include -#include -#include -#include +#include +#include #include #include #include +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x08 + +/* devices */ +static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { + .name = "emi_cs_0_1_4_5", + .modes = pmx_emi_cs_0_1_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear310_pmx_emi_cs_2_3 = { + .name = "emi_cs_2_3", + .modes = pmx_emi_cs_2_3_modes, + .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart1_modes[] = { + { + .ids = 0x00, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear310_pmx_uart1 = { + .name = "uart1", + .modes = pmx_uart1_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart2_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear310_pmx_uart2 = { + .name = "uart2", + .modes = pmx_uart2_modes, + .mode_count = ARRAY_SIZE(pmx_uart2_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear310_pmx_uart3_4_5 = { + .name = "uart3_4_5", + .modes = pmx_uart3_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_fsmc_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear310_pmx_fsmc = { + .name = "fsmc", + .modes = pmx_fsmc_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear310_pmx_rs485_0_1 = { + .name = "rs485_0_1", + .modes = pmx_rs485_0_1_modes, + .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_tdm0_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear310_pmx_tdm0 = { + .name = "tdm0", + .modes = pmx_tdm0_modes, + .mode_count = ARRAY_SIZE(pmx_tdm0_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +static struct pmx_driver pmx_driver = { + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; + /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { { @@ -138,247 +255,17 @@ static struct spear_shirq shirq_intrcomm_ras = { }, }; -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear310_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart2_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart2_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart3_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart3_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart4_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart4_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart5_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart5_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, -}; +/* Add spear310 specific devices here */ -/* uart devices plat data */ -static struct amba_pl011_data spear310_uart_data[] = { - { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart1_tx", - .dma_rx_param = "uart1_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart2_tx", - .dma_rx_param = "uart2_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart3_tx", - .dma_rx_param = "uart3_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart4_tx", - .dma_rx_param = "uart4_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart5_tx", - .dma_rx_param = "uart5_rx", - }, -}; - -/* Add SPEAr310 auxdata to pass platform data */ -static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, - &spear310_uart_data[0]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, - &spear310_uart_data[1]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, - &spear310_uart_data[2]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, - &spear310_uart_data[3]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, - &spear310_uart_data[4]), - {} -}; - -static void __init spear310_dt_init(void) +/* spear310 routines */ +void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { void __iomem *base; - int ret; + int ret = 0; - pl080_plat_data.slave_channels = spear310_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); - - of_platform_populate(NULL, of_default_bus_match_table, - spear310_auxdata_lookup, NULL); + /* call spear3xx family common init function */ + spear3xx_init(); /* shared irq registration */ base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); @@ -387,46 +274,35 @@ static void __init spear310_dt_init(void) shirq_ras1.regs.base = base; ret = spear_shirq_register(&shirq_ras1); if (ret) - pr_err("Error registering Shared IRQ 1\n"); + printk(KERN_ERR "Error registering Shared IRQ 1\n"); /* shirq 2 */ shirq_ras2.regs.base = base; ret = spear_shirq_register(&shirq_ras2); if (ret) - pr_err("Error registering Shared IRQ 2\n"); + printk(KERN_ERR "Error registering Shared IRQ 2\n"); /* shirq 3 */ shirq_ras3.regs.base = base; ret = spear_shirq_register(&shirq_ras3); if (ret) - pr_err("Error registering Shared IRQ 3\n"); + printk(KERN_ERR "Error registering Shared IRQ 3\n"); /* shirq 4 */ shirq_intrcomm_ras.regs.base = base; ret = spear_shirq_register(&shirq_intrcomm_ras); if (ret) - pr_err("Error registering Shared IRQ 4\n"); + printk(KERN_ERR "Error registering Shared IRQ 4\n"); } -} -static const char * const spear310_dt_board_compat[] = { - "st,spear310", - "st,spear310-evb", - NULL, -}; + /* pmx initialization */ + pmx_driver.base = base; + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; -static void __init spear310_map_io(void) -{ - spear3xx_map_io(); - spear310_clk_init(); + ret = pmx_register(&pmx_driver); + if (ret) + printk(KERN_ERR "padmux: registration failed. err no: %d\n", + ret); } - -DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") - .map_io = spear310_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear310_dt_init, - .restart = spear_restart, - .dt_compat = spear310_dt_board_compat, -MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear310_evb.c b/trunk/arch/arm/mach-spear3xx/spear310_evb.c new file mode 100644 index 000000000000..f92c4993f65a --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/spear310_evb.c @@ -0,0 +1,81 @@ +/* + * arch/arm/mach-spear3xx/spear310_evb.c + * + * SPEAr310 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_gpio_pin0, + &spear3xx_pmx_gpio_pin1, + &spear3xx_pmx_gpio_pin2, + &spear3xx_pmx_gpio_pin3, + &spear3xx_pmx_gpio_pin4, + &spear3xx_pmx_gpio_pin5, + &spear3xx_pmx_uart0, + + /* spear310 specific devices */ + &spear310_pmx_emi_cs_0_1_4_5, + &spear310_pmx_emi_cs_2_3, + &spear310_pmx_uart1, + &spear310_pmx_uart2, + &spear310_pmx_uart3_4_5, + &spear310_pmx_fsmc, + &spear310_pmx_rs485_0_1, + &spear310_pmx_tdm0, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &spear3xx_gpio_device, + &spear3xx_uart_device, + + /* spear310 specific devices */ +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear310 specific devices */ +}; + +static void __init spear310_evb_init(void) +{ + unsigned int i; + + /* call spear310 machine init function */ + spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs)); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR310, "ST-SPEAR310-EVB") + .atag_offset = 0x100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear310_evb_init, + .restart = spear_restart, +MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear320.c b/trunk/arch/arm/mach-spear3xx/spear320.c index 4812c692ca35..deaaf199612c 100644 --- a/trunk/arch/arm/mach-spear3xx/spear320.c +++ b/trunk/arch/arm/mach-spear3xx/spear320.c @@ -3,26 +3,387 @@ * * SPEAr320 machine source file * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#define pr_fmt(fmt) "SPEAr320: " fmt - -#include -#include -#include -#include -#include -#include +#include +#include #include #include #include +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x0C +#define MODE_CONFIG_REG 0x10 + +/* modes */ +#define AUTO_NET_SMII_MODE (1 << 0) +#define AUTO_NET_MII_MODE (1 << 1) +#define AUTO_EXP_MODE (1 << 2) +#define SMALL_PRINTERS_MODE (1 << 3) +#define ALL_MODES 0xF + +struct pmx_mode spear320_auto_net_smii_mode = { + .id = AUTO_NET_SMII_MODE, + .name = "Automation Networking SMII Mode", + .mask = 0x00, +}; + +struct pmx_mode spear320_auto_net_mii_mode = { + .id = AUTO_NET_MII_MODE, + .name = "Automation Networking MII Mode", + .mask = 0x01, +}; + +struct pmx_mode spear320_auto_exp_mode = { + .id = AUTO_EXP_MODE, + .name = "Automation Expanded Mode", + .mask = 0x02, +}; + +struct pmx_mode spear320_small_printers_mode = { + .id = SMALL_PRINTERS_MODE, + .name = "Small Printers Mode", + .mask = 0x03, +}; + +/* devices */ +static struct pmx_dev_mode pmx_clcd_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_clcd = { + .name = "clcd", + .modes = pmx_clcd_modes, + .mode_count = ARRAY_SIZE(pmx_clcd_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_emi_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear320_pmx_emi = { + .name = "emi", + .modes = pmx_emi_modes, + .mode_count = ARRAY_SIZE(pmx_emi_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_fsmc_modes[] = { + { + .ids = ALL_MODES, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_fsmc = { + .name = "fsmc", + .modes = pmx_fsmc_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_spp_modes[] = { + { + .ids = SMALL_PRINTERS_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_spp = { + .name = "spp", + .modes = pmx_spp_modes, + .mode_count = ARRAY_SIZE(pmx_spp_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_sdhci_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | + SMALL_PRINTERS_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear320_pmx_sdhci = { + .name = "sdhci", + .modes = pmx_sdhci_modes, + .mode_count = ARRAY_SIZE(pmx_sdhci_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_i2s_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear320_pmx_i2s = { + .name = "i2s", + .modes = pmx_i2s_modes, + .mode_count = ARRAY_SIZE(pmx_i2s_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart1_modes[] = { + { + .ids = ALL_MODES, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev spear320_pmx_uart1 = { + .name = "uart1", + .modes = pmx_uart1_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart1_modem_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | + PMX_SSP_CS_MASK, + }, { + .ids = SMALL_PRINTERS_MODE, + .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | + PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear320_pmx_uart1_modem = { + .name = "uart1_modem", + .modes = pmx_uart1_modem_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart2_modes[] = { + { + .ids = ALL_MODES, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear320_pmx_uart2 = { + .name = "uart2", + .modes = pmx_uart2_modes, + .mode_count = ARRAY_SIZE(pmx_uart2_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_touchscreen_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear320_pmx_touchscreen = { + .name = "touchscreen", + .modes = pmx_touchscreen_modes, + .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_can_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, + .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev spear320_pmx_can = { + .name = "can", + .modes = pmx_can_modes, + .mode_count = ARRAY_SIZE(pmx_can_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_sdhci_led_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear320_pmx_sdhci_led = { + .name = "sdhci_led", + .modes = pmx_sdhci_led_modes, + .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_pwm0_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_pwm0 = { + .name = "pwm0", + .modes = pmx_pwm0_modes, + .mode_count = ARRAY_SIZE(pmx_pwm0_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_pwm1_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_pwm1 = { + .name = "pwm1", + .modes = pmx_pwm1_modes, + .mode_count = ARRAY_SIZE(pmx_pwm1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_pwm2_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_SSP_CS_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_pwm2 = { + .name = "pwm2", + .modes = pmx_pwm2_modes, + .mode_count = ARRAY_SIZE(pmx_pwm2_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_pwm3_modes[] = { + { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_pwm3 = { + .name = "pwm3", + .modes = pmx_pwm3_modes, + .mode_count = ARRAY_SIZE(pmx_pwm3_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_ssp1_modes[] = { + { + .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_ssp1 = { + .name = "ssp1", + .modes = pmx_ssp1_modes, + .mode_count = ARRAY_SIZE(pmx_ssp1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_ssp2_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_ssp2 = { + .name = "ssp2", + .modes = pmx_ssp2_modes, + .mode_count = ARRAY_SIZE(pmx_ssp2_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_mii1_modes[] = { + { + .ids = AUTO_NET_MII_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_mii1 = { + .name = "mii1", + .modes = pmx_mii1_modes, + .mode_count = ARRAY_SIZE(pmx_mii1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_smii0_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_smii0 = { + .name = "smii0", + .modes = pmx_smii0_modes, + .mode_count = ARRAY_SIZE(pmx_smii0_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_smii1_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_smii1 = { + .name = "smii1", + .modes = pmx_smii1_modes, + .mode_count = ARRAY_SIZE(pmx_smii1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_i2c1_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_i2c1 = { + .name = "i2c1", + .modes = pmx_i2c1_modes, + .mode_count = ARRAY_SIZE(pmx_i2c1_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +static struct pmx_driver pmx_driver = { + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; + /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { { @@ -147,250 +508,17 @@ static struct spear_shirq shirq_intrcomm_ras = { }, }; -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear320_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c0_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c0_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart1_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart1_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart2_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart2_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c1_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c1_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c2_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c2_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2s_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2s_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "rs485_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "rs485_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, -}; - -static struct pl022_ssp_controller spear320_ssp_data[] = { - { - .bus_id = 1, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp1_tx", - .dma_rx_param = "ssp1_rx", - .num_chipselect = 2, - }, { - .bus_id = 2, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp2_tx", - .dma_rx_param = "ssp2_rx", - .num_chipselect = 2, - } -}; - -static struct amba_pl011_data spear320_uart_data[] = { - { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart1_tx", - .dma_rx_param = "uart1_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart2_tx", - .dma_rx_param = "uart2_rx", - }, -}; +/* Add spear320 specific devices here */ -/* Add SPEAr310 auxdata to pass platform data */ -static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, - &spear320_ssp_data[0]), - OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, - &spear320_ssp_data[1]), - OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, - &spear320_uart_data[0]), - OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, - &spear320_uart_data[1]), - {} -}; - -static void __init spear320_dt_init(void) +/* spear320 routines */ +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { void __iomem *base; - int ret; - - pl080_plat_data.slave_channels = spear320_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); + int ret = 0; - of_platform_populate(NULL, of_default_bus_match_table, - spear320_auxdata_lookup, NULL); + /* call spear3xx family common init function */ + spear3xx_init(); /* shared irq registration */ base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); @@ -399,40 +527,29 @@ static void __init spear320_dt_init(void) shirq_ras1.regs.base = base; ret = spear_shirq_register(&shirq_ras1); if (ret) - pr_err("Error registering Shared IRQ 1\n"); + printk(KERN_ERR "Error registering Shared IRQ 1\n"); /* shirq 3 */ shirq_ras3.regs.base = base; ret = spear_shirq_register(&shirq_ras3); if (ret) - pr_err("Error registering Shared IRQ 3\n"); + printk(KERN_ERR "Error registering Shared IRQ 3\n"); /* shirq 4 */ shirq_intrcomm_ras.regs.base = base; ret = spear_shirq_register(&shirq_intrcomm_ras); if (ret) - pr_err("Error registering Shared IRQ 4\n"); + printk(KERN_ERR "Error registering Shared IRQ 4\n"); } -} -static const char * const spear320_dt_board_compat[] = { - "st,spear320", - "st,spear320-evb", - NULL, -}; + /* pmx initialization */ + pmx_driver.base = base; + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; -static void __init spear320_map_io(void) -{ - spear3xx_map_io(); - spear320_clk_init(); + ret = pmx_register(&pmx_driver); + if (ret) + printk(KERN_ERR "padmux: registration failed. err no: %d\n", + ret); } - -DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") - .map_io = spear320_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear320_dt_init, - .restart = spear_restart, - .dt_compat = spear320_dt_board_compat, -MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear320_evb.c b/trunk/arch/arm/mach-spear3xx/spear320_evb.c new file mode 100644 index 000000000000..105334ab7021 --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/spear320_evb.c @@ -0,0 +1,79 @@ +/* + * arch/arm/mach-spear3xx/spear320_evb.c + * + * SPEAr320 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, + + /* spear320 specific devices */ + &spear320_pmx_fsmc, + &spear320_pmx_sdhci, + &spear320_pmx_i2s, + &spear320_pmx_uart1, + &spear320_pmx_uart2, + &spear320_pmx_can, + &spear320_pmx_pwm0, + &spear320_pmx_pwm1, + &spear320_pmx_pwm2, + &spear320_pmx_mii1, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &spear3xx_gpio_device, + &spear3xx_uart_device, + + /* spear320 specific devices */ +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear320 specific devices */ +}; + +static void __init spear320_evb_init(void) +{ + unsigned int i; + + /* call spear320 machine init function */ + spear320_init(&spear320_auto_net_mii_mode, pmx_devs, + ARRAY_SIZE(pmx_devs)); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR320, "ST-SPEAR320-EVB") + .atag_offset = 0x100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear320_evb_init, + .restart = spear_restart, +MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear3xx.c b/trunk/arch/arm/mach-spear3xx/spear3xx.c index 12bf879a9ef1..b1733c37f209 100644 --- a/trunk/arch/arm/mach-spear3xx/spear3xx.c +++ b/trunk/arch/arm/mach-spear3xx/spear3xx.c @@ -3,78 +3,71 @@ * * SPEAr3XX machines common source file * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#define pr_fmt(fmt) "SPEAr3xx: " fmt - -#include -#include -#include +#include +#include +#include #include -#include #include -#include +#include +#include #include #include -/* ssp device registration */ -struct pl022_ssp_controller pl022_plat_data = { - .bus_id = 0, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp0_tx", - .dma_rx_param = "ssp0_rx", - /* - * This is number of spi devices that can be connected to spi. There are - * two type of chipselects on which slave devices can work. One is chip - * select provided by spi masters other is controlled through external - * gpio's. We can't use chipselect provided from spi master (because as - * soon as FIFO becomes empty, CS is disabled and transfer ends). So - * this number now depends on number of gpios available for spi. each - * slave on each master requires a separate gpio pin. - */ - .num_chipselect = 2, -}; - -/* dmac device registration */ -struct pl08x_platform_data pl080_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ - PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ - PL080_CONTROL_PROT_SYS), - }, - .lli_buses = PL08X_AHB1, - .mem_buses = PL08X_AHB1, - .get_signal = pl080_get_signal, - .put_signal = pl080_put_signal, +/* Add spear3xx machines common devices here */ +/* gpio device registration */ +static struct pl061_platform_data gpio_plat_data = { + .gpio_base = 0, + .irq_base = SPEAR3XX_GPIO_INT_BASE, }; -/* - * Following will create 16MB static virtual/physical mappings - * PHYSICAL VIRTUAL - * 0xD0000000 0xFD000000 - * 0xFC000000 0xFC000000 - */ +AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE, + {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data); + +/* uart device registration */ +AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE, + {SPEAR3XX_IRQ_UART}, NULL); + +/* Do spear3xx familiy common initialization part here */ +void __init spear3xx_init(void) +{ + /* nothing to do for now */ +} + +/* This will initialize vic */ +void __init spear3xx_init_irq(void) +{ + vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0); +} + +/* Following will create static virtual/physical mappings */ struct map_desc spear3xx_io_desc[] __initdata = { { - .virtual = VA_SPEAR3XX_ICM1_2_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE), - .length = SZ_16M, + .virtual = VA_SPEAR3XX_ICM1_UART_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ML1_VIC_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE), + .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE), - .length = SZ_16M, + .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), + .length = SZ_4K, .type = MT_DEVICE }, }; @@ -83,8 +76,436 @@ struct map_desc spear3xx_io_desc[] __initdata = { void __init spear3xx_map_io(void) { iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); + + /* This will initialize clock framework */ + spear3xx_clk_init(); } +/* pad multiplexing support */ +/* devices */ +static struct pmx_dev_mode pmx_firda_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_firda = { + .name = "firda", + .modes = pmx_firda_modes, + .mode_count = ARRAY_SIZE(pmx_firda_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_i2c_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_I2C_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_i2c = { + .name = "i2c", + .modes = pmx_i2c_modes, + .mode_count = ARRAY_SIZE(pmx_i2c_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_ssp_cs_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_ssp_cs = { + .name = "ssp_chip_selects", + .modes = pmx_ssp_cs_modes, + .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_ssp_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_SSP_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_ssp = { + .name = "ssp", + .modes = pmx_ssp_modes, + .mode_count = ARRAY_SIZE(pmx_ssp_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_mii_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_mii = { + .name = "mii", + .modes = pmx_mii_modes, + .mode_count = ARRAY_SIZE(pmx_mii_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN0_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin0 = { + .name = "gpio_pin0", + .modes = pmx_gpio_pin0_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin1 = { + .name = "gpio_pin1", + .modes = pmx_gpio_pin1_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN2_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin2 = { + .name = "gpio_pin2", + .modes = pmx_gpio_pin2_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN3_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin3 = { + .name = "gpio_pin3", + .modes = pmx_gpio_pin3_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN4_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin4 = { + .name = "gpio_pin4", + .modes = pmx_gpio_pin4_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin5 = { + .name = "gpio_pin5", + .modes = pmx_gpio_pin5_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_uart0_modem_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_uart0_modem = { + .name = "uart0_modem", + .modes = pmx_uart0_modem_modes, + .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_uart0_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_UART0_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_uart0 = { + .name = "uart0", + .modes = pmx_uart0_modes, + .mode_count = ARRAY_SIZE(pmx_uart0_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_timer_3_4_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_timer_3_4 = { + .name = "timer_3_4", + .modes = pmx_timer_3_4_modes, + .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_timer_1_2_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_timer_1_2 = { + .name = "timer_1_2", + .modes = pmx_timer_1_2_modes, + .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), + .enb_on_reset = 0, +}; + +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* plgpios devices */ +static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { + { + .ids = 0x00, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_0_1 = { + .name = "plgpio 0 and 1", + .modes = pmx_plgpio_0_1_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_2_3 = { + .name = "plgpio 2 and 3", + .modes = pmx_plgpio_2_3_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_I2C_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_4_5 = { + .name = "plgpio 4 and 5", + .modes = pmx_plgpio_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_6_9 = { + .name = "plgpio 6 to 9", + .modes = pmx_plgpio_6_9_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_10_27 = { + .name = "plgpio 10 to 27", + .modes = pmx_plgpio_10_27_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_28_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN0_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_28 = { + .name = "plgpio 28", + .modes = pmx_plgpio_28_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_29_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_29 = { + .name = "plgpio 29", + .modes = pmx_plgpio_29_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_30_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN2_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_30 = { + .name = "plgpio 30", + .modes = pmx_plgpio_30_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_31_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN3_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_31 = { + .name = "plgpio 31", + .modes = pmx_plgpio_31_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_32_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN4_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_32 = { + .name = "plgpio 32", + .modes = pmx_plgpio_32_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_33_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_33 = { + .name = "plgpio 33", + .modes = pmx_plgpio_33_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_34_36 = { + .name = "plgpio 34 to 36", + .modes = pmx_plgpio_34_36_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_37_42 = { + .name = "plgpio 37 to 42", + .modes = pmx_plgpio_37_42_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { + .name = "plgpio 43, 44, 47 and 48", + .modes = pmx_plgpio_43_44_47_48_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { + .name = "plgpio 45, 46, 49 and 50", + .modes = pmx_plgpio_45_46_49_50_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), + .enb_on_reset = 1, +}; +#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ + static void __init spear3xx_timer_init(void) { char pclk_name[] = "pll3_48m_clk"; @@ -115,13 +536,3 @@ static void __init spear3xx_timer_init(void) struct sys_timer spear3xx_timer = { .init = spear3xx_timer_init, }; - -static const struct of_device_id vic_of_match[] __initconst = { - { .compatible = "arm,pl190-vic", .data = vic_of_init, }, - { /* Sentinel */ } -}; - -void __init spear3xx_dt_init_irq(void) -{ - of_irq_init(vic_of_match); -} diff --git a/trunk/arch/arm/mach-spear6xx/Makefile.boot b/trunk/arch/arm/mach-spear6xx/Makefile.boot index af493da37ab6..4674a4c221db 100644 --- a/trunk/arch/arm/mach-spear6xx/Makefile.boot +++ b/trunk/arch/arm/mach-spear6xx/Makefile.boot @@ -1,5 +1,3 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 - -dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb diff --git a/trunk/arch/arm/mach-spear6xx/clock.c b/trunk/arch/arm/mach-spear6xx/clock.c index adadef2b27b4..a86499a8a15f 100644 --- a/trunk/arch/arm/mach-spear6xx/clock.c +++ b/trunk/arch/arm/mach-spear6xx/clock.c @@ -623,53 +623,53 @@ static struct clk dummy_apb_pclk; /* array of all spear 6xx clock lookups */ static struct clk_lookup spear_clk_lookups[] = { - CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk), + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, /* root clks */ - CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk), - CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk), + { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, + { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, /* clock derived from 32 KHz os clk */ - CLKDEV_INIT("rtc-spear", NULL, &rtc_clk), + { .dev_id = "rtc-spear", .clk = &rtc_clk}, /* clock derived from 30 MHz os clk */ - CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk), - CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk), - CLKDEV_INIT("wdt", NULL, &wdt_clk), + { .con_id = "pll1_clk", .clk = &pll1_clk}, + { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, + { .dev_id = "wdt", .clk = &wdt_clk}, /* clock derived from pll1 clk */ - CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk), - CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk), - CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk), - CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk), - CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk), - CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk), - CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk), - CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk), - CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk), - CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk), - CLKDEV_INIT("firda", NULL, &firda_clk), - CLKDEV_INIT("clcd", NULL, &clcd_clk), - CLKDEV_INIT("gpt0", NULL, &gpt0_clk), - CLKDEV_INIT("gpt1", NULL, &gpt1_clk), - CLKDEV_INIT("gpt2", NULL, &gpt2_clk), - CLKDEV_INIT("gpt3", NULL, &gpt3_clk), + { .con_id = "cpu_clk", .clk = &cpu_clk}, + { .con_id = "ahb_clk", .clk = &ahb_clk}, + { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, + { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, + { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk}, + { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, + { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, + { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk}, + { .dev_id = "d0000000.serial", .clk = &uart0_clk}, + { .dev_id = "d0080000.serial", .clk = &uart1_clk}, + { .dev_id = "firda", .clk = &firda_clk}, + { .dev_id = "clcd", .clk = &clcd_clk}, + { .dev_id = "gpt0", .clk = &gpt0_clk}, + { .dev_id = "gpt1", .clk = &gpt1_clk}, + { .dev_id = "gpt2", .clk = &gpt2_clk}, + { .dev_id = "gpt3", .clk = &gpt3_clk}, /* clock derived from pll3 clk */ - CLKDEV_INIT("designware_udc", NULL, &usbd_clk), - CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk), - CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk), + { .dev_id = "designware_udc", .clk = &usbd_clk}, + { .con_id = "usbh.0_clk", .clk = &usbh0_clk}, + { .con_id = "usbh.1_clk", .clk = &usbh1_clk}, /* clock derived from ahb clk */ - CLKDEV_INIT(NULL, "apb_clk", &apb_clk), - CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk), - CLKDEV_INIT("fc400000.dma", NULL, &dma_clk), - CLKDEV_INIT("jpeg", NULL, &jpeg_clk), - CLKDEV_INIT("gmac", NULL, &gmac_clk), - CLKDEV_INIT("fc000000.flash", NULL, &smi_clk), - CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk), + { .con_id = "apb_clk", .clk = &apb_clk}, + { .dev_id = "d0200000.i2c", .clk = &i2c_clk}, + { .dev_id = "dma", .clk = &dma_clk}, + { .dev_id = "jpeg", .clk = &jpeg_clk}, + { .dev_id = "gmac", .clk = &gmac_clk}, + { .dev_id = "smi", .clk = &smi_clk}, + { .dev_id = "fsmc-nand", .clk = &fsmc_clk}, /* clock derived from apb clk */ - CLKDEV_INIT("adc", NULL, &adc_clk), - CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk), - CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk), - CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk), - CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk), - CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk), - CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk), + { .dev_id = "adc", .clk = &adc_clk}, + { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, + { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, + { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, + { .dev_id = "f0100000.gpio", .clk = &gpio0_clk}, + { .dev_id = "fc980000.gpio", .clk = &gpio1_clk}, + { .dev_id = "d8100000.gpio", .clk = &gpio2_clk}, }; void __init spear6xx_clk_init(void) diff --git a/trunk/arch/arm/mach-spear6xx/spear6xx.c b/trunk/arch/arm/mach-spear6xx/spear6xx.c index 5b9e30f54cdb..2ed8b14c82c8 100644 --- a/trunk/arch/arm/mach-spear6xx/spear6xx.c +++ b/trunk/arch/arm/mach-spear6xx/spear6xx.c @@ -13,377 +13,15 @@ * warranty of any kind, whether express or implied. */ -#include #include #include #include #include -#include #include #include -#include #include #include -/* dmac device registration */ -static struct pl08x_channel_data spear600_dma_info[] = { - { - .bus_id = "ssp1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp2_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ext0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, -}; - -struct pl08x_platform_data pl080_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ - PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ - PL080_CONTROL_PROT_SYS), - }, - .lli_buses = PL08X_AHB1, - .mem_buses = PL08X_AHB1, - .get_signal = pl080_get_signal, - .put_signal = pl080_put_signal, - .slave_channels = spear600_dma_info, - .num_slave_channels = ARRAY_SIZE(spear600_dma_info), -}; - /* Following will create static virtual/physical mappings */ static struct map_desc spear6xx_io_desc[] __initdata = { { @@ -454,17 +92,9 @@ struct sys_timer spear6xx_timer = { .init = spear6xx_timer_init, }; -/* Add auxdata to pass platform data */ -struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - {} -}; - static void __init spear600_dt_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, - spear6xx_auxdata_lookup, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *spear600_dt_board_compat[] = { diff --git a/trunk/arch/arm/mach-tegra/Makefile b/trunk/arch/arm/mach-tegra/Makefile index 2eb4445ddb14..d87d968115ec 100644 --- a/trunk/arch/arm/mach-tegra/Makefile +++ b/trunk/arch/arm/mach-tegra/Makefile @@ -5,6 +5,7 @@ obj-y += io.o obj-y += irq.o obj-y += clock.o obj-y += timer.o +obj-y += pinmux.o obj-y += fuse.o obj-y += pmc.o obj-y += flowctrl.o @@ -13,6 +14,8 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/trunk/arch/arm/mach-tegra/board-dt-tegra20.c b/trunk/arch/arm/mach-tegra/board-dt-tegra20.c index 5b9d5f4c0686..0952494f481a 100644 --- a/trunk/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/trunk/arch/arm/mach-tegra/board-dt-tegra20.c @@ -47,7 +47,15 @@ #include "clock.h" #include "devices.h" +void harmony_pinmux_init(void); +void paz00_pinmux_init(void); +void seaboard_pinmux_init(void); +void trimslice_pinmux_init(void); +void ventana_pinmux_init(void); + struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), @@ -87,10 +95,33 @@ static struct of_device_id tegra_dt_match_table[] __initdata = { {} }; +static struct { + char *machine; + void (*init)(void); +} pinmux_configs[] = { + { "compulab,trimslice", trimslice_pinmux_init }, + { "nvidia,harmony", harmony_pinmux_init }, + { "compal,paz00", paz00_pinmux_init }, + { "nvidia,seaboard", seaboard_pinmux_init }, + { "nvidia,ventana", ventana_pinmux_init }, +}; + static void __init tegra_dt_init(void) { + int i; + tegra_clk_init_from_table(tegra_dt_clk_init_table); + for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) { + if (of_machine_is_compatible(pinmux_configs[i].machine)) { + pinmux_configs[i].init(); + break; + } + } + + WARN(i == ARRAY_SIZE(pinmux_configs), + "Unknown platform! Pinmuxing not initialized\n"); + /* * Finished with the static registrations now; fill in the missing * devices diff --git a/trunk/arch/arm/mach-tegra/board-harmony-pinmux.c b/trunk/arch/arm/mach-tegra/board-harmony-pinmux.c index 83d420fbc58c..1af85bccc0f1 100644 --- a/trunk/arch/arm/mach-tegra/board-harmony-pinmux.c +++ b/trunk/arch/arm/mach-tegra/board-harmony-pinmux.c @@ -2,7 +2,6 @@ * arch/arm/mach-tegra/board-harmony-pinmux.c * * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -16,138 +15,153 @@ */ #include +#include +#include +#include +#include + +#include "gpio-names.h" #include "board-harmony.h" #include "board-pinmux.h" -static struct pinctrl_map harmony_map[] = { - TEGRA_MAP_MUXCONF("ata", "ide", none, driven), - TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("atc", "nand", none, driven), - TEGRA_MAP_MUXCONF("atd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("ate", "gmi", none, driven), - TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven), - TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate), - TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate), - TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate), - TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven), - TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate), - TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate), - TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate), - TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven), - TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven), - TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven), - TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven), - TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate), - TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven), - TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven), - TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven), - TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate), - TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven), - TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate), - TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate), - TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven), - TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate), - TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven), - TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven), - TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven), - TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate), - TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven), - TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate), - TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate), - TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven), - TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven), - TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("spia", "gmi", none, driven), - TEGRA_MAP_MUXCONF("spib", "gmi", none, driven), - TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate), - TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate), - TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate), - TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate), - TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate), - TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("uad", "irda", up, tristate), - TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate), - TEGRA_MAP_CONF("ck32", none, na), - TEGRA_MAP_CONF("ddrc", none, na), - TEGRA_MAP_CONF("pmca", none, na), - TEGRA_MAP_CONF("pmcb", none, na), - TEGRA_MAP_CONF("pmcc", none, na), - TEGRA_MAP_CONF("pmcd", none, na), - TEGRA_MAP_CONF("pmce", none, na), - TEGRA_MAP_CONF("xm2c", none, na), - TEGRA_MAP_CONF("xm2d", none, na), - TEGRA_MAP_CONF("ls", up, na), - TEGRA_MAP_CONF("lc", up, na), - TEGRA_MAP_CONF("ld17_0", down, na), - TEGRA_MAP_CONF("ld19_18", down, na), - TEGRA_MAP_CONF("ld21_20", down, na), - TEGRA_MAP_CONF("ld23_22", down, na), +static struct tegra_pingroup_config harmony_pinmux[] = { + {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static struct tegra_gpio_table gpio_table[] = { + { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true }, + { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, + { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, + { .gpio = TEGRA_GPIO_INT_MIC_EN, .enable = true }, + { .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true }, }; static struct tegra_board_pinmux_conf conf = { - .maps = harmony_map, - .map_count = ARRAY_SIZE(harmony_map), + .pgs = harmony_pinmux, + .pg_count = ARRAY_SIZE(harmony_pinmux), + .gpios = gpio_table, + .gpio_count = ARRAY_SIZE(gpio_table), }; void harmony_pinmux_init(void) diff --git a/trunk/arch/arm/mach-tegra/board-paz00-pinmux.c b/trunk/arch/arm/mach-tegra/board-paz00-pinmux.c index 6f1111b48e7c..c775572dcea4 100644 --- a/trunk/arch/arm/mach-tegra/board-paz00-pinmux.c +++ b/trunk/arch/arm/mach-tegra/board-paz00-pinmux.c @@ -2,7 +2,6 @@ * arch/arm/mach-tegra/board-paz00-pinmux.c * * Copyright (C) 2010 Marc Dietrich - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -16,138 +15,150 @@ */ #include +#include +#include +#include +#include + +#include "gpio-names.h" #include "board-paz00.h" #include "board-pinmux.h" -static struct pinctrl_map paz00_map[] = { - TEGRA_MAP_MUXCONF("ata", "gmi", none, driven), - TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("atc", "gmi", none, driven), - TEGRA_MAP_MUXCONF("atd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("ate", "gmi", none, driven), - TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven), - TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven), - TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate), - TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate), - TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven), - TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven), - TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate), - TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate), - TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven), - TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate), - TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate), - TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven), - TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven), - TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven), - TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven), - TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven), - TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven), - TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven), - TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven), - TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven), - TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven), - TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven), - TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("owc", "owr", up, tristate), - TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven), - TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven), - TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven), - TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate), - TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate), - TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate), - TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven), - TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate), - TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate), - TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate), - TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven), - TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven), - TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate), - TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate), - TEGRA_MAP_MUXCONF("spic", "gmi", up, driven), - TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate), - TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate), - TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate), - TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven), - TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven), - TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven), - TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven), - TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate), - TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven), - TEGRA_MAP_CONF("ck32", none, na), - TEGRA_MAP_CONF("ddrc", none, na), - TEGRA_MAP_CONF("pmca", none, na), - TEGRA_MAP_CONF("pmcb", none, na), - TEGRA_MAP_CONF("pmcc", none, na), - TEGRA_MAP_CONF("pmcd", none, na), - TEGRA_MAP_CONF("pmce", none, na), - TEGRA_MAP_CONF("xm2c", none, na), - TEGRA_MAP_CONF("xm2d", none, na), - TEGRA_MAP_CONF("ls", up, na), - TEGRA_MAP_CONF("lc", up, na), - TEGRA_MAP_CONF("ld17_0", down, na), - TEGRA_MAP_CONF("ld19_18", down, na), - TEGRA_MAP_CONF("ld21_20", down, na), - TEGRA_MAP_CONF("ld23_22", down, na), +static struct tegra_pingroup_config paz00_pinmux[] = { + {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static struct tegra_gpio_table gpio_table[] = { + { .gpio = TEGRA_GPIO_SD1_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, + { .gpio = TEGRA_ULPI_RST, .enable = true }, + { .gpio = TEGRA_WIFI_PWRN, .enable = true }, + { .gpio = TEGRA_WIFI_RST, .enable = true }, + { .gpio = TEGRA_WIFI_LED, .enable = true }, }; static struct tegra_board_pinmux_conf conf = { - .maps = paz00_map, - .map_count = ARRAY_SIZE(paz00_map), + .pgs = paz00_pinmux, + .pg_count = ARRAY_SIZE(paz00_pinmux), + .gpios = gpio_table, + .gpio_count = ARRAY_SIZE(gpio_table), }; void paz00_pinmux_init(void) diff --git a/trunk/arch/arm/mach-tegra/board-pinmux.c b/trunk/arch/arm/mach-tegra/board-pinmux.c index a5574c71b931..adc3efe979b3 100644 --- a/trunk/arch/arm/mach-tegra/board-pinmux.c +++ b/trunk/arch/arm/mach-tegra/board-pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -15,59 +15,75 @@ #include #include #include +#include #include +#include +#include + #include "board-pinmux.h" #include "devices.h" -unsigned long tegra_pincfg_pullnone_driven[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN), -}; +struct tegra_board_pinmux_conf *confs[2]; -unsigned long tegra_pincfg_pullnone_tristate[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE), -}; +static void tegra_board_pinmux_setup_gpios(void) +{ + int i; -unsigned long tegra_pincfg_pullnone_na[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE), -}; + for (i = 0; i < ARRAY_SIZE(confs); i++) { + if (!confs[i]) + continue; -unsigned long tegra_pincfg_pullup_driven[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN), -}; + tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count); + } +} -unsigned long tegra_pincfg_pullup_tristate[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE), -}; +static void tegra_board_pinmux_setup_pinmux(void) +{ + int i; -unsigned long tegra_pincfg_pullup_na[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP), -}; + for (i = 0; i < ARRAY_SIZE(confs); i++) { + if (!confs[i]) + continue; -unsigned long tegra_pincfg_pulldown_driven[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN), -}; + tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count); -unsigned long tegra_pincfg_pulldown_tristate[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE), -}; + if (confs[i]->drives) + tegra_drive_pinmux_config_table(confs[i]->drives, + confs[i]->drive_count); + } +} -unsigned long tegra_pincfg_pulldown_na[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN), -}; +static int tegra_board_pinmux_bus_notify(struct notifier_block *nb, + unsigned long event, void *vdev) +{ + static bool had_gpio; + static bool had_pinmux; -unsigned long tegra_pincfg_pullna_driven[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN), -}; + struct device *dev = vdev; + const char *devname; + + if (event != BUS_NOTIFY_BOUND_DRIVER) + return NOTIFY_DONE; -unsigned long tegra_pincfg_pullna_tristate[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE), + devname = dev_name(dev); + + if (!had_gpio && !strcmp(devname, GPIO_DEV)) { + tegra_board_pinmux_setup_gpios(); + had_gpio = true; + } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) { + tegra_board_pinmux_setup_pinmux(); + had_pinmux = true; + } + + if (had_gpio && had_pinmux) + return NOTIFY_STOP_MASK; + else + return NOTIFY_DONE; +} + +static struct notifier_block nb = { + .notifier_call = tegra_board_pinmux_bus_notify, }; static struct platform_device *devices[] = { @@ -78,10 +94,11 @@ static struct platform_device *devices[] = { void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, struct tegra_board_pinmux_conf *conf_b) { - if (conf_a) - pinctrl_register_mappings(conf_a->maps, conf_a->map_count); - if (conf_b) - pinctrl_register_mappings(conf_b->maps, conf_b->map_count); + confs[0] = conf_a; + confs[1] = conf_b; + + bus_register_notifier(&platform_bus_type, &nb); - platform_add_devices(devices, ARRAY_SIZE(devices)); + if (!of_machine_is_compatible("nvidia,tegra20")) + platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/trunk/arch/arm/mach-tegra/board-pinmux.h b/trunk/arch/arm/mach-tegra/board-pinmux.h index c5f3f3381e86..4aac73546f54 100644 --- a/trunk/arch/arm/mach-tegra/board-pinmux.h +++ b/trunk/arch/arm/mach-tegra/board-pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -15,37 +15,21 @@ #ifndef __MACH_TEGRA_BOARD_PINMUX_H #define __MACH_TEGRA_BOARD_PINMUX_H -#include +#define GPIO_DEV "tegra-gpio" +#define PINMUX_DEV "tegra-pinmux" -#include +struct tegra_pingroup_config; +struct tegra_gpio_table; -#define PINMUX_DEV "tegra20-pinctrl" - -#define TEGRA_MAP_MUX(_group_, _function_) \ - PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_) - -#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \ - PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_) - -#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \ - TEGRA_MAP_MUX(_group_, _function_), \ - TEGRA_MAP_CONF(_group_, _pull_, _drive_) +struct tegra_board_pinmux_conf { + struct tegra_pingroup_config *pgs; + int pg_count; -extern unsigned long tegra_pincfg_pullnone_driven[2]; -extern unsigned long tegra_pincfg_pullnone_tristate[2]; -extern unsigned long tegra_pincfg_pullnone_na[1]; -extern unsigned long tegra_pincfg_pullup_driven[2]; -extern unsigned long tegra_pincfg_pullup_tristate[2]; -extern unsigned long tegra_pincfg_pullup_na[1]; -extern unsigned long tegra_pincfg_pulldown_driven[2]; -extern unsigned long tegra_pincfg_pulldown_tristate[2]; -extern unsigned long tegra_pincfg_pulldown_na[1]; -extern unsigned long tegra_pincfg_pullna_driven[1]; -extern unsigned long tegra_pincfg_pullna_tristate[1]; + struct tegra_drive_pingroup_config *drives; + int drive_count; -struct tegra_board_pinmux_conf { - struct pinctrl_map *maps; - int map_count; + struct tegra_gpio_table *gpios; + int gpio_count; }; void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, diff --git a/trunk/arch/arm/mach-tegra/board-seaboard-pinmux.c b/trunk/arch/arm/mach-tegra/board-seaboard-pinmux.c index 11fc8a568c64..55e7e43a14ad 100644 --- a/trunk/arch/arm/mach-tegra/board-seaboard-pinmux.c +++ b/trunk/arch/arm/mach-tegra/board-seaboard-pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2012 NVIDIA Corporation + * Copyright (C) 2010,2011 NVIDIA Corporation * Copyright (C) 2011 Google, Inc. * * This software is licensed under the terms of the GNU General Public @@ -14,176 +14,216 @@ */ #include +#include +#include +#include -#include "board-seaboard.h" +#include +#include + +#include "gpio-names.h" #include "board-pinmux.h" +#include "board-seaboard.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = { + DEFAULT_DRIVE(SDIO1), +}; + +static struct tegra_pingroup_config common_pinmux[] = { + {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static struct tegra_pingroup_config seaboard_pinmux[] = { + {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, +}; -static unsigned long seaboard_pincfg_drive_sdio1[] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3), +static struct tegra_pingroup_config ventana_pinmux[] = { + {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, }; -static struct pinctrl_map common_map[] = { - TEGRA_MAP_MUXCONF("ata", "ide", none, driven), - TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("atc", "nand", none, driven), - TEGRA_MAP_MUXCONF("atd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven), - TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven), - TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate), - TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate), - TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven), - TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven), - TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate), - TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven), - TEGRA_MAP_MUXCONF("dta", "vi", down, driven), - TEGRA_MAP_MUXCONF("dtb", "vi", down, driven), - TEGRA_MAP_MUXCONF("dtc", "vi", down, driven), - TEGRA_MAP_MUXCONF("dtd", "vi", down, driven), - TEGRA_MAP_MUXCONF("dte", "vi", down, tristate), - TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven), - TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate), - TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven), - TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven), - TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven), - TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate), - TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate), - TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven), - TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven), - TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven), - TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven), - TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate), - TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate), - TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven), - TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate), - TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate), - TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate), - TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate), - TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven), - TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven), - TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven), - TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven), - TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven), - TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven), - TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven), - TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate), - TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven), - TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven), - TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven), - TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven), - TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate), - TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate), - TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven), - TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven), - TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven), - TEGRA_MAP_MUXCONF("uad", "irda", none, driven), - TEGRA_MAP_MUXCONF("uca", "uartc", none, driven), - TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven), - TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven), - TEGRA_MAP_CONF("ck32", none, na), - TEGRA_MAP_CONF("ddrc", none, na), - TEGRA_MAP_CONF("pmca", none, na), - TEGRA_MAP_CONF("pmcb", none, na), - TEGRA_MAP_CONF("pmcc", none, na), - TEGRA_MAP_CONF("pmcd", none, na), - TEGRA_MAP_CONF("pmce", none, na), - TEGRA_MAP_CONF("xm2c", none, na), - TEGRA_MAP_CONF("xm2d", none, na), - TEGRA_MAP_CONF("ls", up, na), - TEGRA_MAP_CONF("lc", up, na), - TEGRA_MAP_CONF("ld17_0", down, na), - TEGRA_MAP_CONF("ld19_18", down, na), - TEGRA_MAP_CONF("ld21_20", down, na), - TEGRA_MAP_CONF("ld23_22", down, na), +static struct tegra_gpio_table common_gpio_table[] = { + { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, + { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, }; -static struct pinctrl_map seaboard_map[] = { - TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven), - TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven), - TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven), - TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate), - TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate), - TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate), - TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate), - TEGRA_MAP_MUXCONF("spic", "gmi", up, driven), - TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate), - PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1), +static struct tegra_gpio_table seaboard_gpio_table[] = { + { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, + { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, + { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, + { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, + { .gpio = TEGRA_GPIO_USB1, .enable = true }, }; -static struct pinctrl_map ventana_map[] = { - TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven), - TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate), - TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven), - TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate), +static struct tegra_gpio_table ventana_gpio_table[] = { + /* hp_det */ + { .gpio = TEGRA_GPIO_PW2, .enable = true }, + /* int_mic_en */ + { .gpio = TEGRA_GPIO_PX0, .enable = true }, + /* ext_mic_en */ + { .gpio = TEGRA_GPIO_PX1, .enable = true }, }; static struct tegra_board_pinmux_conf common_conf = { - .maps = common_map, - .map_count = ARRAY_SIZE(common_map), + .pgs = common_pinmux, + .pg_count = ARRAY_SIZE(common_pinmux), + .gpios = common_gpio_table, + .gpio_count = ARRAY_SIZE(common_gpio_table), }; static struct tegra_board_pinmux_conf seaboard_conf = { - .maps = seaboard_map, - .map_count = ARRAY_SIZE(seaboard_map), + .pgs = seaboard_pinmux, + .pg_count = ARRAY_SIZE(seaboard_pinmux), + .drives = seaboard_drive_pinmux, + .drive_count = ARRAY_SIZE(seaboard_drive_pinmux), + .gpios = seaboard_gpio_table, + .gpio_count = ARRAY_SIZE(seaboard_gpio_table), }; static struct tegra_board_pinmux_conf ventana_conf = { - .maps = ventana_map, - .map_count = ARRAY_SIZE(ventana_map), + .pgs = ventana_pinmux, + .pg_count = ARRAY_SIZE(ventana_pinmux), + .gpios = ventana_gpio_table, + .gpio_count = ARRAY_SIZE(ventana_gpio_table), }; void seaboard_pinmux_init(void) diff --git a/trunk/arch/arm/mach-tegra/board-seaboard.c b/trunk/arch/arm/mach-tegra/board-seaboard.c index a0184fb44222..d669847f0485 100644 --- a/trunk/arch/arm/mach-tegra/board-seaboard.c +++ b/trunk/arch/arm/mach-tegra/board-seaboard.c @@ -24,7 +24,6 @@ #include #include #include -#include #include @@ -187,10 +186,20 @@ static struct i2c_board_info __initdata wm8903_device = { static int seaboard_ehci_init(void) { - struct tegra_ehci_platform_data *pdata; + int gpio_status; - pdata = tegra_ehci1_device.dev.platform_data; - pdata->vbus_gpio = TEGRA_GPIO_USB1; + gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1"); + if (gpio_status < 0) { + pr_err("VBUS_USB1 request GPIO FAILED\n"); + WARN_ON(1); + } + + gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1); + if (gpio_status < 0) { + pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n"); + WARN_ON(1); + } + gpio_set_value(TEGRA_GPIO_USB1, 1); platform_device_register(&tegra_ehci1_device); platform_device_register(&tegra_ehci3_device); @@ -200,6 +209,9 @@ static int seaboard_ehci_init(void) static void __init seaboard_i2c_init(void) { + gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018"); + gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ); + isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ); i2c_register_board_info(0, &isl29018_device, 1); @@ -249,6 +261,7 @@ static void __init tegra_kaen_init(void) debug_uart_platform_data[0].irq = INT_UARTB; seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE; + tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE); seaboard_common_init(); diff --git a/trunk/arch/arm/mach-tegra/board-trimslice-pinmux.c b/trunk/arch/arm/mach-tegra/board-trimslice-pinmux.c index 7b39511c0d4d..a21a2be57cb6 100644 --- a/trunk/arch/arm/mach-tegra/board-trimslice-pinmux.c +++ b/trunk/arch/arm/mach-tegra/board-trimslice-pinmux.c @@ -2,7 +2,6 @@ * arch/arm/mach-tegra/board-trimslice-pinmux.c * * Copyright (C) 2011 CompuLab, Ltd. - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -14,139 +13,150 @@ * GNU General Public License for more details. * */ +#include #include +#include +#include -#include "board-trimslice.h" +#include +#include + +#include "gpio-names.h" #include "board-pinmux.h" +#include "board-trimslice.h" + +static struct tegra_pingroup_config trimslice_pinmux[] = { + {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static struct tegra_gpio_table gpio_table[] = { + { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */ + { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */ -static struct pinctrl_map trimslice_map[] = { - TEGRA_MAP_MUXCONF("ata", "ide", none, tristate), - TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("atc", "nand", none, tristate), - TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven), - TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate), - TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate), - TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate), - TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven), - TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate), - TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate), - TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate), - TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven), - TEGRA_MAP_MUXCONF("dta", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dte", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven), - TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate), - TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven), - TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven), - TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven), - TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven), - TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven), - TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate), - TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate), - TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate), - TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate), - TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate), - TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate), - TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven), - TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven), - TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven), - TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven), - TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven), - TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven), - TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate), - TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate), - TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven), - TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate), - TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate), - TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate), - TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate), - TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate), - TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate), - TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven), - TEGRA_MAP_MUXCONF("uad", "irda", up, tristate), - TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate), - TEGRA_MAP_CONF("ck32", none, na), - TEGRA_MAP_CONF("ddrc", none, na), - TEGRA_MAP_CONF("pmca", none, na), - TEGRA_MAP_CONF("pmcb", none, na), - TEGRA_MAP_CONF("pmcc", none, na), - TEGRA_MAP_CONF("pmcd", none, na), - TEGRA_MAP_CONF("pmce", none, na), - TEGRA_MAP_CONF("xm2c", none, na), - TEGRA_MAP_CONF("xm2d", none, na), - TEGRA_MAP_CONF("ls", up, na), - TEGRA_MAP_CONF("lc", up, na), - TEGRA_MAP_CONF("ld17_0", down, na), - TEGRA_MAP_CONF("ld19_18", down, na), - TEGRA_MAP_CONF("ld21_20", down, na), - TEGRA_MAP_CONF("ld23_22", down, na), + { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */ + { .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */ }; static struct tegra_board_pinmux_conf conf = { - .maps = trimslice_map, - .map_count = ARRAY_SIZE(trimslice_map), + .pgs = trimslice_pinmux, + .pg_count = ARRAY_SIZE(trimslice_pinmux), + .gpios = gpio_table, + .gpio_count = ARRAY_SIZE(gpio_table), }; void trimslice_pinmux_init(void) diff --git a/trunk/arch/arm/mach-tegra/board-trimslice.c b/trunk/arch/arm/mach-tegra/board-trimslice.c index f6f5b6a11325..cd52820a3e37 100644 --- a/trunk/arch/arm/mach-tegra/board-trimslice.c +++ b/trunk/arch/arm/mach-tegra/board-trimslice.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -112,13 +111,19 @@ static void trimslice_i2c_init(void) static void trimslice_usb_init(void) { - struct tegra_ehci_platform_data *pdata; - - pdata = tegra_ehci1_device.dev.platform_data; - pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE; + int err; platform_device_register(&tegra_ehci3_device); + platform_device_register(&tegra_ehci2_device); + + err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH, + "usb1mode"); + if (err) { + pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err); + return; + } + platform_device_register(&tegra_ehci1_device); } diff --git a/trunk/arch/arm/mach-tegra/devices.c b/trunk/arch/arm/mach-tegra/devices.c index bd3035e0cea1..5f6b867e20b4 100644 --- a/trunk/arch/arm/mach-tegra/devices.c +++ b/trunk/arch/arm/mach-tegra/devices.c @@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = { }; struct platform_device tegra_pinmux_device = { - .name = "tegra20-pinctrl", + .name = "tegra-pinmux", .id = -1, .resource = pinmux_resource, .num_resources = ARRAY_SIZE(pinmux_resource), @@ -448,20 +448,17 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { struct tegra_ehci_platform_data tegra_ehci1_pdata = { .operating_mode = TEGRA_USB_OTG, .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, }; struct tegra_ehci_platform_data tegra_ehci2_pdata = { .phy_config = &tegra_ehci2_ulpi_phy_config, .operating_mode = TEGRA_USB_HOST, .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, }; struct tegra_ehci_platform_data tegra_ehci3_pdata = { .operating_mode = TEGRA_USB_HOST, .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, }; static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); diff --git a/trunk/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/trunk/arch/arm/mach-tegra/include/mach/gpio-tegra.h index a978b3cc3a8d..6140820555e1 100644 --- a/trunk/arch/arm/mach-tegra/include/mach/gpio-tegra.h +++ b/trunk/arch/arm/mach-tegra/include/mach/gpio-tegra.h @@ -25,4 +25,13 @@ #define TEGRA_NR_GPIOS INT_GPIO_NR +struct tegra_gpio_table { + int gpio; /* GPIO number */ + bool enable; /* Enable for GPIO at init? */ +}; + +void tegra_gpio_config(struct tegra_gpio_table *table, int num); +void tegra_gpio_enable(int gpio); +void tegra_gpio_disable(int gpio); + #endif diff --git a/trunk/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/trunk/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h new file mode 100644 index 000000000000..6a40c1dbab17 --- /dev/null +++ b/trunk/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h @@ -0,0 +1,184 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H +#define __MACH_TEGRA_PINMUX_TEGRA20_H + +enum tegra_pingroup { + TEGRA_PINGROUP_ATA = 0, + TEGRA_PINGROUP_ATB, + TEGRA_PINGROUP_ATC, + TEGRA_PINGROUP_ATD, + TEGRA_PINGROUP_ATE, + TEGRA_PINGROUP_CDEV1, + TEGRA_PINGROUP_CDEV2, + TEGRA_PINGROUP_CRTP, + TEGRA_PINGROUP_CSUS, + TEGRA_PINGROUP_DAP1, + TEGRA_PINGROUP_DAP2, + TEGRA_PINGROUP_DAP3, + TEGRA_PINGROUP_DAP4, + TEGRA_PINGROUP_DDC, + TEGRA_PINGROUP_DTA, + TEGRA_PINGROUP_DTB, + TEGRA_PINGROUP_DTC, + TEGRA_PINGROUP_DTD, + TEGRA_PINGROUP_DTE, + TEGRA_PINGROUP_DTF, + TEGRA_PINGROUP_GMA, + TEGRA_PINGROUP_GMB, + TEGRA_PINGROUP_GMC, + TEGRA_PINGROUP_GMD, + TEGRA_PINGROUP_GME, + TEGRA_PINGROUP_GPU, + TEGRA_PINGROUP_GPU7, + TEGRA_PINGROUP_GPV, + TEGRA_PINGROUP_HDINT, + TEGRA_PINGROUP_I2CP, + TEGRA_PINGROUP_IRRX, + TEGRA_PINGROUP_IRTX, + TEGRA_PINGROUP_KBCA, + TEGRA_PINGROUP_KBCB, + TEGRA_PINGROUP_KBCC, + TEGRA_PINGROUP_KBCD, + TEGRA_PINGROUP_KBCE, + TEGRA_PINGROUP_KBCF, + TEGRA_PINGROUP_LCSN, + TEGRA_PINGROUP_LD0, + TEGRA_PINGROUP_LD1, + TEGRA_PINGROUP_LD10, + TEGRA_PINGROUP_LD11, + TEGRA_PINGROUP_LD12, + TEGRA_PINGROUP_LD13, + TEGRA_PINGROUP_LD14, + TEGRA_PINGROUP_LD15, + TEGRA_PINGROUP_LD16, + TEGRA_PINGROUP_LD17, + TEGRA_PINGROUP_LD2, + TEGRA_PINGROUP_LD3, + TEGRA_PINGROUP_LD4, + TEGRA_PINGROUP_LD5, + TEGRA_PINGROUP_LD6, + TEGRA_PINGROUP_LD7, + TEGRA_PINGROUP_LD8, + TEGRA_PINGROUP_LD9, + TEGRA_PINGROUP_LDC, + TEGRA_PINGROUP_LDI, + TEGRA_PINGROUP_LHP0, + TEGRA_PINGROUP_LHP1, + TEGRA_PINGROUP_LHP2, + TEGRA_PINGROUP_LHS, + TEGRA_PINGROUP_LM0, + TEGRA_PINGROUP_LM1, + TEGRA_PINGROUP_LPP, + TEGRA_PINGROUP_LPW0, + TEGRA_PINGROUP_LPW1, + TEGRA_PINGROUP_LPW2, + TEGRA_PINGROUP_LSC0, + TEGRA_PINGROUP_LSC1, + TEGRA_PINGROUP_LSCK, + TEGRA_PINGROUP_LSDA, + TEGRA_PINGROUP_LSDI, + TEGRA_PINGROUP_LSPI, + TEGRA_PINGROUP_LVP0, + TEGRA_PINGROUP_LVP1, + TEGRA_PINGROUP_LVS, + TEGRA_PINGROUP_OWC, + TEGRA_PINGROUP_PMC, + TEGRA_PINGROUP_PTA, + TEGRA_PINGROUP_RM, + TEGRA_PINGROUP_SDB, + TEGRA_PINGROUP_SDC, + TEGRA_PINGROUP_SDD, + TEGRA_PINGROUP_SDIO1, + TEGRA_PINGROUP_SLXA, + TEGRA_PINGROUP_SLXC, + TEGRA_PINGROUP_SLXD, + TEGRA_PINGROUP_SLXK, + TEGRA_PINGROUP_SPDI, + TEGRA_PINGROUP_SPDO, + TEGRA_PINGROUP_SPIA, + TEGRA_PINGROUP_SPIB, + TEGRA_PINGROUP_SPIC, + TEGRA_PINGROUP_SPID, + TEGRA_PINGROUP_SPIE, + TEGRA_PINGROUP_SPIF, + TEGRA_PINGROUP_SPIG, + TEGRA_PINGROUP_SPIH, + TEGRA_PINGROUP_UAA, + TEGRA_PINGROUP_UAB, + TEGRA_PINGROUP_UAC, + TEGRA_PINGROUP_UAD, + TEGRA_PINGROUP_UCA, + TEGRA_PINGROUP_UCB, + TEGRA_PINGROUP_UDA, + /* these pin groups only have pullup and pull down control */ + TEGRA_PINGROUP_CK32, + TEGRA_PINGROUP_DDRC, + TEGRA_PINGROUP_PMCA, + TEGRA_PINGROUP_PMCB, + TEGRA_PINGROUP_PMCC, + TEGRA_PINGROUP_PMCD, + TEGRA_PINGROUP_PMCE, + TEGRA_PINGROUP_XM2C, + TEGRA_PINGROUP_XM2D, + TEGRA_MAX_PINGROUP, +}; + +enum tegra_drive_pingroup { + TEGRA_DRIVE_PINGROUP_AO1 = 0, + TEGRA_DRIVE_PINGROUP_AO2, + TEGRA_DRIVE_PINGROUP_AT1, + TEGRA_DRIVE_PINGROUP_AT2, + TEGRA_DRIVE_PINGROUP_CDEV1, + TEGRA_DRIVE_PINGROUP_CDEV2, + TEGRA_DRIVE_PINGROUP_CSUS, + TEGRA_DRIVE_PINGROUP_DAP1, + TEGRA_DRIVE_PINGROUP_DAP2, + TEGRA_DRIVE_PINGROUP_DAP3, + TEGRA_DRIVE_PINGROUP_DAP4, + TEGRA_DRIVE_PINGROUP_DBG, + TEGRA_DRIVE_PINGROUP_LCD1, + TEGRA_DRIVE_PINGROUP_LCD2, + TEGRA_DRIVE_PINGROUP_SDMMC2, + TEGRA_DRIVE_PINGROUP_SDMMC3, + TEGRA_DRIVE_PINGROUP_SPI, + TEGRA_DRIVE_PINGROUP_UAA, + TEGRA_DRIVE_PINGROUP_UAB, + TEGRA_DRIVE_PINGROUP_UART2, + TEGRA_DRIVE_PINGROUP_UART3, + TEGRA_DRIVE_PINGROUP_VI1, + TEGRA_DRIVE_PINGROUP_VI2, + TEGRA_DRIVE_PINGROUP_XM2A, + TEGRA_DRIVE_PINGROUP_XM2C, + TEGRA_DRIVE_PINGROUP_XM2D, + TEGRA_DRIVE_PINGROUP_XM2CLK, + TEGRA_DRIVE_PINGROUP_MEMCOMP, + TEGRA_DRIVE_PINGROUP_SDIO1, + TEGRA_DRIVE_PINGROUP_CRT, + TEGRA_DRIVE_PINGROUP_DDC, + TEGRA_DRIVE_PINGROUP_GMA, + TEGRA_DRIVE_PINGROUP_GMB, + TEGRA_DRIVE_PINGROUP_GMC, + TEGRA_DRIVE_PINGROUP_GMD, + TEGRA_DRIVE_PINGROUP_GME, + TEGRA_DRIVE_PINGROUP_OWR, + TEGRA_DRIVE_PINGROUP_UAD, + TEGRA_MAX_DRIVE_PINGROUP, +}; + +#endif + diff --git a/trunk/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/trunk/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h new file mode 100644 index 000000000000..c1aee3eb2df1 --- /dev/null +++ b/trunk/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h @@ -0,0 +1,320 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h + * + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010,2011 Nvidia, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H +#define __MACH_TEGRA_PINMUX_TEGRA30_H + +enum tegra_pingroup { + TEGRA_PINGROUP_ULPI_DATA0 = 0, + TEGRA_PINGROUP_ULPI_DATA1, + TEGRA_PINGROUP_ULPI_DATA2, + TEGRA_PINGROUP_ULPI_DATA3, + TEGRA_PINGROUP_ULPI_DATA4, + TEGRA_PINGROUP_ULPI_DATA5, + TEGRA_PINGROUP_ULPI_DATA6, + TEGRA_PINGROUP_ULPI_DATA7, + TEGRA_PINGROUP_ULPI_CLK, + TEGRA_PINGROUP_ULPI_DIR, + TEGRA_PINGROUP_ULPI_NXT, + TEGRA_PINGROUP_ULPI_STP, + TEGRA_PINGROUP_DAP3_FS, + TEGRA_PINGROUP_DAP3_DIN, + TEGRA_PINGROUP_DAP3_DOUT, + TEGRA_PINGROUP_DAP3_SCLK, + TEGRA_PINGROUP_GPIO_PV0, + TEGRA_PINGROUP_GPIO_PV1, + TEGRA_PINGROUP_SDMMC1_CLK, + TEGRA_PINGROUP_SDMMC1_CMD, + TEGRA_PINGROUP_SDMMC1_DAT3, + TEGRA_PINGROUP_SDMMC1_DAT2, + TEGRA_PINGROUP_SDMMC1_DAT1, + TEGRA_PINGROUP_SDMMC1_DAT0, + TEGRA_PINGROUP_GPIO_PV2, + TEGRA_PINGROUP_GPIO_PV3, + TEGRA_PINGROUP_CLK2_OUT, + TEGRA_PINGROUP_CLK2_REQ, + TEGRA_PINGROUP_LCD_PWR1, + TEGRA_PINGROUP_LCD_PWR2, + TEGRA_PINGROUP_LCD_SDIN, + TEGRA_PINGROUP_LCD_SDOUT, + TEGRA_PINGROUP_LCD_WR_N, + TEGRA_PINGROUP_LCD_CS0_N, + TEGRA_PINGROUP_LCD_DC0, + TEGRA_PINGROUP_LCD_SCK, + TEGRA_PINGROUP_LCD_PWR0, + TEGRA_PINGROUP_LCD_PCLK, + TEGRA_PINGROUP_LCD_DE, + TEGRA_PINGROUP_LCD_HSYNC, + TEGRA_PINGROUP_LCD_VSYNC, + TEGRA_PINGROUP_LCD_D0, + TEGRA_PINGROUP_LCD_D1, + TEGRA_PINGROUP_LCD_D2, + TEGRA_PINGROUP_LCD_D3, + TEGRA_PINGROUP_LCD_D4, + TEGRA_PINGROUP_LCD_D5, + TEGRA_PINGROUP_LCD_D6, + TEGRA_PINGROUP_LCD_D7, + TEGRA_PINGROUP_LCD_D8, + TEGRA_PINGROUP_LCD_D9, + TEGRA_PINGROUP_LCD_D10, + TEGRA_PINGROUP_LCD_D11, + TEGRA_PINGROUP_LCD_D12, + TEGRA_PINGROUP_LCD_D13, + TEGRA_PINGROUP_LCD_D14, + TEGRA_PINGROUP_LCD_D15, + TEGRA_PINGROUP_LCD_D16, + TEGRA_PINGROUP_LCD_D17, + TEGRA_PINGROUP_LCD_D18, + TEGRA_PINGROUP_LCD_D19, + TEGRA_PINGROUP_LCD_D20, + TEGRA_PINGROUP_LCD_D21, + TEGRA_PINGROUP_LCD_D22, + TEGRA_PINGROUP_LCD_D23, + TEGRA_PINGROUP_LCD_CS1_N, + TEGRA_PINGROUP_LCD_M1, + TEGRA_PINGROUP_LCD_DC1, + TEGRA_PINGROUP_HDMI_INT, + TEGRA_PINGROUP_DDC_SCL, + TEGRA_PINGROUP_DDC_SDA, + TEGRA_PINGROUP_CRT_HSYNC, + TEGRA_PINGROUP_CRT_VSYNC, + TEGRA_PINGROUP_VI_D0, + TEGRA_PINGROUP_VI_D1, + TEGRA_PINGROUP_VI_D2, + TEGRA_PINGROUP_VI_D3, + TEGRA_PINGROUP_VI_D4, + TEGRA_PINGROUP_VI_D5, + TEGRA_PINGROUP_VI_D6, + TEGRA_PINGROUP_VI_D7, + TEGRA_PINGROUP_VI_D8, + TEGRA_PINGROUP_VI_D9, + TEGRA_PINGROUP_VI_D10, + TEGRA_PINGROUP_VI_D11, + TEGRA_PINGROUP_VI_PCLK, + TEGRA_PINGROUP_VI_MCLK, + TEGRA_PINGROUP_VI_VSYNC, + TEGRA_PINGROUP_VI_HSYNC, + TEGRA_PINGROUP_UART2_RXD, + TEGRA_PINGROUP_UART2_TXD, + TEGRA_PINGROUP_UART2_RTS_N, + TEGRA_PINGROUP_UART2_CTS_N, + TEGRA_PINGROUP_UART3_TXD, + TEGRA_PINGROUP_UART3_RXD, + TEGRA_PINGROUP_UART3_CTS_N, + TEGRA_PINGROUP_UART3_RTS_N, + TEGRA_PINGROUP_GPIO_PU0, + TEGRA_PINGROUP_GPIO_PU1, + TEGRA_PINGROUP_GPIO_PU2, + TEGRA_PINGROUP_GPIO_PU3, + TEGRA_PINGROUP_GPIO_PU4, + TEGRA_PINGROUP_GPIO_PU5, + TEGRA_PINGROUP_GPIO_PU6, + TEGRA_PINGROUP_GEN1_I2C_SDA, + TEGRA_PINGROUP_GEN1_I2C_SCL, + TEGRA_PINGROUP_DAP4_FS, + TEGRA_PINGROUP_DAP4_DIN, + TEGRA_PINGROUP_DAP4_DOUT, + TEGRA_PINGROUP_DAP4_SCLK, + TEGRA_PINGROUP_CLK3_OUT, + TEGRA_PINGROUP_CLK3_REQ, + TEGRA_PINGROUP_GMI_WP_N, + TEGRA_PINGROUP_GMI_IORDY, + TEGRA_PINGROUP_GMI_WAIT, + TEGRA_PINGROUP_GMI_ADV_N, + TEGRA_PINGROUP_GMI_CLK, + TEGRA_PINGROUP_GMI_CS0_N, + TEGRA_PINGROUP_GMI_CS1_N, + TEGRA_PINGROUP_GMI_CS2_N, + TEGRA_PINGROUP_GMI_CS3_N, + TEGRA_PINGROUP_GMI_CS4_N, + TEGRA_PINGROUP_GMI_CS6_N, + TEGRA_PINGROUP_GMI_CS7_N, + TEGRA_PINGROUP_GMI_AD0, + TEGRA_PINGROUP_GMI_AD1, + TEGRA_PINGROUP_GMI_AD2, + TEGRA_PINGROUP_GMI_AD3, + TEGRA_PINGROUP_GMI_AD4, + TEGRA_PINGROUP_GMI_AD5, + TEGRA_PINGROUP_GMI_AD6, + TEGRA_PINGROUP_GMI_AD7, + TEGRA_PINGROUP_GMI_AD8, + TEGRA_PINGROUP_GMI_AD9, + TEGRA_PINGROUP_GMI_AD10, + TEGRA_PINGROUP_GMI_AD11, + TEGRA_PINGROUP_GMI_AD12, + TEGRA_PINGROUP_GMI_AD13, + TEGRA_PINGROUP_GMI_AD14, + TEGRA_PINGROUP_GMI_AD15, + TEGRA_PINGROUP_GMI_A16, + TEGRA_PINGROUP_GMI_A17, + TEGRA_PINGROUP_GMI_A18, + TEGRA_PINGROUP_GMI_A19, + TEGRA_PINGROUP_GMI_WR_N, + TEGRA_PINGROUP_GMI_OE_N, + TEGRA_PINGROUP_GMI_DQS, + TEGRA_PINGROUP_GMI_RST_N, + TEGRA_PINGROUP_GEN2_I2C_SCL, + TEGRA_PINGROUP_GEN2_I2C_SDA, + TEGRA_PINGROUP_SDMMC4_CLK, + TEGRA_PINGROUP_SDMMC4_CMD, + TEGRA_PINGROUP_SDMMC4_DAT0, + TEGRA_PINGROUP_SDMMC4_DAT1, + TEGRA_PINGROUP_SDMMC4_DAT2, + TEGRA_PINGROUP_SDMMC4_DAT3, + TEGRA_PINGROUP_SDMMC4_DAT4, + TEGRA_PINGROUP_SDMMC4_DAT5, + TEGRA_PINGROUP_SDMMC4_DAT6, + TEGRA_PINGROUP_SDMMC4_DAT7, + TEGRA_PINGROUP_SDMMC4_RST_N, + TEGRA_PINGROUP_CAM_MCLK, + TEGRA_PINGROUP_GPIO_PCC1, + TEGRA_PINGROUP_GPIO_PBB0, + TEGRA_PINGROUP_CAM_I2C_SCL, + TEGRA_PINGROUP_CAM_I2C_SDA, + TEGRA_PINGROUP_GPIO_PBB3, + TEGRA_PINGROUP_GPIO_PBB4, + TEGRA_PINGROUP_GPIO_PBB5, + TEGRA_PINGROUP_GPIO_PBB6, + TEGRA_PINGROUP_GPIO_PBB7, + TEGRA_PINGROUP_GPIO_PCC2, + TEGRA_PINGROUP_JTAG_RTCK, + TEGRA_PINGROUP_PWR_I2C_SCL, + TEGRA_PINGROUP_PWR_I2C_SDA, + TEGRA_PINGROUP_KB_ROW0, + TEGRA_PINGROUP_KB_ROW1, + TEGRA_PINGROUP_KB_ROW2, + TEGRA_PINGROUP_KB_ROW3, + TEGRA_PINGROUP_KB_ROW4, + TEGRA_PINGROUP_KB_ROW5, + TEGRA_PINGROUP_KB_ROW6, + TEGRA_PINGROUP_KB_ROW7, + TEGRA_PINGROUP_KB_ROW8, + TEGRA_PINGROUP_KB_ROW9, + TEGRA_PINGROUP_KB_ROW10, + TEGRA_PINGROUP_KB_ROW11, + TEGRA_PINGROUP_KB_ROW12, + TEGRA_PINGROUP_KB_ROW13, + TEGRA_PINGROUP_KB_ROW14, + TEGRA_PINGROUP_KB_ROW15, + TEGRA_PINGROUP_KB_COL0, + TEGRA_PINGROUP_KB_COL1, + TEGRA_PINGROUP_KB_COL2, + TEGRA_PINGROUP_KB_COL3, + TEGRA_PINGROUP_KB_COL4, + TEGRA_PINGROUP_KB_COL5, + TEGRA_PINGROUP_KB_COL6, + TEGRA_PINGROUP_KB_COL7, + TEGRA_PINGROUP_CLK_32K_OUT, + TEGRA_PINGROUP_SYS_CLK_REQ, + TEGRA_PINGROUP_CORE_PWR_REQ, + TEGRA_PINGROUP_CPU_PWR_REQ, + TEGRA_PINGROUP_PWR_INT_N, + TEGRA_PINGROUP_CLK_32K_IN, + TEGRA_PINGROUP_OWR, + TEGRA_PINGROUP_DAP1_FS, + TEGRA_PINGROUP_DAP1_DIN, + TEGRA_PINGROUP_DAP1_DOUT, + TEGRA_PINGROUP_DAP1_SCLK, + TEGRA_PINGROUP_CLK1_REQ, + TEGRA_PINGROUP_CLK1_OUT, + TEGRA_PINGROUP_SPDIF_IN, + TEGRA_PINGROUP_SPDIF_OUT, + TEGRA_PINGROUP_DAP2_FS, + TEGRA_PINGROUP_DAP2_DIN, + TEGRA_PINGROUP_DAP2_DOUT, + TEGRA_PINGROUP_DAP2_SCLK, + TEGRA_PINGROUP_SPI2_MOSI, + TEGRA_PINGROUP_SPI2_MISO, + TEGRA_PINGROUP_SPI2_CS0_N, + TEGRA_PINGROUP_SPI2_SCK, + TEGRA_PINGROUP_SPI1_MOSI, + TEGRA_PINGROUP_SPI1_SCK, + TEGRA_PINGROUP_SPI1_CS0_N, + TEGRA_PINGROUP_SPI1_MISO, + TEGRA_PINGROUP_SPI2_CS1_N, + TEGRA_PINGROUP_SPI2_CS2_N, + TEGRA_PINGROUP_SDMMC3_CLK, + TEGRA_PINGROUP_SDMMC3_CMD, + TEGRA_PINGROUP_SDMMC3_DAT0, + TEGRA_PINGROUP_SDMMC3_DAT1, + TEGRA_PINGROUP_SDMMC3_DAT2, + TEGRA_PINGROUP_SDMMC3_DAT3, + TEGRA_PINGROUP_SDMMC3_DAT4, + TEGRA_PINGROUP_SDMMC3_DAT5, + TEGRA_PINGROUP_SDMMC3_DAT6, + TEGRA_PINGROUP_SDMMC3_DAT7, + TEGRA_PINGROUP_PEX_L0_PRSNT_N, + TEGRA_PINGROUP_PEX_L0_RST_N, + TEGRA_PINGROUP_PEX_L0_CLKREQ_N, + TEGRA_PINGROUP_PEX_WAKE_N, + TEGRA_PINGROUP_PEX_L1_PRSNT_N, + TEGRA_PINGROUP_PEX_L1_RST_N, + TEGRA_PINGROUP_PEX_L1_CLKREQ_N, + TEGRA_PINGROUP_PEX_L2_PRSNT_N, + TEGRA_PINGROUP_PEX_L2_RST_N, + TEGRA_PINGROUP_PEX_L2_CLKREQ_N, + TEGRA_PINGROUP_HDMI_CEC, + TEGRA_MAX_PINGROUP, +}; + +enum tegra_drive_pingroup { + TEGRA_DRIVE_PINGROUP_AO1 = 0, + TEGRA_DRIVE_PINGROUP_AO2, + TEGRA_DRIVE_PINGROUP_AT1, + TEGRA_DRIVE_PINGROUP_AT2, + TEGRA_DRIVE_PINGROUP_AT3, + TEGRA_DRIVE_PINGROUP_AT4, + TEGRA_DRIVE_PINGROUP_AT5, + TEGRA_DRIVE_PINGROUP_CDEV1, + TEGRA_DRIVE_PINGROUP_CDEV2, + TEGRA_DRIVE_PINGROUP_CSUS, + TEGRA_DRIVE_PINGROUP_DAP1, + TEGRA_DRIVE_PINGROUP_DAP2, + TEGRA_DRIVE_PINGROUP_DAP3, + TEGRA_DRIVE_PINGROUP_DAP4, + TEGRA_DRIVE_PINGROUP_DBG, + TEGRA_DRIVE_PINGROUP_LCD1, + TEGRA_DRIVE_PINGROUP_LCD2, + TEGRA_DRIVE_PINGROUP_SDIO2, + TEGRA_DRIVE_PINGROUP_SDIO3, + TEGRA_DRIVE_PINGROUP_SPI, + TEGRA_DRIVE_PINGROUP_UAA, + TEGRA_DRIVE_PINGROUP_UAB, + TEGRA_DRIVE_PINGROUP_UART2, + TEGRA_DRIVE_PINGROUP_UART3, + TEGRA_DRIVE_PINGROUP_VI1, + TEGRA_DRIVE_PINGROUP_SDIO1, + TEGRA_DRIVE_PINGROUP_CRT, + TEGRA_DRIVE_PINGROUP_DDC, + TEGRA_DRIVE_PINGROUP_GMA, + TEGRA_DRIVE_PINGROUP_GMB, + TEGRA_DRIVE_PINGROUP_GMC, + TEGRA_DRIVE_PINGROUP_GMD, + TEGRA_DRIVE_PINGROUP_GME, + TEGRA_DRIVE_PINGROUP_GMF, + TEGRA_DRIVE_PINGROUP_GMG, + TEGRA_DRIVE_PINGROUP_GMH, + TEGRA_DRIVE_PINGROUP_OWR, + TEGRA_DRIVE_PINGROUP_UAD, + TEGRA_DRIVE_PINGROUP_GPV, + TEGRA_DRIVE_PINGROUP_DEV3, + TEGRA_DRIVE_PINGROUP_CEC, + TEGRA_MAX_DRIVE_PINGROUP, +}; + +#endif + diff --git a/trunk/arch/arm/mach-tegra/include/mach/pinmux.h b/trunk/arch/arm/mach-tegra/include/mach/pinmux.h new file mode 100644 index 000000000000..055f1792c8ff --- /dev/null +++ b/trunk/arch/arm/mach-tegra/include/mach/pinmux.h @@ -0,0 +1,302 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux.h + * + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010,2011 Nvidia, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_H +#define __MACH_TEGRA_PINMUX_H + +enum tegra_mux_func { + TEGRA_MUX_RSVD = 0x8000, + TEGRA_MUX_RSVD1 = 0x8000, + TEGRA_MUX_RSVD2 = 0x8001, + TEGRA_MUX_RSVD3 = 0x8002, + TEGRA_MUX_RSVD4 = 0x8003, + TEGRA_MUX_INVALID = 0x4000, + TEGRA_MUX_NONE = -1, + TEGRA_MUX_AHB_CLK, + TEGRA_MUX_APB_CLK, + TEGRA_MUX_AUDIO_SYNC, + TEGRA_MUX_CRT, + TEGRA_MUX_DAP1, + TEGRA_MUX_DAP2, + TEGRA_MUX_DAP3, + TEGRA_MUX_DAP4, + TEGRA_MUX_DAP5, + TEGRA_MUX_DISPLAYA, + TEGRA_MUX_DISPLAYB, + TEGRA_MUX_EMC_TEST0_DLL, + TEGRA_MUX_EMC_TEST1_DLL, + TEGRA_MUX_GMI, + TEGRA_MUX_GMI_INT, + TEGRA_MUX_HDMI, + TEGRA_MUX_I2C, + TEGRA_MUX_I2C2, + TEGRA_MUX_I2C3, + TEGRA_MUX_IDE, + TEGRA_MUX_IRDA, + TEGRA_MUX_KBC, + TEGRA_MUX_MIO, + TEGRA_MUX_MIPI_HS, + TEGRA_MUX_NAND, + TEGRA_MUX_OSC, + TEGRA_MUX_OWR, + TEGRA_MUX_PCIE, + TEGRA_MUX_PLLA_OUT, + TEGRA_MUX_PLLC_OUT1, + TEGRA_MUX_PLLM_OUT1, + TEGRA_MUX_PLLP_OUT2, + TEGRA_MUX_PLLP_OUT3, + TEGRA_MUX_PLLP_OUT4, + TEGRA_MUX_PWM, + TEGRA_MUX_PWR_INTR, + TEGRA_MUX_PWR_ON, + TEGRA_MUX_RTCK, + TEGRA_MUX_SDIO1, + TEGRA_MUX_SDIO2, + TEGRA_MUX_SDIO3, + TEGRA_MUX_SDIO4, + TEGRA_MUX_SFLASH, + TEGRA_MUX_SPDIF, + TEGRA_MUX_SPI1, + TEGRA_MUX_SPI2, + TEGRA_MUX_SPI2_ALT, + TEGRA_MUX_SPI3, + TEGRA_MUX_SPI4, + TEGRA_MUX_TRACE, + TEGRA_MUX_TWC, + TEGRA_MUX_UARTA, + TEGRA_MUX_UARTB, + TEGRA_MUX_UARTC, + TEGRA_MUX_UARTD, + TEGRA_MUX_UARTE, + TEGRA_MUX_ULPI, + TEGRA_MUX_VI, + TEGRA_MUX_VI_SENSOR_CLK, + TEGRA_MUX_XIO, + TEGRA_MUX_BLINK, + TEGRA_MUX_CEC, + TEGRA_MUX_CLK12, + TEGRA_MUX_DAP, + TEGRA_MUX_DAPSDMMC2, + TEGRA_MUX_DDR, + TEGRA_MUX_DEV3, + TEGRA_MUX_DTV, + TEGRA_MUX_VI_ALT1, + TEGRA_MUX_VI_ALT2, + TEGRA_MUX_VI_ALT3, + TEGRA_MUX_EMC_DLL, + TEGRA_MUX_EXTPERIPH1, + TEGRA_MUX_EXTPERIPH2, + TEGRA_MUX_EXTPERIPH3, + TEGRA_MUX_GMI_ALT, + TEGRA_MUX_HDA, + TEGRA_MUX_HSI, + TEGRA_MUX_I2C4, + TEGRA_MUX_I2C5, + TEGRA_MUX_I2CPWR, + TEGRA_MUX_I2S0, + TEGRA_MUX_I2S1, + TEGRA_MUX_I2S2, + TEGRA_MUX_I2S3, + TEGRA_MUX_I2S4, + TEGRA_MUX_NAND_ALT, + TEGRA_MUX_POPSDIO4, + TEGRA_MUX_POPSDMMC4, + TEGRA_MUX_PWM0, + TEGRA_MUX_PWM1, + TEGRA_MUX_PWM2, + TEGRA_MUX_PWM3, + TEGRA_MUX_SATA, + TEGRA_MUX_SPI5, + TEGRA_MUX_SPI6, + TEGRA_MUX_SYSCLK, + TEGRA_MUX_VGP1, + TEGRA_MUX_VGP2, + TEGRA_MUX_VGP3, + TEGRA_MUX_VGP4, + TEGRA_MUX_VGP5, + TEGRA_MUX_VGP6, + TEGRA_MUX_SAFE, + TEGRA_MAX_MUX, +}; + +enum tegra_pullupdown { + TEGRA_PUPD_NORMAL = 0, + TEGRA_PUPD_PULL_DOWN, + TEGRA_PUPD_PULL_UP, +}; + +enum tegra_tristate { + TEGRA_TRI_NORMAL = 0, + TEGRA_TRI_TRISTATE = 1, +}; + +enum tegra_pin_io { + TEGRA_PIN_OUTPUT = 0, + TEGRA_PIN_INPUT = 1, +}; + +enum tegra_vddio { + TEGRA_VDDIO_BB = 0, + TEGRA_VDDIO_LCD, + TEGRA_VDDIO_VI, + TEGRA_VDDIO_UART, + TEGRA_VDDIO_DDR, + TEGRA_VDDIO_NAND, + TEGRA_VDDIO_SYS, + TEGRA_VDDIO_AUDIO, + TEGRA_VDDIO_SD, + TEGRA_VDDIO_CAM, + TEGRA_VDDIO_GMI, + TEGRA_VDDIO_PEXCTL, + TEGRA_VDDIO_SDMMC1, + TEGRA_VDDIO_SDMMC3, + TEGRA_VDDIO_SDMMC4, +}; + +struct tegra_pingroup_config { + int pingroup; + enum tegra_mux_func func; + enum tegra_pullupdown pupd; + enum tegra_tristate tristate; +}; + +enum tegra_slew { + TEGRA_SLEW_FASTEST = 0, + TEGRA_SLEW_FAST, + TEGRA_SLEW_SLOW, + TEGRA_SLEW_SLOWEST, + TEGRA_MAX_SLEW, +}; + +enum tegra_pull_strength { + TEGRA_PULL_0 = 0, + TEGRA_PULL_1, + TEGRA_PULL_2, + TEGRA_PULL_3, + TEGRA_PULL_4, + TEGRA_PULL_5, + TEGRA_PULL_6, + TEGRA_PULL_7, + TEGRA_PULL_8, + TEGRA_PULL_9, + TEGRA_PULL_10, + TEGRA_PULL_11, + TEGRA_PULL_12, + TEGRA_PULL_13, + TEGRA_PULL_14, + TEGRA_PULL_15, + TEGRA_PULL_16, + TEGRA_PULL_17, + TEGRA_PULL_18, + TEGRA_PULL_19, + TEGRA_PULL_20, + TEGRA_PULL_21, + TEGRA_PULL_22, + TEGRA_PULL_23, + TEGRA_PULL_24, + TEGRA_PULL_25, + TEGRA_PULL_26, + TEGRA_PULL_27, + TEGRA_PULL_28, + TEGRA_PULL_29, + TEGRA_PULL_30, + TEGRA_PULL_31, + TEGRA_MAX_PULL, +}; + +enum tegra_drive { + TEGRA_DRIVE_DIV_8 = 0, + TEGRA_DRIVE_DIV_4, + TEGRA_DRIVE_DIV_2, + TEGRA_DRIVE_DIV_1, + TEGRA_MAX_DRIVE, +}; + +enum tegra_hsm { + TEGRA_HSM_DISABLE = 0, + TEGRA_HSM_ENABLE, +}; + +enum tegra_schmitt { + TEGRA_SCHMITT_DISABLE = 0, + TEGRA_SCHMITT_ENABLE, +}; + +struct tegra_drive_pingroup_config { + int pingroup; + enum tegra_hsm hsm; + enum tegra_schmitt schmitt; + enum tegra_drive drive; + enum tegra_pull_strength pull_down; + enum tegra_pull_strength pull_up; + enum tegra_slew slew_rising; + enum tegra_slew slew_falling; +}; + +struct tegra_drive_pingroup_desc { + const char *name; + s16 reg_bank; + s16 reg; +}; + +struct tegra_pingroup_desc { + const char *name; + int funcs[4]; + int func_safe; + int vddio; + enum tegra_pin_io io_default; + s16 tri_bank; /* Register bank the tri_reg exists within */ + s16 mux_bank; /* Register bank the mux_reg exists within */ + s16 pupd_bank; /* Register bank the pupd_reg exists within */ + s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */ + s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */ + s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */ + s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ + s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ + s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ + s8 lock_bit; /* offset of the LOCK bit into mux register bit */ + s8 od_bit; /* offset of the OD bit into mux register bit */ + s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */ +}; + +typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max); + +void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, + const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); + +void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, + const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); + +int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate); +int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd); + +void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, + int len); + +void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, + int len); +void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config, + int len); +void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config, + int len); +void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config, + int len, enum tegra_tristate tristate); +void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, + int len, enum tegra_pullupdown pupd); +#endif diff --git a/trunk/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/trunk/arch/arm/mach-tegra/pinmux-tegra20-tables.c new file mode 100644 index 000000000000..734add1280b7 --- /dev/null +++ b/trunk/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -0,0 +1,244 @@ +/* + * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c + * + * Common pinmux configurations for Tegra20 SoCs + * + * Copyright (C) 2010 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define TRISTATE_REG_A 0x14 +#define PIN_MUX_CTL_REG_A 0x80 +#define PULLUPDOWN_REG_A 0xa0 +#define PINGROUP_REG_A 0x868 + +#define DRIVE_PINGROUP(pg_name, r) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg_bank = 3, \ + .reg = ((r) - PINGROUP_REG_A) \ + } + +static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { + DRIVE_PINGROUP(AO1, 0x868), + DRIVE_PINGROUP(AO2, 0x86c), + DRIVE_PINGROUP(AT1, 0x870), + DRIVE_PINGROUP(AT2, 0x874), + DRIVE_PINGROUP(CDEV1, 0x878), + DRIVE_PINGROUP(CDEV2, 0x87c), + DRIVE_PINGROUP(CSUS, 0x880), + DRIVE_PINGROUP(DAP1, 0x884), + DRIVE_PINGROUP(DAP2, 0x888), + DRIVE_PINGROUP(DAP3, 0x88c), + DRIVE_PINGROUP(DAP4, 0x890), + DRIVE_PINGROUP(DBG, 0x894), + DRIVE_PINGROUP(LCD1, 0x898), + DRIVE_PINGROUP(LCD2, 0x89c), + DRIVE_PINGROUP(SDMMC2, 0x8a0), + DRIVE_PINGROUP(SDMMC3, 0x8a4), + DRIVE_PINGROUP(SPI, 0x8a8), + DRIVE_PINGROUP(UAA, 0x8ac), + DRIVE_PINGROUP(UAB, 0x8b0), + DRIVE_PINGROUP(UART2, 0x8b4), + DRIVE_PINGROUP(UART3, 0x8b8), + DRIVE_PINGROUP(VI1, 0x8bc), + DRIVE_PINGROUP(VI2, 0x8c0), + DRIVE_PINGROUP(XM2A, 0x8c4), + DRIVE_PINGROUP(XM2C, 0x8c8), + DRIVE_PINGROUP(XM2D, 0x8cc), + DRIVE_PINGROUP(XM2CLK, 0x8d0), + DRIVE_PINGROUP(MEMCOMP, 0x8d4), + DRIVE_PINGROUP(SDIO1, 0x8e0), + DRIVE_PINGROUP(CRT, 0x8ec), + DRIVE_PINGROUP(DDC, 0x8f0), + DRIVE_PINGROUP(GMA, 0x8f4), + DRIVE_PINGROUP(GMB, 0x8f8), + DRIVE_PINGROUP(GMC, 0x8fc), + DRIVE_PINGROUP(GMD, 0x900), + DRIVE_PINGROUP(GME, 0x904), + DRIVE_PINGROUP(OWR, 0x908), + DRIVE_PINGROUP(UAD, 0x90c), +}; + +#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \ + tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \ + [TEGRA_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .vddio = TEGRA_VDDIO_ ## vdd, \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_ ## f2, \ + TEGRA_MUX_ ## f3, \ + }, \ + .func_safe = TEGRA_MUX_ ## f_safe, \ + .tri_bank = 0, \ + .tri_reg = ((tri_r) - TRISTATE_REG_A), \ + .tri_bit = tri_b, \ + .mux_bank = 1, \ + .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \ + .mux_bit = mux_b, \ + .pupd_bank = 2, \ + .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ + .pupd_bit = pupd_b, \ + .lock_bit = -1, \ + .od_bit = -1, \ + .ioreset_bit = -1, \ + .io_default = -1, \ + } + +static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { + PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), + PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), + PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), + PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6), + PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8), + PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0), + PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2), + PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24), + PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24), + PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10), + PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12), + PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14), + PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16), + PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28), + PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18), + PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20), + PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22), + PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24), + PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26), + PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28), + PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20), + PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22), + PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24), + PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26), + PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24), + PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20), + PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6), + PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30), + PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22), + PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2), + PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22), + PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20), + PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8), + PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10), + PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12), + PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14), + PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2), + PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0), + PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20), + PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12), + PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12), + PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12), + PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12), + PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12), + PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12), + PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12), + PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12), + PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12), + PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12), + PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12), + PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12), + PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12), + PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12), + PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12), + PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12), + PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12), + PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12), + PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20), + PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18), + PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16), + PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14), + PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14), + PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22), + PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22), + PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22), + PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18), + PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20), + PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20), + PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20), + PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22), + PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20), + PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20), + PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20), + PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20), + PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22), + PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22), + PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16), + PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22), + PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30), + PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1), + PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4), + PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0), + PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1), + PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28), + PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30), + PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18), + PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22), + PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26), + PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28), + PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30), + PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16), + PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18), + PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4), + PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6), + PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8), + PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10), + PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12), + PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14), + PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16), + PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18), + PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0), + PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2), + PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4), + PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6), + PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8), + PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10), + PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16), + /* these pin groups only have pullup and pull down control */ + PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14), + PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26), + PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4), + PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6), + PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8), + PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10), + PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12), + PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), + PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), +}; + +void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max) +{ + *pg = tegra_soc_pingroups; + *pg_max = TEGRA_MAX_PINGROUP; + *pgdrive = tegra_soc_drive_pingroups; + *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP; +} + diff --git a/trunk/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/trunk/arch/arm/mach-tegra/pinmux-tegra30-tables.c new file mode 100644 index 000000000000..14fc0e4c1c44 --- /dev/null +++ b/trunk/arch/arm/mach-tegra/pinmux-tegra30-tables.c @@ -0,0 +1,376 @@ +/* + * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c + * + * Common pinmux configurations for Tegra30 SoCs + * + * Copyright (C) 2010,2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define PINGROUP_REG_A 0x868 +#define MUXCTL_REG_A 0x3000 + +#define DRIVE_PINGROUP(pg_name, r) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg_bank = 0, \ + .reg = ((r) - PINGROUP_REG_A) \ + } + +static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { + DRIVE_PINGROUP(AO1, 0x868), + DRIVE_PINGROUP(AO2, 0x86c), + DRIVE_PINGROUP(AT1, 0x870), + DRIVE_PINGROUP(AT2, 0x874), + DRIVE_PINGROUP(AT3, 0x878), + DRIVE_PINGROUP(AT4, 0x87c), + DRIVE_PINGROUP(AT5, 0x880), + DRIVE_PINGROUP(CDEV1, 0x884), + DRIVE_PINGROUP(CDEV2, 0x888), + DRIVE_PINGROUP(CSUS, 0x88c), + DRIVE_PINGROUP(DAP1, 0x890), + DRIVE_PINGROUP(DAP2, 0x894), + DRIVE_PINGROUP(DAP3, 0x898), + DRIVE_PINGROUP(DAP4, 0x89c), + DRIVE_PINGROUP(DBG, 0x8a0), + DRIVE_PINGROUP(LCD1, 0x8a4), + DRIVE_PINGROUP(LCD2, 0x8a8), + DRIVE_PINGROUP(SDIO2, 0x8ac), + DRIVE_PINGROUP(SDIO3, 0x8b0), + DRIVE_PINGROUP(SPI, 0x8b4), + DRIVE_PINGROUP(UAA, 0x8b8), + DRIVE_PINGROUP(UAB, 0x8bc), + DRIVE_PINGROUP(UART2, 0x8c0), + DRIVE_PINGROUP(UART3, 0x8c4), + DRIVE_PINGROUP(VI1, 0x8c8), + DRIVE_PINGROUP(SDIO1, 0x8ec), + DRIVE_PINGROUP(CRT, 0x8f8), + DRIVE_PINGROUP(DDC, 0x8fc), + DRIVE_PINGROUP(GMA, 0x900), + DRIVE_PINGROUP(GMB, 0x904), + DRIVE_PINGROUP(GMC, 0x908), + DRIVE_PINGROUP(GMD, 0x90c), + DRIVE_PINGROUP(GME, 0x910), + DRIVE_PINGROUP(GMF, 0x914), + DRIVE_PINGROUP(GMG, 0x918), + DRIVE_PINGROUP(GMH, 0x91c), + DRIVE_PINGROUP(OWR, 0x920), + DRIVE_PINGROUP(UAD, 0x924), + DRIVE_PINGROUP(GPV, 0x928), + DRIVE_PINGROUP(DEV3, 0x92c), + DRIVE_PINGROUP(CEC, 0x938), +}; + +#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \ + [TEGRA_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .vddio = TEGRA_VDDIO_ ## vdd, \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_ ## f2, \ + TEGRA_MUX_ ## f3, \ + }, \ + .func_safe = TEGRA_MUX_ ## fs, \ + .tri_bank = 1, \ + .tri_reg = ((reg) - MUXCTL_REG_A), \ + .tri_bit = 4, \ + .mux_bank = 1, \ + .mux_reg = ((reg) - MUXCTL_REG_A), \ + .mux_bit = 0, \ + .pupd_bank = 1, \ + .pupd_reg = ((reg) - MUXCTL_REG_A), \ + .pupd_bit = 2, \ + .io_default = TEGRA_PIN_ ## iod, \ + .od_bit = 6, \ + .lock_bit = 7, \ + .ioreset_bit = 8, \ + } + +static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { + /* NAME VDD f0 f1 f2 f3 fSafe io reg */ + PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000), + PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004), + PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008), + PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c), + PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010), + PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014), + PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018), + PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c), + PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020), + PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024), + PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028), + PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c), + PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030), + PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034), + PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038), + PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c), + PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040), + PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044), + PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048), + PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c), + PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050), + PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054), + PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058), + PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c), + PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060), + PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064), + PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068), + PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c), + PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070), + PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074), + PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078), + PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c), + PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080), + PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084), + PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088), + PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c), + PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090), + PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094), + PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098), + PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c), + PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0), + PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4), + PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8), + PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac), + PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0), + PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4), + PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8), + PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc), + PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0), + PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4), + PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8), + PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc), + PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0), + PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4), + PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8), + PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc), + PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0), + PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4), + PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8), + PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec), + PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0), + PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4), + PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8), + PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc), + PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100), + PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104), + PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108), + PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c), + PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110), + PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114), + PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118), + PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c), + PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120), + PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124), + PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128), + PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c), + PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130), + PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134), + PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138), + PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c), + PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140), + PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144), + PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148), + PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c), + PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150), + PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154), + PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158), + PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c), + PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160), + PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164), + PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168), + PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c), + PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170), + PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174), + PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178), + PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c), + PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180), + PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184), + PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188), + PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c), + PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190), + PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194), + PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198), + PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c), + PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0), + PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4), + PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8), + PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac), + PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0), + PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4), + PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8), + PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc), + PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0), + PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4), + PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8), + PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc), + PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0), + PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4), + PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8), + PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc), + PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0), + PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4), + PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8), + PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec), + PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0), + PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4), + PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8), + PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc), + PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200), + PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204), + PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208), + PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c), + PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210), + PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214), + PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218), + PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c), + PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220), + PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224), + PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228), + PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c), + PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230), + PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234), + PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238), + PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c), + PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240), + PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244), + PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248), + PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c), + PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250), + PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254), + PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258), + PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c), + PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260), + PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264), + PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268), + PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c), + PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270), + PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274), + PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278), + PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c), + PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280), + PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284), + PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288), + PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c), + PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290), + PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294), + PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298), + PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c), + PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0), + PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4), + PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8), + PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac), + PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0), + PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4), + PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8), + PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc), + PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0), + PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4), + PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8), + PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc), + PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0), + PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4), + PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8), + PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc), + PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0), + PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4), + PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8), + PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec), + PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0), + PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4), + PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8), + PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc), + PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300), + PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304), + PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308), + PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c), + PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310), + PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314), + PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318), + PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c), + PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320), + PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324), + PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328), + PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c), + PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330), + PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334), + PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338), + PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c), + PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340), + PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344), + PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348), + PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c), + PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350), + PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354), + PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358), + PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c), + PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360), + PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364), + PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368), + PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c), + PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370), + PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374), + PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378), + PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c), + PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380), + PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384), + PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388), + PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c), + PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390), + PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394), + PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398), + PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c), + PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0), + PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4), + PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8), + PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac), + PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0), + PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4), + PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8), + PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc), + PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0), + PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4), + PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8), + PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc), + PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0), + PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4), + PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8), + PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc), + PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0), +}; + +void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max) +{ + *pg = tegra_soc_pingroups; + *pg_max = TEGRA_MAX_PINGROUP; + *pgdrive = tegra_soc_drive_pingroups; + *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP; +} + diff --git a/trunk/arch/arm/mach-tegra/pinmux.c b/trunk/arch/arm/mach-tegra/pinmux.c new file mode 100644 index 000000000000..ac35d2b76850 --- /dev/null +++ b/trunk/arch/arm/mach-tegra/pinmux.c @@ -0,0 +1,987 @@ +/* + * linux/arch/arm/mach-tegra/pinmux.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define HSM_EN(reg) (((reg) >> 2) & 0x1) +#define SCHMT_EN(reg) (((reg) >> 3) & 0x1) +#define LPMD(reg) (((reg) >> 4) & 0x3) +#define DRVDN(reg) (((reg) >> 12) & 0x1f) +#define DRVUP(reg) (((reg) >> 20) & 0x1f) +#define SLWR(reg) (((reg) >> 28) & 0x3) +#define SLWF(reg) (((reg) >> 30) & 0x3) + +static const struct tegra_pingroup_desc *pingroups; +static const struct tegra_drive_pingroup_desc *drive_pingroups; +static int pingroup_max; +static int drive_max; + +static char *tegra_mux_names[TEGRA_MAX_MUX] = { + [TEGRA_MUX_AHB_CLK] = "AHB_CLK", + [TEGRA_MUX_APB_CLK] = "APB_CLK", + [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC", + [TEGRA_MUX_CRT] = "CRT", + [TEGRA_MUX_DAP1] = "DAP1", + [TEGRA_MUX_DAP2] = "DAP2", + [TEGRA_MUX_DAP3] = "DAP3", + [TEGRA_MUX_DAP4] = "DAP4", + [TEGRA_MUX_DAP5] = "DAP5", + [TEGRA_MUX_DISPLAYA] = "DISPLAYA", + [TEGRA_MUX_DISPLAYB] = "DISPLAYB", + [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL", + [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL", + [TEGRA_MUX_GMI] = "GMI", + [TEGRA_MUX_GMI_INT] = "GMI_INT", + [TEGRA_MUX_HDMI] = "HDMI", + [TEGRA_MUX_I2C] = "I2C", + [TEGRA_MUX_I2C2] = "I2C2", + [TEGRA_MUX_I2C3] = "I2C3", + [TEGRA_MUX_IDE] = "IDE", + [TEGRA_MUX_IRDA] = "IRDA", + [TEGRA_MUX_KBC] = "KBC", + [TEGRA_MUX_MIO] = "MIO", + [TEGRA_MUX_MIPI_HS] = "MIPI_HS", + [TEGRA_MUX_NAND] = "NAND", + [TEGRA_MUX_OSC] = "OSC", + [TEGRA_MUX_OWR] = "OWR", + [TEGRA_MUX_PCIE] = "PCIE", + [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT", + [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1", + [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1", + [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2", + [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3", + [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4", + [TEGRA_MUX_PWM] = "PWM", + [TEGRA_MUX_PWR_INTR] = "PWR_INTR", + [TEGRA_MUX_PWR_ON] = "PWR_ON", + [TEGRA_MUX_RTCK] = "RTCK", + [TEGRA_MUX_SDIO1] = "SDIO1", + [TEGRA_MUX_SDIO2] = "SDIO2", + [TEGRA_MUX_SDIO3] = "SDIO3", + [TEGRA_MUX_SDIO4] = "SDIO4", + [TEGRA_MUX_SFLASH] = "SFLASH", + [TEGRA_MUX_SPDIF] = "SPDIF", + [TEGRA_MUX_SPI1] = "SPI1", + [TEGRA_MUX_SPI2] = "SPI2", + [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT", + [TEGRA_MUX_SPI3] = "SPI3", + [TEGRA_MUX_SPI4] = "SPI4", + [TEGRA_MUX_TRACE] = "TRACE", + [TEGRA_MUX_TWC] = "TWC", + [TEGRA_MUX_UARTA] = "UARTA", + [TEGRA_MUX_UARTB] = "UARTB", + [TEGRA_MUX_UARTC] = "UARTC", + [TEGRA_MUX_UARTD] = "UARTD", + [TEGRA_MUX_UARTE] = "UARTE", + [TEGRA_MUX_ULPI] = "ULPI", + [TEGRA_MUX_VI] = "VI", + [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", + [TEGRA_MUX_XIO] = "XIO", + [TEGRA_MUX_BLINK] = "BLINK", + [TEGRA_MUX_CEC] = "CEC", + [TEGRA_MUX_CLK12] = "CLK12", + [TEGRA_MUX_DAP] = "DAP", + [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2", + [TEGRA_MUX_DDR] = "DDR", + [TEGRA_MUX_DEV3] = "DEV3", + [TEGRA_MUX_DTV] = "DTV", + [TEGRA_MUX_VI_ALT1] = "VI_ALT1", + [TEGRA_MUX_VI_ALT2] = "VI_ALT2", + [TEGRA_MUX_VI_ALT3] = "VI_ALT3", + [TEGRA_MUX_EMC_DLL] = "EMC_DLL", + [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1", + [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2", + [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3", + [TEGRA_MUX_GMI_ALT] = "GMI_ALT", + [TEGRA_MUX_HDA] = "HDA", + [TEGRA_MUX_HSI] = "HSI", + [TEGRA_MUX_I2C4] = "I2C4", + [TEGRA_MUX_I2C5] = "I2C5", + [TEGRA_MUX_I2CPWR] = "I2CPWR", + [TEGRA_MUX_I2S0] = "I2S0", + [TEGRA_MUX_I2S1] = "I2S1", + [TEGRA_MUX_I2S2] = "I2S2", + [TEGRA_MUX_I2S3] = "I2S3", + [TEGRA_MUX_I2S4] = "I2S4", + [TEGRA_MUX_NAND_ALT] = "NAND_ALT", + [TEGRA_MUX_POPSDIO4] = "POPSDIO4", + [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4", + [TEGRA_MUX_PWM0] = "PWM0", + [TEGRA_MUX_PWM1] = "PWM2", + [TEGRA_MUX_PWM2] = "PWM2", + [TEGRA_MUX_PWM3] = "PWM3", + [TEGRA_MUX_SATA] = "SATA", + [TEGRA_MUX_SPI5] = "SPI5", + [TEGRA_MUX_SPI6] = "SPI6", + [TEGRA_MUX_SYSCLK] = "SYSCLK", + [TEGRA_MUX_VGP1] = "VGP1", + [TEGRA_MUX_VGP2] = "VGP2", + [TEGRA_MUX_VGP3] = "VGP3", + [TEGRA_MUX_VGP4] = "VGP4", + [TEGRA_MUX_VGP5] = "VGP5", + [TEGRA_MUX_VGP6] = "VGP6", + [TEGRA_MUX_SAFE] = "", +}; + +static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = { + [TEGRA_DRIVE_DIV_8] = "DIV_8", + [TEGRA_DRIVE_DIV_4] = "DIV_4", + [TEGRA_DRIVE_DIV_2] = "DIV_2", + [TEGRA_DRIVE_DIV_1] = "DIV_1", +}; + +static const char *tegra_slew_names[TEGRA_MAX_SLEW] = { + [TEGRA_SLEW_FASTEST] = "FASTEST", + [TEGRA_SLEW_FAST] = "FAST", + [TEGRA_SLEW_SLOW] = "SLOW", + [TEGRA_SLEW_SLOWEST] = "SLOWEST", +}; + +static DEFINE_SPINLOCK(mux_lock); + +static const char *pingroup_name(int pg) +{ + if (pg < 0 || pg >= pingroup_max) + return ""; + + return pingroups[pg].name; +} + +static const char *func_name(enum tegra_mux_func func) +{ + if (func == TEGRA_MUX_RSVD1) + return "RSVD1"; + + if (func == TEGRA_MUX_RSVD2) + return "RSVD2"; + + if (func == TEGRA_MUX_RSVD3) + return "RSVD3"; + + if (func == TEGRA_MUX_RSVD4) + return "RSVD4"; + + if (func == TEGRA_MUX_NONE) + return "NONE"; + + if (func < 0 || func >= TEGRA_MAX_MUX) + return ""; + + return tegra_mux_names[func]; +} + + +static const char *tri_name(unsigned long val) +{ + return val ? "TRISTATE" : "NORMAL"; +} + +static const char *pupd_name(unsigned long val) +{ + switch (val) { + case 0: + return "NORMAL"; + + case 1: + return "PULL_DOWN"; + + case 2: + return "PULL_UP"; + + default: + return "RSVD"; + } +} + +static int nbanks; +static void __iomem **regs; + +static inline u32 pg_readl(u32 bank, u32 reg) +{ + return readl(regs[bank] + reg); +} + +static inline void pg_writel(u32 val, u32 bank, u32 reg) +{ + writel(val, regs[bank] + reg); +} + +static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) +{ + int mux = -1; + int i; + unsigned long reg; + unsigned long flags; + int pg = config->pingroup; + enum tegra_mux_func func = config->func; + + if (pg < 0 || pg >= pingroup_max) + return -ERANGE; + + if (pingroups[pg].mux_reg < 0) + return -EINVAL; + + if (func < 0) + return -ERANGE; + + if (func == TEGRA_MUX_SAFE) + func = pingroups[pg].func_safe; + + if (func & TEGRA_MUX_RSVD) { + mux = func & 0x3; + } else { + for (i = 0; i < 4; i++) { + if (pingroups[pg].funcs[i] == func) { + mux = i; + break; + } + } + } + + if (mux < 0) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg); + reg &= ~(0x3 << pingroups[pg].mux_bit); + reg |= mux << pingroups[pg].mux_bit; + pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate) +{ + unsigned long reg; + unsigned long flags; + + if (pg < 0 || pg >= pingroup_max) + return -ERANGE; + + if (pingroups[pg].tri_reg < 0) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg); + reg &= ~(0x1 << pingroups[pg].tri_bit); + if (tristate) + reg |= 1 << pingroups[pg].tri_bit; + pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd) +{ + unsigned long reg; + unsigned long flags; + + if (pg < 0 || pg >= pingroup_max) + return -ERANGE; + + if (pingroups[pg].pupd_reg < 0) + return -EINVAL; + + if (pupd != TEGRA_PUPD_NORMAL && + pupd != TEGRA_PUPD_PULL_DOWN && + pupd != TEGRA_PUPD_PULL_UP) + return -EINVAL; + + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg); + reg &= ~(0x3 << pingroups[pg].pupd_bit); + reg |= pupd << pingroups[pg].pupd_bit; + pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config) +{ + int pingroup = config->pingroup; + enum tegra_mux_func func = config->func; + enum tegra_pullupdown pupd = config->pupd; + enum tegra_tristate tristate = config->tristate; + int err; + + if (pingroups[pingroup].mux_reg >= 0) { + err = tegra_pinmux_set_func(config); + if (err < 0) + pr_err("pinmux: can't set pingroup %s func to %s: %d\n", + pingroup_name(pingroup), func_name(func), err); + } + + if (pingroups[pingroup].pupd_reg >= 0) { + err = tegra_pinmux_set_pullupdown(pingroup, pupd); + if (err < 0) + pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n", + pingroup_name(pingroup), pupd_name(pupd), err); + } + + if (pingroups[pingroup].tri_reg >= 0) { + err = tegra_pinmux_set_tristate(pingroup, tristate); + if (err < 0) + pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n", + pingroup_name(pingroup), tri_name(func), err); + } +} + +void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + tegra_pinmux_config_pingroup(&config[i]); +} + +static const char *drive_pinmux_name(int pg) +{ + if (pg < 0 || pg >= drive_max) + return ""; + + return drive_pingroups[pg].name; +} + +static const char *enable_name(unsigned long val) +{ + return val ? "ENABLE" : "DISABLE"; +} + +static const char *drive_name(unsigned long val) +{ + if (val >= TEGRA_MAX_DRIVE) + return ""; + + return tegra_drive_names[val]; +} + +static const char *slew_name(unsigned long val) +{ + if (val >= TEGRA_MAX_SLEW) + return ""; + + return tegra_slew_names[val]; +} + +static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= drive_max) + return -ERANGE; + + if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + if (hsm == TEGRA_HSM_ENABLE) + reg |= (1 << 2); + else + reg &= ~(1 << 2); + pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= drive_max) + return -ERANGE; + + if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + if (schmitt == TEGRA_SCHMITT_ENABLE) + reg |= (1 << 3); + else + reg &= ~(1 << 3); + pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= drive_max) + return -ERANGE; + + if (drive < 0 || drive >= TEGRA_MAX_DRIVE) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + reg &= ~(0x3 << 4); + reg |= drive << 4; + pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_pull_down(int pg, + enum tegra_pull_strength pull_down) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= drive_max) + return -ERANGE; + + if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + reg &= ~(0x1f << 12); + reg |= pull_down << 12; + pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_pull_up(int pg, + enum tegra_pull_strength pull_up) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= drive_max) + return -ERANGE; + + if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + reg &= ~(0x1f << 12); + reg |= pull_up << 12; + pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_slew_rising(int pg, + enum tegra_slew slew_rising) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= drive_max) + return -ERANGE; + + if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + reg &= ~(0x3 << 28); + reg |= slew_rising << 28; + pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_slew_falling(int pg, + enum tegra_slew slew_falling) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= drive_max) + return -ERANGE; + + if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + reg &= ~(0x3 << 30); + reg |= slew_falling << 30; + pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static void tegra_drive_pinmux_config_pingroup(int pingroup, + enum tegra_hsm hsm, + enum tegra_schmitt schmitt, + enum tegra_drive drive, + enum tegra_pull_strength pull_down, + enum tegra_pull_strength pull_up, + enum tegra_slew slew_rising, + enum tegra_slew slew_falling) +{ + int err; + + err = tegra_drive_pinmux_set_hsm(pingroup, hsm); + if (err < 0) + pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n", + drive_pinmux_name(pingroup), + enable_name(hsm), err); + + err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt); + if (err < 0) + pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n", + drive_pinmux_name(pingroup), + enable_name(schmitt), err); + + err = tegra_drive_pinmux_set_drive(pingroup, drive); + if (err < 0) + pr_err("pinmux: can't set pingroup %s drive to %s: %d\n", + drive_pinmux_name(pingroup), + drive_name(drive), err); + + err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down); + if (err < 0) + pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n", + drive_pinmux_name(pingroup), + pull_down, err); + + err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up); + if (err < 0) + pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n", + drive_pinmux_name(pingroup), + pull_up, err); + + err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising); + if (err < 0) + pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n", + drive_pinmux_name(pingroup), + slew_name(slew_rising), err); + + err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling); + if (err < 0) + pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n", + drive_pinmux_name(pingroup), + slew_name(slew_falling), err); +} + +void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, + int len) +{ + int i; + + for (i = 0; i < len; i++) + tegra_drive_pinmux_config_pingroup(config[i].pingroup, + config[i].hsm, + config[i].schmitt, + config[i].drive, + config[i].pull_down, + config[i].pull_up, + config[i].slew_rising, + config[i].slew_falling); +} + +void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config, + int len) +{ + int i; + struct tegra_pingroup_config c; + + for (i = 0; i < len; i++) { + int err; + c = config[i]; + if (c.pingroup < 0 || c.pingroup >= pingroup_max) { + WARN_ON(1); + continue; + } + c.func = pingroups[c.pingroup].func_safe; + err = tegra_pinmux_set_func(&c); + if (err < 0) + pr_err("%s: tegra_pinmux_set_func returned %d setting " + "%s to %s\n", __func__, err, + pingroup_name(c.pingroup), func_name(c.func)); + } +} + +void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config, + int len) +{ + int i; + + for (i = 0; i < len; i++) { + int err; + if (config[i].pingroup < 0 || + config[i].pingroup >= pingroup_max) { + WARN_ON(1); + continue; + } + err = tegra_pinmux_set_func(&config[i]); + if (err < 0) + pr_err("%s: tegra_pinmux_set_func returned %d setting " + "%s to %s\n", __func__, err, + pingroup_name(config[i].pingroup), + func_name(config[i].func)); + } +} + +void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config, + int len, enum tegra_tristate tristate) +{ + int i; + int err; + int pingroup; + + for (i = 0; i < len; i++) { + pingroup = config[i].pingroup; + if (pingroups[pingroup].tri_reg >= 0) { + err = tegra_pinmux_set_tristate(pingroup, tristate); + if (err < 0) + pr_err("pinmux: can't set pingroup %s tristate" + " to %s: %d\n", pingroup_name(pingroup), + tri_name(tristate), err); + } + } +} + +void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, + int len, enum tegra_pullupdown pupd) +{ + int i; + int err; + int pingroup; + + for (i = 0; i < len; i++) { + pingroup = config[i].pingroup; + if (pingroups[pingroup].pupd_reg >= 0) { + err = tegra_pinmux_set_pullupdown(pingroup, pupd); + if (err < 0) + pr_err("pinmux: can't set pingroup %s pullupdown" + " to %s: %d\n", pingroup_name(pingroup), + pupd_name(pupd), err); + } + } +} + +static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init }, +#endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init }, +#endif + { }, +}; + +static int __devinit tegra_pinmux_probe(struct platform_device *pdev) +{ + struct resource *res; + int i; + int config_bad = 0; + const struct of_device_id *match; + + match = of_match_device(tegra_pinmux_of_match, &pdev->dev); + + if (match) + ((pinmux_init)(match->data))(&pingroups, &pingroup_max, + &drive_pingroups, &drive_max); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + else + /* no device tree available, so we must be on tegra20 */ + tegra20_pinmux_init(&pingroups, &pingroup_max, + &drive_pingroups, &drive_max); +#else + pr_warn("non Tegra20 platform requires pinmux devicetree node\n"); +#endif + + for (i = 0; ; i++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) + break; + } + nbanks = i; + + for (i = 0; i < pingroup_max; i++) { + if (pingroups[i].tri_bank >= nbanks) { + dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i); + config_bad = 1; + } + + if (pingroups[i].mux_bank >= nbanks) { + dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i); + config_bad = 1; + } + + if (pingroups[i].pupd_bank >= nbanks) { + dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i); + config_bad = 1; + } + } + + for (i = 0; i < drive_max; i++) { + if (drive_pingroups[i].reg_bank >= nbanks) { + dev_err(&pdev->dev, + "drive pingroup %d: bad reg_bank\n", i); + config_bad = 1; + } + } + + if (config_bad) + return -ENODEV; + + regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL); + if (!regs) { + dev_err(&pdev->dev, "Can't alloc regs pointer\n"); + return -ENODEV; + } + + for (i = 0; i < nbanks; i++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) { + dev_err(&pdev->dev, "Missing MEM resource\n"); + return -ENODEV; + } + + if (!devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), + dev_name(&pdev->dev))) { + dev_err(&pdev->dev, + "Couldn't request MEM resource %d\n", i); + return -ENODEV; + } + + regs[i] = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!regs) { + dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i); + return -ENODEV; + } + } + + return 0; +} + +static struct platform_driver tegra_pinmux_driver = { + .driver = { + .name = "tegra-pinmux", + .owner = THIS_MODULE, + .of_match_table = tegra_pinmux_of_match, + }, + .probe = tegra_pinmux_probe, +}; + +static int __init tegra_pinmux_init(void) +{ + return platform_driver_register(&tegra_pinmux_driver); +} +postcore_initcall(tegra_pinmux_init); + +#ifdef CONFIG_DEBUG_FS + +#include +#include + +static void dbg_pad_field(struct seq_file *s, int len) +{ + seq_putc(s, ','); + + while (len-- > -1) + seq_putc(s, ' '); +} + +static int dbg_pinmux_show(struct seq_file *s, void *unused) +{ + int i; + int len; + + for (i = 0; i < pingroup_max; i++) { + unsigned long reg; + unsigned long tri; + unsigned long mux; + unsigned long pupd; + + seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name); + len = strlen(pingroups[i].name); + dbg_pad_field(s, 5 - len); + + if (pingroups[i].mux_reg < 0) { + seq_printf(s, "TEGRA_MUX_NONE"); + len = strlen("NONE"); + } else { + reg = pg_readl(pingroups[i].mux_bank, + pingroups[i].mux_reg); + mux = (reg >> pingroups[i].mux_bit) & 0x3; + if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) { + seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1); + len = 5; + } else { + seq_printf(s, "TEGRA_MUX_%s", + tegra_mux_names[pingroups[i].funcs[mux]]); + len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]); + } + } + dbg_pad_field(s, 13-len); + + if (pingroups[i].pupd_reg < 0) { + seq_printf(s, "TEGRA_PUPD_NORMAL"); + len = strlen("NORMAL"); + } else { + reg = pg_readl(pingroups[i].pupd_bank, + pingroups[i].pupd_reg); + pupd = (reg >> pingroups[i].pupd_bit) & 0x3; + seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd)); + len = strlen(pupd_name(pupd)); + } + dbg_pad_field(s, 9 - len); + + if (pingroups[i].tri_reg < 0) { + seq_printf(s, "TEGRA_TRI_NORMAL"); + } else { + reg = pg_readl(pingroups[i].tri_bank, + pingroups[i].tri_reg); + tri = (reg >> pingroups[i].tri_bit) & 0x1; + + seq_printf(s, "TEGRA_TRI_%s", tri_name(tri)); + } + seq_printf(s, "},\n"); + } + return 0; +} + +static int dbg_pinmux_open(struct inode *inode, struct file *file) +{ + return single_open(file, dbg_pinmux_show, &inode->i_private); +} + +static const struct file_operations debug_fops = { + .open = dbg_pinmux_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) +{ + int i; + int len; + + for (i = 0; i < drive_max; i++) { + u32 reg; + + seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s", + drive_pingroups[i].name); + len = strlen(drive_pingroups[i].name); + dbg_pad_field(s, 7 - len); + + + reg = pg_readl(drive_pingroups[i].reg_bank, + drive_pingroups[i].reg); + if (HSM_EN(reg)) { + seq_printf(s, "TEGRA_HSM_ENABLE"); + len = 16; + } else { + seq_printf(s, "TEGRA_HSM_DISABLE"); + len = 17; + } + dbg_pad_field(s, 17 - len); + + if (SCHMT_EN(reg)) { + seq_printf(s, "TEGRA_SCHMITT_ENABLE"); + len = 21; + } else { + seq_printf(s, "TEGRA_SCHMITT_DISABLE"); + len = 22; + } + dbg_pad_field(s, 22 - len); + + seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg))); + len = strlen(drive_name(LPMD(reg))); + dbg_pad_field(s, 5 - len); + + seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg)); + len = DRVDN(reg) < 10 ? 1 : 2; + dbg_pad_field(s, 2 - len); + + seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg)); + len = DRVUP(reg) < 10 ? 1 : 2; + dbg_pad_field(s, 2 - len); + + seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg))); + len = strlen(slew_name(SLWR(reg))); + dbg_pad_field(s, 7 - len); + + seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg))); + + seq_printf(s, "},\n"); + } + return 0; +} + +static int dbg_drive_pinmux_open(struct inode *inode, struct file *file) +{ + return single_open(file, dbg_drive_pinmux_show, &inode->i_private); +} + +static const struct file_operations debug_drive_fops = { + .open = dbg_drive_pinmux_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init tegra_pinmux_debuginit(void) +{ + (void) debugfs_create_file("tegra_pinmux", S_IRUGO, + NULL, NULL, &debug_fops); + (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO, + NULL, NULL, &debug_drive_fops); + return 0; +} +late_initcall(tegra_pinmux_debuginit); +#endif diff --git a/trunk/arch/arm/mach-tegra/usb_phy.c b/trunk/arch/arm/mach-tegra/usb_phy.c index d71d2fed6721..c5b2ac04e2a0 100644 --- a/trunk/arch/arm/mach-tegra/usb_phy.c +++ b/trunk/arch/arm/mach-tegra/usb_phy.c @@ -711,6 +711,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs, err = -ENXIO; goto err1; } + tegra_gpio_enable(ulpi_config->reset_gpio); gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); gpio_direction_output(ulpi_config->reset_gpio, 0); phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); diff --git a/trunk/arch/arm/mach-ux500/Kconfig b/trunk/arch/arm/mach-ux500/Kconfig index 4adb49396665..ef7099eea0f2 100644 --- a/trunk/arch/arm/mach-ux500/Kconfig +++ b/trunk/arch/arm/mach-ux500/Kconfig @@ -9,8 +9,6 @@ config UX500_SOC_COMMON select ARM_ERRATA_754322 select ARM_ERRATA_764369 select CACHE_L2X0 - select PINCTRL - select PINCTRL_NOMADIK config UX500_SOC_DB5500 bool @@ -22,7 +20,6 @@ config UX500_SOC_DB8500 select REGULATOR select REGULATOR_DB8500_PRCMU select CPU_FREQ_TABLE if CPU_FREQ - select PINCTRL_DB8500 menu "Ux500 target platform (boards)" diff --git a/trunk/arch/arm/mach-ux500/Makefile b/trunk/arch/arm/mach-ux500/Makefile index 11729bc62194..465b9ec9510a 100644 --- a/trunk/arch/arm/mach-ux500/Makefile +++ b/trunk/arch/arm/mach-ux500/Makefile @@ -11,8 +11,7 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ board-mop500-regulators.o \ board-mop500-uib.o board-mop500-stuib.o \ board-mop500-u8500uib.o \ - board-mop500-pins.o \ - board-mop500-msp.o + board-mop500-pins.o obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/trunk/arch/arm/mach-ux500/board-mop500-msp.c b/trunk/arch/arm/mach-ux500/board-mop500-msp.c deleted file mode 100644 index 996048038743..000000000000 --- a/trunk/arch/arm/mach-ux500/board-mop500-msp.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL), version 2 - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "ste-dma40-db8500.h" -#include "board-mop500.h" -#include "devices-db8500.h" -#include "pins-db8500.h" - -/* MSP1/3 Tx/Rx usage protection */ -static DEFINE_SPINLOCK(msp_rxtx_lock); - -/* Reference Count */ -static int msp_rxtx_ref; - -/* Pin modes */ -struct pinctrl *msp1_p; -struct pinctrl_state *msp1_def; -struct pinctrl_state *msp1_sleep; - -int msp13_i2s_init(void) -{ - int retval = 0; - unsigned long flags; - - spin_lock_irqsave(&msp_rxtx_lock, flags); - if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) { - retval = pinctrl_select_state(msp1_p, msp1_def); - if (retval) - pr_err("could not set MSP1 defstate\n"); - } - if (!retval) - msp_rxtx_ref++; - spin_unlock_irqrestore(&msp_rxtx_lock, flags); - - return retval; -} - -int msp13_i2s_exit(void) -{ - int retval = 0; - unsigned long flags; - - spin_lock_irqsave(&msp_rxtx_lock, flags); - WARN_ON(!msp_rxtx_ref); - msp_rxtx_ref--; - if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) { - retval = pinctrl_select_state(msp1_p, msp1_sleep); - if (retval) - pr_err("could not set MSP1 sleepstate\n"); - } - spin_unlock_irqrestore(&msp_rxtx_lock, flags); - - return retval; -} - -static struct stedma40_chan_cfg msp0_dma_rx = { - .high_priority = true, - .dir = STEDMA40_PERIPH_TO_MEM, - - .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - /* data_width is set during configuration */ -}; - -static struct stedma40_chan_cfg msp0_dma_tx = { - .high_priority = true, - .dir = STEDMA40_MEM_TO_PERIPH, - - .src_dev_type = STEDMA40_DEV_DST_MEMORY, - .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - /* data_width is set during configuration */ -}; - -static struct msp_i2s_platform_data msp0_platform_data = { - .id = MSP_I2S_0, - .msp_i2s_dma_rx = &msp0_dma_rx, - .msp_i2s_dma_tx = &msp0_dma_tx, -}; - -static struct stedma40_chan_cfg msp1_dma_rx = { - .high_priority = true, - .dir = STEDMA40_PERIPH_TO_MEM, - - .src_dev_type = DB8500_DMA_DEV30_MSP3_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - /* data_width is set during configuration */ -}; - -static struct stedma40_chan_cfg msp1_dma_tx = { - .high_priority = true, - .dir = STEDMA40_MEM_TO_PERIPH, - - .src_dev_type = STEDMA40_DEV_DST_MEMORY, - .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - /* data_width is set during configuration */ -}; - -static struct msp_i2s_platform_data msp1_platform_data = { - .id = MSP_I2S_1, - .msp_i2s_dma_rx = NULL, - .msp_i2s_dma_tx = &msp1_dma_tx, - .msp_i2s_init = msp13_i2s_init, - .msp_i2s_exit = msp13_i2s_exit, -}; - -static struct stedma40_chan_cfg msp2_dma_rx = { - .high_priority = true, - .dir = STEDMA40_PERIPH_TO_MEM, - - .src_dev_type = DB8500_DMA_DEV14_MSP2_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - - /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */ - .src_info.psize = STEDMA40_PSIZE_LOG_1, - .dst_info.psize = STEDMA40_PSIZE_LOG_1, - - /* data_width is set during configuration */ -}; - -static struct stedma40_chan_cfg msp2_dma_tx = { - .high_priority = true, - .dir = STEDMA40_MEM_TO_PERIPH, - - .src_dev_type = STEDMA40_DEV_DST_MEMORY, - .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - .use_fixed_channel = true, - .phy_channel = 1, - - /* data_width is set during configuration */ -}; - -static struct platform_device *db8500_add_msp_i2s(struct device *parent, - int id, - resource_size_t base, int irq, - struct msp_i2s_platform_data *pdata) -{ - struct platform_device *pdev; - struct resource res[] = { - DEFINE_RES_MEM(base, SZ_4K), - DEFINE_RES_IRQ(irq), - }; - - pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n", - id, irq); - pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); - if (!pdev) { - pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n", - id); - return NULL; - } - - return pdev; -} - -/* Platform device for ASoC U8500 machine */ -static struct platform_device snd_soc_u8500 = { - .name = "snd-soc-u8500", - .id = 0, - .dev = { - .platform_data = NULL, - }, -}; - -/* Platform device for Ux500-PCM */ -static struct platform_device ux500_pcm = { - .name = "ux500-pcm", - .id = 0, - .dev = { - .platform_data = NULL, - }, -}; - -static struct msp_i2s_platform_data msp2_platform_data = { - .id = MSP_I2S_2, - .msp_i2s_dma_rx = &msp2_dma_rx, - .msp_i2s_dma_tx = &msp2_dma_tx, -}; - -static struct msp_i2s_platform_data msp3_platform_data = { - .id = MSP_I2S_3, - .msp_i2s_dma_rx = &msp1_dma_rx, - .msp_i2s_dma_tx = NULL, - .msp_i2s_init = msp13_i2s_init, - .msp_i2s_exit = msp13_i2s_exit, -}; - -int mop500_msp_init(struct device *parent) -{ - struct platform_device *msp1; - - pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__); - platform_device_register(&snd_soc_u8500); - - pr_info("Initialize MSP I2S-devices.\n"); - db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, - &msp0_platform_data); - msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, - &msp1_platform_data); - db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, - &msp2_platform_data); - db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, - &msp3_platform_data); - - /* Get the pinctrl handle for MSP1 */ - if (msp1) { - msp1_p = pinctrl_get(&msp1->dev); - if (IS_ERR(msp1_p)) - dev_err(&msp1->dev, "could not get MSP1 pinctrl\n"); - else { - msp1_def = pinctrl_lookup_state(msp1_p, - PINCTRL_STATE_DEFAULT); - if (IS_ERR(msp1_def)) { - dev_err(&msp1->dev, - "could not get MSP1 defstate\n"); - } - msp1_sleep = pinctrl_lookup_state(msp1_p, - PINCTRL_STATE_SLEEP); - if (IS_ERR(msp1_sleep)) - dev_err(&msp1->dev, - "could not get MSP1 idlestate\n"); - } - } - - pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__); - platform_device_register(&ux500_pcm); - - return 0; -} diff --git a/trunk/arch/arm/mach-ux500/board-mop500-msp.h b/trunk/arch/arm/mach-ux500/board-mop500-msp.h deleted file mode 100644 index 6fcfb5e2cc94..000000000000 --- a/trunk/arch/arm/mach-ux500/board-mop500-msp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2012 - * - * Author: Ola Lilja , - * for ST-Ericsson. - * - * License terms: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -void mop500_msp_init(struct device *parent); diff --git a/trunk/arch/arm/mach-ux500/board-mop500-pins.c b/trunk/arch/arm/mach-ux500/board-mop500-pins.c index 32fd99204464..f5413dca532c 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500-pins.c +++ b/trunk/arch/arm/mach-ux500/board-mop500-pins.c @@ -7,508 +7,299 @@ #include #include #include -#include -#include #include #include #include - #include #include "pins-db8500.h" -#include "board-mop500.h" -enum custom_pin_cfg_t { - PINS_FOR_DEFAULT, - PINS_FOR_U9500, -}; +static pin_cfg_t mop500_pins_common[] = { + /* I2C */ + GPIO147_I2C0_SCL, + GPIO148_I2C0_SDA, + GPIO16_I2C1_SCL, + GPIO17_I2C1_SDA, + GPIO10_I2C2_SDA, + GPIO11_I2C2_SCL, + GPIO229_I2C3_SDA, + GPIO230_I2C3_SCL, -static enum custom_pin_cfg_t pinsfor; - -/* These simply sets bias for pins */ -#define BIAS(a,b) static unsigned long a[] = { b } - -BIAS(pd, PIN_PULL_DOWN); -BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); -BIAS(in_nopull, PIN_INPUT_NOPULL); -BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE); -BIAS(in_pu, PIN_INPUT_PULLUP); -BIAS(in_pd, PIN_INPUT_PULLDOWN); -BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP); -BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW); -BIAS(out_hi, PIN_OUTPUT_HIGH); -BIAS(out_lo, PIN_OUTPUT_LOW); -BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE); -/* These also force them into GPIO mode */ -BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED); -BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED); -BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); -BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); -BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); -BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); -/* Sleep modes */ -BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE); -BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE); -BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); - -/* We use these to define hog settings that are always done on boot */ -#define DB8500_MUX_HOG(group,func) \ - PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func) -#define DB8500_PIN_HOG(pin,conf) \ - PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf) - -/* These are default states associated with device and changed runtime */ -#define DB8500_MUX(group,func,dev) \ - PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func) -#define DB8500_PIN(pin,conf,dev) \ - PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf) - -#define DB8500_PIN_SLEEP(pin,conf,dev) \ - PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \ - pin, conf) - -/* Pin control settings */ -static struct pinctrl_map __initdata mop500_family_pinmap[] = { - /* - * uMSP0, mux in 4 pins, regular placement of RX/TX - * explicitly set the pins to no pull - */ - DB8500_MUX_HOG("msp0txrx_a_1", "msp0"), - DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"), - DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */ - DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */ - DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */ - DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */ - /* MSP2 for HDMI, pull down TXD, TCK, TFS */ - DB8500_MUX_HOG("msp2_a_1", "msp2"), - DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */ - DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */ - DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */ - DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */ - /* - * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to - * pull-up - * TODO: is this really correct? Snowball doesn't have a LCD. - */ - DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"), - DB8500_PIN_HOG("GPIO68_E1", in_pu), - DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu), - /* - * STMPE1601/tc35893 keypad IRQ GPIO 218 - * TODO: set for snowball and HREF really?? - */ - DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu), - /* - * UART0, we do not mux in u0 here. - * uart-0 pins gpio configuration should be kept intact to prevent - * a glitch in tx line when the tty dev is opened. Later these pins + /* MSP0 */ + GPIO12_MSP0_TXD, + GPIO13_MSP0_TFS, + GPIO14_MSP0_TCK, + GPIO15_MSP0_RXD, + + /* MSP2: HDMI */ + GPIO193_MSP2_TXD, + GPIO194_MSP2_TCK, + GPIO195_MSP2_TFS, + GPIO196_MSP2_RXD | PIN_OUTPUT_LOW, + + /* Touch screen INTERFACE */ + GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */ + + /* STMPE1601/tc35893 keypad IRQ */ + GPIO218_GPIO | PIN_INPUT_PULLUP, + + /* MMC0 (MicroSD card) */ + GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, + GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, + GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, + + GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, + GPIO23_MC0_CLK | PIN_OUTPUT_LOW, + GPIO24_MC0_CMD | PIN_INPUT_PULLUP, + GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, + GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, + GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, + GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, + + /* SDI1 (SDIO) */ + GPIO208_MC1_CLK | PIN_OUTPUT_LOW, + GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL, + GPIO210_MC1_CMD | PIN_INPUT_PULLUP, + GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP, + GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP, + GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP, + GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP, + + /* MMC2 (On-board DATA INTERFACE eMMC) */ + GPIO128_MC2_CLK | PIN_OUTPUT_LOW, + GPIO129_MC2_CMD | PIN_INPUT_PULLUP, + GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL, + GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP, + GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP, + GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP, + GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP, + GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP, + GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP, + GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP, + GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP, + + /* MMC4 (On-board STORAGE INTERFACE eMMC) */ + GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, + GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, + GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, + GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, + GPIO201_MC4_CMD | PIN_INPUT_PULLUP, + GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, + GPIO203_MC4_CLK | PIN_OUTPUT_LOW, + GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, + GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, + GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, + GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, + + /* SKE keypad */ + GPIO153_KP_I7, + GPIO154_KP_I6, + GPIO155_KP_I5, + GPIO156_KP_I4, + GPIO157_KP_O7, + GPIO158_KP_O6, + GPIO159_KP_O5, + GPIO160_KP_O4, + GPIO161_KP_I3, + GPIO162_KP_I2, + GPIO163_KP_I1, + GPIO164_KP_I0, + GPIO165_KP_O3, + GPIO166_KP_O2, + GPIO167_KP_O1, + GPIO168_KP_O0, + + /* UART */ + /* uart-0 pins gpio configuration should be + * kept intact to prevent glitch in tx line + * when tty dev is opened. Later these pins * are configured to uart mop500_pins_uart0 + * + * It will be replaced with uart configuration + * once the issue is solved. */ - DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */ - DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */ - /* - * Mux in UART2 on altfunction C and set pull-ups. - * TODO: is this used on U8500 variants and Snowball really? - * The setting on GPIO31 conflicts with magnetometer use on hrefv60 - */ - DB8500_MUX_HOG("u2rxtx_c_1", "u2"), - DB8500_MUX_HOG("u2ctsrts_c_1", "u2"), - DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */ - DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */ - /* - * The following pin sets were known as "runtime pins" before being - * converted to the pinctrl model. Here we model them as "default" - * states. - */ - /* Mux in UART0 after initialization */ - DB8500_MUX("u0_a_1", "u0", "uart0"), - DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */ - DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */ - DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */ - DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */ - /* UART0 sleep state */ - DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"), - /* MSP1 for ALSA codec */ - DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"), - DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"), - DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"), - DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"), - DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"), - DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"), - /* MSP1 sleep state */ - DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"), - DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"), - DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"), - DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"), - /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */ - DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"), - DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"), - /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */ - DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"), - /* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */ - DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"), - DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"), - DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"), - DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"), - DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"), - DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"), - DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"), - DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"), - DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"), - DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"), - DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"), - DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"), - /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */ - DB8500_MUX("mc0_a_1", "mc0", "sdi0"), - DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */ - DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */ - DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */ - DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */ - DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */ - DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */ - DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */ - DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */ - DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */ - DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */ - /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */ - DB8500_MUX("mc1_a_1", "mc1", "sdi1"), - DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */ - DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */ - DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */ - DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */ - DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */ - DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */ - DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */ - /* Mux in SDI2 (here called MC2) used for for PoP eMMC */ - DB8500_MUX("mc2_a_1", "mc2", "sdi2"), - DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */ - DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */ - DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */ - DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */ - DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */ - DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */ - DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */ - DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */ - DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */ - DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */ - DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */ - /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */ - DB8500_MUX("mc4_a_1", "mc4", "sdi4"), - DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */ - DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */ - DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */ - DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */ - DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */ - DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */ - DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */ - DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */ - DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */ - DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */ - DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */ - /* Mux in USB pins, drive STP high */ - DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"), - DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */ - /* Mux in SPI2 pins on the "other C1" altfunction */ - DB8500_MUX("spi2_oc1_1", "spi2", "spi2"), - DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */ - DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */ - DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */ - DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */ -}; + GPIO0_GPIO | PIN_INPUT_PULLUP, + GPIO1_GPIO | PIN_OUTPUT_HIGH, + GPIO2_GPIO | PIN_INPUT_PULLUP, + GPIO3_GPIO | PIN_OUTPUT_HIGH, -/* - * These are specifically for the MOP500 and HREFP (pre-v60) version of the - * board, which utilized a TC35892 GPIO expander instead of using a lot of - * on-chip pins as the HREFv60 and later does. - */ -static struct pinctrl_map __initdata mop500_pinmap[] = { - /* Mux in SSP0, pull down RXD pin */ - DB8500_MUX_HOG("ssp0_a_1", "ssp0"), - DB8500_PIN_HOG("GPIO145_C13", pd), - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up - * the pins. - */ - DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"), - DB8500_PIN_HOG("GPIO6_AF6", in_pu), - DB8500_PIN_HOG("GPIO7_AG5", in_pu), - /* TC35892 IRQ, pull up the line, let the driver mux in the pin */ - DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu), - /* Mux in UART1 and set the pull-ups */ - DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_MUX_HOG("u1ctsrts_a_1", "u1"), - DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */ - DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */ - /* - * Runtime stuff: make it possible to mux in the SKE keypad - * and bias the pins - */ - DB8500_MUX("kp_a_2", "kp", "ske"), - DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */ - DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */ - DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */ - DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */ - DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */ - DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */ - DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */ - DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */ - DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */ - DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */ - DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */ - DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */ - DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */ - DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */ - DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */ - DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */ - /* Mux in and drive the SDI0 DAT31DIR line high at runtime */ - DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"), - DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"), -}; + GPIO29_U2_RXD | PIN_INPUT_PULLUP, + GPIO30_U2_TXD | PIN_OUTPUT_HIGH, + GPIO31_U2_CTSn | PIN_INPUT_PULLUP, + GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, -/* - * The HREFv60 series of platforms is using available pins on the DB8500 - * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0 - * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines. - */ -static struct pinctrl_map __initdata hrefv60_pinmap[] = { - /* Drive WLAN_ENA low */ - DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */ - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant - * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias - * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. - */ - DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"), - DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */ - DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */ - DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */ - DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */ - /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ - DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */ - DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */ - /* - * Display Interface 1 uses GPIO 65 for RST (reset). - * Display Interface 2 uses GPIO 66 for RST (reset). - * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) - */ - DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */ - DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */ - /* - * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and - * GPIO 67 for interrupts. Pull-up the IRQ line and drive both - * reset signals low. - */ - DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */ - DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */ - DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */ - /* - * Drive D19-D23 for the ETM PTM trace interface low, - * (presumably pins are unconnected therefore grounded here, - * the "other alt C1" setting enables these pins) - */ - DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo), - DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo), - DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo), - DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo), - DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo), - /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */ - DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */ - DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */ - /* NFC ENA and RESET to low, pulldown IRQ line */ - DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */ - DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */ - DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */ - /* - * SKE keyboard partly on alt A and partly on "Other alt C1" - * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three - * rows of 6 keys, then pull up force sensing interrup and - * drive reset and force sensing WU low. - */ - DB8500_MUX_HOG("kp_a_1", "kp"), - DB8500_MUX_HOG("kp_oc1_1", "kp"), - DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */ - DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */ - DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */ - DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */ - DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */ - DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */ - DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */ - DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */ - DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */ - DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */ - DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */ - /* DiPro Sensor interrupt */ - DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */ - /* Audio Amplifier HF enable */ - DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */ - /* GBF interface, pull low to reset state */ - DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */ - /* MSP : HDTV INTERFACE GPIO line */ - DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd), - /* Accelerometer interrupt lines */ - DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */ - DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */ - /* SD card detect GPIO pin */ - DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu), - /* - * Runtime stuff - * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor - * etc. - */ - DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"), - DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"), - DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"), - /* - * Make it possible to mux in the SKE keypad and bias the pins - * FIXME: what's the point with this on HREFv60? KP/SKE is already - * muxed in at another place! Enabling this will bork. - */ - DB8500_MUX("kp_a_2", "kp", "ske"), - DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */ - DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */ - DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */ - DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */ - DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */ - DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */ - DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */ - DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */ - DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */ - DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */ - DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */ - DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */ - DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */ - DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */ - DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */ - DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */ + /* Display & HDMI HW sync */ + GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP, + GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP, }; -static struct pinctrl_map __initdata u9500_pinmap[] = { - /* Mux in UART1 (just RX/TX) and set the pull-ups */ - DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_PIN_HOG("GPIO4_AH6", in_pu), - DB8500_PIN_HOG("GPIO5_AG6", out_hi), - /* WLAN_IRQ line */ - DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu), - /* HSI */ - DB8500_MUX_HOG("hsir_a_1", "hsi"), - DB8500_MUX_HOG("hsit_a_1", "hsi"), - DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */ - DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */ - DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */ - DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */ - DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */ - DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */ - DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */ - DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */ -}; +static pin_cfg_t mop500_pins_default[] = { + /* SSP0 */ + GPIO143_SSP0_CLK, + GPIO144_SSP0_FRM, + GPIO145_SSP0_RXD | PIN_PULL_DOWN, + GPIO146_SSP0_TXD, + -static struct pinctrl_map __initdata u8500_pinmap[] = { - DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */ - DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */ + GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */ + + /* SDI0 (MicroSD card) */ + GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, + + /* UART */ + GPIO4_U1_RXD | PIN_INPUT_PULLUP, + GPIO5_U1_TXD | PIN_OUTPUT_HIGH, + GPIO6_U1_CTSn | PIN_INPUT_PULLUP, + GPIO7_U1_RTSn | PIN_OUTPUT_HIGH, }; -static struct pinctrl_map __initdata snowball_pinmap[] = { - /* Mux in SSP0 connected to AB8500, pull down RXD pin */ - DB8500_MUX_HOG("ssp0_a_1", "ssp0"), - DB8500_PIN_HOG("GPIO145_C13", pd), - /* Always drive the MC0 DAT31DIR line high on these boards */ - DB8500_PIN_HOG("GPIO21_AB3", out_hi), - /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */ - DB8500_MUX_HOG("sm_b_1", "sm"), - /* Drive RSTn_LAN high */ - DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi), - /* Accelerometer/Magnetometer */ - DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */ - DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */ - DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */ - /* WLAN/GBF */ - DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */ - DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */ - DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */ - DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */ +static pin_cfg_t hrefv60_pins[] = { + /* WLAN */ + GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ + GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */ + + /* XENON Flashgun INTERFACE */ + GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */ + GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */ + GPIO170_GPIO | PIN_OUTPUT_LOW, /* XENON_CHARGE */ + + /* Assistant LED INTERFACE */ + GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */ + GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */ + + /* Magnetometer */ + GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */ + GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */ + + /* Display Interface */ + GPIO65_GPIO | PIN_OUTPUT_LOW, /* DISP1 RST */ + GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */ + + /* Touch screen INTERFACE */ + GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */ + + /* Touch screen INTERFACE 2 */ + GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */ + GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */ + + /* ETM_PTM_TRACE INTERFACE */ + GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */ + GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */ + GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */ + GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */ + GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */ + + /* NAHJ INTERFACE */ + GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */ + GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */ + + /* NFC INTERFACE */ + GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */ + GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */ + GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */ + + /* Keyboard MATRIX INTERFACE */ + GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */ + GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */ + GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */ + GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */ + GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */ + GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */ + GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */ + GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */ + GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */ + GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */ + GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */ + + /* DiPro Sensor Interface */ + GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */ + + /* HAL SWITCH INTERFACE */ + GPIO145_GPIO | PIN_INPUT_PULLDOWN,/* HAL_SW */ + + /* Audio Amplifier Interface */ + GPIO149_GPIO | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */ + + /* GBF INTERFACE */ + GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */ + + /* MSP : HDTV INTERFACE */ + GPIO192_GPIO | PIN_INPUT_PULLDOWN, + + /* ACCELEROMETER_INTERFACE */ + GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */ + GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */ + + /* Proximity Sensor */ + GPIO217_GPIO | PIN_INPUT_PULLUP, + + }; -/* - * passing "pinsfor=" in kernel cmdline allows for custom - * configuration of GPIOs on u8500 derived boards. - */ -static int __init early_pinsfor(char *p) -{ - pinsfor = PINS_FOR_DEFAULT; +static pin_cfg_t snowball_pins[] = { + /* SSP0, to AB8500 */ + GPIO143_SSP0_CLK, + GPIO144_SSP0_FRM, + GPIO145_SSP0_RXD | PIN_PULL_DOWN, + GPIO146_SSP0_TXD, - if (strcmp(p, "u9500-21") == 0) - pinsfor = PINS_FOR_U9500; + /* MMC0: MicroSD card */ + GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, - return 0; -} -early_param("pinsfor", early_pinsfor); + /* MMC2: LAN */ + GPIO86_SM_ADQ0, + GPIO87_SM_ADQ1, + GPIO88_SM_ADQ2, + GPIO89_SM_ADQ3, + GPIO90_SM_ADQ4, + GPIO91_SM_ADQ5, + GPIO92_SM_ADQ6, + GPIO93_SM_ADQ7, -int pins_for_u9500(void) -{ - if (pinsfor == PINS_FOR_U9500) - return 1; + GPIO94_SM_ADVn, + GPIO95_SM_CS0n, + GPIO96_SM_OEn, + GPIO97_SM_WEn, - return 0; -} + GPIO128_SM_CKO, + GPIO130_SM_FBCLK, + GPIO131_SM_ADQ8, + GPIO132_SM_ADQ9, + GPIO133_SM_ADQ10, + GPIO134_SM_ADQ11, + GPIO135_SM_ADQ12, + GPIO136_SM_ADQ13, + GPIO137_SM_ADQ14, + GPIO138_SM_ADQ15, -static void __init mop500_href_family_pinmaps_init(void) -{ - switch (pinsfor) { - case PINS_FOR_U9500: - pinctrl_register_mappings(u9500_pinmap, - ARRAY_SIZE(u9500_pinmap)); - break; - case PINS_FOR_DEFAULT: - pinctrl_register_mappings(u8500_pinmap, - ARRAY_SIZE(u8500_pinmap)); - default: - break; - } -} + /* RSTn_LAN */ + GPIO141_GPIO | PIN_OUTPUT_HIGH, +}; -void __init mop500_pinmaps_init(void) +void __init mop500_pins_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); - pinctrl_register_mappings(mop500_pinmap, - ARRAY_SIZE(mop500_pinmap)); - mop500_href_family_pinmaps_init(); + nmk_config_pins(mop500_pins_common, + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(mop500_pins_default, + ARRAY_SIZE(mop500_pins_default)); } -void __init snowball_pinmaps_init(void) +void __init snowball_pins_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); - pinctrl_register_mappings(snowball_pinmap, - ARRAY_SIZE(snowball_pinmap)); - pinctrl_register_mappings(u8500_pinmap, - ARRAY_SIZE(u8500_pinmap)); + nmk_config_pins(mop500_pins_common, + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(snowball_pins, + ARRAY_SIZE(snowball_pins)); } -void __init hrefv60_pinmaps_init(void) +void __init hrefv60_pins_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); - pinctrl_register_mappings(hrefv60_pinmap, - ARRAY_SIZE(hrefv60_pinmap)); - mop500_href_family_pinmaps_init(); + nmk_config_pins(mop500_pins_common, + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(hrefv60_pins, + ARRAY_SIZE(hrefv60_pins)); } diff --git a/trunk/arch/arm/mach-ux500/board-mop500.c b/trunk/arch/arm/mach-ux500/board-mop500.c index 1dc31652b97a..77d03c1fbd04 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500.c +++ b/trunk/arch/arm/mach-ux500/board-mop500.c @@ -1,4 +1,3 @@ - /* * Copyright (C) 2008-2009 ST-Ericsson * @@ -30,17 +29,18 @@ #include #include #include + #include #include -#include -#include +#include #include #include #include #include #include +#include #include #include @@ -48,11 +48,11 @@ #include #include +#include "pins-db8500.h" #include "ste-dma40-db8500.h" #include "devices-db8500.h" #include "board-mop500.h" #include "board-mop500-regulators.h" -#include "board-mop500-msp.h" static struct gpio_led snowball_led_array[] = { { @@ -520,6 +520,14 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = { }; #endif + +static pin_cfg_t mop500_pins_uart0[] = { + GPIO0_U0_CTSn | PIN_INPUT_PULLUP, + GPIO1_U0_RTSn | PIN_OUTPUT_HIGH, + GPIO2_U0_RXD | PIN_INPUT_PULLUP, + GPIO3_U0_TXD | PIN_OUTPUT_HIGH, +}; + #define PRCC_K_SOFTRST_SET 0x18 #define PRCC_K_SOFTRST_CLEAR 0x1C static void ux500_uart0_reset(void) @@ -540,33 +548,24 @@ static void ux500_uart0_reset(void) udelay(1); } -/* This needs to be referenced by callbacks */ -struct pinctrl *u0_p; -struct pinctrl_state *u0_def; -struct pinctrl_state *u0_sleep; - static void ux500_uart0_init(void) { int ret; - if (IS_ERR(u0_p) || IS_ERR(u0_def)) - return; - - ret = pinctrl_select_state(u0_p, u0_def); - if (ret) - pr_err("could not set UART0 defstate\n"); + ret = nmk_config_pins(mop500_pins_uart0, + ARRAY_SIZE(mop500_pins_uart0)); + if (ret < 0) + pr_err("pl011: uart pins_enable failed\n"); } static void ux500_uart0_exit(void) { int ret; - if (IS_ERR(u0_p) || IS_ERR(u0_sleep)) - return; - - ret = pinctrl_select_state(u0_p, u0_sleep); - if (ret) - pr_err("could not set UART0 idlestate\n"); + ret = nmk_config_pins_sleep(mop500_pins_uart0, + ARRAY_SIZE(mop500_pins_uart0)); + if (ret < 0) + pr_err("pl011: uart pins_disable failed\n"); } static struct amba_pl011_data uart0_plat = { @@ -598,28 +597,7 @@ static struct amba_pl011_data uart2_plat = { static void __init mop500_uart_init(struct device *parent) { - struct amba_device *uart0_device; - - uart0_device = db8500_add_uart0(parent, &uart0_plat); - if (uart0_device) { - u0_p = pinctrl_get(&uart0_device->dev); - if (IS_ERR(u0_p)) - dev_err(&uart0_device->dev, - "could not get UART0 pinctrl\n"); - else { - u0_def = pinctrl_lookup_state(u0_p, - PINCTRL_STATE_DEFAULT); - if (IS_ERR(u0_def)) { - dev_err(&uart0_device->dev, - "could not get UART0 defstate\n"); - } - u0_sleep = pinctrl_lookup_state(u0_p, - PINCTRL_STATE_SLEEP); - if (IS_ERR(u0_sleep)) - dev_err(&uart0_device->dev, - "could not get UART0 idlestate\n"); - } - } + db8500_add_uart0(parent, &uart0_plat); db8500_add_uart1(parent, &uart1_plat); db8500_add_uart2(parent, &uart2_plat); } @@ -639,9 +617,10 @@ static void __init mop500_init_machine(void) mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; - mop500_pinmaps_init(); parent = u8500_init_devices(); + mop500_pins_init(); + /* FIXME: parent of ab8500 should be prcmu */ for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) mop500_platform_devs[i]->dev.parent = parent; @@ -652,7 +631,6 @@ static void __init mop500_init_machine(void) mop500_i2c_init(parent); mop500_sdi_init(parent); mop500_spi_init(parent); - mop500_msp_init(parent); mop500_uart_init(parent); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); @@ -671,9 +649,10 @@ static void __init snowball_init_machine(void) int i2c0_devs; int i; - snowball_pinmaps_init(); parent = u8500_init_devices(); + snowball_pins_init(); + for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) snowball_platform_devs[i]->dev.parent = parent; @@ -683,7 +662,6 @@ static void __init snowball_init_machine(void) mop500_i2c_init(parent); snowball_sdi_init(parent); mop500_spi_init(parent); - mop500_msp_init(parent); mop500_uart_init(parent); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); @@ -708,9 +686,10 @@ static void __init hrefv60_init_machine(void) */ mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; - hrefv60_pinmaps_init(); parent = u8500_init_devices(); + hrefv60_pins_init(); + for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) mop500_platform_devs[i]->dev.parent = parent; @@ -720,7 +699,6 @@ static void __init hrefv60_init_machine(void) mop500_i2c_init(parent); hrefv60_sdi_init(parent); mop500_spi_init(parent); - mop500_msp_init(parent); mop500_uart_init(parent); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); @@ -768,22 +746,10 @@ MACHINE_END #ifdef CONFIG_MACH_UX500_DT struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { - /* Requires DMA and call-back bindings. */ OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), - /* Requires DMA bindings. */ OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), - /* Requires clock name bindings. */ - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), {}, }; @@ -799,14 +765,6 @@ static void __init u8500_init_machine(void) int i2c0_devs; int i; - /* Pinmaps must be in place before devices register */ - if (of_machine_is_compatible("st-ericsson,mop500")) - mop500_pinmaps_init(); - else if (of_machine_is_compatible("calaosystems,snowball-a9500")) - snowball_pinmaps_init(); - else if (of_machine_is_compatible("st-ericsson,hrefv60+")) - hrefv60_pinmaps_init(); - parent = u8500_init_devices(); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); @@ -820,12 +778,14 @@ static void __init u8500_init_machine(void) if (of_machine_is_compatible("st-ericsson,mop500")) { mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; + mop500_pins_init(); platform_add_devices(mop500_platform_devs, ARRAY_SIZE(mop500_platform_devs)); mop500_sdi_init(parent); } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { + snowball_pins_init(); platform_add_devices(snowball_platform_devs, ARRAY_SIZE(snowball_platform_devs)); @@ -838,6 +798,7 @@ static void __init u8500_init_machine(void) */ mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; + hrefv60_pins_init(); platform_add_devices(mop500_platform_devs, ARRAY_SIZE(mop500_platform_devs)); diff --git a/trunk/arch/arm/mach-ux500/board-mop500.h b/trunk/arch/arm/mach-ux500/board-mop500.h index bc44c07c71a9..fdcfa8721bb4 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500.h +++ b/trunk/arch/arm/mach-ux500/board-mop500.h @@ -7,9 +7,6 @@ #ifndef __BOARD_MOP500_H #define __BOARD_MOP500_H -/* For NOMADIK_NR_GPIO */ -#include - /* Snowball specific GPIO assignments, this board has no GPIO expander */ #define SNOWBALL_ACCEL_INT1_GPIO 163 #define SNOWBALL_ACCEL_INT2_GPIO 164 @@ -76,7 +73,6 @@ #define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */ #define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ -struct device; struct i2c_board_info; extern void mop500_sdi_init(struct device *parent); @@ -85,9 +81,9 @@ extern void hrefv60_sdi_init(struct device *parent); extern void mop500_sdi_tc35892_init(struct device *parent); void __init mop500_u8500uib_init(void); void __init mop500_stuib_init(void); -void __init mop500_pinmaps_init(void); -void __init snowball_pinmaps_init(void); -void __init hrefv60_pinmaps_init(void); +void __init mop500_pins_init(void); +void __init hrefv60_pins_init(void); +void __init snowball_pins_init(void); void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, unsigned n); diff --git a/trunk/arch/arm/mach-ux500/clock.c b/trunk/arch/arm/mach-ux500/clock.c index 700042cb6681..ec35f0aa5665 100644 --- a/trunk/arch/arm/mach-ux500/clock.c +++ b/trunk/arch/arm/mach-ux500/clock.c @@ -336,7 +336,6 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ */ /* Peripheral Cluster #1 */ -static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk); static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); @@ -406,7 +405,7 @@ static struct clk_lookup u8500_clks[] = { CLK(slimbus0, "slimbus0", NULL), CLK(i2c2, "nmk-i2c.2", NULL), CLK(sdi0, "sdi0", NULL), - CLK(msp0, "ux500-msp-i2s.0", NULL), + CLK(msp0, "msp0", NULL), CLK(i2c1, "nmk-i2c.1", NULL), CLK(uart1, "uart1", NULL), CLK(uart0, "uart0", NULL), @@ -456,8 +455,7 @@ static struct clk_lookup u8500_clks[] = { /* Peripheral Cluster #1 */ CLK(i2c4, "nmk-i2c.4", NULL), CLK(spi3, "spi3", NULL), - CLK(msp1, "ux500-msp-i2s.1", NULL), - CLK(msp3, "ux500-msp-i2s.3", NULL), + CLK(msp1, "msp1", NULL), /* Peripheral Cluster #2 */ CLK(gpio1, "gpio.6", NULL), @@ -467,7 +465,7 @@ static struct clk_lookup u8500_clks[] = { CLK(spi0, "spi0", NULL), CLK(sdi3, "sdi3", NULL), CLK(sdi1, "sdi1", NULL), - CLK(msp2, "ux500-msp-i2s.2", NULL), + CLK(msp2, "msp2", NULL), CLK(sdi4, "sdi4", NULL), CLK(pwl, "pwl", NULL), CLK(spi1, "spi1", NULL), diff --git a/trunk/arch/arm/mach-ux500/cpu-db8500.c b/trunk/arch/arm/mach-ux500/cpu-db8500.c index d992d2b44907..9bd8163896cf 100644 --- a/trunk/arch/arm/mach-ux500/cpu-db8500.c +++ b/trunk/arch/arm/mach-ux500/cpu-db8500.c @@ -141,7 +141,6 @@ static void __init db8500_add_gpios(struct device *parent) dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), IRQ_DB8500_GPIO0, &pdata); - dbx500_add_pinctrl(parent, "pinctrl-db8500"); } static int usb_db8500_rx_dma_cfg[] = { diff --git a/trunk/arch/arm/mach-ux500/cpu.c b/trunk/arch/arm/mach-ux500/cpu.c index f6522f9f129c..d11f3892a27d 100644 --- a/trunk/arch/arm/mach-ux500/cpu.c +++ b/trunk/arch/arm/mach-ux500/cpu.c @@ -30,18 +30,6 @@ void __iomem *_PRCMU_BASE; -/* - * FIXME: Should we set up the GPIO domain here? - * - * The problem is that we cannot put the interrupt resources into the platform - * device until the irqdomain has been added. Right now, we set the GIC interrupt - * domain from init_irq(), then load the gpio driver from - * core_initcall(nmk_gpio_init) and add the platform devices from - * arch_initcall(customize_machine). - * - * This feels fragile because it depends on the gpio device getting probed - * _before_ any device uses the gpio interrupts. -*/ static const struct of_device_id ux500_dt_irq_match[] = { { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, {}, diff --git a/trunk/arch/arm/mach-ux500/devices-common.h b/trunk/arch/arm/mach-ux500/devices-common.h index 939f7503e8db..39c74ec82add 100644 --- a/trunk/arch/arm/mach-ux500/devices-common.h +++ b/trunk/arch/arm/mach-ux500/devices-common.h @@ -93,16 +93,4 @@ struct nmk_gpio_platform_data; void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, int irq, struct nmk_gpio_platform_data *pdata); -static inline void -dbx500_add_pinctrl(struct device *parent, const char *name) -{ - struct platform_device_info pdevinfo = { - .parent = parent, - .name = name, - .id = -1, - }; - - platform_device_register_full(&pdevinfo); -} - #endif diff --git a/trunk/arch/arm/mach-ux500/devices-db8500.h b/trunk/arch/arm/mach-ux500/devices-db8500.h index e22b78626068..9fd93e9da529 100644 --- a/trunk/arch/arm/mach-ux500/devices-db8500.h +++ b/trunk/arch/arm/mach-ux500/devices-db8500.h @@ -34,6 +34,7 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base, return dbx500_add_amba_device(parent, name, base, irq, pdata, 0); } + #define db8500_add_i2c0(parent, pdata) \ dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata) #define db8500_add_i2c1(parent, pdata) \ @@ -45,6 +46,15 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base, #define db8500_add_i2c4(parent, pdata) \ dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata) +#define db8500_add_msp0_i2s(parent, pdata) \ + dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata) +#define db8500_add_msp1_i2s(parent, pdata) \ + dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata) +#define db8500_add_msp2_i2s(parent, pdata) \ + dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata) +#define db8500_add_msp3_i2s(parent, pdata) \ + dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata) + #define db8500_add_msp0_spi(parent, pdata) \ dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \ IRQ_DB8500_MSP0, pdata) diff --git a/trunk/arch/arm/mach-ux500/include/mach/msp.h b/trunk/arch/arm/mach-ux500/include/mach/msp.h deleted file mode 100644 index 798be19129ef..000000000000 --- a/trunk/arch/arm/mach-ux500/include/mach/msp.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __MSP_H -#define __MSP_H - -#include - -enum msp_i2s_id { - MSP_I2S_0 = 0, - MSP_I2S_1, - MSP_I2S_2, - MSP_I2S_3, -}; - -/* Platform data structure for a MSP I2S-device */ -struct msp_i2s_platform_data { - enum msp_i2s_id id; - struct stedma40_chan_cfg *msp_i2s_dma_rx; - struct stedma40_chan_cfg *msp_i2s_dma_tx; - int (*msp_i2s_init) (void); - int (*msp_i2s_exit) (void); -}; - -#endif diff --git a/trunk/arch/arm/mach-ux500/pins-db8500.h b/trunk/arch/arm/mach-ux500/pins-db8500.h index 062c7acf4576..8b1d1a7a679e 100644 --- a/trunk/arch/arm/mach-ux500/pins-db8500.h +++ b/trunk/arch/arm/mach-ux500/pins-db8500.h @@ -35,40 +35,40 @@ #define GPIO4_GPIO PIN_CFG(4, GPIO) #define GPIO4_U1_RXD PIN_CFG(4, ALT_A) -#define GPIO4_I2C4_SCL PIN_CFG(4, ALT_B) +#define GPIO4_I2C4_SCL PIN_CFG_INPUT(4, ALT_B, PULLUP) #define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) #define GPIO5_GPIO PIN_CFG(5, GPIO) #define GPIO5_U1_TXD PIN_CFG(5, ALT_A) -#define GPIO5_I2C4_SDA PIN_CFG(5, ALT_B) +#define GPIO5_I2C4_SDA PIN_CFG_INPUT(5, ALT_B, PULLUP) #define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) #define GPIO6_GPIO PIN_CFG(6, GPIO) #define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) -#define GPIO6_I2C1_SCL PIN_CFG(6, ALT_B) +#define GPIO6_I2C1_SCL PIN_CFG_INPUT(6, ALT_B, PULLUP) #define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) #define GPIO7_GPIO PIN_CFG(7, GPIO) #define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) -#define GPIO7_I2C1_SDA PIN_CFG(7, ALT_B) +#define GPIO7_I2C1_SDA PIN_CFG_INPUT(7, ALT_B, PULLUP) #define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) #define GPIO8_GPIO PIN_CFG(8, GPIO) -#define GPIO8_IPI2C_SDA PIN_CFG(8, ALT_A) -#define GPIO8_I2C2_SDA PIN_CFG(8, ALT_B) +#define GPIO8_IPI2C_SDA PIN_CFG_INPUT(8, ALT_A, PULLUP) +#define GPIO8_I2C2_SDA PIN_CFG_INPUT(8, ALT_B, PULLUP) #define GPIO9_GPIO PIN_CFG(9, GPIO) -#define GPIO9_IPI2C_SCL PIN_CFG(9, ALT_A) -#define GPIO9_I2C2_SCL PIN_CFG(9, ALT_B) +#define GPIO9_IPI2C_SCL PIN_CFG_INPUT(9, ALT_A, PULLUP) +#define GPIO9_I2C2_SCL PIN_CFG_INPUT(9, ALT_B, PULLUP) #define GPIO10_GPIO PIN_CFG(10, GPIO) -#define GPIO10_IPI2C_SDA PIN_CFG(10, ALT_A) -#define GPIO10_I2C2_SDA PIN_CFG(10, ALT_B) +#define GPIO10_IPI2C_SDA PIN_CFG_INPUT(10, ALT_A, PULLUP) +#define GPIO10_I2C2_SDA PIN_CFG_INPUT(10, ALT_B, PULLUP) #define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) #define GPIO11_GPIO PIN_CFG(11, GPIO) -#define GPIO11_IPI2C_SCL PIN_CFG(11, ALT_A) -#define GPIO11_I2C2_SCL PIN_CFG(11, ALT_B) +#define GPIO11_IPI2C_SCL PIN_CFG_INPUT(11, ALT_A, PULLUP) +#define GPIO11_I2C2_SCL PIN_CFG_INPUT(11, ALT_B, PULLUP) #define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) #define GPIO12_GPIO PIN_CFG(12, GPIO) @@ -87,12 +87,12 @@ #define GPIO16_GPIO PIN_CFG(16, GPIO) #define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) -#define GPIO16_I2C1_SCL PIN_CFG(16, ALT_B) +#define GPIO16_I2C1_SCL PIN_CFG_INPUT(16, ALT_B, PULLUP) #define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) #define GPIO17_GPIO PIN_CFG(17, GPIO) #define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) -#define GPIO17_I2C1_SDA PIN_CFG(17, ALT_B) +#define GPIO17_I2C1_SDA PIN_CFG_INPUT(17, ALT_B, PULLUP) #define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) #define GPIO18_GPIO PIN_CFG(18, GPIO) @@ -434,10 +434,10 @@ #define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) #define GPIO147_GPIO PIN_CFG(147, GPIO) -#define GPIO147_I2C0_SCL PIN_CFG(147, ALT_A) +#define GPIO147_I2C0_SCL PIN_CFG_INPUT(147, ALT_A, PULLUP) #define GPIO148_GPIO PIN_CFG(148, GPIO) -#define GPIO148_I2C0_SDA PIN_CFG(148, ALT_A) +#define GPIO148_I2C0_SDA PIN_CFG_INPUT(148, ALT_A, PULLUP) #define GPIO149_GPIO PIN_CFG(149, GPIO) #define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) @@ -459,82 +459,82 @@ #define GPIO152_KP_O9 PIN_CFG(152, ALT_C) #define GPIO153_GPIO PIN_CFG(153, GPIO) -#define GPIO153_KP_I7 PIN_CFG(153, ALT_A) +#define GPIO153_KP_I7 PIN_CFG_INPUT(153, ALT_A, PULLDOWN) #define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) #define GPIO153_U2_RXD PIN_CFG(153, ALT_C) #define GPIO154_GPIO PIN_CFG(154, GPIO) -#define GPIO154_KP_I6 PIN_CFG(154, ALT_A) +#define GPIO154_KP_I6 PIN_CFG_INPUT(154, ALT_A, PULLDOWN) #define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) #define GPIO154_U2_TXD PIN_CFG(154, ALT_C) #define GPIO155_GPIO PIN_CFG(155, GPIO) -#define GPIO155_KP_I5 PIN_CFG(155, ALT_A) +#define GPIO155_KP_I5 PIN_CFG_INPUT(155, ALT_A, PULLDOWN) #define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) #define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) #define GPIO156_GPIO PIN_CFG(156, GPIO) -#define GPIO156_KP_I4 PIN_CFG(156, ALT_A) +#define GPIO156_KP_I4 PIN_CFG_INPUT(156, ALT_A, PULLDOWN) #define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) #define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) #define GPIO157_GPIO PIN_CFG(157, GPIO) -#define GPIO157_KP_O7 PIN_CFG(157, ALT_A) +#define GPIO157_KP_O7 PIN_CFG_INPUT(157, ALT_A, PULLUP) #define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) #define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) #define GPIO158_GPIO PIN_CFG(158, GPIO) -#define GPIO158_KP_O6 PIN_CFG(158, ALT_A) +#define GPIO158_KP_O6 PIN_CFG_INPUT(158, ALT_A, PULLUP) #define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) #define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) #define GPIO159_GPIO PIN_CFG(159, GPIO) -#define GPIO159_KP_O5 PIN_CFG(159, ALT_A) +#define GPIO159_KP_O5 PIN_CFG_INPUT(159, ALT_A, PULLUP) #define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) #define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) #define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_KP_O4 PIN_CFG(160, ALT_A) +#define GPIO160_KP_O4 PIN_CFG_INPUT(160, ALT_A, PULLUP) #define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) #define GPIO160_NONE PIN_CFG(160, ALT_C) #define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_KP_I3 PIN_CFG(161, ALT_A) +#define GPIO161_KP_I3 PIN_CFG_INPUT(161, ALT_A, PULLDOWN) #define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) #define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) #define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_KP_I2 PIN_CFG(162, ALT_A) +#define GPIO162_KP_I2 PIN_CFG_INPUT(162, ALT_A, PULLDOWN) #define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) #define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) #define GPIO163_GPIO PIN_CFG(163, GPIO) -#define GPIO163_KP_I1 PIN_CFG(163, ALT_A) +#define GPIO163_KP_I1 PIN_CFG_INPUT(163, ALT_A, PULLDOWN) #define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) #define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) #define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_KP_I0 PIN_CFG(164, ALT_A) +#define GPIO164_KP_I0 PIN_CFG_INPUT(164, ALT_A, PULLUP) #define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) #define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) #define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_KP_O3 PIN_CFG(165, ALT_A) +#define GPIO165_KP_O3 PIN_CFG_INPUT(165, ALT_A, PULLUP) #define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) #define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) #define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_KP_O2 PIN_CFG(166, ALT_A) +#define GPIO166_KP_O2 PIN_CFG_INPUT(166, ALT_A, PULLUP) #define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) #define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) #define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_KP_O1 PIN_CFG(167, ALT_A) +#define GPIO167_KP_O1 PIN_CFG_INPUT(167, ALT_A, PULLUP) #define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) #define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) #define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_KP_O0 PIN_CFG(168, ALT_A) +#define GPIO168_KP_O0 PIN_CFG_INPUT(168, ALT_A, PULLUP) #define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) #define GPIO168_NONE PIN_CFG(168, ALT_C) @@ -637,7 +637,7 @@ #define GPIO216_GPIO PIN_CFG(216, GPIO) #define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) #define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) -#define GPIO216_I2C3_SDA PIN_CFG(216, ALT_C) +#define GPIO216_I2C3_SDA PIN_CFG_INPUT(216, ALT_C, PULLUP) #define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C) #define GPIO217_GPIO PIN_CFG(217, GPIO) @@ -649,7 +649,7 @@ #define GPIO218_GPIO PIN_CFG(218, GPIO) #define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) #define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) -#define GPIO218_I2C3_SCL PIN_CFG(218, ALT_C) +#define GPIO218_I2C3_SCL PIN_CFG_INPUT(218, ALT_C, PULLUP) #define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C) #define GPIO219_GPIO PIN_CFG(219, GPIO) @@ -698,12 +698,12 @@ #define GPIO229_GPIO PIN_CFG(229, GPIO) #define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) #define GPIO229_PWL PIN_CFG(229, ALT_B) -#define GPIO229_I2C3_SDA PIN_CFG(229, ALT_C) +#define GPIO229_I2C3_SDA PIN_CFG_INPUT(229, ALT_C, PULLUP) #define GPIO230_GPIO PIN_CFG(230, GPIO) #define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) #define GPIO230_PWL PIN_CFG(230, ALT_B) -#define GPIO230_I2C3_SCL PIN_CFG(230, ALT_C) +#define GPIO230_I2C3_SCL PIN_CFG_INPUT(230, ALT_C, PULLUP) #define GPIO256_GPIO PIN_CFG(256, GPIO) #define GPIO256_USB_NXT PIN_CFG(256, ALT_A) diff --git a/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h index 826de74bfdd1..9605bf227df9 100644 --- a/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h +++ b/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h @@ -29,7 +29,6 @@ #define NMK_GPIO_SLPC 0x1c #define NMK_GPIO_AFSLA 0x20 #define NMK_GPIO_AFSLB 0x24 -#define NMK_GPIO_LOWEMI 0x28 #define NMK_GPIO_RIMSC 0x40 #define NMK_GPIO_FIMSC 0x44 @@ -62,14 +61,7 @@ enum nmk_gpio_slpm { extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode); extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull); -#ifdef CONFIG_PINCTRL_NOMADIK extern int nmk_gpio_set_mode(int gpio, int gpio_mode); -#else -static inline int nmk_gpio_set_mode(int gpio, int gpio_mode) -{ - return -ENODEV; -} -#endif extern int nmk_gpio_get_mode(int gpio); extern void nmk_gpio_wakeups_suspend(void); diff --git a/trunk/arch/arm/plat-nomadik/include/plat/pincfg.h b/trunk/arch/arm/plat-nomadik/include/plat/pincfg.h index 9c949c7c98a7..22cb97d2d8ad 100644 --- a/trunk/arch/arm/plat-nomadik/include/plat/pincfg.h +++ b/trunk/arch/arm/plat-nomadik/include/plat/pincfg.h @@ -24,7 +24,6 @@ * bit 16..18 - SLPM pull up/down state * bit 19..20 - SLPM direction * bit 21..22 - SLPM Value (if output) - * bit 23..25 - PDIS value (if input) * * to facilitate the definition, the following macros are provided * @@ -68,10 +67,6 @@ typedef unsigned long pin_cfg_t; /* These two replace the above in DB8500v2+ */ #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) -#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE - -#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ -#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ #define PIN_DIR_SHIFT 14 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) @@ -110,33 +105,6 @@ typedef unsigned long pin_cfg_t; #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_PDIS_SHIFT 23 -#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) -#define PIN_SLPM_PDIS(x) \ - (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) -#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) -#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) -#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) - -#define PIN_LOWEMI_SHIFT 25 -#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) -#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) -#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) -#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) - -#define PIN_GPIOMODE_SHIFT 26 -#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) -#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) -#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) -#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) - -#define PIN_SLEEPMODE_SHIFT 27 -#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) -#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) -#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) -#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) - - /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) diff --git a/trunk/arch/arm/plat-spear/Kconfig b/trunk/arch/arm/plat-spear/Kconfig index 387655b5ce05..1bb3dbce8810 100644 --- a/trunk/arch/arm/plat-spear/Kconfig +++ b/trunk/arch/arm/plat-spear/Kconfig @@ -9,11 +9,9 @@ choice default ARCH_SPEAR3XX config ARCH_SPEAR3XX - bool "ST SPEAr3xx with Device Tree" + bool "SPEAr3XX" select ARM_VIC select CPU_ARM926T - select USE_OF - select PINCTRL help Supports for ARM's SPEAR3XX family diff --git a/trunk/arch/arm/plat-spear/Makefile b/trunk/arch/arm/plat-spear/Makefile index 7744802c83e7..e0f2e5b9530c 100644 --- a/trunk/arch/arm/plat-spear/Makefile +++ b/trunk/arch/arm/plat-spear/Makefile @@ -3,6 +3,6 @@ # # Common support -obj-y := clock.o restart.o time.o pl080.o +obj-y := clock.o restart.o time.o -obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o +obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o diff --git a/trunk/arch/arm/plat-spear/include/plat/padmux.h b/trunk/arch/arm/plat-spear/include/plat/padmux.h new file mode 100644 index 000000000000..877f3adcf610 --- /dev/null +++ b/trunk/arch/arm/plat-spear/include/plat/padmux.h @@ -0,0 +1,92 @@ +/* + * arch/arm/plat-spear/include/plat/padmux.h + * + * SPEAr platform specific gpio pads muxing file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_PADMUX_H +#define __PLAT_PADMUX_H + +#include + +/* + * struct pmx_reg: configuration structure for mode reg and mux reg + * + * offset: offset of mode reg + * mask: mask of mode reg + */ +struct pmx_reg { + u32 offset; + u32 mask; +}; + +/* + * struct pmx_dev_mode: configuration structure every group of modes of a device + * + * ids: all modes for this configuration + * mask: mask for supported mode + */ +struct pmx_dev_mode { + u32 ids; + u32 mask; +}; + +/* + * struct pmx_mode: mode definition structure + * + * name: mode name + * mask: mode mask + */ +struct pmx_mode { + char *name; + u32 id; + u32 mask; +}; + +/* + * struct pmx_dev: device definition structure + * + * name: device name + * modes: device configuration array for different modes supported + * mode_count: size of modes array + * is_active: is peripheral active/enabled + * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg + */ +struct pmx_dev { + char *name; + struct pmx_dev_mode *modes; + u8 mode_count; + bool is_active; + bool enb_on_reset; +}; + +/* + * struct pmx_driver: driver definition structure + * + * mode: mode to be set + * devs: array of pointer to pmx devices + * devs_count: ARRAY_SIZE of devs + * base: base address of soc config registers + * mode_reg: structure of mode config register + * mux_reg: structure of device mux config register + */ +struct pmx_driver { + struct pmx_mode *mode; + struct pmx_dev **devs; + u8 devs_count; + u32 *base; + struct pmx_reg mode_reg; + struct pmx_reg mux_reg; +}; + +/* pmx functions */ +int pmx_register(struct pmx_driver *driver); + +#endif /* __PLAT_PADMUX_H */ diff --git a/trunk/arch/arm/plat-spear/include/plat/pl080.h b/trunk/arch/arm/plat-spear/include/plat/pl080.h deleted file mode 100644 index e14a3e4932f9..000000000000 --- a/trunk/arch/arm/plat-spear/include/plat/pl080.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/pl080.h - * - * DMAC pl080 definitions for SPEAr platform - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_PL080_H -#define __PLAT_PL080_H - -struct pl08x_dma_chan; -int pl080_get_signal(struct pl08x_dma_chan *ch); -void pl080_put_signal(struct pl08x_dma_chan *ch); - -#endif /* __PLAT_PL080_H */ diff --git a/trunk/arch/arm/plat-spear/padmux.c b/trunk/arch/arm/plat-spear/padmux.c new file mode 100644 index 000000000000..555eec6dc1cb --- /dev/null +++ b/trunk/arch/arm/plat-spear/padmux.c @@ -0,0 +1,164 @@ +/* + * arch/arm/plat-spear/include/plat/padmux.c + * + * SPEAr platform specific gpio pads muxing source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include + +/* + * struct pmx: pmx definition structure + * + * base: base address of configuration registers + * mode_reg: mode configurations + * mux_reg: muxing configurations + * active_mode: pointer to current active mode + */ +struct pmx { + u32 base; + struct pmx_reg mode_reg; + struct pmx_reg mux_reg; + struct pmx_mode *active_mode; +}; + +static struct pmx *pmx; + +/** + * pmx_mode_set - Enables an multiplexing mode + * @mode - pointer to pmx mode + * + * It will set mode of operation in hardware. + * Returns -ve on Err otherwise 0 + */ +static int pmx_mode_set(struct pmx_mode *mode) +{ + u32 val; + + if (!mode->name) + return -EFAULT; + + pmx->active_mode = mode; + + val = readl(pmx->base + pmx->mode_reg.offset); + val &= ~pmx->mode_reg.mask; + val |= mode->mask & pmx->mode_reg.mask; + writel(val, pmx->base + pmx->mode_reg.offset); + + return 0; +} + +/** + * pmx_devs_enable - Enables list of devices + * @devs - pointer to pmx device array + * @count - number of devices to enable + * + * It will enable pads for all required peripherals once and only once. + * If peripheral is not supported by current mode then request is rejected. + * Conflicts between peripherals are not handled and peripherals will be + * enabled in the order they are present in pmx_dev array. + * In case of conflicts last peripheral enabled will be present. + * Returns -ve on Err otherwise 0 + */ +static int pmx_devs_enable(struct pmx_dev **devs, u8 count) +{ + u32 val, i, mask; + + if (!count) + return -EINVAL; + + val = readl(pmx->base + pmx->mux_reg.offset); + for (i = 0; i < count; i++) { + u8 j = 0; + + if (!devs[i]->name || !devs[i]->modes) { + printk(KERN_ERR "padmux: dev name or modes is null\n"); + continue; + } + /* check if peripheral exists in active mode */ + if (pmx->active_mode) { + bool found = false; + for (j = 0; j < devs[i]->mode_count; j++) { + if (devs[i]->modes[j].ids & + pmx->active_mode->id) { + found = true; + break; + } + } + if (found == false) { + printk(KERN_ERR "%s device not available in %s"\ + "mode\n", devs[i]->name, + pmx->active_mode->name); + continue; + } + } + + /* enable peripheral */ + mask = devs[i]->modes[j].mask & pmx->mux_reg.mask; + if (devs[i]->enb_on_reset) + val &= ~mask; + else + val |= mask; + + devs[i]->is_active = true; + } + writel(val, pmx->base + pmx->mux_reg.offset); + kfree(pmx); + + /* this will ensure that multiplexing can't be changed now */ + pmx = (struct pmx *)-1; + + return 0; +} + +/** + * pmx_register - registers a platform requesting pad mux feature + * @driver - pointer to driver structure containing driver specific parameters + * + * Also this must be called only once. This will allocate memory for pmx + * structure, will call pmx_mode_set, will call pmx_devs_enable. + * Returns -ve on Err otherwise 0 + */ +int pmx_register(struct pmx_driver *driver) +{ + int ret = 0; + + if (pmx) + return -EPERM; + if (!driver->base || !driver->devs) + return -EFAULT; + + pmx = kzalloc(sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->base = (u32)driver->base; + pmx->mode_reg.offset = driver->mode_reg.offset; + pmx->mode_reg.mask = driver->mode_reg.mask; + pmx->mux_reg.offset = driver->mux_reg.offset; + pmx->mux_reg.mask = driver->mux_reg.mask; + + /* choose mode to enable */ + if (driver->mode) { + ret = pmx_mode_set(driver->mode); + if (ret) + goto pmx_fail; + } + ret = pmx_devs_enable(driver->devs, driver->devs_count); + if (ret) + goto pmx_fail; + + return 0; + +pmx_fail: + return ret; +} diff --git a/trunk/arch/arm/plat-spear/pl080.c b/trunk/arch/arm/plat-spear/pl080.c deleted file mode 100644 index d53d75e1af5e..000000000000 --- a/trunk/arch/arm/plat-spear/pl080.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * arch/arm/plat-spear/pl080.c - * - * DMAC pl080 definitions for SPEAr platform - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include - -static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); - -struct { - unsigned char busy; - unsigned char val; -} signals[16] = {{0, 0}, }; - -int pl080_get_signal(struct pl08x_dma_chan *ch) -{ - const struct pl08x_channel_data *cd = ch->cd; - unsigned int signal = cd->min_signal, val; - unsigned long flags; - - spin_lock_irqsave(&lock, flags); - - /* Return if signal is already acquired by somebody else */ - if (signals[signal].busy && - (signals[signal].val != cd->muxval)) { - spin_unlock_irqrestore(&lock, flags); - return -EBUSY; - } - - /* If acquiring for the first time, configure it */ - if (!signals[signal].busy) { - val = readl(DMA_CHN_CFG); - - /* - * Each request line has two bits in DMA_CHN_CFG register. To - * goto the bits of current request line, do left shift of - * value by 2 * signal number. - */ - val &= ~(0x3 << (signal * 2)); - val |= cd->muxval << (signal * 2); - writel(val, DMA_CHN_CFG); - } - - signals[signal].busy++; - signals[signal].val = cd->muxval; - spin_unlock_irqrestore(&lock, flags); - - return signal; -} - -void pl080_put_signal(struct pl08x_dma_chan *ch) -{ - const struct pl08x_channel_data *cd = ch->cd; - unsigned long flags; - - spin_lock_irqsave(&lock, flags); - - /* if signal is not used */ - if (!signals[cd->min_signal].busy) - BUG(); - - signals[cd->min_signal].busy--; - - spin_unlock_irqrestore(&lock, flags); -} diff --git a/trunk/drivers/clk/clkdev.c b/trunk/drivers/clk/clkdev.c index c535cf8c5770..6db161f64ae0 100644 --- a/trunk/drivers/clk/clkdev.c +++ b/trunk/drivers/clk/clkdev.c @@ -35,12 +35,7 @@ static DEFINE_MUTEX(clocks_mutex); static struct clk_lookup *clk_find(const char *dev_id, const char *con_id) { struct clk_lookup *p, *cl = NULL; - int match, best_found = 0, best_possible = 0; - - if (dev_id) - best_possible += 2; - if (con_id) - best_possible += 1; + int match, best = 0; list_for_each_entry(p, &clocks, node) { match = 0; @@ -55,10 +50,10 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id) match += 1; } - if (match > best_found) { + if (match > best) { cl = p; - if (match != best_possible) - best_found = match; + if (match != 3) + best = match; else break; } @@ -94,51 +89,6 @@ void clk_put(struct clk *clk) } EXPORT_SYMBOL(clk_put); -static void devm_clk_release(struct device *dev, void *res) -{ - clk_put(*(struct clk **)res); -} - -struct clk *devm_clk_get(struct device *dev, const char *id) -{ - struct clk **ptr, *clk; - - ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL); - if (!ptr) - return ERR_PTR(-ENOMEM); - - clk = clk_get(dev, id); - if (!IS_ERR(clk)) { - *ptr = clk; - devres_add(dev, ptr); - } else { - devres_free(ptr); - } - - return clk; -} -EXPORT_SYMBOL(devm_clk_get); - -static int devm_clk_match(struct device *dev, void *res, void *data) -{ - struct clk **c = res; - if (!c || !*c) { - WARN_ON(!c || !*c); - return 0; - } - return *c == data; -} - -void devm_clk_put(struct device *dev, struct clk *clk) -{ - int ret; - - ret = devres_destroy(dev, devm_clk_release, devm_clk_match, clk); - - WARN_ON(ret); -} -EXPORT_SYMBOL(devm_clk_put); - void clkdev_add(struct clk_lookup *cl) { mutex_lock(&clocks_mutex); @@ -166,9 +116,8 @@ struct clk_lookup_alloc { char con_id[MAX_CON_ID]; }; -static struct clk_lookup * __init_refok -vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, - va_list ap) +struct clk_lookup * __init_refok +clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) { struct clk_lookup_alloc *cla; @@ -183,25 +132,16 @@ vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, } if (dev_fmt) { + va_list ap; + + va_start(ap, dev_fmt); vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap); cla->cl.dev_id = cla->dev_id; + va_end(ap); } return &cla->cl; } - -struct clk_lookup * __init_refok -clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) -{ - struct clk_lookup *cl; - va_list ap; - - va_start(ap, dev_fmt); - cl = vclkdev_alloc(clk, con_id, dev_fmt, ap); - va_end(ap); - - return cl; -} EXPORT_SYMBOL(clkdev_alloc); int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, @@ -233,65 +173,3 @@ void clkdev_drop(struct clk_lookup *cl) kfree(cl); } EXPORT_SYMBOL(clkdev_drop); - -/** - * clk_register_clkdev - register one clock lookup for a struct clk - * @clk: struct clk to associate with all clk_lookups - * @con_id: connection ID string on device - * @dev_id: format string describing device name - * - * con_id or dev_id may be NULL as a wildcard, just as in the rest of - * clkdev. - * - * To make things easier for mass registration, we detect error clks - * from a previous clk_register() call, and return the error code for - * those. This is to permit this function to be called immediately - * after clk_register(). - */ -int clk_register_clkdev(struct clk *clk, const char *con_id, - const char *dev_fmt, ...) -{ - struct clk_lookup *cl; - va_list ap; - - if (IS_ERR(clk)) - return PTR_ERR(clk); - - va_start(ap, dev_fmt); - cl = vclkdev_alloc(clk, con_id, dev_fmt, ap); - va_end(ap); - - if (!cl) - return -ENOMEM; - - clkdev_add(cl); - - return 0; -} - -/** - * clk_register_clkdevs - register a set of clk_lookup for a struct clk - * @clk: struct clk to associate with all clk_lookups - * @cl: array of clk_lookup structures with con_id and dev_id pre-initialized - * @num: number of clk_lookup structures to register - * - * To make things easier for mass registration, we detect error clks - * from a previous clk_register() call, and return the error code for - * those. This is to permit this function to be called immediately - * after clk_register(). - */ -int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num) -{ - unsigned i; - - if (IS_ERR(clk)) - return PTR_ERR(clk); - - for (i = 0; i < num; i++, cl++) { - cl->clk = clk; - clkdev_add(cl); - } - - return 0; -} -EXPORT_SYMBOL(clk_register_clkdevs); diff --git a/trunk/drivers/gpio/Makefile b/trunk/drivers/gpio/Makefile index a4193ab1b266..007f54bd0081 100644 --- a/trunk/drivers/gpio/Makefile +++ b/trunk/drivers/gpio/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o +obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o diff --git a/trunk/drivers/pinctrl/pinctrl-nomadik.c b/trunk/drivers/gpio/gpio-nomadik.c similarity index 56% rename from trunk/drivers/pinctrl/pinctrl-nomadik.c rename to trunk/drivers/gpio/gpio-nomadik.c index b8e01c3eaa95..839624f9fe6a 100644 --- a/trunk/drivers/pinctrl/pinctrl-nomadik.c +++ b/trunk/drivers/gpio/gpio-nomadik.c @@ -22,20 +22,14 @@ #include #include #include -#include #include -#include -#include -#include -/* Since we request GPIOs from ourself */ -#include #include #include #include - -#include "pinctrl-nomadik.h" +#include +#include /* * The GPIO module in the Nomadik family of Systems-on-Chip is an @@ -49,7 +43,6 @@ struct nmk_gpio_chip { struct gpio_chip chip; - struct irq_domain *domain; void __iomem *addr; struct clk *clk; unsigned int bank; @@ -65,16 +58,8 @@ struct nmk_gpio_chip { u32 real_wake; u32 rwimsc; u32 fwimsc; - u32 rimsc; - u32 fimsc; + u32 slpm; u32 pull_up; - u32 lowemi; -}; - -struct nmk_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - const struct nmk_pinctrl_soc_data *soc; }; static struct nmk_gpio_chip * @@ -139,24 +124,6 @@ static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, } } -static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, - unsigned offset, bool lowemi) -{ - u32 bit = BIT(offset); - bool enabled = nmk_chip->lowemi & bit; - - if (lowemi == enabled) - return; - - if (lowemi) - nmk_chip->lowemi |= bit; - else - nmk_chip->lowemi &= ~bit; - - writel_relaxed(nmk_chip->lowemi, - nmk_chip->addr + NMK_GPIO_LOWEMI); -} - static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, unsigned offset) { @@ -183,8 +150,8 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, unsigned offset, int gpio_mode, bool glitch) { - u32 rwimsc = nmk_chip->rwimsc; - u32 fwimsc = nmk_chip->fwimsc; + u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); + u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); if (glitch && nmk_chip->set_ioforce) { u32 bit = BIT(offset); @@ -206,36 +173,6 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, } } -static void -nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) -{ - u32 falling = nmk_chip->fimsc & BIT(offset); - u32 rising = nmk_chip->rimsc & BIT(offset); - int gpio = nmk_chip->chip.base + offset; - int irq = NOMADIK_GPIO_TO_IRQ(gpio); - struct irq_data *d = irq_get_irq_data(irq); - - if (!rising && !falling) - return; - - if (!d || !irqd_irq_disabled(d)) - return; - - if (rising) { - nmk_chip->rimsc &= ~BIT(offset); - writel_relaxed(nmk_chip->rimsc, - nmk_chip->addr + NMK_GPIO_RIMSC); - } - - if (falling) { - nmk_chip->fimsc &= ~BIT(offset); - writel_relaxed(nmk_chip->fimsc, - nmk_chip->addr + NMK_GPIO_FIMSC); - } - - dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); -} - static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) { @@ -301,17 +238,6 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, __nmk_gpio_set_pull(nmk_chip, offset, pull); } - __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); - - /* - * If the pin is switching to altfunc, and there was an interrupt - * installed on it which has been lazy disabled, actually mask the - * interrupt to prevent spurious interrupts that would occur while the - * pin is under control of the peripheral. Only SKE does this. - */ - if (af != NMK_GPIO_ALT_GPIO) - nmk_gpio_disable_lazy_irq(nmk_chip, offset); - /* * If we've backed up the SLPM registers (glitch workaround), modify * the backups since they will be restored. @@ -408,7 +334,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) struct nmk_gpio_chip *nmk_chip; int pin = PIN_NUM(cfgs[i]); - nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); if (!nmk_chip) { ret = -EINVAL; break; @@ -416,7 +342,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) clk_enable(nmk_chip->clk); spin_lock(&nmk_chip->lock); - __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, + __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, cfgs[i], sleep, glitch ? slpm : NULL); spin_unlock(&nmk_chip->lock); clk_disable(nmk_chip->clk); @@ -500,7 +426,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -508,7 +434,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); - __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); + __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); spin_unlock(&nmk_chip->lock); spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); @@ -535,13 +461,13 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; clk_enable(nmk_chip->clk); spin_lock_irqsave(&nmk_chip->lock, flags); - __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); + __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); spin_unlock_irqrestore(&nmk_chip->lock, flags); clk_disable(nmk_chip->clk); @@ -563,13 +489,13 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; clk_enable(nmk_chip->clk); spin_lock_irqsave(&nmk_chip->lock, flags); - __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); + __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); spin_unlock_irqrestore(&nmk_chip->lock, flags); clk_disable(nmk_chip->clk); @@ -582,11 +508,11 @@ int nmk_gpio_get_mode(int gpio) struct nmk_gpio_chip *nmk_chip; u32 afunc, bfunc, bit; - nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; - bit = 1 << (gpio % NMK_GPIO_PER_CHIP); + bit = 1 << (gpio - nmk_chip->chip.base); clk_enable(nmk_chip->clk); @@ -603,19 +529,21 @@ EXPORT_SYMBOL(nmk_gpio_get_mode); /* IRQ functions */ static inline int nmk_gpio_get_bitmask(int gpio) { - return 1 << (gpio % NMK_GPIO_PER_CHIP); + return 1 << (gpio % 32); } static void nmk_gpio_irq_ack(struct irq_data *d) { + int gpio; struct nmk_gpio_chip *nmk_chip; + gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); if (!nmk_chip) return; clk_enable(nmk_chip->clk); - writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); + writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); clk_disable(nmk_chip->clk); } @@ -628,52 +556,37 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, int gpio, enum nmk_gpio_irq_type which, bool enable) { + u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; + u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; u32 bitmask = nmk_gpio_get_bitmask(gpio); - u32 *rimscval; - u32 *fimscval; - u32 rimscreg; - u32 fimscreg; - - if (which == NORMAL) { - rimscreg = NMK_GPIO_RIMSC; - fimscreg = NMK_GPIO_FIMSC; - rimscval = &nmk_chip->rimsc; - fimscval = &nmk_chip->fimsc; - } else { - rimscreg = NMK_GPIO_RWIMSC; - fimscreg = NMK_GPIO_FWIMSC; - rimscval = &nmk_chip->rwimsc; - fimscval = &nmk_chip->fwimsc; - } + u32 reg; /* we must individually set/clear the two edges */ if (nmk_chip->edge_rising & bitmask) { + reg = readl(nmk_chip->addr + rimsc); if (enable) - *rimscval |= bitmask; + reg |= bitmask; else - *rimscval &= ~bitmask; - writel(*rimscval, nmk_chip->addr + rimscreg); + reg &= ~bitmask; + writel(reg, nmk_chip->addr + rimsc); } if (nmk_chip->edge_falling & bitmask) { + reg = readl(nmk_chip->addr + fimsc); if (enable) - *fimscval |= bitmask; + reg |= bitmask; else - *fimscval &= ~bitmask; - writel(*fimscval, nmk_chip->addr + fimscreg); + reg &= ~bitmask; + writel(reg, nmk_chip->addr + fimsc); } } static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, int gpio, bool on) { - /* - * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is - * disabled, since setting SLPM to 1 increases power consumption, and - * wakeup is anyhow controlled by the RIMSC and FIMSC registers. - */ - if (nmk_chip->sleepmode && on) { - __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base, - NMK_GPIO_SLPM_WAKEUP_ENABLE); + if (nmk_chip->sleepmode) { + __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, + on ? NMK_GPIO_SLPM_WAKEUP_ENABLE + : NMK_GPIO_SLPM_WAKEUP_DISABLE); } __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); @@ -681,12 +594,14 @@ static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) { + int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; + gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); - bitmask = nmk_gpio_get_bitmask(d->hwirq); + bitmask = nmk_gpio_get_bitmask(gpio); if (!nmk_chip) return -EINVAL; @@ -694,10 +609,10 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); + __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); if (!(nmk_chip->real_wake & bitmask)) - __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); + __nmk_gpio_set_wake(nmk_chip, gpio, enable); spin_unlock(&nmk_chip->lock); spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); @@ -721,18 +636,20 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; + int gpio; + gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); if (!nmk_chip) return -EINVAL; - bitmask = nmk_gpio_get_bitmask(d->hwirq); + bitmask = nmk_gpio_get_bitmask(gpio); clk_enable(nmk_chip->clk); spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); if (irqd_irq_disabled(d)) - __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); + __nmk_gpio_set_wake(nmk_chip, gpio, on); if (on) nmk_chip->real_wake |= bitmask; @@ -750,14 +667,17 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) { bool enabled = !irqd_irq_disabled(d); bool wake = irqd_is_wakeup_set(d); + int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; + gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); - bitmask = nmk_gpio_get_bitmask(d->hwirq); + bitmask = nmk_gpio_get_bitmask(gpio); if (!nmk_chip) return -EINVAL; + if (type & IRQ_TYPE_LEVEL_HIGH) return -EINVAL; if (type & IRQ_TYPE_LEVEL_LOW) @@ -767,10 +687,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) spin_lock_irqsave(&nmk_chip->lock, flags); if (enabled) - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); + __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); if (enabled || wake) - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); + __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); nmk_chip->edge_rising &= ~bitmask; if (type & IRQ_TYPE_EDGE_RISING) @@ -781,10 +701,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) nmk_chip->edge_falling |= bitmask; if (enabled) - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); + __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); if (enabled || wake) - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); + __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); spin_unlock_irqrestore(&nmk_chip->lock, flags); clk_disable(nmk_chip->clk); @@ -830,7 +750,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, chained_irq_enter(host_chip, desc); nmk_chip = irq_get_handler_data(irq); - first_irq = nmk_chip->domain->revmap_data.legacy.first_irq; + first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); while (status) { int bit = __ffs(status); @@ -864,6 +784,18 @@ static void nmk_gpio_secondary_irq_handler(unsigned int irq, static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) { + unsigned int first_irq; + int i; + + first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); + for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { + irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, + handle_edge_irq); + set_irq_flags(i, IRQF_VALID); + irq_set_chip_data(i, nmk_chip); + irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); + } + irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); @@ -877,25 +809,6 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) } /* I/O Functions */ - -static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - /* - * Map back to global GPIO space and request muxing, the direction - * parameter does not matter for this controller. - */ - int gpio = chip->base + offset; - - return pinctrl_request_gpio(gpio); -} - -static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - - pinctrl_free_gpio(gpio); -} - static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) { struct nmk_gpio_chip *nmk_chip = @@ -959,23 +872,21 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - return irq_find_mapping(nmk_chip->domain, offset); + return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; } #ifdef CONFIG_DEBUG_FS #include -static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip, - unsigned offset, unsigned gpio) +static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { - const char *label = gpiochip_is_requested(chip, offset); + int mode; + unsigned i; + unsigned gpio = chip->base; + int is_out; struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - int mode; - bool is_out; - bool pull; - u32 bit = 1 << offset; const char *modes[] = { [NMK_GPIO_ALT_GPIO] = "gpio", [NMK_GPIO_ALT_A] = "altA", @@ -984,70 +895,61 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip, }; clk_enable(nmk_chip->clk); - is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); - pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); - mode = nmk_gpio_get_mode(gpio); - - seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", - gpio, label ?: "(none)", - is_out ? "out" : "in ", - chip->get - ? (chip->get(chip, offset) ? "hi" : "lo") - : "? ", - (mode < 0) ? "unknown" : modes[mode], - pull ? "pull" : "none"); - - if (label && !is_out) { - int irq = gpio_to_irq(gpio); - struct irq_desc *desc = irq_to_desc(irq); - - /* This races with request_irq(), set_irq_type(), - * and set_irq_wake() ... but those are "rare". - */ - if (irq >= 0 && desc->action) { - char *trigger; - u32 bitmask = nmk_gpio_get_bitmask(gpio); - - if (nmk_chip->edge_rising & bitmask) - trigger = "edge-rising"; - else if (nmk_chip->edge_falling & bitmask) - trigger = "edge-falling"; - else - trigger = "edge-undefined"; - - seq_printf(s, " irq-%d %s%s", - irq, trigger, - irqd_is_wakeup_set(&desc->irq_data) - ? " wakeup" : ""); - } - } - clk_disable(nmk_chip->clk); -} - -static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - unsigned i; - unsigned gpio = chip->base; for (i = 0; i < chip->ngpio; i++, gpio++) { - nmk_gpio_dbg_show_one(s, chip, i, gpio); + const char *label = gpiochip_is_requested(chip, i); + bool pull; + u32 bit = 1 << i; + + is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; + pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); + mode = nmk_gpio_get_mode(gpio); + seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", + gpio, label ?: "(none)", + is_out ? "out" : "in ", + chip->get + ? (chip->get(chip, i) ? "hi" : "lo") + : "? ", + (mode < 0) ? "unknown" : modes[mode], + pull ? "pull" : "none"); + + if (label && !is_out) { + int irq = gpio_to_irq(gpio); + struct irq_desc *desc = irq_to_desc(irq); + + /* This races with request_irq(), set_irq_type(), + * and set_irq_wake() ... but those are "rare". + */ + if (irq >= 0 && desc->action) { + char *trigger; + u32 bitmask = nmk_gpio_get_bitmask(gpio); + + if (nmk_chip->edge_rising & bitmask) + trigger = "edge-rising"; + else if (nmk_chip->edge_falling & bitmask) + trigger = "edge-falling"; + else + trigger = "edge-undefined"; + + seq_printf(s, " irq-%d %s%s", + irq, trigger, + irqd_is_wakeup_set(&desc->irq_data) + ? " wakeup" : ""); + } + } + seq_printf(s, "\n"); } + + clk_disable(nmk_chip->clk); } #else -static inline void nmk_gpio_dbg_show_one(struct seq_file *s, - struct gpio_chip *chip, - unsigned offset, unsigned gpio) -{ -} #define nmk_gpio_dbg_show NULL #endif /* This structure is replicated for each GPIO block allocated at probe time */ static struct gpio_chip nmk_gpio_template = { - .request = nmk_gpio_request, - .free = nmk_gpio_free, .direction_input = nmk_gpio_make_input, .get = nmk_gpio_get_input, .direction_output = nmk_gpio_make_output, @@ -1106,11 +1008,21 @@ void nmk_gpio_wakeups_suspend(void) clk_enable(chip->clk); + chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC); + chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC); + writel(chip->rwimsc & chip->real_wake, chip->addr + NMK_GPIO_RWIMSC); writel(chip->fwimsc & chip->real_wake, chip->addr + NMK_GPIO_FWIMSC); + if (chip->sleepmode) { + chip->slpm = readl(chip->addr + NMK_GPIO_SLPC); + + /* 0 -> wakeup enable */ + writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC); + } + clk_disable(chip->clk); } } @@ -1130,6 +1042,9 @@ void nmk_gpio_wakeups_resume(void) writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); + if (chip->sleepmode) + writel(chip->slpm, chip->addr + NMK_GPIO_SLPC); + clk_disable(chip->clk); } } @@ -1153,62 +1068,19 @@ void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) } } -int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct nmk_gpio_chip *nmk_chip = d->host_data; - - if (!nmk_chip) - return -EINVAL; - - irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); - set_irq_flags(irq, IRQF_VALID); - irq_set_chip_data(irq, nmk_chip); - irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); - - return 0; -} - -const struct irq_domain_ops nmk_gpio_irq_simple_ops = { - .map = nmk_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - static int __devinit nmk_gpio_probe(struct platform_device *dev) { struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; - struct device_node *np = dev->dev.of_node; struct nmk_gpio_chip *nmk_chip; struct gpio_chip *chip; struct resource *res; struct clk *clk; int secondary_irq; - void __iomem *base; int irq; int ret; - if (!pdata && !np) { - dev_err(&dev->dev, "No platform data or device tree found\n"); + if (!pdata) return -ENODEV; - } - - if (np) { - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return -ENOMEM; - - if (of_get_property(np, "supports-sleepmode", NULL)) - pdata->supports_sleepmode = true; - - if (of_property_read_u32(np, "gpio-bank", &dev->id)) { - dev_err(&dev->dev, "gpio-bank property not found\n"); - ret = -EINVAL; - goto out; - } - - pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; - pdata->num_gpio = NMK_GPIO_PER_CHIP; - } res = platform_get_resource(dev, IORESOURCE_MEM, 0); if (!res) { @@ -1234,16 +1106,10 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) goto out; } - base = ioremap(res->start, resource_size(res)); - if (!base) { - ret = -ENOMEM; - goto out_release; - } - clk = clk_get(&dev->dev, NULL); if (IS_ERR(clk)) { ret = PTR_ERR(clk); - goto out_unmap; + goto out_release; } nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); @@ -1251,14 +1117,13 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) ret = -ENOMEM; goto out_clk; } - /* * The virt address in nmk_chip->addr is in the nomadik register space, * so we can simply convert the resource address, without remapping */ nmk_chip->bank = dev->id; nmk_chip->clk = clk; - nmk_chip->addr = base; + nmk_chip->addr = io_p2v(res->start); nmk_chip->chip = nmk_gpio_template; nmk_chip->parent_irq = irq; nmk_chip->secondary_parent_irq = secondary_irq; @@ -1274,14 +1139,6 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) chip->dev = &dev->dev; chip->owner = THIS_MODULE; - clk_enable(nmk_chip->clk); - nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); - clk_disable(nmk_chip->clk); - -#ifdef CONFIG_OF_GPIO - chip->of_node = np; -#endif - ret = gpiochip_add(&nmk_chip->chip); if (ret) goto out_free; @@ -1289,22 +1146,12 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); nmk_gpio_chips[nmk_chip->bank] = nmk_chip; - platform_set_drvdata(dev, nmk_chip); - nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP, - NOMADIK_GPIO_TO_IRQ(pdata->first_gpio), - 0, &nmk_gpio_irq_simple_ops, nmk_chip); - if (!nmk_chip->domain) { - pr_err("%s: Failed to create irqdomain\n", np->full_name); - ret = -ENOSYS; - goto out_free; - } - nmk_gpio_init_irq(nmk_chip); - dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); - + dev_info(&dev->dev, "at address %p\n", + nmk_chip->addr); return 0; out_free: @@ -1312,465 +1159,25 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) out_clk: clk_disable(clk); clk_put(clk); -out_unmap: - iounmap(base); out_release: release_mem_region(res->start, resource_size(res)); out: dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, pdata->first_gpio, pdata->first_gpio+31); - if (np) - kfree(pdata); - return ret; } -static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - return npct->soc->ngroups; -} - -static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - return npct->soc->groups[selector].name; -} - -static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - *pins = npct->soc->groups[selector].pins; - *num_pins = npct->soc->groups[selector].npins; - return 0; -} - -static struct pinctrl_gpio_range * -nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - int i; - - for (i = 0; i < npct->soc->gpio_num_ranges; i++) { - struct pinctrl_gpio_range *range; - - range = &npct->soc->gpio_ranges[i]; - if (offset >= range->pin_base && - offset <= (range->pin_base + range->npins - 1)) - return range; - } - return NULL; -} - -static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - struct pinctrl_gpio_range *range; - struct gpio_chip *chip; - - range = nmk_match_gpio_range(pctldev, offset); - if (!range || !range->gc) { - seq_printf(s, "invalid pin offset"); - return; - } - chip = range->gc; - nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset); -} - -static struct pinctrl_ops nmk_pinctrl_ops = { - .get_groups_count = nmk_get_groups_cnt, - .get_group_name = nmk_get_group_name, - .get_group_pins = nmk_get_group_pins, - .pin_dbg_show = nmk_pin_dbg_show, -}; - -static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - return npct->soc->nfunctions; -} - -static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - return npct->soc->functions[function].name; -} - -static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, - unsigned function, - const char * const **groups, - unsigned * const num_groups) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - *groups = npct->soc->functions[function].groups; - *num_groups = npct->soc->functions[function].ngroups; - - return 0; -} - -static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - const struct nmk_pingroup *g; - static unsigned int slpm[NUM_BANKS]; - unsigned long flags; - bool glitch; - int ret = -EINVAL; - int i; - - g = &npct->soc->groups[group]; - - if (g->altsetting < 0) - return -EINVAL; - - dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); - - /* Handle this special glitch on altfunction C */ - glitch = (g->altsetting == NMK_GPIO_ALT_C); - - if (glitch) { - spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); - - /* Initially don't put any pins to sleep when switching */ - memset(slpm, 0xff, sizeof(slpm)); - - /* - * Then mask the pins that need to be sleeping now when we're - * switching to the ALT C function. - */ - for (i = 0; i < g->npins; i++) - slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); - nmk_gpio_glitch_slpm_init(slpm); - } - - for (i = 0; i < g->npins; i++) { - struct pinctrl_gpio_range *range; - struct nmk_gpio_chip *nmk_chip; - struct gpio_chip *chip; - unsigned bit; - - range = nmk_match_gpio_range(pctldev, g->pins[i]); - if (!range) { - dev_err(npct->dev, - "invalid pin offset %d in group %s at index %d\n", - g->pins[i], g->name, i); - goto out_glitch; - } - if (!range->gc) { - dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", - g->pins[i], g->name, i); - goto out_glitch; - } - chip = range->gc; - nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); - - clk_enable(nmk_chip->clk); - bit = g->pins[i] % NMK_GPIO_PER_CHIP; - /* - * If the pin is switching to altfunc, and there was an - * interrupt installed on it which has been lazy disabled, - * actually mask the interrupt to prevent spurious interrupts - * that would occur while the pin is under control of the - * peripheral. Only SKE does this. - */ - nmk_gpio_disable_lazy_irq(nmk_chip, bit); - - __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch); - clk_disable(nmk_chip->clk); - } - - /* When all pins are successfully reconfigured we get here */ - ret = 0; - -out_glitch: - if (glitch) { - nmk_gpio_glitch_slpm_restore(slpm); - spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); - } - - return ret; -} - -static void nmk_pmx_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - const struct nmk_pingroup *g; - - g = &npct->soc->groups[group]; - - if (g->altsetting < 0) - return; - - /* Poke out the mux, set the pin to some default state? */ - dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); -} - -int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - struct nmk_gpio_chip *nmk_chip; - struct gpio_chip *chip; - unsigned bit; - - if (!range) { - dev_err(npct->dev, "invalid range\n"); - return -EINVAL; - } - if (!range->gc) { - dev_err(npct->dev, "missing GPIO chip in range\n"); - return -EINVAL; - } - chip = range->gc; - nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - - dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); - - clk_enable(nmk_chip->clk); - bit = offset % NMK_GPIO_PER_CHIP; - /* There is no glitch when converting any pin to GPIO */ - __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); - clk_disable(nmk_chip->clk); - - return 0; -} - -void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); - /* Set the pin to some default state, GPIO is usually default */ -} - -static struct pinmux_ops nmk_pinmux_ops = { - .get_functions_count = nmk_pmx_get_funcs_cnt, - .get_function_name = nmk_pmx_get_func_name, - .get_function_groups = nmk_pmx_get_func_groups, - .enable = nmk_pmx_enable, - .disable = nmk_pmx_disable, - .gpio_request_enable = nmk_gpio_request_enable, - .gpio_disable_free = nmk_gpio_disable_free, -}; - -int nmk_pin_config_get(struct pinctrl_dev *pctldev, - unsigned pin, - unsigned long *config) -{ - /* Not implemented */ - return -EINVAL; -} - -int nmk_pin_config_set(struct pinctrl_dev *pctldev, - unsigned pin, - unsigned long config) -{ - static const char *pullnames[] = { - [NMK_GPIO_PULL_NONE] = "none", - [NMK_GPIO_PULL_UP] = "up", - [NMK_GPIO_PULL_DOWN] = "down", - [3] /* illegal */ = "??" - }; - static const char *slpmnames[] = { - [NMK_GPIO_SLPM_INPUT] = "input/wakeup", - [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", - }; - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - struct nmk_gpio_chip *nmk_chip; - struct pinctrl_gpio_range *range; - struct gpio_chip *chip; - unsigned bit; - - /* - * The pin config contains pin number and altfunction fields, here - * we just ignore that part. It's being handled by the framework and - * pinmux callback respectively. - */ - pin_cfg_t cfg = (pin_cfg_t) config; - int pull = PIN_PULL(cfg); - int slpm = PIN_SLPM(cfg); - int output = PIN_DIR(cfg); - int val = PIN_VAL(cfg); - bool lowemi = PIN_LOWEMI(cfg); - bool gpiomode = PIN_GPIOMODE(cfg); - bool sleep = PIN_SLEEPMODE(cfg); - - range = nmk_match_gpio_range(pctldev, pin); - if (!range) { - dev_err(npct->dev, "invalid pin offset %d\n", pin); - return -EINVAL; - } - if (!range->gc) { - dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", - pin); - return -EINVAL; - } - chip = range->gc; - nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - - if (sleep) { - int slpm_pull = PIN_SLPM_PULL(cfg); - int slpm_output = PIN_SLPM_DIR(cfg); - int slpm_val = PIN_SLPM_VAL(cfg); - - /* All pins go into GPIO mode at sleep */ - gpiomode = true; - - /* - * The SLPM_* values are normal values + 1 to allow zero to - * mean "same as normal". - */ - if (slpm_pull) - pull = slpm_pull - 1; - if (slpm_output) - output = slpm_output - 1; - if (slpm_val) - val = slpm_val - 1; - - dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", - pin, - slpm_pull ? pullnames[pull] : "same", - slpm_output ? (output ? "output" : "input") : "same", - slpm_val ? (val ? "high" : "low") : "same"); - } - - dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", - pin, cfg, pullnames[pull], slpmnames[slpm], - output ? "output " : "input", - output ? (val ? "high" : "low") : "", - lowemi ? "on" : "off" ); - - clk_enable(nmk_chip->clk); - bit = pin % NMK_GPIO_PER_CHIP; - if (gpiomode) - /* No glitch when going to GPIO mode */ - __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); - if (output) - __nmk_gpio_make_output(nmk_chip, bit, val); - else { - __nmk_gpio_make_input(nmk_chip, bit); - __nmk_gpio_set_pull(nmk_chip, bit, pull); - } - /* TODO: isn't this only applicable on output pins? */ - __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); - - __nmk_gpio_set_slpm(nmk_chip, bit, slpm); - clk_disable(nmk_chip->clk); - return 0; -} - -static struct pinconf_ops nmk_pinconf_ops = { - .pin_config_get = nmk_pin_config_get, - .pin_config_set = nmk_pin_config_set, -}; - -static struct pinctrl_desc nmk_pinctrl_desc = { - .name = "pinctrl-nomadik", - .pctlops = &nmk_pinctrl_ops, - .pmxops = &nmk_pinmux_ops, - .confops = &nmk_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int __devinit nmk_pinctrl_probe(struct platform_device *pdev) -{ - const struct platform_device_id *platid = platform_get_device_id(pdev); - struct nmk_pinctrl *npct; - int i; - - npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); - if (!npct) - return -ENOMEM; - - /* Poke in other ASIC variants here */ - if (platid->driver_data == PINCTRL_NMK_DB8500) - nmk_pinctrl_db8500_init(&npct->soc); - - /* - * We need all the GPIO drivers to probe FIRST, or we will not be able - * to obtain references to the struct gpio_chip * for them, and we - * need this to proceed. - */ - for (i = 0; i < npct->soc->gpio_num_ranges; i++) { - if (!nmk_gpio_chips[i]) { - dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); - devm_kfree(&pdev->dev, npct); - return -EPROBE_DEFER; - } - npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip; - } - - nmk_pinctrl_desc.pins = npct->soc->pins; - nmk_pinctrl_desc.npins = npct->soc->npins; - npct->dev = &pdev->dev; - npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); - if (!npct->pctl) { - dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); - return -EINVAL; - } - - /* We will handle a range of GPIO pins */ - for (i = 0; i < npct->soc->gpio_num_ranges; i++) - pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); - - platform_set_drvdata(pdev, npct); - dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); - - return 0; -} - -static const struct of_device_id nmk_gpio_match[] = { - { .compatible = "st,nomadik-gpio", }, - {} -}; - static struct platform_driver nmk_gpio_driver = { .driver = { .owner = THIS_MODULE, .name = "gpio", - .of_match_table = nmk_gpio_match, }, .probe = nmk_gpio_probe, }; -static const struct platform_device_id nmk_pinctrl_id[] = { - { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, - { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, -}; - -static struct platform_driver nmk_pinctrl_driver = { - .driver = { - .owner = THIS_MODULE, - .name = "pinctrl-nomadik", - }, - .probe = nmk_pinctrl_probe, - .id_table = nmk_pinctrl_id, -}; - static int __init nmk_gpio_init(void) { - int ret; - - ret = platform_driver_register(&nmk_gpio_driver); - if (ret) - return ret; - return platform_driver_register(&nmk_pinctrl_driver); + return platform_driver_register(&nmk_gpio_driver); } core_initcall(nmk_gpio_init); diff --git a/trunk/drivers/gpio/gpio-tegra.c b/trunk/drivers/gpio/gpio-tegra.c index dc5184d57892..12f349b3830d 100644 --- a/trunk/drivers/gpio/gpio-tegra.c +++ b/trunk/drivers/gpio/gpio-tegra.c @@ -26,10 +26,10 @@ #include #include #include -#include #include +#include #include #include @@ -108,29 +108,18 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value) tegra_gpio_writel(val, reg); } -static void tegra_gpio_enable(int gpio) +void tegra_gpio_enable(int gpio) { tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); } EXPORT_SYMBOL_GPL(tegra_gpio_enable); -static void tegra_gpio_disable(int gpio) +void tegra_gpio_disable(int gpio) { tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); } EXPORT_SYMBOL_GPL(tegra_gpio_disable); -int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - return pinctrl_request_gpio(offset); -} - -void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - pinctrl_free_gpio(offset); - tegra_gpio_disable(offset); -} - static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); @@ -144,7 +133,6 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); - tegra_gpio_enable(offset); return 0; } @@ -153,7 +141,6 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, { tegra_gpio_set(chip, offset, value); tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); - tegra_gpio_enable(offset); return 0; } @@ -164,14 +151,13 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) static struct gpio_chip tegra_gpio_chip = { .label = "tegra-gpio", - .request = tegra_gpio_request, - .free = tegra_gpio_free, .direction_input = tegra_gpio_direction_input, .get = tegra_gpio_get, .direction_output = tegra_gpio_direction_output, .set = tegra_gpio_set, .to_irq = tegra_gpio_to_irq, .base = 0, + .ngpio = TEGRA_NR_GPIOS, }; static void tegra_gpio_irq_ack(struct irq_data *d) @@ -238,9 +224,6 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) spin_unlock_irqrestore(&bank->lvl_lock[port], flags); - tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); - tegra_gpio_enable(gpio); - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) __irq_set_handler_locked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) @@ -507,6 +490,20 @@ static int __init tegra_gpio_init(void) } postcore_initcall(tegra_gpio_init); +void tegra_gpio_config(struct tegra_gpio_table *table, int num) +{ + int i; + + for (i = 0; i < num; i++) { + int gpio = table[i].gpio; + + if (table[i].enable) + tegra_gpio_enable(gpio); + else + tegra_gpio_disable(gpio); + } +} + #ifdef CONFIG_DEBUG_FS #include diff --git a/trunk/drivers/mmc/host/sdhci-tegra.c b/trunk/drivers/mmc/host/sdhci-tegra.c index ff5a16991939..53b26502f6e2 100644 --- a/trunk/drivers/mmc/host/sdhci-tegra.c +++ b/trunk/drivers/mmc/host/sdhci-tegra.c @@ -269,6 +269,7 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) "failed to allocate power gpio\n"); goto err_power_req; } + tegra_gpio_enable(plat->power_gpio); gpio_direction_output(plat->power_gpio, 1); } @@ -279,6 +280,7 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) "failed to allocate cd gpio\n"); goto err_cd_req; } + tegra_gpio_enable(plat->cd_gpio); gpio_direction_input(plat->cd_gpio); rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq, @@ -299,6 +301,7 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) "failed to allocate wp gpio\n"); goto err_wp_req; } + tegra_gpio_enable(plat->wp_gpio); gpio_direction_input(plat->wp_gpio); } @@ -326,17 +329,23 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) clk_disable(pltfm_host->clk); clk_put(pltfm_host->clk); err_clk_get: - if (gpio_is_valid(plat->wp_gpio)) + if (gpio_is_valid(plat->wp_gpio)) { + tegra_gpio_disable(plat->wp_gpio); gpio_free(plat->wp_gpio); + } err_wp_req: if (gpio_is_valid(plat->cd_gpio)) free_irq(gpio_to_irq(plat->cd_gpio), host); err_cd_irq_req: - if (gpio_is_valid(plat->cd_gpio)) + if (gpio_is_valid(plat->cd_gpio)) { + tegra_gpio_disable(plat->cd_gpio); gpio_free(plat->cd_gpio); + } err_cd_req: - if (gpio_is_valid(plat->power_gpio)) + if (gpio_is_valid(plat->power_gpio)) { + tegra_gpio_disable(plat->power_gpio); gpio_free(plat->power_gpio); + } err_power_req: err_no_plat: sdhci_pltfm_free(pdev); @@ -353,16 +362,21 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev) sdhci_remove_host(host, dead); - if (gpio_is_valid(plat->wp_gpio)) + if (gpio_is_valid(plat->wp_gpio)) { + tegra_gpio_disable(plat->wp_gpio); gpio_free(plat->wp_gpio); + } if (gpio_is_valid(plat->cd_gpio)) { free_irq(gpio_to_irq(plat->cd_gpio), host); + tegra_gpio_disable(plat->cd_gpio); gpio_free(plat->cd_gpio); } - if (gpio_is_valid(plat->power_gpio)) + if (gpio_is_valid(plat->power_gpio)) { + tegra_gpio_disable(plat->power_gpio); gpio_free(plat->power_gpio); + } clk_disable(pltfm_host->clk); clk_put(pltfm_host->clk); diff --git a/trunk/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/trunk/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8478fd9701a3..b68e04310bd8 100644 --- a/trunk/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/trunk/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -496,7 +496,7 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this) if (ret) goto exit_dma_channels; - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); + pinctrl = devm_pinctrl_get_select_default(&this->pdev->dev); if (IS_ERR(pinctrl)) { ret = PTR_ERR(pinctrl); goto exit_pin; diff --git a/trunk/drivers/of/base.c b/trunk/drivers/of/base.c index d9bfd49b1935..580644986945 100644 --- a/trunk/drivers/of/base.c +++ b/trunk/drivers/of/base.c @@ -1260,44 +1260,3 @@ int of_alias_get_id(struct device_node *np, const char *stem) return id; } EXPORT_SYMBOL_GPL(of_alias_get_id); - -const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur, - u32 *pu) -{ - const void *curv = cur; - - if (!prop) - return NULL; - - if (!cur) { - curv = prop->value; - goto out_val; - } - - curv += sizeof(*cur); - if (curv >= prop->value + prop->length) - return NULL; - -out_val: - *pu = be32_to_cpup(curv); - return curv; -} -EXPORT_SYMBOL_GPL(of_prop_next_u32); - -const char *of_prop_next_string(struct property *prop, const char *cur) -{ - const void *curv = cur; - - if (!prop) - return NULL; - - if (!cur) - return prop->value; - - curv += strlen(cur) + 1; - if (curv >= prop->value + prop->length) - return NULL; - - return curv; -} -EXPORT_SYMBOL_GPL(of_prop_next_string); diff --git a/trunk/drivers/pinctrl/Kconfig b/trunk/drivers/pinctrl/Kconfig index ce2e756b19ad..abfb96408779 100644 --- a/trunk/drivers/pinctrl/Kconfig +++ b/trunk/drivers/pinctrl/Kconfig @@ -4,6 +4,7 @@ config PINCTRL bool + depends on EXPERIMENTAL if PINCTRL @@ -26,19 +27,6 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. -config PINCTRL_IMX - bool - select PINMUX - select PINCONF - -config PINCTRL_IMX6Q - bool "IMX6Q pinctrl driver" - depends on OF - depends on SOC_IMX6Q - select PINCTRL_IMX - help - Say Y here to enable the imx6q pinctrl driver - config PINCTRL_PXA3xx bool select PINMUX @@ -49,31 +37,6 @@ config PINCTRL_MMP2 select PINCTRL_PXA3xx select PINCONF -config PINCTRL_MXS - bool - -config PINCTRL_IMX23 - bool - select PINMUX - select PINCONF - select PINCTRL_MXS - -config PINCTRL_IMX28 - bool - select PINMUX - select PINCONF - select PINCTRL_MXS - -config PINCTRL_NOMADIK - bool "Nomadik pin controller driver" - depends on ARCH_U8500 || ARCH_NOMADIK - select PINMUX - select PINCONF - -config PINCTRL_DB8500 - bool "DB8500 pin controller driver" - depends on PINCTRL_NOMADIK && ARCH_U8500 - config PINCTRL_PXA168 bool "PXA168 pin controller driver" depends on ARCH_MMP @@ -121,8 +84,6 @@ config PINCTRL_COH901 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 ports of 8 GPIO pins each. -source "drivers/pinctrl/spear/Kconfig" - endmenu endif diff --git a/trunk/drivers/pinctrl/Makefile b/trunk/drivers/pinctrl/Makefile index 8e764ade929a..6d4150b4eced 100644 --- a/trunk/drivers/pinctrl/Makefile +++ b/trunk/drivers/pinctrl/Makefile @@ -5,19 +5,9 @@ ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG obj-$(CONFIG_PINCTRL) += core.o obj-$(CONFIG_PINMUX) += pinmux.o obj-$(CONFIG_PINCONF) += pinconf.o -ifeq ($(CONFIG_OF),y) -obj-$(CONFIG_PINCTRL) += devicetree.o -endif obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o -obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o -obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o -obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o -obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o -obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o -obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o -obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o @@ -26,5 +16,3 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o - -obj-$(CONFIG_PLAT_SPEAR) += spear/ diff --git a/trunk/drivers/pinctrl/core.c b/trunk/drivers/pinctrl/core.c index c3b331b74fa0..df6296c5f47b 100644 --- a/trunk/drivers/pinctrl/core.c +++ b/trunk/drivers/pinctrl/core.c @@ -23,11 +23,9 @@ #include #include #include -#include #include #include #include "core.h" -#include "devicetree.h" #include "pinmux.h" #include "pinconf.h" @@ -43,13 +41,11 @@ struct pinctrl_maps { unsigned num_maps; }; -static bool pinctrl_dummy_state; - /* Mutex taken by all entry points */ DEFINE_MUTEX(pinctrl_mutex); /* Global list of pin control devices (struct pinctrl_dev) */ -LIST_HEAD(pinctrldev_list); +static LIST_HEAD(pinctrldev_list); /* List of pin controller handles (struct pinctrl) */ static LIST_HEAD(pinctrl_list); @@ -63,19 +59,6 @@ static LIST_HEAD(pinctrl_maps); _i_ < _maps_node_->num_maps; \ i++, _map_ = &_maps_node_->maps[_i_]) -/** - * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support - * - * Usually this function is called by platforms without pinctrl driver support - * but run with some shared drivers using pinctrl APIs. - * After calling this function, the pinctrl core will return successfully - * with creating a dummy state for the driver to keep going smoothly. - */ -void pinctrl_provide_dummies(void) -{ - pinctrl_dummy_state = true; -} - const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev) { /* We're not allowed to register devices without name */ @@ -140,25 +123,6 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name) return -EINVAL; } -/** - * pin_get_name_from_id() - look up a pin name from a pin id - * @pctldev: the pin control device to lookup the pin on - * @name: the name of the pin to look up - */ -const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin) -{ - const struct pin_desc *desc; - - desc = pin_desc_get(pctldev, pin); - if (desc == NULL) { - dev_err(pctldev->dev, "failed to get pin(%d) name\n", - pin); - return NULL; - } - - return desc->name; -} - /** * pin_is_valid() - check if pin exists on controller * @pctldev: the pin control device to check the pin on @@ -291,8 +255,7 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio) * * Find the pin controller handling a certain GPIO pin from the pinspace of * the GPIO subsystem, return the device and the matching GPIO range. Returns - * -EPROBE_DEFER if the GPIO range could not be found in any device since it - * may still have not been registered. + * negative if the GPIO range could not be found in any device. */ static int pinctrl_get_device_gpio_range(unsigned gpio, struct pinctrl_dev **outdev, @@ -312,7 +275,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio, } } - return -EPROBE_DEFER; + return -EINVAL; } /** @@ -355,10 +318,9 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, const char *pin_group) { const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - unsigned ngroups = pctlops->get_groups_count(pctldev); unsigned group_selector = 0; - while (group_selector < ngroups) { + while (pctlops->list_groups(pctldev, group_selector) >= 0) { const char *gname = pctlops->get_group_name(pctldev, group_selector); if (!strcmp(gname, pin_group)) { @@ -398,7 +360,7 @@ int pinctrl_request_gpio(unsigned gpio) ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { mutex_unlock(&pinctrl_mutex); - return ret; + return -EINVAL; } /* Convert to the pin controllers number space */ @@ -554,14 +516,11 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map) setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); if (setting->pctldev == NULL) { - dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe", + dev_err(p->dev, "unknown pinctrl device %s in map entry", map->ctrl_dev_name); kfree(setting); - /* - * OK let us guess that the driver is not there yet, and - * let's defer obtaining this pinctrl handle to later... - */ - return -EPROBE_DEFER; + /* Eventually, this should trigger deferred probe */ + return -ENODEV; } switch (map->type) { @@ -620,13 +579,6 @@ static struct pinctrl *create_pinctrl(struct device *dev) } p->dev = dev; INIT_LIST_HEAD(&p->states); - INIT_LIST_HEAD(&p->dt_maps); - - ret = pinctrl_dt_to_map(p); - if (ret < 0) { - kfree(p); - return ERR_PTR(ret); - } devname = dev_name(dev); @@ -710,8 +662,6 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist) kfree(state); } - pinctrl_dt_free_maps(p); - if (inlist) list_del(&p->node); kfree(p); @@ -735,18 +685,8 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p, struct pinctrl_state *state; state = find_state(p, name); - if (!state) { - if (pinctrl_dummy_state) { - /* create dummy state */ - dev_dbg(p->dev, "using pinctrl dummy state (%s)\n", - name); - state = create_state(p, name); - if (IS_ERR(state)) - return state; - } else { - return ERR_PTR(-ENODEV); - } - } + if (!state) + return ERR_PTR(-ENODEV); return state; } @@ -847,63 +787,15 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state) } EXPORT_SYMBOL_GPL(pinctrl_select_state); -static void devm_pinctrl_release(struct device *dev, void *res) -{ - pinctrl_put(*(struct pinctrl **)res); -} - -/** - * struct devm_pinctrl_get() - Resource managed pinctrl_get() - * @dev: the device to obtain the handle for - * - * If there is a need to explicitly destroy the returned struct pinctrl, - * devm_pinctrl_put() should be used, rather than plain pinctrl_put(). - */ -struct pinctrl *devm_pinctrl_get(struct device *dev) -{ - struct pinctrl **ptr, *p; - - ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL); - if (!ptr) - return ERR_PTR(-ENOMEM); - - p = pinctrl_get(dev); - if (!IS_ERR(p)) { - *ptr = p; - devres_add(dev, ptr); - } else { - devres_free(ptr); - } - - return p; -} -EXPORT_SYMBOL_GPL(devm_pinctrl_get); - -static int devm_pinctrl_match(struct device *dev, void *res, void *data) -{ - struct pinctrl **p = res; - - return *p == data; -} - /** - * devm_pinctrl_put() - Resource managed pinctrl_put() - * @p: the pinctrl handle to release - * - * Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally - * this function will not need to be called and the resource management - * code will ensure that the resource is freed. + * pinctrl_register_mappings() - register a set of pin controller mappings + * @maps: the pincontrol mappings table to register. This should probably be + * marked with __initdata so it can be discarded after boot. This + * function will perform a shallow copy for the mapping entries. + * @num_maps: the number of maps in the mapping table */ -void devm_pinctrl_put(struct pinctrl *p) -{ - WARN_ON(devres_destroy(p->dev, devm_pinctrl_release, - devm_pinctrl_match, p)); - pinctrl_put(p); -} -EXPORT_SYMBOL_GPL(devm_pinctrl_put); - -int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, - bool dup, bool locked) +int pinctrl_register_mappings(struct pinctrl_map const *maps, + unsigned num_maps) { int i, ret; struct pinctrl_maps *maps_node; @@ -937,13 +829,13 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, case PIN_MAP_TYPE_MUX_GROUP: ret = pinmux_validate_map(&maps[i], i); if (ret < 0) - return ret; + return 0; break; case PIN_MAP_TYPE_CONFIGS_PIN: case PIN_MAP_TYPE_CONFIGS_GROUP: ret = pinconf_validate_map(&maps[i], i); if (ret < 0) - return ret; + return 0; break; default: pr_err("failed to register map %s (%d): invalid type given\n", @@ -959,52 +851,20 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, } maps_node->num_maps = num_maps; - if (dup) { - maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, - GFP_KERNEL); - if (!maps_node->maps) { - pr_err("failed to duplicate mapping table\n"); - kfree(maps_node); - return -ENOMEM; - } - } else { - maps_node->maps = maps; + maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL); + if (!maps_node->maps) { + pr_err("failed to duplicate mapping table\n"); + kfree(maps_node); + return -ENOMEM; } - if (!locked) - mutex_lock(&pinctrl_mutex); + mutex_lock(&pinctrl_mutex); list_add_tail(&maps_node->node, &pinctrl_maps); - if (!locked) - mutex_unlock(&pinctrl_mutex); + mutex_unlock(&pinctrl_mutex); return 0; } -/** - * pinctrl_register_mappings() - register a set of pin controller mappings - * @maps: the pincontrol mappings table to register. This should probably be - * marked with __initdata so it can be discarded after boot. This - * function will perform a shallow copy for the mapping entries. - * @num_maps: the number of maps in the mapping table - */ -int pinctrl_register_mappings(struct pinctrl_map const *maps, - unsigned num_maps) -{ - return pinctrl_register_map(maps, num_maps, true, false); -} - -void pinctrl_unregister_map(struct pinctrl_map const *map) -{ - struct pinctrl_maps *maps_node; - - list_for_each_entry(maps_node, &pinctrl_maps, node) { - if (maps_node->maps == map) { - list_del(&maps_node->node); - return; - } - } -} - #ifdef CONFIG_DEBUG_FS static int pinctrl_pins_show(struct seq_file *s, void *what) @@ -1046,17 +906,15 @@ static int pinctrl_groups_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; const struct pinctrl_ops *ops = pctldev->desc->pctlops; - unsigned ngroups, selector = 0; + unsigned selector = 0; - ngroups = ops->get_groups_count(pctldev); mutex_lock(&pinctrl_mutex); seq_puts(s, "registered pin groups:\n"); - while (selector < ngroups) { + while (ops->list_groups(pctldev, selector) >= 0) { const unsigned *pins; unsigned num_pins; const char *gname = ops->get_group_name(pctldev, selector); - const char *pname; int ret; int i; @@ -1066,14 +924,10 @@ static int pinctrl_groups_show(struct seq_file *s, void *what) seq_printf(s, "%s [ERROR GETTING PINS]\n", gname); else { - seq_printf(s, "group: %s\n", gname); - for (i = 0; i < num_pins; i++) { - pname = pin_get_name(pctldev, pins[i]); - if (WARN_ON(!pname)) - return -EINVAL; - seq_printf(s, "pin %d (%s)\n", pins[i], pname); - } - seq_puts(s, "\n"); + seq_printf(s, "group: %s, pins = [ ", gname); + for (i = 0; i < num_pins; i++) + seq_printf(s, "%d ", pins[i]); + seq_puts(s, "]\n"); } selector++; } @@ -1372,14 +1226,11 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev) const struct pinctrl_ops *ops = pctldev->desc->pctlops; if (!ops || - !ops->get_groups_count || + !ops->list_groups || !ops->get_group_name || !ops->get_group_pins) return -EINVAL; - if (ops->dt_node_to_map && !ops->dt_free_map) - return -EINVAL; - return 0; } @@ -1417,29 +1268,37 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, /* check core ops for sanity */ ret = pinctrl_check_ops(pctldev); if (ret) { - dev_err(dev, "pinctrl ops lacks necessary functions\n"); + pr_err("%s pinctrl ops lacks necessary functions\n", + pctldesc->name); goto out_err; } /* If we're implementing pinmuxing, check the ops for sanity */ if (pctldesc->pmxops) { ret = pinmux_check_ops(pctldev); - if (ret) + if (ret) { + pr_err("%s pinmux ops lacks necessary functions\n", + pctldesc->name); goto out_err; + } } /* If we're implementing pinconfig, check the ops for sanity */ if (pctldesc->confops) { ret = pinconf_check_ops(pctldev); - if (ret) + if (ret) { + pr_err("%s pin config ops lacks necessary functions\n", + pctldesc->name); goto out_err; + } } /* Register all the pins */ - dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins); + pr_debug("try to register %d pins on %s...\n", + pctldesc->npins, pctldesc->name); ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins); if (ret) { - dev_err(dev, "error during pin registration\n"); + pr_err("error during pin registration\n"); pinctrl_free_pindescs(pctldev, pctldesc->pins, pctldesc->npins); goto out_err; @@ -1454,15 +1313,8 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, struct pinctrl_state *s = pinctrl_lookup_state_locked(pctldev->p, PINCTRL_STATE_DEFAULT); - if (IS_ERR(s)) { - dev_dbg(dev, "failed to lookup the default state\n"); - } else { - ret = pinctrl_select_state_locked(pctldev->p, s); - if (ret) { - dev_err(dev, - "failed to select default state\n"); - } - } + if (!IS_ERR(s)) + pinctrl_select_state_locked(pctldev->p, s); } mutex_unlock(&pinctrl_mutex); diff --git a/trunk/drivers/pinctrl/core.h b/trunk/drivers/pinctrl/core.h index 1f40ff68a8c4..17ecf651b123 100644 --- a/trunk/drivers/pinctrl/core.h +++ b/trunk/drivers/pinctrl/core.h @@ -52,15 +52,12 @@ struct pinctrl_dev { * @dev: the device using this pin control handle * @states: a list of states for this device * @state: the current state - * @dt_maps: the mapping table chunks dynamically parsed from device tree for - * this device, if any */ struct pinctrl { struct list_head node; struct device *dev; struct list_head states; struct pinctrl_state *state; - struct list_head dt_maps; }; /** @@ -103,8 +100,7 @@ struct pinctrl_setting_configs { * struct pinctrl_setting - an individual mux or config setting * @node: list node for struct pinctrl_settings's @settings field * @type: the type of setting - * @pctldev: pin control device handling to be programmed. Not used for - * PIN_MAP_TYPE_DUMMY_STATE. + * @pctldev: pin control device handling to be programmed * @data: Data specific to the setting type */ struct pinctrl_setting { @@ -148,7 +144,6 @@ struct pin_desc { struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name); -const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin); int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, const char *pin_group); @@ -158,9 +153,4 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev, return radix_tree_lookup(&pctldev->pin_desc_tree, pin); } -int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, - bool dup, bool locked); -void pinctrl_unregister_map(struct pinctrl_map const *map); - extern struct mutex pinctrl_mutex; -extern struct list_head pinctrldev_list; diff --git a/trunk/drivers/pinctrl/devicetree.c b/trunk/drivers/pinctrl/devicetree.c deleted file mode 100644 index fcb1de45473c..000000000000 --- a/trunk/drivers/pinctrl/devicetree.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Device tree integration for the pin control subsystem - * - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -#include "core.h" -#include "devicetree.h" - -/** - * struct pinctrl_dt_map - mapping table chunk parsed from device tree - * @node: list node for struct pinctrl's @dt_maps field - * @pctldev: the pin controller that allocated this struct, and will free it - * @maps: the mapping table entries - */ -struct pinctrl_dt_map { - struct list_head node; - struct pinctrl_dev *pctldev; - struct pinctrl_map *map; - unsigned num_maps; -}; - -static void dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - if (pctldev) { - struct pinctrl_ops *ops = pctldev->desc->pctlops; - ops->dt_free_map(pctldev, map, num_maps); - } else { - /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ - kfree(map); - } -} - -void pinctrl_dt_free_maps(struct pinctrl *p) -{ - struct pinctrl_dt_map *dt_map, *n1; - - list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) { - pinctrl_unregister_map(dt_map->map); - list_del(&dt_map->node); - dt_free_map(dt_map->pctldev, dt_map->map, - dt_map->num_maps); - kfree(dt_map); - } - - of_node_put(p->dev->of_node); -} - -static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, - struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - struct pinctrl_dt_map *dt_map; - - /* Initialize common mapping table entry fields */ - for (i = 0; i < num_maps; i++) { - map[i].dev_name = dev_name(p->dev); - map[i].name = statename; - if (pctldev) - map[i].ctrl_dev_name = dev_name(pctldev->dev); - } - - /* Remember the converted mapping table entries */ - dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL); - if (!dt_map) { - dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n"); - dt_free_map(pctldev, map, num_maps); - return -ENOMEM; - } - - dt_map->pctldev = pctldev; - dt_map->map = map; - dt_map->num_maps = num_maps; - list_add_tail(&dt_map->node, &p->dt_maps); - - return pinctrl_register_map(map, num_maps, false, true); -} - -static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np) -{ - struct pinctrl_dev *pctldev; - - list_for_each_entry(pctldev, &pinctrldev_list, node) - if (pctldev->dev->of_node == np) - return pctldev; - - return NULL; -} - -static int dt_to_map_one_config(struct pinctrl *p, const char *statename, - struct device_node *np_config) -{ - struct device_node *np_pctldev; - struct pinctrl_dev *pctldev; - struct pinctrl_ops *ops; - int ret; - struct pinctrl_map *map; - unsigned num_maps; - - /* Find the pin controller containing np_config */ - np_pctldev = of_node_get(np_config); - for (;;) { - np_pctldev = of_get_next_parent(np_pctldev); - if (!np_pctldev || of_node_is_root(np_pctldev)) { - dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n", - np_config->full_name); - of_node_put(np_pctldev); - /* OK let's just assume this will appear later then */ - return -EPROBE_DEFER; - } - pctldev = find_pinctrl_by_of_node(np_pctldev); - if (pctldev) - break; - } - of_node_put(np_pctldev); - - /* - * Call pinctrl driver to parse device tree node, and - * generate mapping table entries - */ - ops = pctldev->desc->pctlops; - if (!ops->dt_node_to_map) { - dev_err(p->dev, "pctldev %s doesn't support DT\n", - dev_name(pctldev->dev)); - return -ENODEV; - } - ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps); - if (ret < 0) - return ret; - - /* Stash the mapping table chunk away for later use */ - return dt_remember_or_free_map(p, statename, pctldev, map, num_maps); -} - -static int dt_remember_dummy_state(struct pinctrl *p, const char *statename) -{ - struct pinctrl_map *map; - - map = kzalloc(sizeof(*map), GFP_KERNEL); - if (!map) { - dev_err(p->dev, "failed to alloc struct pinctrl_map\n"); - return -ENOMEM; - } - - /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ - map->type = PIN_MAP_TYPE_DUMMY_STATE; - - return dt_remember_or_free_map(p, statename, NULL, map, 1); -} - -int pinctrl_dt_to_map(struct pinctrl *p) -{ - struct device_node *np = p->dev->of_node; - int state, ret; - char *propname; - struct property *prop; - const char *statename; - const __be32 *list; - int size, config; - phandle phandle; - struct device_node *np_config; - - /* CONFIG_OF enabled, p->dev not instantiated from DT */ - if (!np) { - dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n"); - return 0; - } - - /* We may store pointers to property names within the node */ - of_node_get(np); - - /* For each defined state ID */ - for (state = 0; ; state++) { - /* Retrieve the pinctrl-* property */ - propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state); - prop = of_find_property(np, propname, &size); - kfree(propname); - if (!prop) - break; - list = prop->value; - size /= sizeof(*list); - - /* Determine whether pinctrl-names property names the state */ - ret = of_property_read_string_index(np, "pinctrl-names", - state, &statename); - /* - * If not, statename is just the integer state ID. But rather - * than dynamically allocate it and have to free it later, - * just point part way into the property name for the string. - */ - if (ret < 0) { - /* strlen("pinctrl-") == 8 */ - statename = prop->name + 8; - } - - /* For every referenced pin configuration node in it */ - for (config = 0; config < size; config++) { - phandle = be32_to_cpup(list++); - - /* Look up the pin configuration node */ - np_config = of_find_node_by_phandle(phandle); - if (!np_config) { - dev_err(p->dev, - "prop %s index %i invalid phandle\n", - prop->name, config); - ret = -EINVAL; - goto err; - } - - /* Parse the node */ - ret = dt_to_map_one_config(p, statename, np_config); - of_node_put(np_config); - if (ret < 0) - goto err; - } - - /* No entries in DT? Generate a dummy state table entry */ - if (!size) { - ret = dt_remember_dummy_state(p, statename); - if (ret < 0) - goto err; - } - } - - return 0; - -err: - pinctrl_dt_free_maps(p); - return ret; -} diff --git a/trunk/drivers/pinctrl/devicetree.h b/trunk/drivers/pinctrl/devicetree.h deleted file mode 100644 index 760bc4960f58..000000000000 --- a/trunk/drivers/pinctrl/devicetree.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Internal interface to pinctrl device tree integration - * - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifdef CONFIG_OF - -void pinctrl_dt_free_maps(struct pinctrl *p); -int pinctrl_dt_to_map(struct pinctrl *p); - -#else - -static inline int pinctrl_dt_to_map(struct pinctrl *p) -{ - return 0; -} - -static inline void pinctrl_dt_free_maps(struct pinctrl *p) -{ -} - -#endif diff --git a/trunk/drivers/pinctrl/pinconf.c b/trunk/drivers/pinctrl/pinconf.c index 7ce139ef7e64..7321e8601294 100644 --- a/trunk/drivers/pinctrl/pinconf.c +++ b/trunk/drivers/pinctrl/pinconf.c @@ -28,17 +28,11 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev) const struct pinconf_ops *ops = pctldev->desc->confops; /* We must be able to read out pin status */ - if (!ops->pin_config_get && !ops->pin_config_group_get) { - dev_err(pctldev->dev, - "pinconf must be able to read out pin status\n"); + if (!ops->pin_config_get && !ops->pin_config_group_get) return -EINVAL; - } /* We have to be able to config the pins in SOME way */ - if (!ops->pin_config_set && !ops->pin_config_group_set) { - dev_err(pctldev->dev, - "pinconf has to be able to set a pins config\n"); + if (!ops->pin_config_set && !ops->pin_config_group_set) return -EINVAL; - } return 0; } @@ -385,16 +379,8 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) { - struct pinctrl_dev *pctldev; - const struct pinconf_ops *confops; int i; - pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); - if (pctldev) - confops = pctldev->desc->confops; - else - confops = NULL; - switch (map->type) { case PIN_MAP_TYPE_CONFIGS_PIN: seq_printf(s, "pin "); @@ -408,15 +394,8 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) seq_printf(s, "%s\n", map->data.configs.group_or_pin); - for (i = 0; i < map->data.configs.num_configs; i++) { - seq_printf(s, "config "); - if (confops && confops->pin_config_config_dbg_show) - confops->pin_config_config_dbg_show(pctldev, s, - map->data.configs.configs[i]); - else - seq_printf(s, "%08lx", map->data.configs.configs[i]); - seq_printf(s, "\n"); - } + for (i = 0; i < map->data.configs.num_configs; i++) + seq_printf(s, "config %08lx\n", map->data.configs.configs[i]); } void pinconf_show_setting(struct seq_file *s, @@ -424,7 +403,6 @@ void pinconf_show_setting(struct seq_file *s, { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - const struct pinconf_ops *confops = pctldev->desc->confops; struct pin_desc *desc; int i; @@ -450,15 +428,8 @@ void pinconf_show_setting(struct seq_file *s, * FIXME: We should really get the pin controler to dump the config * values, so they can be decoded to something meaningful. */ - for (i = 0; i < setting->data.configs.num_configs; i++) { - seq_printf(s, " "); - if (confops && confops->pin_config_config_dbg_show) - confops->pin_config_config_dbg_show(pctldev, s, - setting->data.configs.configs[i]); - else - seq_printf(s, "%08lx", - setting->data.configs.configs[i]); - } + for (i = 0; i < setting->data.configs.num_configs; i++) + seq_printf(s, " %08lx", setting->data.configs.configs[i]); seq_printf(s, "\n"); } @@ -477,14 +448,10 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev, static int pinconf_pins_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; - const struct pinconf_ops *ops = pctldev->desc->confops; unsigned i, pin; - if (!ops || !ops->pin_config_get) - return 0; - seq_puts(s, "Pin config settings per pin\n"); - seq_puts(s, "Format: pin (name): configs\n"); + seq_puts(s, "Format: pin (name): pinmux setting array\n"); mutex_lock(&pinctrl_mutex); @@ -528,18 +495,17 @@ static int pinconf_groups_show(struct seq_file *s, void *what) struct pinctrl_dev *pctldev = s->private; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; const struct pinconf_ops *ops = pctldev->desc->confops; - unsigned ngroups = pctlops->get_groups_count(pctldev); unsigned selector = 0; if (!ops || !ops->pin_config_group_get) return 0; seq_puts(s, "Pin config settings per pin group\n"); - seq_puts(s, "Format: group (name): configs\n"); + seq_puts(s, "Format: group (name): pinmux setting array\n"); mutex_lock(&pinctrl_mutex); - while (selector < ngroups) { + while (pctlops->list_groups(pctldev, selector) >= 0) { const char *gname = pctlops->get_group_name(pctldev, selector); seq_printf(s, "%u (%s):", selector, gname); diff --git a/trunk/drivers/pinctrl/pinconf.h b/trunk/drivers/pinctrl/pinconf.h index e3ed8cb072a5..54510de5e8c6 100644 --- a/trunk/drivers/pinctrl/pinconf.h +++ b/trunk/drivers/pinctrl/pinconf.h @@ -19,6 +19,11 @@ int pinconf_map_to_setting(struct pinctrl_map const *map, struct pinctrl_setting *setting); void pinconf_free_setting(struct pinctrl_setting const *setting); int pinconf_apply_setting(struct pinctrl_setting const *setting); +void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map); +void pinconf_show_setting(struct seq_file *s, + struct pinctrl_setting const *setting); +void pinconf_init_device_debugfs(struct dentry *devroot, + struct pinctrl_dev *pctldev); /* * You will only be interested in these if you're using PINCONF @@ -56,18 +61,6 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting) return 0; } -#endif - -#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS) - -void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map); -void pinconf_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting); -void pinconf_init_device_debugfs(struct dentry *devroot, - struct pinctrl_dev *pctldev); - -#else - static inline void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) { diff --git a/trunk/drivers/pinctrl/pinctrl-coh901.c b/trunk/drivers/pinctrl/pinctrl-coh901.c index 55697a5d7482..0797eba3e33a 100644 --- a/trunk/drivers/pinctrl/pinctrl-coh901.c +++ b/trunk/drivers/pinctrl/pinctrl-coh901.c @@ -174,7 +174,7 @@ struct u300_gpio_confdata { /* Initial configuration */ -static const struct __initconst u300_gpio_confdata +static const struct __initdata u300_gpio_confdata bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { /* Port 0, pins 0-7 */ { @@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { } }; -static const struct __initconst u300_gpio_confdata +static const struct __initdata u300_gpio_confdata bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { /* Port 0, pins 0-7 */ { diff --git a/trunk/drivers/pinctrl/pinctrl-imx.c b/trunk/drivers/pinctrl/pinctrl-imx.c deleted file mode 100644 index 8faf613ff1b2..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx.c +++ /dev/null @@ -1,627 +0,0 @@ -/* - * Core driver for the imx pin controller - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro Ltd. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" -#include "pinctrl-imx.h" - -#define IMX_PMX_DUMP(info, p, m, c, n) \ -{ \ - int i, j; \ - printk("Format: Pin Mux Config\n"); \ - for (i = 0; i < n; i++) { \ - j = p[i]; \ - printk("%s %d 0x%lx\n", \ - info->pins[j].name, \ - m[i], c[i]); \ - } \ -} - -/* The bits in CONFIG cell defined in binding doc*/ -#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ -#define IMX_PAD_SION 0x40000000 /* set SION */ - -/** - * @dev: a pointer back to containing device - * @base: the offset to the controller in virtual memory - */ -struct imx_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - const struct imx_pinctrl_soc_info *info; -}; - -static const struct imx_pin_reg *imx_find_pin_reg( - const struct imx_pinctrl_soc_info *info, - unsigned pin, bool is_mux, unsigned mux) -{ - const struct imx_pin_reg *pin_reg = NULL; - int i; - - for (i = 0; i < info->npin_regs; i++) { - pin_reg = &info->pin_regs[i]; - if (pin_reg->pid != pin) - continue; - if (!is_mux) - break; - else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK)) - break; - } - - if (!pin_reg) { - dev_err(info->dev, "Pin(%s): unable to find pin reg map\n", - info->pins[pin].name); - return NULL; - } - - return pin_reg; -} - -static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( - const struct imx_pinctrl_soc_info *info, - const char *name) -{ - const struct imx_pin_group *grp = NULL; - int i; - - for (i = 0; i < info->ngroups; i++) { - if (!strcmp(info->groups[i].name, name)) { - grp = &info->groups[i]; - break; - } - } - - return grp; -} - -static int imx_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->ngroups; -} - -static const char *imx_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->groups[selector].name; -} - -static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *npins) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - if (selector >= info->ngroups) - return -EINVAL; - - *pins = info->groups[selector].pins; - *npins = info->groups[selector].npins; - - return 0; -} - -static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, "%s", dev_name(pctldev->dev)); -} - -static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_group *grp; - struct pinctrl_map *new_map; - struct device_node *parent; - int map_num = 1; - int i; - - /* - * first find the group of this node and check if we need create - * config maps for pins - */ - grp = imx_pinctrl_find_group_by_name(info, np->name); - if (!grp) { - dev_err(info->dev, "unable to find group for node %s\n", - np->name); - return -EINVAL; - } - - for (i = 0; i < grp->npins; i++) { - if (!(grp->configs[i] & IMX_NO_PAD_CTL)) - map_num++; - } - - new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - *map = new_map; - *num_maps = map_num; - - /* create mux map */ - parent = of_get_parent(np); - if (!parent) - return -EINVAL; - new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[0].data.mux.function = parent->name; - new_map[0].data.mux.group = np->name; - of_node_put(parent); - - /* create config map */ - new_map++; - for (i = 0; i < grp->npins; i++) { - if (!(grp->configs[i] & IMX_NO_PAD_CTL)) { - new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[i].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i]); - new_map[i].data.configs.configs = &grp->configs[i]; - new_map[i].data.configs.num_configs = 1; - } - } - - dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", - new_map->data.mux.function, new_map->data.mux.group, map_num); - - return 0; -} - -static void imx_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - kfree(map); -} - -static struct pinctrl_ops imx_pctrl_ops = { - .get_groups_count = imx_get_groups_count, - .get_group_name = imx_get_group_name, - .get_group_pins = imx_get_group_pins, - .pin_dbg_show = imx_pin_dbg_show, - .dt_node_to_map = imx_dt_node_to_map, - .dt_free_map = imx_dt_free_map, - -}; - -static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - const unsigned *pins, *mux; - unsigned int npins, pin_id; - int i; - - /* - * Configure the mux mode for each pin in the group for a specific - * function. - */ - pins = info->groups[group].pins; - npins = info->groups[group].npins; - mux = info->groups[group].mux_mode; - - WARN_ON(!pins || !npins || !mux); - - dev_dbg(ipctl->dev, "enable function %s group %s\n", - info->functions[selector].name, info->groups[group].name); - - for (i = 0; i < npins; i++) { - pin_id = pins[i]; - - pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]); - if (!pin_reg) - return -EINVAL; - - if (!pin_reg->mux_reg) { - dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - writel(mux[i], ipctl->base + pin_reg->mux_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, mux[i]); - - /* some pins also need select input setting, set it if found */ - if (pin_reg->input_reg) { - writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg); - dev_dbg(ipctl->dev, - "==>select_input: offset 0x%x val 0x%x\n", - pin_reg->input_reg, pin_reg->input_val); - } - } - - return 0; -} - -static void imx_pmx_disable(struct pinctrl_dev *pctldev, unsigned func_selector, - unsigned group_selector) -{ - /* nothing to do here */ -} - -static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->nfunctions; -} - -static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->functions[selector].name; -} - -static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - *groups = info->functions[selector].groups; - *num_groups = info->functions[selector].num_groups; - - return 0; -} - -static struct pinmux_ops imx_pmx_ops = { - .get_functions_count = imx_pmx_get_funcs_count, - .get_function_name = imx_pmx_get_func_name, - .get_function_groups = imx_pmx_get_groups, - .enable = imx_pmx_enable, - .disable = imx_pmx_disable, -}; - -static int imx_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg) - return -EINVAL; - - if (!pin_reg->conf_reg) { - dev_err(info->dev, "Pin(%s) does not support config function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - *config = readl(ipctl->base + pin_reg->conf_reg); - - return 0; -} - -static int imx_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long config) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg) - return -EINVAL; - - if (!pin_reg->conf_reg) { - dev_err(info->dev, "Pin(%s) does not support config function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - dev_dbg(ipctl->dev, "pinconf set pin %s\n", - info->pins[pin_id].name); - - writel(config, ipctl->base + pin_reg->conf_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", - pin_reg->conf_reg, config); - - return 0; -} - -static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin_id) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - unsigned long config; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg || !pin_reg->conf_reg) { - seq_printf(s, "N/A"); - return; - } - - config = readl(ipctl->base + pin_reg->conf_reg); - seq_printf(s, "0x%lx", config); -} - -static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - struct imx_pin_group *grp; - unsigned long config; - const char *name; - int i, ret; - - if (group > info->ngroups) - return; - - seq_printf(s, "\n"); - grp = &info->groups[group]; - for (i = 0; i < grp->npins; i++) { - name = pin_get_name(pctldev, grp->pins[i]); - ret = imx_pinconf_get(pctldev, grp->pins[i], &config); - if (ret) - return; - seq_printf(s, "%s: 0x%lx", name, config); - } -} - -struct pinconf_ops imx_pinconf_ops = { - .pin_config_get = imx_pinconf_get, - .pin_config_set = imx_pinconf_set, - .pin_config_dbg_show = imx_pinconf_dbg_show, - .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc imx_pinctrl_desc = { - .pctlops = &imx_pctrl_ops, - .pmxops = &imx_pmx_ops, - .confops = &imx_pinconf_ops, - .owner = THIS_MODULE, -}; - -/* decode pin id and mux from pin function id got from device tree*/ -static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info, - unsigned int pin_func_id, unsigned int *pin_id, - unsigned int *mux) -{ - if (pin_func_id > info->npin_regs) - return -EINVAL; - - *pin_id = info->pin_regs[pin_func_id].pid; - *mux = info->pin_regs[pin_func_id].mux_mode; - - return 0; -} - -static int __devinit imx_pinctrl_parse_groups(struct device_node *np, - struct imx_pin_group *grp, - struct imx_pinctrl_soc_info *info, - u32 index) -{ - unsigned int pin_func_id; - int ret, size; - const const __be32 *list; - int i, j; - u32 config; - - dev_dbg(info->dev, "group(%d): %s\n", index, np->name); - - /* Initialise group */ - grp->name = np->name; - - /* - * the binding format is fsl,pins = , - * do sanity check and calculate pins number - */ - list = of_get_property(np, "fsl,pins", &size); - /* we do not check return since it's safe node passed down */ - size /= sizeof(*list); - if (!size || size % 2) { - dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n"); - return -EINVAL; - } - - grp->npins = size / 2; - grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long), - GFP_KERNEL); - for (i = 0, j = 0; i < size; i += 2, j++) { - pin_func_id = be32_to_cpu(*list++); - ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id, - &grp->pins[j], &grp->mux_mode[j]); - if (ret) { - dev_err(info->dev, "get invalid pin function id\n"); - return -EINVAL; - } - /* SION bit is in mux register */ - config = be32_to_cpu(*list++); - if (config & IMX_PAD_SION) - grp->mux_mode[j] |= IOMUXC_CONFIG_SION; - grp->configs[j] = config & ~IMX_PAD_SION; - } - -#ifdef DEBUG - IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins); -#endif - return 0; -} - -static int __devinit imx_pinctrl_parse_functions(struct device_node *np, - struct imx_pinctrl_soc_info *info, u32 index) -{ - struct device_node *child; - struct imx_pmx_func *func; - struct imx_pin_group *grp; - int ret; - static u32 grp_index; - u32 i = 0; - - dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); - - func = &info->functions[index]; - - /* Initialise function */ - func->name = np->name; - func->num_groups = of_get_child_count(np); - if (func->num_groups <= 0) { - dev_err(info->dev, "no groups defined\n"); - return -EINVAL; - } - func->groups = devm_kzalloc(info->dev, - func->num_groups * sizeof(char *), GFP_KERNEL); - - for_each_child_of_node(np, child) { - func->groups[i] = child->name; - grp = &info->groups[grp_index++]; - ret = imx_pinctrl_parse_groups(child, grp, info, i++); - if (ret) - return ret; - } - - return 0; -} - -static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - int ret; - u32 nfuncs = 0; - u32 i = 0; - - if (!np) - return -ENODEV; - - nfuncs = of_get_child_count(np); - if (nfuncs <= 0) { - dev_err(&pdev->dev, "no functions defined\n"); - return -EINVAL; - } - - info->nfunctions = nfuncs; - info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), - GFP_KERNEL); - if (!info->functions) - return -ENOMEM; - - info->ngroups = 0; - for_each_child_of_node(np, child) - info->ngroups += of_get_child_count(child); - info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), - GFP_KERNEL); - if (!info->groups) - return -ENOMEM; - - for_each_child_of_node(np, child) { - ret = imx_pinctrl_parse_functions(child, info, i++); - if (ret) { - dev_err(&pdev->dev, "failed to parse function\n"); - return ret; - } - } - - return 0; -} - -int __devinit imx_pinctrl_probe(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info) -{ - struct imx_pinctrl *ipctl; - struct resource *res; - int ret; - - if (!info || !info->pins || !info->npins - || !info->pin_regs || !info->npin_regs) { - dev_err(&pdev->dev, "wrong pinctrl info\n"); - return -EINVAL; - } - info->dev = &pdev->dev; - - /* Create state holders etc for this driver */ - ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); - if (!ipctl) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENOENT; - - ipctl->base = devm_request_and_ioremap(&pdev->dev, res); - if (!ipctl->base) - return -EBUSY; - - imx_pinctrl_desc.name = dev_name(&pdev->dev); - imx_pinctrl_desc.pins = info->pins; - imx_pinctrl_desc.npins = info->npins; - - ret = imx_pinctrl_probe_dt(pdev, info); - if (ret) { - dev_err(&pdev->dev, "fail to probe dt properties\n"); - return ret; - } - - ipctl->info = info; - ipctl->dev = info->dev; - platform_set_drvdata(pdev, ipctl); - ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); - if (!ipctl->pctl) { - dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - return -EINVAL; - } - - dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); - - return 0; -} - -int __devexit imx_pinctrl_remove(struct platform_device *pdev) -{ - struct imx_pinctrl *ipctl = platform_get_drvdata(pdev); - - pinctrl_unregister(ipctl->pctl); - - return 0; -} diff --git a/trunk/drivers/pinctrl/pinctrl-imx.h b/trunk/drivers/pinctrl/pinctrl-imx.h deleted file mode 100644 index 9b65e7828f1d..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * IMX pinmux core definitions - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro Ltd. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __DRIVERS_PINCTRL_IMX_H -#define __DRIVERS_PINCTRL_IMX_H - -struct platform_device; - -/** - * struct imx_pin_group - describes an IMX pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @npins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - * @mux_mode: the mux mode for each pin in this group. The size of this - * array is the same as pins. - * @configs: the config for each pin in this group. The size of this - * array is the same as pins. - */ -struct imx_pin_group { - const char *name; - unsigned int *pins; - unsigned npins; - unsigned int *mux_mode; - unsigned long *configs; -}; - -/** - * struct imx_pmx_func - describes IMX pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @num_groups: the number of groups - */ -struct imx_pmx_func { - const char *name; - const char **groups; - unsigned num_groups; -}; - -/** - * struct imx_pin_reg - describe a pin reg map - * The last 3 members are used for select input setting - * @pid: pin id - * @mux_reg: mux register offset - * @conf_reg: config register offset - * @mux_mode: mux mode - * @input_reg: select input register offset for this mux if any - * 0 if no select input setting needed. - * @input_val: the value set to select input register - */ -struct imx_pin_reg { - u16 pid; - u16 mux_reg; - u16 conf_reg; - u8 mux_mode; - u16 input_reg; - u8 input_val; -}; - -struct imx_pinctrl_soc_info { - struct device *dev; - const struct pinctrl_pin_desc *pins; - unsigned int npins; - const struct imx_pin_reg *pin_regs; - unsigned int npin_regs; - struct imx_pin_group *groups; - unsigned int ngroups; - struct imx_pmx_func *functions; - unsigned int nfunctions; -}; - -#define NO_MUX 0x0 -#define NO_PAD 0x0 - -#define IMX_PIN_REG(id, conf, mux, mode, input, val) \ - { \ - .pid = id, \ - .conf_reg = conf, \ - .mux_reg = mux, \ - .mux_mode = mode, \ - .input_reg = input, \ - .input_val = val, \ - } - -#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) - -#define PAD_CTL_MASK(len) ((1 << len) - 1) -#define IMX_MUX_MASK 0x7 -#define IOMUXC_CONFIG_SION (0x1 << 4) - -int imx_pinctrl_probe(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info); -int imx_pinctrl_remove(struct platform_device *pdev); -#endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/trunk/drivers/pinctrl/pinctrl-imx23.c b/trunk/drivers/pinctrl/pinctrl-imx23.c deleted file mode 100644 index 75d3eff94296..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx23.c +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include "pinctrl-mxs.h" - -enum imx23_pin_enum { - GPMI_D00 = PINID(0, 0), - GPMI_D01 = PINID(0, 1), - GPMI_D02 = PINID(0, 2), - GPMI_D03 = PINID(0, 3), - GPMI_D04 = PINID(0, 4), - GPMI_D05 = PINID(0, 5), - GPMI_D06 = PINID(0, 6), - GPMI_D07 = PINID(0, 7), - GPMI_D08 = PINID(0, 8), - GPMI_D09 = PINID(0, 9), - GPMI_D10 = PINID(0, 10), - GPMI_D11 = PINID(0, 11), - GPMI_D12 = PINID(0, 12), - GPMI_D13 = PINID(0, 13), - GPMI_D14 = PINID(0, 14), - GPMI_D15 = PINID(0, 15), - GPMI_CLE = PINID(0, 16), - GPMI_ALE = PINID(0, 17), - GPMI_CE2N = PINID(0, 18), - GPMI_RDY0 = PINID(0, 19), - GPMI_RDY1 = PINID(0, 20), - GPMI_RDY2 = PINID(0, 21), - GPMI_RDY3 = PINID(0, 22), - GPMI_WPN = PINID(0, 23), - GPMI_WRN = PINID(0, 24), - GPMI_RDN = PINID(0, 25), - AUART1_CTS = PINID(0, 26), - AUART1_RTS = PINID(0, 27), - AUART1_RX = PINID(0, 28), - AUART1_TX = PINID(0, 29), - I2C_SCL = PINID(0, 30), - I2C_SDA = PINID(0, 31), - LCD_D00 = PINID(1, 0), - LCD_D01 = PINID(1, 1), - LCD_D02 = PINID(1, 2), - LCD_D03 = PINID(1, 3), - LCD_D04 = PINID(1, 4), - LCD_D05 = PINID(1, 5), - LCD_D06 = PINID(1, 6), - LCD_D07 = PINID(1, 7), - LCD_D08 = PINID(1, 8), - LCD_D09 = PINID(1, 9), - LCD_D10 = PINID(1, 10), - LCD_D11 = PINID(1, 11), - LCD_D12 = PINID(1, 12), - LCD_D13 = PINID(1, 13), - LCD_D14 = PINID(1, 14), - LCD_D15 = PINID(1, 15), - LCD_D16 = PINID(1, 16), - LCD_D17 = PINID(1, 17), - LCD_RESET = PINID(1, 18), - LCD_RS = PINID(1, 19), - LCD_WR = PINID(1, 20), - LCD_CS = PINID(1, 21), - LCD_DOTCK = PINID(1, 22), - LCD_ENABLE = PINID(1, 23), - LCD_HSYNC = PINID(1, 24), - LCD_VSYNC = PINID(1, 25), - PWM0 = PINID(1, 26), - PWM1 = PINID(1, 27), - PWM2 = PINID(1, 28), - PWM3 = PINID(1, 29), - PWM4 = PINID(1, 30), - SSP1_CMD = PINID(2, 0), - SSP1_DETECT = PINID(2, 1), - SSP1_DATA0 = PINID(2, 2), - SSP1_DATA1 = PINID(2, 3), - SSP1_DATA2 = PINID(2, 4), - SSP1_DATA3 = PINID(2, 5), - SSP1_SCK = PINID(2, 6), - ROTARYA = PINID(2, 7), - ROTARYB = PINID(2, 8), - EMI_A00 = PINID(2, 9), - EMI_A01 = PINID(2, 10), - EMI_A02 = PINID(2, 11), - EMI_A03 = PINID(2, 12), - EMI_A04 = PINID(2, 13), - EMI_A05 = PINID(2, 14), - EMI_A06 = PINID(2, 15), - EMI_A07 = PINID(2, 16), - EMI_A08 = PINID(2, 17), - EMI_A09 = PINID(2, 18), - EMI_A10 = PINID(2, 19), - EMI_A11 = PINID(2, 20), - EMI_A12 = PINID(2, 21), - EMI_BA0 = PINID(2, 22), - EMI_BA1 = PINID(2, 23), - EMI_CASN = PINID(2, 24), - EMI_CE0N = PINID(2, 25), - EMI_CE1N = PINID(2, 26), - GPMI_CE1N = PINID(2, 27), - GPMI_CE0N = PINID(2, 28), - EMI_CKE = PINID(2, 29), - EMI_RASN = PINID(2, 30), - EMI_WEN = PINID(2, 31), - EMI_D00 = PINID(3, 0), - EMI_D01 = PINID(3, 1), - EMI_D02 = PINID(3, 2), - EMI_D03 = PINID(3, 3), - EMI_D04 = PINID(3, 4), - EMI_D05 = PINID(3, 5), - EMI_D06 = PINID(3, 6), - EMI_D07 = PINID(3, 7), - EMI_D08 = PINID(3, 8), - EMI_D09 = PINID(3, 9), - EMI_D10 = PINID(3, 10), - EMI_D11 = PINID(3, 11), - EMI_D12 = PINID(3, 12), - EMI_D13 = PINID(3, 13), - EMI_D14 = PINID(3, 14), - EMI_D15 = PINID(3, 15), - EMI_DQM0 = PINID(3, 16), - EMI_DQM1 = PINID(3, 17), - EMI_DQS0 = PINID(3, 18), - EMI_DQS1 = PINID(3, 19), - EMI_CLK = PINID(3, 20), - EMI_CLKN = PINID(3, 21), -}; - -static const struct pinctrl_pin_desc imx23_pins[] = { - MXS_PINCTRL_PIN(GPMI_D00), - MXS_PINCTRL_PIN(GPMI_D01), - MXS_PINCTRL_PIN(GPMI_D02), - MXS_PINCTRL_PIN(GPMI_D03), - MXS_PINCTRL_PIN(GPMI_D04), - MXS_PINCTRL_PIN(GPMI_D05), - MXS_PINCTRL_PIN(GPMI_D06), - MXS_PINCTRL_PIN(GPMI_D07), - MXS_PINCTRL_PIN(GPMI_D08), - MXS_PINCTRL_PIN(GPMI_D09), - MXS_PINCTRL_PIN(GPMI_D10), - MXS_PINCTRL_PIN(GPMI_D11), - MXS_PINCTRL_PIN(GPMI_D12), - MXS_PINCTRL_PIN(GPMI_D13), - MXS_PINCTRL_PIN(GPMI_D14), - MXS_PINCTRL_PIN(GPMI_D15), - MXS_PINCTRL_PIN(GPMI_CLE), - MXS_PINCTRL_PIN(GPMI_ALE), - MXS_PINCTRL_PIN(GPMI_CE2N), - MXS_PINCTRL_PIN(GPMI_RDY0), - MXS_PINCTRL_PIN(GPMI_RDY1), - MXS_PINCTRL_PIN(GPMI_RDY2), - MXS_PINCTRL_PIN(GPMI_RDY3), - MXS_PINCTRL_PIN(GPMI_WPN), - MXS_PINCTRL_PIN(GPMI_WRN), - MXS_PINCTRL_PIN(GPMI_RDN), - MXS_PINCTRL_PIN(AUART1_CTS), - MXS_PINCTRL_PIN(AUART1_RTS), - MXS_PINCTRL_PIN(AUART1_RX), - MXS_PINCTRL_PIN(AUART1_TX), - MXS_PINCTRL_PIN(I2C_SCL), - MXS_PINCTRL_PIN(I2C_SDA), - MXS_PINCTRL_PIN(LCD_D00), - MXS_PINCTRL_PIN(LCD_D01), - MXS_PINCTRL_PIN(LCD_D02), - MXS_PINCTRL_PIN(LCD_D03), - MXS_PINCTRL_PIN(LCD_D04), - MXS_PINCTRL_PIN(LCD_D05), - MXS_PINCTRL_PIN(LCD_D06), - MXS_PINCTRL_PIN(LCD_D07), - MXS_PINCTRL_PIN(LCD_D08), - MXS_PINCTRL_PIN(LCD_D09), - MXS_PINCTRL_PIN(LCD_D10), - MXS_PINCTRL_PIN(LCD_D11), - MXS_PINCTRL_PIN(LCD_D12), - MXS_PINCTRL_PIN(LCD_D13), - MXS_PINCTRL_PIN(LCD_D14), - MXS_PINCTRL_PIN(LCD_D15), - MXS_PINCTRL_PIN(LCD_D16), - MXS_PINCTRL_PIN(LCD_D17), - MXS_PINCTRL_PIN(LCD_RESET), - MXS_PINCTRL_PIN(LCD_RS), - MXS_PINCTRL_PIN(LCD_WR), - MXS_PINCTRL_PIN(LCD_CS), - MXS_PINCTRL_PIN(LCD_DOTCK), - MXS_PINCTRL_PIN(LCD_ENABLE), - MXS_PINCTRL_PIN(LCD_HSYNC), - MXS_PINCTRL_PIN(LCD_VSYNC), - MXS_PINCTRL_PIN(PWM0), - MXS_PINCTRL_PIN(PWM1), - MXS_PINCTRL_PIN(PWM2), - MXS_PINCTRL_PIN(PWM3), - MXS_PINCTRL_PIN(PWM4), - MXS_PINCTRL_PIN(SSP1_CMD), - MXS_PINCTRL_PIN(SSP1_DETECT), - MXS_PINCTRL_PIN(SSP1_DATA0), - MXS_PINCTRL_PIN(SSP1_DATA1), - MXS_PINCTRL_PIN(SSP1_DATA2), - MXS_PINCTRL_PIN(SSP1_DATA3), - MXS_PINCTRL_PIN(SSP1_SCK), - MXS_PINCTRL_PIN(ROTARYA), - MXS_PINCTRL_PIN(ROTARYB), - MXS_PINCTRL_PIN(EMI_A00), - MXS_PINCTRL_PIN(EMI_A01), - MXS_PINCTRL_PIN(EMI_A02), - MXS_PINCTRL_PIN(EMI_A03), - MXS_PINCTRL_PIN(EMI_A04), - MXS_PINCTRL_PIN(EMI_A05), - MXS_PINCTRL_PIN(EMI_A06), - MXS_PINCTRL_PIN(EMI_A07), - MXS_PINCTRL_PIN(EMI_A08), - MXS_PINCTRL_PIN(EMI_A09), - MXS_PINCTRL_PIN(EMI_A10), - MXS_PINCTRL_PIN(EMI_A11), - MXS_PINCTRL_PIN(EMI_A12), - MXS_PINCTRL_PIN(EMI_BA0), - MXS_PINCTRL_PIN(EMI_BA1), - MXS_PINCTRL_PIN(EMI_CASN), - MXS_PINCTRL_PIN(EMI_CE0N), - MXS_PINCTRL_PIN(EMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE0N), - MXS_PINCTRL_PIN(EMI_CKE), - MXS_PINCTRL_PIN(EMI_RASN), - MXS_PINCTRL_PIN(EMI_WEN), - MXS_PINCTRL_PIN(EMI_D00), - MXS_PINCTRL_PIN(EMI_D01), - MXS_PINCTRL_PIN(EMI_D02), - MXS_PINCTRL_PIN(EMI_D03), - MXS_PINCTRL_PIN(EMI_D04), - MXS_PINCTRL_PIN(EMI_D05), - MXS_PINCTRL_PIN(EMI_D06), - MXS_PINCTRL_PIN(EMI_D07), - MXS_PINCTRL_PIN(EMI_D08), - MXS_PINCTRL_PIN(EMI_D09), - MXS_PINCTRL_PIN(EMI_D10), - MXS_PINCTRL_PIN(EMI_D11), - MXS_PINCTRL_PIN(EMI_D12), - MXS_PINCTRL_PIN(EMI_D13), - MXS_PINCTRL_PIN(EMI_D14), - MXS_PINCTRL_PIN(EMI_D15), - MXS_PINCTRL_PIN(EMI_DQM0), - MXS_PINCTRL_PIN(EMI_DQM1), - MXS_PINCTRL_PIN(EMI_DQS0), - MXS_PINCTRL_PIN(EMI_DQS1), - MXS_PINCTRL_PIN(EMI_CLK), - MXS_PINCTRL_PIN(EMI_CLKN), -}; - -static struct mxs_regs imx23_regs = { - .muxsel = 0x100, - .drive = 0x200, - .pull = 0x400, -}; - -static struct mxs_pinctrl_soc_data imx23_pinctrl_data = { - .regs = &imx23_regs, - .pins = imx23_pins, - .npins = ARRAY_SIZE(imx23_pins), -}; - -static int __devinit imx23_pinctrl_probe(struct platform_device *pdev) -{ - return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data); -} - -static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = { - { .compatible = "fsl,imx23-pinctrl", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match); - -static struct platform_driver imx23_pinctrl_driver = { - .driver = { - .name = "imx23-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx23_pinctrl_of_match, - }, - .probe = imx23_pinctrl_probe, - .remove = __devexit_p(mxs_pinctrl_remove), -}; - -static int __init imx23_pinctrl_init(void) -{ - return platform_driver_register(&imx23_pinctrl_driver); -} -arch_initcall(imx23_pinctrl_init); - -static void __exit imx23_pinctrl_exit(void) -{ - platform_driver_unregister(&imx23_pinctrl_driver); -} -module_exit(imx23_pinctrl_exit); - -MODULE_AUTHOR("Shawn Guo "); -MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/pinctrl/pinctrl-imx28.c b/trunk/drivers/pinctrl/pinctrl-imx28.c deleted file mode 100644 index b973026811a2..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx28.c +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include "pinctrl-mxs.h" - -enum imx28_pin_enum { - GPMI_D00 = PINID(0, 0), - GPMI_D01 = PINID(0, 1), - GPMI_D02 = PINID(0, 2), - GPMI_D03 = PINID(0, 3), - GPMI_D04 = PINID(0, 4), - GPMI_D05 = PINID(0, 5), - GPMI_D06 = PINID(0, 6), - GPMI_D07 = PINID(0, 7), - GPMI_CE0N = PINID(0, 16), - GPMI_CE1N = PINID(0, 17), - GPMI_CE2N = PINID(0, 18), - GPMI_CE3N = PINID(0, 19), - GPMI_RDY0 = PINID(0, 20), - GPMI_RDY1 = PINID(0, 21), - GPMI_RDY2 = PINID(0, 22), - GPMI_RDY3 = PINID(0, 23), - GPMI_RDN = PINID(0, 24), - GPMI_WRN = PINID(0, 25), - GPMI_ALE = PINID(0, 26), - GPMI_CLE = PINID(0, 27), - GPMI_RESETN = PINID(0, 28), - LCD_D00 = PINID(1, 0), - LCD_D01 = PINID(1, 1), - LCD_D02 = PINID(1, 2), - LCD_D03 = PINID(1, 3), - LCD_D04 = PINID(1, 4), - LCD_D05 = PINID(1, 5), - LCD_D06 = PINID(1, 6), - LCD_D07 = PINID(1, 7), - LCD_D08 = PINID(1, 8), - LCD_D09 = PINID(1, 9), - LCD_D10 = PINID(1, 10), - LCD_D11 = PINID(1, 11), - LCD_D12 = PINID(1, 12), - LCD_D13 = PINID(1, 13), - LCD_D14 = PINID(1, 14), - LCD_D15 = PINID(1, 15), - LCD_D16 = PINID(1, 16), - LCD_D17 = PINID(1, 17), - LCD_D18 = PINID(1, 18), - LCD_D19 = PINID(1, 19), - LCD_D20 = PINID(1, 20), - LCD_D21 = PINID(1, 21), - LCD_D22 = PINID(1, 22), - LCD_D23 = PINID(1, 23), - LCD_RD_E = PINID(1, 24), - LCD_WR_RWN = PINID(1, 25), - LCD_RS = PINID(1, 26), - LCD_CS = PINID(1, 27), - LCD_VSYNC = PINID(1, 28), - LCD_HSYNC = PINID(1, 29), - LCD_DOTCLK = PINID(1, 30), - LCD_ENABLE = PINID(1, 31), - SSP0_DATA0 = PINID(2, 0), - SSP0_DATA1 = PINID(2, 1), - SSP0_DATA2 = PINID(2, 2), - SSP0_DATA3 = PINID(2, 3), - SSP0_DATA4 = PINID(2, 4), - SSP0_DATA5 = PINID(2, 5), - SSP0_DATA6 = PINID(2, 6), - SSP0_DATA7 = PINID(2, 7), - SSP0_CMD = PINID(2, 8), - SSP0_DETECT = PINID(2, 9), - SSP0_SCK = PINID(2, 10), - SSP1_SCK = PINID(2, 12), - SSP1_CMD = PINID(2, 13), - SSP1_DATA0 = PINID(2, 14), - SSP1_DATA3 = PINID(2, 15), - SSP2_SCK = PINID(2, 16), - SSP2_MOSI = PINID(2, 17), - SSP2_MISO = PINID(2, 18), - SSP2_SS0 = PINID(2, 19), - SSP2_SS1 = PINID(2, 20), - SSP2_SS2 = PINID(2, 21), - SSP3_SCK = PINID(2, 24), - SSP3_MOSI = PINID(2, 25), - SSP3_MISO = PINID(2, 26), - SSP3_SS0 = PINID(2, 27), - AUART0_RX = PINID(3, 0), - AUART0_TX = PINID(3, 1), - AUART0_CTS = PINID(3, 2), - AUART0_RTS = PINID(3, 3), - AUART1_RX = PINID(3, 4), - AUART1_TX = PINID(3, 5), - AUART1_CTS = PINID(3, 6), - AUART1_RTS = PINID(3, 7), - AUART2_RX = PINID(3, 8), - AUART2_TX = PINID(3, 9), - AUART2_CTS = PINID(3, 10), - AUART2_RTS = PINID(3, 11), - AUART3_RX = PINID(3, 12), - AUART3_TX = PINID(3, 13), - AUART3_CTS = PINID(3, 14), - AUART3_RTS = PINID(3, 15), - PWM0 = PINID(3, 16), - PWM1 = PINID(3, 17), - PWM2 = PINID(3, 18), - SAIF0_MCLK = PINID(3, 20), - SAIF0_LRCLK = PINID(3, 21), - SAIF0_BITCLK = PINID(3, 22), - SAIF0_SDATA0 = PINID(3, 23), - I2C0_SCL = PINID(3, 24), - I2C0_SDA = PINID(3, 25), - SAIF1_SDATA0 = PINID(3, 26), - SPDIF = PINID(3, 27), - PWM3 = PINID(3, 28), - PWM4 = PINID(3, 29), - LCD_RESET = PINID(3, 30), - ENET0_MDC = PINID(4, 0), - ENET0_MDIO = PINID(4, 1), - ENET0_RX_EN = PINID(4, 2), - ENET0_RXD0 = PINID(4, 3), - ENET0_RXD1 = PINID(4, 4), - ENET0_TX_CLK = PINID(4, 5), - ENET0_TX_EN = PINID(4, 6), - ENET0_TXD0 = PINID(4, 7), - ENET0_TXD1 = PINID(4, 8), - ENET0_RXD2 = PINID(4, 9), - ENET0_RXD3 = PINID(4, 10), - ENET0_TXD2 = PINID(4, 11), - ENET0_TXD3 = PINID(4, 12), - ENET0_RX_CLK = PINID(4, 13), - ENET0_COL = PINID(4, 14), - ENET0_CRS = PINID(4, 15), - ENET_CLK = PINID(4, 16), - JTAG_RTCK = PINID(4, 20), - EMI_D00 = PINID(5, 0), - EMI_D01 = PINID(5, 1), - EMI_D02 = PINID(5, 2), - EMI_D03 = PINID(5, 3), - EMI_D04 = PINID(5, 4), - EMI_D05 = PINID(5, 5), - EMI_D06 = PINID(5, 6), - EMI_D07 = PINID(5, 7), - EMI_D08 = PINID(5, 8), - EMI_D09 = PINID(5, 9), - EMI_D10 = PINID(5, 10), - EMI_D11 = PINID(5, 11), - EMI_D12 = PINID(5, 12), - EMI_D13 = PINID(5, 13), - EMI_D14 = PINID(5, 14), - EMI_D15 = PINID(5, 15), - EMI_ODT0 = PINID(5, 16), - EMI_DQM0 = PINID(5, 17), - EMI_ODT1 = PINID(5, 18), - EMI_DQM1 = PINID(5, 19), - EMI_DDR_OPEN_FB = PINID(5, 20), - EMI_CLK = PINID(5, 21), - EMI_DQS0 = PINID(5, 22), - EMI_DQS1 = PINID(5, 23), - EMI_DDR_OPEN = PINID(5, 26), - EMI_A00 = PINID(6, 0), - EMI_A01 = PINID(6, 1), - EMI_A02 = PINID(6, 2), - EMI_A03 = PINID(6, 3), - EMI_A04 = PINID(6, 4), - EMI_A05 = PINID(6, 5), - EMI_A06 = PINID(6, 6), - EMI_A07 = PINID(6, 7), - EMI_A08 = PINID(6, 8), - EMI_A09 = PINID(6, 9), - EMI_A10 = PINID(6, 10), - EMI_A11 = PINID(6, 11), - EMI_A12 = PINID(6, 12), - EMI_A13 = PINID(6, 13), - EMI_A14 = PINID(6, 14), - EMI_BA0 = PINID(6, 16), - EMI_BA1 = PINID(6, 17), - EMI_BA2 = PINID(6, 18), - EMI_CASN = PINID(6, 19), - EMI_RASN = PINID(6, 20), - EMI_WEN = PINID(6, 21), - EMI_CE0N = PINID(6, 22), - EMI_CE1N = PINID(6, 23), - EMI_CKE = PINID(6, 24), -}; - -static const struct pinctrl_pin_desc imx28_pins[] = { - MXS_PINCTRL_PIN(GPMI_D00), - MXS_PINCTRL_PIN(GPMI_D01), - MXS_PINCTRL_PIN(GPMI_D02), - MXS_PINCTRL_PIN(GPMI_D03), - MXS_PINCTRL_PIN(GPMI_D04), - MXS_PINCTRL_PIN(GPMI_D05), - MXS_PINCTRL_PIN(GPMI_D06), - MXS_PINCTRL_PIN(GPMI_D07), - MXS_PINCTRL_PIN(GPMI_CE0N), - MXS_PINCTRL_PIN(GPMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE2N), - MXS_PINCTRL_PIN(GPMI_CE3N), - MXS_PINCTRL_PIN(GPMI_RDY0), - MXS_PINCTRL_PIN(GPMI_RDY1), - MXS_PINCTRL_PIN(GPMI_RDY2), - MXS_PINCTRL_PIN(GPMI_RDY3), - MXS_PINCTRL_PIN(GPMI_RDN), - MXS_PINCTRL_PIN(GPMI_WRN), - MXS_PINCTRL_PIN(GPMI_ALE), - MXS_PINCTRL_PIN(GPMI_CLE), - MXS_PINCTRL_PIN(GPMI_RESETN), - MXS_PINCTRL_PIN(LCD_D00), - MXS_PINCTRL_PIN(LCD_D01), - MXS_PINCTRL_PIN(LCD_D02), - MXS_PINCTRL_PIN(LCD_D03), - MXS_PINCTRL_PIN(LCD_D04), - MXS_PINCTRL_PIN(LCD_D05), - MXS_PINCTRL_PIN(LCD_D06), - MXS_PINCTRL_PIN(LCD_D07), - MXS_PINCTRL_PIN(LCD_D08), - MXS_PINCTRL_PIN(LCD_D09), - MXS_PINCTRL_PIN(LCD_D10), - MXS_PINCTRL_PIN(LCD_D11), - MXS_PINCTRL_PIN(LCD_D12), - MXS_PINCTRL_PIN(LCD_D13), - MXS_PINCTRL_PIN(LCD_D14), - MXS_PINCTRL_PIN(LCD_D15), - MXS_PINCTRL_PIN(LCD_D16), - MXS_PINCTRL_PIN(LCD_D17), - MXS_PINCTRL_PIN(LCD_D18), - MXS_PINCTRL_PIN(LCD_D19), - MXS_PINCTRL_PIN(LCD_D20), - MXS_PINCTRL_PIN(LCD_D21), - MXS_PINCTRL_PIN(LCD_D22), - MXS_PINCTRL_PIN(LCD_D23), - MXS_PINCTRL_PIN(LCD_RD_E), - MXS_PINCTRL_PIN(LCD_WR_RWN), - MXS_PINCTRL_PIN(LCD_RS), - MXS_PINCTRL_PIN(LCD_CS), - MXS_PINCTRL_PIN(LCD_VSYNC), - MXS_PINCTRL_PIN(LCD_HSYNC), - MXS_PINCTRL_PIN(LCD_DOTCLK), - MXS_PINCTRL_PIN(LCD_ENABLE), - MXS_PINCTRL_PIN(SSP0_DATA0), - MXS_PINCTRL_PIN(SSP0_DATA1), - MXS_PINCTRL_PIN(SSP0_DATA2), - MXS_PINCTRL_PIN(SSP0_DATA3), - MXS_PINCTRL_PIN(SSP0_DATA4), - MXS_PINCTRL_PIN(SSP0_DATA5), - MXS_PINCTRL_PIN(SSP0_DATA6), - MXS_PINCTRL_PIN(SSP0_DATA7), - MXS_PINCTRL_PIN(SSP0_CMD), - MXS_PINCTRL_PIN(SSP0_DETECT), - MXS_PINCTRL_PIN(SSP0_SCK), - MXS_PINCTRL_PIN(SSP1_SCK), - MXS_PINCTRL_PIN(SSP1_CMD), - MXS_PINCTRL_PIN(SSP1_DATA0), - MXS_PINCTRL_PIN(SSP1_DATA3), - MXS_PINCTRL_PIN(SSP2_SCK), - MXS_PINCTRL_PIN(SSP2_MOSI), - MXS_PINCTRL_PIN(SSP2_MISO), - MXS_PINCTRL_PIN(SSP2_SS0), - MXS_PINCTRL_PIN(SSP2_SS1), - MXS_PINCTRL_PIN(SSP2_SS2), - MXS_PINCTRL_PIN(SSP3_SCK), - MXS_PINCTRL_PIN(SSP3_MOSI), - MXS_PINCTRL_PIN(SSP3_MISO), - MXS_PINCTRL_PIN(SSP3_SS0), - MXS_PINCTRL_PIN(AUART0_RX), - MXS_PINCTRL_PIN(AUART0_TX), - MXS_PINCTRL_PIN(AUART0_CTS), - MXS_PINCTRL_PIN(AUART0_RTS), - MXS_PINCTRL_PIN(AUART1_RX), - MXS_PINCTRL_PIN(AUART1_TX), - MXS_PINCTRL_PIN(AUART1_CTS), - MXS_PINCTRL_PIN(AUART1_RTS), - MXS_PINCTRL_PIN(AUART2_RX), - MXS_PINCTRL_PIN(AUART2_TX), - MXS_PINCTRL_PIN(AUART2_CTS), - MXS_PINCTRL_PIN(AUART2_RTS), - MXS_PINCTRL_PIN(AUART3_RX), - MXS_PINCTRL_PIN(AUART3_TX), - MXS_PINCTRL_PIN(AUART3_CTS), - MXS_PINCTRL_PIN(AUART3_RTS), - MXS_PINCTRL_PIN(PWM0), - MXS_PINCTRL_PIN(PWM1), - MXS_PINCTRL_PIN(PWM2), - MXS_PINCTRL_PIN(SAIF0_MCLK), - MXS_PINCTRL_PIN(SAIF0_LRCLK), - MXS_PINCTRL_PIN(SAIF0_BITCLK), - MXS_PINCTRL_PIN(SAIF0_SDATA0), - MXS_PINCTRL_PIN(I2C0_SCL), - MXS_PINCTRL_PIN(I2C0_SDA), - MXS_PINCTRL_PIN(SAIF1_SDATA0), - MXS_PINCTRL_PIN(SPDIF), - MXS_PINCTRL_PIN(PWM3), - MXS_PINCTRL_PIN(PWM4), - MXS_PINCTRL_PIN(LCD_RESET), - MXS_PINCTRL_PIN(ENET0_MDC), - MXS_PINCTRL_PIN(ENET0_MDIO), - MXS_PINCTRL_PIN(ENET0_RX_EN), - MXS_PINCTRL_PIN(ENET0_RXD0), - MXS_PINCTRL_PIN(ENET0_RXD1), - MXS_PINCTRL_PIN(ENET0_TX_CLK), - MXS_PINCTRL_PIN(ENET0_TX_EN), - MXS_PINCTRL_PIN(ENET0_TXD0), - MXS_PINCTRL_PIN(ENET0_TXD1), - MXS_PINCTRL_PIN(ENET0_RXD2), - MXS_PINCTRL_PIN(ENET0_RXD3), - MXS_PINCTRL_PIN(ENET0_TXD2), - MXS_PINCTRL_PIN(ENET0_TXD3), - MXS_PINCTRL_PIN(ENET0_RX_CLK), - MXS_PINCTRL_PIN(ENET0_COL), - MXS_PINCTRL_PIN(ENET0_CRS), - MXS_PINCTRL_PIN(ENET_CLK), - MXS_PINCTRL_PIN(JTAG_RTCK), - MXS_PINCTRL_PIN(EMI_D00), - MXS_PINCTRL_PIN(EMI_D01), - MXS_PINCTRL_PIN(EMI_D02), - MXS_PINCTRL_PIN(EMI_D03), - MXS_PINCTRL_PIN(EMI_D04), - MXS_PINCTRL_PIN(EMI_D05), - MXS_PINCTRL_PIN(EMI_D06), - MXS_PINCTRL_PIN(EMI_D07), - MXS_PINCTRL_PIN(EMI_D08), - MXS_PINCTRL_PIN(EMI_D09), - MXS_PINCTRL_PIN(EMI_D10), - MXS_PINCTRL_PIN(EMI_D11), - MXS_PINCTRL_PIN(EMI_D12), - MXS_PINCTRL_PIN(EMI_D13), - MXS_PINCTRL_PIN(EMI_D14), - MXS_PINCTRL_PIN(EMI_D15), - MXS_PINCTRL_PIN(EMI_ODT0), - MXS_PINCTRL_PIN(EMI_DQM0), - MXS_PINCTRL_PIN(EMI_ODT1), - MXS_PINCTRL_PIN(EMI_DQM1), - MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB), - MXS_PINCTRL_PIN(EMI_CLK), - MXS_PINCTRL_PIN(EMI_DQS0), - MXS_PINCTRL_PIN(EMI_DQS1), - MXS_PINCTRL_PIN(EMI_DDR_OPEN), - MXS_PINCTRL_PIN(EMI_A00), - MXS_PINCTRL_PIN(EMI_A01), - MXS_PINCTRL_PIN(EMI_A02), - MXS_PINCTRL_PIN(EMI_A03), - MXS_PINCTRL_PIN(EMI_A04), - MXS_PINCTRL_PIN(EMI_A05), - MXS_PINCTRL_PIN(EMI_A06), - MXS_PINCTRL_PIN(EMI_A07), - MXS_PINCTRL_PIN(EMI_A08), - MXS_PINCTRL_PIN(EMI_A09), - MXS_PINCTRL_PIN(EMI_A10), - MXS_PINCTRL_PIN(EMI_A11), - MXS_PINCTRL_PIN(EMI_A12), - MXS_PINCTRL_PIN(EMI_A13), - MXS_PINCTRL_PIN(EMI_A14), - MXS_PINCTRL_PIN(EMI_BA0), - MXS_PINCTRL_PIN(EMI_BA1), - MXS_PINCTRL_PIN(EMI_BA2), - MXS_PINCTRL_PIN(EMI_CASN), - MXS_PINCTRL_PIN(EMI_RASN), - MXS_PINCTRL_PIN(EMI_WEN), - MXS_PINCTRL_PIN(EMI_CE0N), - MXS_PINCTRL_PIN(EMI_CE1N), - MXS_PINCTRL_PIN(EMI_CKE), -}; - -static struct mxs_regs imx28_regs = { - .muxsel = 0x100, - .drive = 0x300, - .pull = 0x600, -}; - -static struct mxs_pinctrl_soc_data imx28_pinctrl_data = { - .regs = &imx28_regs, - .pins = imx28_pins, - .npins = ARRAY_SIZE(imx28_pins), -}; - -static int __devinit imx28_pinctrl_probe(struct platform_device *pdev) -{ - return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data); -} - -static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = { - { .compatible = "fsl,imx28-pinctrl", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match); - -static struct platform_driver imx28_pinctrl_driver = { - .driver = { - .name = "imx28-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx28_pinctrl_of_match, - }, - .probe = imx28_pinctrl_probe, - .remove = __devexit_p(mxs_pinctrl_remove), -}; - -static int __init imx28_pinctrl_init(void) -{ - return platform_driver_register(&imx28_pinctrl_driver); -} -arch_initcall(imx28_pinctrl_init); - -static void __exit imx28_pinctrl_exit(void) -{ - platform_driver_unregister(&imx28_pinctrl_driver); -} -module_exit(imx28_pinctrl_exit); - -MODULE_AUTHOR("Shawn Guo "); -MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/pinctrl/pinctrl-imx6q.c b/trunk/drivers/pinctrl/pinctrl-imx6q.c deleted file mode 100644 index 7737d4d71a3c..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx6q.c +++ /dev/null @@ -1,2331 +0,0 @@ -/* - * imx6q pinctrl driver based on imx pinmux core - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro, Inc. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx6q_pads { - MX6Q_PAD_SD2_DAT1 = 0, - MX6Q_PAD_SD2_DAT2 = 1, - MX6Q_PAD_SD2_DAT0 = 2, - MX6Q_PAD_RGMII_TXC = 3, - MX6Q_PAD_RGMII_TD0 = 4, - MX6Q_PAD_RGMII_TD1 = 5, - MX6Q_PAD_RGMII_TD2 = 6, - MX6Q_PAD_RGMII_TD3 = 7, - MX6Q_PAD_RGMII_RX_CTL = 8, - MX6Q_PAD_RGMII_RD0 = 9, - MX6Q_PAD_RGMII_TX_CTL = 10, - MX6Q_PAD_RGMII_RD1 = 11, - MX6Q_PAD_RGMII_RD2 = 12, - MX6Q_PAD_RGMII_RD3 = 13, - MX6Q_PAD_RGMII_RXC = 14, - MX6Q_PAD_EIM_A25 = 15, - MX6Q_PAD_EIM_EB2 = 16, - MX6Q_PAD_EIM_D16 = 17, - MX6Q_PAD_EIM_D17 = 18, - MX6Q_PAD_EIM_D18 = 19, - MX6Q_PAD_EIM_D19 = 20, - MX6Q_PAD_EIM_D20 = 21, - MX6Q_PAD_EIM_D21 = 22, - MX6Q_PAD_EIM_D22 = 23, - MX6Q_PAD_EIM_D23 = 24, - MX6Q_PAD_EIM_EB3 = 25, - MX6Q_PAD_EIM_D24 = 26, - MX6Q_PAD_EIM_D25 = 27, - MX6Q_PAD_EIM_D26 = 28, - MX6Q_PAD_EIM_D27 = 29, - MX6Q_PAD_EIM_D28 = 30, - MX6Q_PAD_EIM_D29 = 31, - MX6Q_PAD_EIM_D30 = 32, - MX6Q_PAD_EIM_D31 = 33, - MX6Q_PAD_EIM_A24 = 34, - MX6Q_PAD_EIM_A23 = 35, - MX6Q_PAD_EIM_A22 = 36, - MX6Q_PAD_EIM_A21 = 37, - MX6Q_PAD_EIM_A20 = 38, - MX6Q_PAD_EIM_A19 = 39, - MX6Q_PAD_EIM_A18 = 40, - MX6Q_PAD_EIM_A17 = 41, - MX6Q_PAD_EIM_A16 = 42, - MX6Q_PAD_EIM_CS0 = 43, - MX6Q_PAD_EIM_CS1 = 44, - MX6Q_PAD_EIM_OE = 45, - MX6Q_PAD_EIM_RW = 46, - MX6Q_PAD_EIM_LBA = 47, - MX6Q_PAD_EIM_EB0 = 48, - MX6Q_PAD_EIM_EB1 = 49, - MX6Q_PAD_EIM_DA0 = 50, - MX6Q_PAD_EIM_DA1 = 51, - MX6Q_PAD_EIM_DA2 = 52, - MX6Q_PAD_EIM_DA3 = 53, - MX6Q_PAD_EIM_DA4 = 54, - MX6Q_PAD_EIM_DA5 = 55, - MX6Q_PAD_EIM_DA6 = 56, - MX6Q_PAD_EIM_DA7 = 57, - MX6Q_PAD_EIM_DA8 = 58, - MX6Q_PAD_EIM_DA9 = 59, - MX6Q_PAD_EIM_DA10 = 60, - MX6Q_PAD_EIM_DA11 = 61, - MX6Q_PAD_EIM_DA12 = 62, - MX6Q_PAD_EIM_DA13 = 63, - MX6Q_PAD_EIM_DA14 = 64, - MX6Q_PAD_EIM_DA15 = 65, - MX6Q_PAD_EIM_WAIT = 66, - MX6Q_PAD_EIM_BCLK = 67, - MX6Q_PAD_DI0_DISP_CLK = 68, - MX6Q_PAD_DI0_PIN15 = 69, - MX6Q_PAD_DI0_PIN2 = 70, - MX6Q_PAD_DI0_PIN3 = 71, - MX6Q_PAD_DI0_PIN4 = 72, - MX6Q_PAD_DISP0_DAT0 = 73, - MX6Q_PAD_DISP0_DAT1 = 74, - MX6Q_PAD_DISP0_DAT2 = 75, - MX6Q_PAD_DISP0_DAT3 = 76, - MX6Q_PAD_DISP0_DAT4 = 77, - MX6Q_PAD_DISP0_DAT5 = 78, - MX6Q_PAD_DISP0_DAT6 = 79, - MX6Q_PAD_DISP0_DAT7 = 80, - MX6Q_PAD_DISP0_DAT8 = 81, - MX6Q_PAD_DISP0_DAT9 = 82, - MX6Q_PAD_DISP0_DAT10 = 83, - MX6Q_PAD_DISP0_DAT11 = 84, - MX6Q_PAD_DISP0_DAT12 = 85, - MX6Q_PAD_DISP0_DAT13 = 86, - MX6Q_PAD_DISP0_DAT14 = 87, - MX6Q_PAD_DISP0_DAT15 = 88, - MX6Q_PAD_DISP0_DAT16 = 89, - MX6Q_PAD_DISP0_DAT17 = 90, - MX6Q_PAD_DISP0_DAT18 = 91, - MX6Q_PAD_DISP0_DAT19 = 92, - MX6Q_PAD_DISP0_DAT20 = 93, - MX6Q_PAD_DISP0_DAT21 = 94, - MX6Q_PAD_DISP0_DAT22 = 95, - MX6Q_PAD_DISP0_DAT23 = 96, - MX6Q_PAD_ENET_MDIO = 97, - MX6Q_PAD_ENET_REF_CLK = 98, - MX6Q_PAD_ENET_RX_ER = 99, - MX6Q_PAD_ENET_CRS_DV = 100, - MX6Q_PAD_ENET_RXD1 = 101, - MX6Q_PAD_ENET_RXD0 = 102, - MX6Q_PAD_ENET_TX_EN = 103, - MX6Q_PAD_ENET_TXD1 = 104, - MX6Q_PAD_ENET_TXD0 = 105, - MX6Q_PAD_ENET_MDC = 106, - MX6Q_PAD_DRAM_D40 = 107, - MX6Q_PAD_DRAM_D41 = 108, - MX6Q_PAD_DRAM_D42 = 109, - MX6Q_PAD_DRAM_D43 = 110, - MX6Q_PAD_DRAM_D44 = 111, - MX6Q_PAD_DRAM_D45 = 112, - MX6Q_PAD_DRAM_D46 = 113, - MX6Q_PAD_DRAM_D47 = 114, - MX6Q_PAD_DRAM_SDQS5 = 115, - MX6Q_PAD_DRAM_DQM5 = 116, - MX6Q_PAD_DRAM_D32 = 117, - MX6Q_PAD_DRAM_D33 = 118, - MX6Q_PAD_DRAM_D34 = 119, - MX6Q_PAD_DRAM_D35 = 120, - MX6Q_PAD_DRAM_D36 = 121, - MX6Q_PAD_DRAM_D37 = 122, - MX6Q_PAD_DRAM_D38 = 123, - MX6Q_PAD_DRAM_D39 = 124, - MX6Q_PAD_DRAM_DQM4 = 125, - MX6Q_PAD_DRAM_SDQS4 = 126, - MX6Q_PAD_DRAM_D24 = 127, - MX6Q_PAD_DRAM_D25 = 128, - MX6Q_PAD_DRAM_D26 = 129, - MX6Q_PAD_DRAM_D27 = 130, - MX6Q_PAD_DRAM_D28 = 131, - MX6Q_PAD_DRAM_D29 = 132, - MX6Q_PAD_DRAM_SDQS3 = 133, - MX6Q_PAD_DRAM_D30 = 134, - MX6Q_PAD_DRAM_D31 = 135, - MX6Q_PAD_DRAM_DQM3 = 136, - MX6Q_PAD_DRAM_D16 = 137, - MX6Q_PAD_DRAM_D17 = 138, - MX6Q_PAD_DRAM_D18 = 139, - MX6Q_PAD_DRAM_D19 = 140, - MX6Q_PAD_DRAM_D20 = 141, - MX6Q_PAD_DRAM_D21 = 142, - MX6Q_PAD_DRAM_D22 = 143, - MX6Q_PAD_DRAM_SDQS2 = 144, - MX6Q_PAD_DRAM_D23 = 145, - MX6Q_PAD_DRAM_DQM2 = 146, - MX6Q_PAD_DRAM_A0 = 147, - MX6Q_PAD_DRAM_A1 = 148, - MX6Q_PAD_DRAM_A2 = 149, - MX6Q_PAD_DRAM_A3 = 150, - MX6Q_PAD_DRAM_A4 = 151, - MX6Q_PAD_DRAM_A5 = 152, - MX6Q_PAD_DRAM_A6 = 153, - MX6Q_PAD_DRAM_A7 = 154, - MX6Q_PAD_DRAM_A8 = 155, - MX6Q_PAD_DRAM_A9 = 156, - MX6Q_PAD_DRAM_A10 = 157, - MX6Q_PAD_DRAM_A11 = 158, - MX6Q_PAD_DRAM_A12 = 159, - MX6Q_PAD_DRAM_A13 = 160, - MX6Q_PAD_DRAM_A14 = 161, - MX6Q_PAD_DRAM_A15 = 162, - MX6Q_PAD_DRAM_CAS = 163, - MX6Q_PAD_DRAM_CS0 = 164, - MX6Q_PAD_DRAM_CS1 = 165, - MX6Q_PAD_DRAM_RAS = 166, - MX6Q_PAD_DRAM_RESET = 167, - MX6Q_PAD_DRAM_SDBA0 = 168, - MX6Q_PAD_DRAM_SDBA1 = 169, - MX6Q_PAD_DRAM_SDCLK_0 = 170, - MX6Q_PAD_DRAM_SDBA2 = 171, - MX6Q_PAD_DRAM_SDCKE0 = 172, - MX6Q_PAD_DRAM_SDCLK_1 = 173, - MX6Q_PAD_DRAM_SDCKE1 = 174, - MX6Q_PAD_DRAM_SDODT0 = 175, - MX6Q_PAD_DRAM_SDODT1 = 176, - MX6Q_PAD_DRAM_SDWE = 177, - MX6Q_PAD_DRAM_D0 = 178, - MX6Q_PAD_DRAM_D1 = 179, - MX6Q_PAD_DRAM_D2 = 180, - MX6Q_PAD_DRAM_D3 = 181, - MX6Q_PAD_DRAM_D4 = 182, - MX6Q_PAD_DRAM_D5 = 183, - MX6Q_PAD_DRAM_SDQS0 = 184, - MX6Q_PAD_DRAM_D6 = 185, - MX6Q_PAD_DRAM_D7 = 186, - MX6Q_PAD_DRAM_DQM0 = 187, - MX6Q_PAD_DRAM_D8 = 188, - MX6Q_PAD_DRAM_D9 = 189, - MX6Q_PAD_DRAM_D10 = 190, - MX6Q_PAD_DRAM_D11 = 191, - MX6Q_PAD_DRAM_D12 = 192, - MX6Q_PAD_DRAM_D13 = 193, - MX6Q_PAD_DRAM_D14 = 194, - MX6Q_PAD_DRAM_SDQS1 = 195, - MX6Q_PAD_DRAM_D15 = 196, - MX6Q_PAD_DRAM_DQM1 = 197, - MX6Q_PAD_DRAM_D48 = 198, - MX6Q_PAD_DRAM_D49 = 199, - MX6Q_PAD_DRAM_D50 = 200, - MX6Q_PAD_DRAM_D51 = 201, - MX6Q_PAD_DRAM_D52 = 202, - MX6Q_PAD_DRAM_D53 = 203, - MX6Q_PAD_DRAM_D54 = 204, - MX6Q_PAD_DRAM_D55 = 205, - MX6Q_PAD_DRAM_SDQS6 = 206, - MX6Q_PAD_DRAM_DQM6 = 207, - MX6Q_PAD_DRAM_D56 = 208, - MX6Q_PAD_DRAM_SDQS7 = 209, - MX6Q_PAD_DRAM_D57 = 210, - MX6Q_PAD_DRAM_D58 = 211, - MX6Q_PAD_DRAM_D59 = 212, - MX6Q_PAD_DRAM_D60 = 213, - MX6Q_PAD_DRAM_DQM7 = 214, - MX6Q_PAD_DRAM_D61 = 215, - MX6Q_PAD_DRAM_D62 = 216, - MX6Q_PAD_DRAM_D63 = 217, - MX6Q_PAD_KEY_COL0 = 218, - MX6Q_PAD_KEY_ROW0 = 219, - MX6Q_PAD_KEY_COL1 = 220, - MX6Q_PAD_KEY_ROW1 = 221, - MX6Q_PAD_KEY_COL2 = 222, - MX6Q_PAD_KEY_ROW2 = 223, - MX6Q_PAD_KEY_COL3 = 224, - MX6Q_PAD_KEY_ROW3 = 225, - MX6Q_PAD_KEY_COL4 = 226, - MX6Q_PAD_KEY_ROW4 = 227, - MX6Q_PAD_GPIO_0 = 228, - MX6Q_PAD_GPIO_1 = 229, - MX6Q_PAD_GPIO_9 = 230, - MX6Q_PAD_GPIO_3 = 231, - MX6Q_PAD_GPIO_6 = 232, - MX6Q_PAD_GPIO_2 = 233, - MX6Q_PAD_GPIO_4 = 234, - MX6Q_PAD_GPIO_5 = 235, - MX6Q_PAD_GPIO_7 = 236, - MX6Q_PAD_GPIO_8 = 237, - MX6Q_PAD_GPIO_16 = 238, - MX6Q_PAD_GPIO_17 = 239, - MX6Q_PAD_GPIO_18 = 240, - MX6Q_PAD_GPIO_19 = 241, - MX6Q_PAD_CSI0_PIXCLK = 242, - MX6Q_PAD_CSI0_MCLK = 243, - MX6Q_PAD_CSI0_DATA_EN = 244, - MX6Q_PAD_CSI0_VSYNC = 245, - MX6Q_PAD_CSI0_DAT4 = 246, - MX6Q_PAD_CSI0_DAT5 = 247, - MX6Q_PAD_CSI0_DAT6 = 248, - MX6Q_PAD_CSI0_DAT7 = 249, - MX6Q_PAD_CSI0_DAT8 = 250, - MX6Q_PAD_CSI0_DAT9 = 251, - MX6Q_PAD_CSI0_DAT10 = 252, - MX6Q_PAD_CSI0_DAT11 = 253, - MX6Q_PAD_CSI0_DAT12 = 254, - MX6Q_PAD_CSI0_DAT13 = 255, - MX6Q_PAD_CSI0_DAT14 = 256, - MX6Q_PAD_CSI0_DAT15 = 257, - MX6Q_PAD_CSI0_DAT16 = 258, - MX6Q_PAD_CSI0_DAT17 = 259, - MX6Q_PAD_CSI0_DAT18 = 260, - MX6Q_PAD_CSI0_DAT19 = 261, - MX6Q_PAD_JTAG_TMS = 262, - MX6Q_PAD_JTAG_MOD = 263, - MX6Q_PAD_JTAG_TRSTB = 264, - MX6Q_PAD_JTAG_TDI = 265, - MX6Q_PAD_JTAG_TCK = 266, - MX6Q_PAD_JTAG_TDO = 267, - MX6Q_PAD_LVDS1_TX3_P = 268, - MX6Q_PAD_LVDS1_TX2_P = 269, - MX6Q_PAD_LVDS1_CLK_P = 270, - MX6Q_PAD_LVDS1_TX1_P = 271, - MX6Q_PAD_LVDS1_TX0_P = 272, - MX6Q_PAD_LVDS0_TX3_P = 273, - MX6Q_PAD_LVDS0_CLK_P = 274, - MX6Q_PAD_LVDS0_TX2_P = 275, - MX6Q_PAD_LVDS0_TX1_P = 276, - MX6Q_PAD_LVDS0_TX0_P = 277, - MX6Q_PAD_TAMPER = 278, - MX6Q_PAD_PMIC_ON_REQ = 279, - MX6Q_PAD_PMIC_STBY_REQ = 280, - MX6Q_PAD_POR_B = 281, - MX6Q_PAD_BOOT_MODE1 = 282, - MX6Q_PAD_RESET_IN_B = 283, - MX6Q_PAD_BOOT_MODE0 = 284, - MX6Q_PAD_TEST_MODE = 285, - MX6Q_PAD_SD3_DAT7 = 286, - MX6Q_PAD_SD3_DAT6 = 287, - MX6Q_PAD_SD3_DAT5 = 288, - MX6Q_PAD_SD3_DAT4 = 289, - MX6Q_PAD_SD3_CMD = 290, - MX6Q_PAD_SD3_CLK = 291, - MX6Q_PAD_SD3_DAT0 = 292, - MX6Q_PAD_SD3_DAT1 = 293, - MX6Q_PAD_SD3_DAT2 = 294, - MX6Q_PAD_SD3_DAT3 = 295, - MX6Q_PAD_SD3_RST = 296, - MX6Q_PAD_NANDF_CLE = 297, - MX6Q_PAD_NANDF_ALE = 298, - MX6Q_PAD_NANDF_WP_B = 299, - MX6Q_PAD_NANDF_RB0 = 300, - MX6Q_PAD_NANDF_CS0 = 301, - MX6Q_PAD_NANDF_CS1 = 302, - MX6Q_PAD_NANDF_CS2 = 303, - MX6Q_PAD_NANDF_CS3 = 304, - MX6Q_PAD_SD4_CMD = 305, - MX6Q_PAD_SD4_CLK = 306, - MX6Q_PAD_NANDF_D0 = 307, - MX6Q_PAD_NANDF_D1 = 308, - MX6Q_PAD_NANDF_D2 = 309, - MX6Q_PAD_NANDF_D3 = 310, - MX6Q_PAD_NANDF_D4 = 311, - MX6Q_PAD_NANDF_D5 = 312, - MX6Q_PAD_NANDF_D6 = 313, - MX6Q_PAD_NANDF_D7 = 314, - MX6Q_PAD_SD4_DAT0 = 315, - MX6Q_PAD_SD4_DAT1 = 316, - MX6Q_PAD_SD4_DAT2 = 317, - MX6Q_PAD_SD4_DAT3 = 318, - MX6Q_PAD_SD4_DAT4 = 319, - MX6Q_PAD_SD4_DAT5 = 320, - MX6Q_PAD_SD4_DAT6 = 321, - MX6Q_PAD_SD4_DAT7 = 322, - MX6Q_PAD_SD1_DAT1 = 323, - MX6Q_PAD_SD1_DAT0 = 324, - MX6Q_PAD_SD1_DAT3 = 325, - MX6Q_PAD_SD1_CMD = 326, - MX6Q_PAD_SD1_DAT2 = 327, - MX6Q_PAD_SD1_CLK = 328, - MX6Q_PAD_SD2_CLK = 329, - MX6Q_PAD_SD2_CMD = 330, - MX6Q_PAD_SD2_DAT3 = 331, -}; - -/* imx6q register maps */ -static struct imx_pin_reg imx6q_pin_regs[] = { - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */ - IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */ - IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */ - IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */ - IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */ - IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */ - IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */ - IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */ - IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */ - IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */ - IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */ -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P), - IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER), - IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ), - IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ), - IMX_PINCTRL_PIN(MX6Q_PAD_POR_B), - IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1), - IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B), - IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0), - IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3), -}; - -static struct imx_pinctrl_soc_info imx6q_pinctrl_info = { - .pins = imx6q_pinctrl_pads, - .npins = ARRAY_SIZE(imx6q_pinctrl_pads), - .pin_regs = imx6q_pin_regs, - .npin_regs = ARRAY_SIZE(imx6q_pin_regs), -}; - -static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = { - { .compatible = "fsl,imx6q-iomuxc", }, - { /* sentinel */ } -}; - -static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info); -} - -static struct platform_driver imx6q_pinctrl_driver = { - .driver = { - .name = "imx6q-pinctrl", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx6q_pinctrl_of_match), - }, - .probe = imx6q_pinctrl_probe, - .remove = __devexit_p(imx_pinctrl_remove), -}; - -static int __init imx6q_pinctrl_init(void) -{ - return platform_driver_register(&imx6q_pinctrl_driver); -} -arch_initcall(imx6q_pinctrl_init); - -static void __exit imx6q_pinctrl_exit(void) -{ - platform_driver_unregister(&imx6q_pinctrl_driver); -} -module_exit(imx6q_pinctrl_exit); -MODULE_AUTHOR("Dong Aisheng "); -MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/pinctrl/pinctrl-mxs.c b/trunk/drivers/pinctrl/pinctrl-mxs.c deleted file mode 100644 index 93cd959971c5..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-mxs.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "core.h" -#include "pinctrl-mxs.h" - -#define SUFFIX_LEN 4 - -struct mxs_pinctrl_data { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - struct mxs_pinctrl_soc_data *soc; -}; - -static int mxs_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->ngroups; -} - -static const char *mxs_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->groups[group].name; -} - -static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, - const unsigned **pins, unsigned *num_pins) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *pins = d->soc->groups[group].pins; - *num_pins = d->soc->groups[group].npins; - - return 0; -} - -static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, " %s", dev_name(pctldev->dev)); -} - -static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct pinctrl_map *new_map; - char *group; - unsigned new_num; - unsigned long config = 0; - unsigned long *pconfig; - int length = strlen(np->name) + SUFFIX_LEN; - u32 val; - int ret; - - ret = of_property_read_u32(np, "fsl,drive-strength", &val); - if (!ret) - config = val | MA_PRESENT; - ret = of_property_read_u32(np, "fsl,voltage", &val); - if (!ret) - config |= val << VOL_SHIFT | VOL_PRESENT; - ret = of_property_read_u32(np, "fsl,pull-up", &val); - if (!ret) - config |= val << PULL_SHIFT | PULL_PRESENT; - - new_num = config ? 2 : 1; - new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[0].data.mux.function = np->name; - - /* Compose group name */ - group = kzalloc(length, GFP_KERNEL); - if (!group) - return -ENOMEM; - of_property_read_u32(np, "reg", &val); - snprintf(group, length, "%s.%d", np->name, val); - new_map[0].data.mux.group = group; - - if (config) { - pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL); - if (!pconfig) { - ret = -ENOMEM; - goto free; - } - - new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP; - new_map[1].data.configs.group_or_pin = group; - new_map[1].data.configs.configs = pconfig; - new_map[1].data.configs.num_configs = 1; - } - - *map = new_map; - *num_maps = new_num; - - return 0; - -free: - kfree(new_map); - return ret; -} - -static void mxs_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) { - if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) - kfree(map[i].data.mux.group); - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - } - - kfree(map); -} - -static struct pinctrl_ops mxs_pinctrl_ops = { - .get_groups_count = mxs_get_groups_count, - .get_group_name = mxs_get_group_name, - .get_group_pins = mxs_get_group_pins, - .pin_dbg_show = mxs_pin_dbg_show, - .dt_node_to_map = mxs_dt_node_to_map, - .dt_free_map = mxs_dt_free_map, -}; - -static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->nfunctions; -} - -static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->functions[function].name; -} - -static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned group, - const char * const **groups, - unsigned * const num_groups) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *groups = d->soc->functions[group].groups; - *num_groups = d->soc->functions[group].ngroups; - - return 0; -} - -static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - struct mxs_group *g = &d->soc->groups[group]; - void __iomem *reg; - u8 bank, shift; - u16 pin; - int i; - - for (i = 0; i < g->npins; i++) { - bank = PINID_TO_BANK(g->pins[i]); - pin = PINID_TO_PIN(g->pins[i]); - reg = d->base + d->soc->regs->muxsel; - reg += bank * 0x20 + pin / 16 * 0x10; - shift = pin % 16 * 2; - - writel(0x3 << shift, reg + CLR); - writel(g->muxsel[i] << shift, reg + SET); - } - - return 0; -} - -static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - /* Nothing to do here */ -} - -static struct pinmux_ops mxs_pinmux_ops = { - .get_functions_count = mxs_pinctrl_get_funcs_count, - .get_function_name = mxs_pinctrl_get_func_name, - .get_function_groups = mxs_pinctrl_get_func_groups, - .enable = mxs_pinctrl_enable, - .disable = mxs_pinctrl_disable, -}; - -static int mxs_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long *config) -{ - return -ENOTSUPP; -} - -static int mxs_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) -{ - return -ENOTSUPP; -} - -static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned group, unsigned long *config) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *config = d->soc->groups[group].config; - - return 0; -} - -static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - struct mxs_group *g = &d->soc->groups[group]; - void __iomem *reg; - u8 ma, vol, pull, bank, shift; - u16 pin; - int i; - - ma = CONFIG_TO_MA(config); - vol = CONFIG_TO_VOL(config); - pull = CONFIG_TO_PULL(config); - - for (i = 0; i < g->npins; i++) { - bank = PINID_TO_BANK(g->pins[i]); - pin = PINID_TO_PIN(g->pins[i]); - - /* drive */ - reg = d->base + d->soc->regs->drive; - reg += bank * 0x40 + pin / 8 * 0x10; - - /* mA */ - if (config & MA_PRESENT) { - shift = pin % 8 * 4; - writel(0x3 << shift, reg + CLR); - writel(ma << shift, reg + SET); - } - - /* vol */ - if (config & VOL_PRESENT) { - shift = pin % 8 * 4 + 2; - if (vol) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); - } - - /* pull */ - if (config & PULL_PRESENT) { - reg = d->base + d->soc->regs->pull; - reg += bank * 0x10; - shift = pin; - if (pull) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); - } - } - - /* cache the config value for mxs_pinconf_group_get() */ - g->config = config; - - return 0; -} - -static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin) -{ - /* Not support */ -} - -static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ - unsigned long config; - - if (!mxs_pinconf_group_get(pctldev, group, &config)) - seq_printf(s, "0x%lx", config); -} - -struct pinconf_ops mxs_pinconf_ops = { - .pin_config_get = mxs_pinconf_get, - .pin_config_set = mxs_pinconf_set, - .pin_config_group_get = mxs_pinconf_group_get, - .pin_config_group_set = mxs_pinconf_group_set, - .pin_config_dbg_show = mxs_pinconf_dbg_show, - .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc mxs_pinctrl_desc = { - .pctlops = &mxs_pinctrl_ops, - .pmxops = &mxs_pinmux_ops, - .confops = &mxs_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev, - struct device_node *np, int idx, - const char **out_name) -{ - struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); - struct mxs_group *g = &d->soc->groups[idx]; - struct property *prop; - const char *propname = "fsl,pinmux-ids"; - char *group; - int length = strlen(np->name) + SUFFIX_LEN; - int i; - u32 val; - - group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL); - if (!group) - return -ENOMEM; - of_property_read_u32(np, "reg", &val); - snprintf(group, length, "%s.%d", np->name, val); - g->name = group; - - prop = of_find_property(np, propname, &length); - if (!prop) - return -EINVAL; - g->npins = length / sizeof(u32); - - g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins), - GFP_KERNEL); - if (!g->pins) - return -ENOMEM; - - g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel), - GFP_KERNEL); - if (!g->muxsel) - return -ENOMEM; - - of_property_read_u32_array(np, propname, g->pins, g->npins); - for (i = 0; i < g->npins; i++) { - g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]); - g->pins[i] = MUXID_TO_PINID(g->pins[i]); - } - - *out_name = g->name; - - return 0; -} - -static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev, - struct mxs_pinctrl_data *d) -{ - struct mxs_pinctrl_soc_data *soc = d->soc; - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - struct mxs_function *f; - const char *fn, *fnull = ""; - int i = 0, idxf = 0, idxg = 0; - int ret; - u32 val; - - child = of_get_next_child(np, NULL); - if (!child) { - dev_err(&pdev->dev, "no group is defined\n"); - return -ENOENT; - } - - /* Count total functions and groups */ - fn = fnull; - for_each_child_of_node(np, child) { - /* Skip pure pinconf node */ - if (of_property_read_u32(child, "reg", &val)) - continue; - if (strcmp(fn, child->name)) { - fn = child->name; - soc->nfunctions++; - } - soc->ngroups++; - } - - soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions * - sizeof(*soc->functions), GFP_KERNEL); - if (!soc->functions) - return -ENOMEM; - - soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups * - sizeof(*soc->groups), GFP_KERNEL); - if (!soc->groups) - return -ENOMEM; - - /* Count groups for each function */ - fn = fnull; - f = &soc->functions[idxf]; - for_each_child_of_node(np, child) { - if (of_property_read_u32(child, "reg", &val)) - continue; - if (strcmp(fn, child->name)) { - f = &soc->functions[idxf++]; - f->name = fn = child->name; - } - f->ngroups++; - }; - - /* Get groups for each function */ - idxf = 0; - fn = fnull; - for_each_child_of_node(np, child) { - if (of_property_read_u32(child, "reg", &val)) - continue; - if (strcmp(fn, child->name)) { - f = &soc->functions[idxf++]; - f->groups = devm_kzalloc(&pdev->dev, f->ngroups * - sizeof(*f->groups), - GFP_KERNEL); - if (!f->groups) - return -ENOMEM; - fn = child->name; - i = 0; - } - ret = mxs_pinctrl_parse_group(pdev, child, idxg++, - &f->groups[i++]); - if (ret) - return ret; - } - - return 0; -} - -int __devinit mxs_pinctrl_probe(struct platform_device *pdev, - struct mxs_pinctrl_soc_data *soc) -{ - struct device_node *np = pdev->dev.of_node; - struct mxs_pinctrl_data *d; - int ret; - - d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL); - if (!d) - return -ENOMEM; - - d->dev = &pdev->dev; - d->soc = soc; - - d->base = of_iomap(np, 0); - if (!d->base) - return -EADDRNOTAVAIL; - - mxs_pinctrl_desc.pins = d->soc->pins; - mxs_pinctrl_desc.npins = d->soc->npins; - mxs_pinctrl_desc.name = dev_name(&pdev->dev); - - platform_set_drvdata(pdev, d); - - ret = mxs_pinctrl_probe_dt(pdev, d); - if (ret) { - dev_err(&pdev->dev, "dt probe failed: %d\n", ret); - goto err; - } - - d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d); - if (!d->pctl) { - dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n"); - ret = -EINVAL; - goto err; - } - - return 0; - -err: - iounmap(d->base); - return ret; -} -EXPORT_SYMBOL_GPL(mxs_pinctrl_probe); - -int __devexit mxs_pinctrl_remove(struct platform_device *pdev) -{ - struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); - - pinctrl_unregister(d->pctl); - iounmap(d->base); - - return 0; -} -EXPORT_SYMBOL_GPL(mxs_pinctrl_remove); diff --git a/trunk/drivers/pinctrl/pinctrl-mxs.h b/trunk/drivers/pinctrl/pinctrl-mxs.h deleted file mode 100644 index fdd88d0bae22..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-mxs.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __PINCTRL_MXS_H -#define __PINCTRL_MXS_H - -#include -#include - -#define SET 0x4 -#define CLR 0x8 -#define TOG 0xc - -#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) -#define PINID(bank, pin) ((bank) * 32 + (pin)) - -/* - * pinmux-id bit field definitions - * - * bank: 15..12 (4) - * pin: 11..4 (8) - * muxsel: 3..0 (4) - */ -#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff) -#define MUXID_TO_MUXSEL(m) ((m) & 0xf) - -#define PINID_TO_BANK(p) ((p) >> 5) -#define PINID_TO_PIN(p) ((p) % 32) - -/* - * pin config bit field definitions - * - * pull-up: 6..5 (2) - * voltage: 4..3 (2) - * mA: 2..0 (3) - * - * MSB of each field is presence bit for the config. - */ -#define PULL_PRESENT (1 << 6) -#define PULL_SHIFT 5 -#define VOL_PRESENT (1 << 4) -#define VOL_SHIFT 3 -#define MA_PRESENT (1 << 2) -#define MA_SHIFT 0 -#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1) -#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1) -#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3) - -struct mxs_function { - const char *name; - const char **groups; - unsigned ngroups; -}; - -struct mxs_group { - const char *name; - unsigned int *pins; - unsigned npins; - u8 *muxsel; - u8 config; -}; - -struct mxs_regs { - u16 muxsel; - u16 drive; - u16 pull; -}; - -struct mxs_pinctrl_soc_data { - const struct mxs_regs *regs; - const struct pinctrl_pin_desc *pins; - unsigned npins; - struct mxs_function *functions; - unsigned nfunctions; - struct mxs_group *groups; - unsigned ngroups; -}; - -int mxs_pinctrl_probe(struct platform_device *pdev, - struct mxs_pinctrl_soc_data *soc); -int mxs_pinctrl_remove(struct platform_device *pdev); - -#endif /* __PINCTRL_MXS_H */ diff --git a/trunk/drivers/pinctrl/pinctrl-nomadik-db8500.c b/trunk/drivers/pinctrl/pinctrl-nomadik-db8500.c deleted file mode 100644 index 8b2022276f71..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-nomadik-db8500.c +++ /dev/null @@ -1,857 +0,0 @@ -#include -#include -#include "pinctrl-nomadik.h" - -/* All the pins that can be used for GPIO and some other functions */ -#define _GPIO(offset) (offset) - -#define DB8500_PIN_AJ5 _GPIO(0) -#define DB8500_PIN_AJ3 _GPIO(1) -#define DB8500_PIN_AH4 _GPIO(2) -#define DB8500_PIN_AH3 _GPIO(3) -#define DB8500_PIN_AH6 _GPIO(4) -#define DB8500_PIN_AG6 _GPIO(5) -#define DB8500_PIN_AF6 _GPIO(6) -#define DB8500_PIN_AG5 _GPIO(7) -#define DB8500_PIN_AD5 _GPIO(8) -#define DB8500_PIN_AE4 _GPIO(9) -#define DB8500_PIN_AF5 _GPIO(10) -#define DB8500_PIN_AG4 _GPIO(11) -#define DB8500_PIN_AC4 _GPIO(12) -#define DB8500_PIN_AF3 _GPIO(13) -#define DB8500_PIN_AE3 _GPIO(14) -#define DB8500_PIN_AC3 _GPIO(15) -#define DB8500_PIN_AD3 _GPIO(16) -#define DB8500_PIN_AD4 _GPIO(17) -#define DB8500_PIN_AC2 _GPIO(18) -#define DB8500_PIN_AC1 _GPIO(19) -#define DB8500_PIN_AB4 _GPIO(20) -#define DB8500_PIN_AB3 _GPIO(21) -#define DB8500_PIN_AA3 _GPIO(22) -#define DB8500_PIN_AA4 _GPIO(23) -#define DB8500_PIN_AB2 _GPIO(24) -#define DB8500_PIN_Y4 _GPIO(25) -#define DB8500_PIN_Y2 _GPIO(26) -#define DB8500_PIN_AA2 _GPIO(27) -#define DB8500_PIN_AA1 _GPIO(28) -#define DB8500_PIN_W2 _GPIO(29) -#define DB8500_PIN_W3 _GPIO(30) -#define DB8500_PIN_V3 _GPIO(31) -#define DB8500_PIN_V2 _GPIO(32) -#define DB8500_PIN_AF2 _GPIO(33) -#define DB8500_PIN_AE1 _GPIO(34) -#define DB8500_PIN_AE2 _GPIO(35) -#define DB8500_PIN_AG2 _GPIO(36) -/* Hole */ -#define DB8500_PIN_F3 _GPIO(64) -#define DB8500_PIN_F1 _GPIO(65) -#define DB8500_PIN_G3 _GPIO(66) -#define DB8500_PIN_G2 _GPIO(67) -#define DB8500_PIN_E1 _GPIO(68) -#define DB8500_PIN_E2 _GPIO(69) -#define DB8500_PIN_G5 _GPIO(70) -#define DB8500_PIN_G4 _GPIO(71) -#define DB8500_PIN_H4 _GPIO(72) -#define DB8500_PIN_H3 _GPIO(73) -#define DB8500_PIN_J3 _GPIO(74) -#define DB8500_PIN_H2 _GPIO(75) -#define DB8500_PIN_J2 _GPIO(76) -#define DB8500_PIN_H1 _GPIO(77) -#define DB8500_PIN_F4 _GPIO(78) -#define DB8500_PIN_E3 _GPIO(79) -#define DB8500_PIN_E4 _GPIO(80) -#define DB8500_PIN_D2 _GPIO(81) -#define DB8500_PIN_C1 _GPIO(82) -#define DB8500_PIN_D3 _GPIO(83) -#define DB8500_PIN_C2 _GPIO(84) -#define DB8500_PIN_D5 _GPIO(85) -#define DB8500_PIN_C6 _GPIO(86) -#define DB8500_PIN_B3 _GPIO(87) -#define DB8500_PIN_C4 _GPIO(88) -#define DB8500_PIN_E6 _GPIO(89) -#define DB8500_PIN_A3 _GPIO(90) -#define DB8500_PIN_B6 _GPIO(91) -#define DB8500_PIN_D6 _GPIO(92) -#define DB8500_PIN_B7 _GPIO(93) -#define DB8500_PIN_D7 _GPIO(94) -#define DB8500_PIN_E8 _GPIO(95) -#define DB8500_PIN_D8 _GPIO(96) -#define DB8500_PIN_D9 _GPIO(97) -/* Hole */ -#define DB8500_PIN_A5 _GPIO(128) -#define DB8500_PIN_B4 _GPIO(129) -#define DB8500_PIN_C8 _GPIO(130) -#define DB8500_PIN_A12 _GPIO(131) -#define DB8500_PIN_C10 _GPIO(132) -#define DB8500_PIN_B10 _GPIO(133) -#define DB8500_PIN_B9 _GPIO(134) -#define DB8500_PIN_A9 _GPIO(135) -#define DB8500_PIN_C7 _GPIO(136) -#define DB8500_PIN_A7 _GPIO(137) -#define DB8500_PIN_C5 _GPIO(138) -#define DB8500_PIN_C9 _GPIO(139) -#define DB8500_PIN_B11 _GPIO(140) -#define DB8500_PIN_C12 _GPIO(141) -#define DB8500_PIN_C11 _GPIO(142) -#define DB8500_PIN_D12 _GPIO(143) -#define DB8500_PIN_B13 _GPIO(144) -#define DB8500_PIN_C13 _GPIO(145) -#define DB8500_PIN_D13 _GPIO(146) -#define DB8500_PIN_C15 _GPIO(147) -#define DB8500_PIN_B16 _GPIO(148) -#define DB8500_PIN_B14 _GPIO(149) -#define DB8500_PIN_C14 _GPIO(150) -#define DB8500_PIN_D17 _GPIO(151) -#define DB8500_PIN_D16 _GPIO(152) -#define DB8500_PIN_B17 _GPIO(153) -#define DB8500_PIN_C16 _GPIO(154) -#define DB8500_PIN_C19 _GPIO(155) -#define DB8500_PIN_C17 _GPIO(156) -#define DB8500_PIN_A18 _GPIO(157) -#define DB8500_PIN_C18 _GPIO(158) -#define DB8500_PIN_B19 _GPIO(159) -#define DB8500_PIN_B20 _GPIO(160) -#define DB8500_PIN_D21 _GPIO(161) -#define DB8500_PIN_D20 _GPIO(162) -#define DB8500_PIN_C20 _GPIO(163) -#define DB8500_PIN_B21 _GPIO(164) -#define DB8500_PIN_C21 _GPIO(165) -#define DB8500_PIN_A22 _GPIO(166) -#define DB8500_PIN_B24 _GPIO(167) -#define DB8500_PIN_C22 _GPIO(168) -#define DB8500_PIN_D22 _GPIO(169) -#define DB8500_PIN_C23 _GPIO(170) -#define DB8500_PIN_D23 _GPIO(171) -/* Hole */ -#define DB8500_PIN_AJ27 _GPIO(192) -#define DB8500_PIN_AH27 _GPIO(193) -#define DB8500_PIN_AF27 _GPIO(194) -#define DB8500_PIN_AG28 _GPIO(195) -#define DB8500_PIN_AG26 _GPIO(196) -#define DB8500_PIN_AH24 _GPIO(197) -#define DB8500_PIN_AG25 _GPIO(198) -#define DB8500_PIN_AH23 _GPIO(199) -#define DB8500_PIN_AH26 _GPIO(200) -#define DB8500_PIN_AF24 _GPIO(201) -#define DB8500_PIN_AF25 _GPIO(202) -#define DB8500_PIN_AE23 _GPIO(203) -#define DB8500_PIN_AF23 _GPIO(204) -#define DB8500_PIN_AG23 _GPIO(205) -#define DB8500_PIN_AG24 _GPIO(206) -#define DB8500_PIN_AJ23 _GPIO(207) -#define DB8500_PIN_AH16 _GPIO(208) -#define DB8500_PIN_AG15 _GPIO(209) -#define DB8500_PIN_AJ15 _GPIO(210) -#define DB8500_PIN_AG14 _GPIO(211) -#define DB8500_PIN_AF13 _GPIO(212) -#define DB8500_PIN_AG13 _GPIO(213) -#define DB8500_PIN_AH15 _GPIO(214) -#define DB8500_PIN_AH13 _GPIO(215) -#define DB8500_PIN_AG12 _GPIO(216) -#define DB8500_PIN_AH12 _GPIO(217) -#define DB8500_PIN_AH11 _GPIO(218) -#define DB8500_PIN_AG10 _GPIO(219) -#define DB8500_PIN_AH10 _GPIO(220) -#define DB8500_PIN_AJ11 _GPIO(221) -#define DB8500_PIN_AJ9 _GPIO(222) -#define DB8500_PIN_AH9 _GPIO(223) -#define DB8500_PIN_AG9 _GPIO(224) -#define DB8500_PIN_AG8 _GPIO(225) -#define DB8500_PIN_AF8 _GPIO(226) -#define DB8500_PIN_AH7 _GPIO(227) -#define DB8500_PIN_AJ6 _GPIO(228) -#define DB8500_PIN_AG7 _GPIO(229) -#define DB8500_PIN_AF7 _GPIO(230) -/* Hole */ -#define DB8500_PIN_AF28 _GPIO(256) -#define DB8500_PIN_AE29 _GPIO(257) -#define DB8500_PIN_AD29 _GPIO(258) -#define DB8500_PIN_AC29 _GPIO(259) -#define DB8500_PIN_AD28 _GPIO(260) -#define DB8500_PIN_AD26 _GPIO(261) -#define DB8500_PIN_AE26 _GPIO(262) -#define DB8500_PIN_AG29 _GPIO(263) -#define DB8500_PIN_AE27 _GPIO(264) -#define DB8500_PIN_AD27 _GPIO(265) -#define DB8500_PIN_AC28 _GPIO(266) -#define DB8500_PIN_AC27 _GPIO(267) - -/* - * The names of the pins are denoted by GPIO number and ball name, even - * though they can be used for other things than GPIO, this is the first - * column in the table of the data sheet and often used on schematics and - * such. - */ -static const struct pinctrl_pin_desc nmk_db8500_pins[] = { - PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"), - PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"), - PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"), - PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"), - PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"), - PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"), - PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"), - PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"), - PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"), - PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"), - PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"), - PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"), - PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"), - PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"), - PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"), - PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"), - PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"), - PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"), - PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"), - PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"), - PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"), - PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"), - PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"), - PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"), - PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"), - PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"), - PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"), - PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"), - PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"), - PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"), - PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"), - PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"), - PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"), - PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"), - PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"), - PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"), - PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"), - /* Hole */ - PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"), - PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"), - PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"), - PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"), - PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"), - PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"), - PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"), - PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"), - PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"), - PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"), - PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"), - PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"), - PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"), - PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"), - PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"), - PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"), - PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"), - PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"), - PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"), - PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"), - PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"), - PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"), - PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"), - PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"), - PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"), - PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"), - PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"), - PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"), - PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"), - PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"), - PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"), - PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"), - PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"), - PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"), - /* Hole */ - PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"), - PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"), - PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"), - PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"), - PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"), - PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"), - PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"), - PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"), - PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"), - PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"), - PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"), - PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"), - PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"), - PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"), - PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"), - PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"), - PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"), - PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"), - PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"), - PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"), - PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"), - PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"), - PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"), - PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"), - PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"), - PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"), - PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"), - PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"), - PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"), - PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"), - PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"), - PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"), - PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"), - PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"), - PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"), - PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"), - PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"), - PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"), - PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"), - PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"), - PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"), - PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"), - PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"), - PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"), - /* Hole */ - PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"), - PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"), - PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"), - PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"), - PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"), - PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"), - PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"), - PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"), - PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"), - PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"), - PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"), - PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"), - PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"), - PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"), - PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"), - PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"), - PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"), - PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"), - PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"), - PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"), - PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"), - PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"), - PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"), - PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"), - PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"), - PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"), - PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"), - PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"), - PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"), - PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"), - PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"), - PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"), - PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"), - PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"), - PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"), - PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"), - PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"), - PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"), - PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"), - /* Hole */ - PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"), - PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"), - PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"), - PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"), - PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"), - PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"), - PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"), - PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"), - PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"), - PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"), - PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"), - PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"), -}; - -#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \ - .pin_base = b, .npins = c } - -/* - * This matches the 32-pin gpio chips registered by the GPIO portion. This - * cannot be const since we assign the struct gpio_chip * pointer at runtime. - */ -static struct pinctrl_gpio_range nmk_db8500_ranges[] = { - DB8500_GPIO_RANGE(0, 0, 32), - DB8500_GPIO_RANGE(1, 32, 5), - DB8500_GPIO_RANGE(2, 64, 32), - DB8500_GPIO_RANGE(3, 96, 2), - DB8500_GPIO_RANGE(4, 128, 32), - DB8500_GPIO_RANGE(5, 160, 12), - DB8500_GPIO_RANGE(6, 192, 32), - DB8500_GPIO_RANGE(7, 224, 7), - DB8500_GPIO_RANGE(8, 256, 12), -}; - -/* - * Read the pin group names like this: - * u0_a_1 = first groups of pins for uart0 on alt function a - * i2c2_b_2 = second group of pins for i2c2 on alt function b - * - * The groups are arranged as sets per altfunction column, so we can - * mux in one group at a time by selecting the same altfunction for them - * all. When functions require pins on different altfunctions, you need - * to combine several groups. - */ - -/* Altfunction A column */ -static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, - DB8500_PIN_AH4, DB8500_PIN_AH3 }; -static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; -static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; -/* Image processor I2C line, this is driven by image processor firmware */ -static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; -static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; -/* MSP0 can only be on these pins, but TXD and RXD can be flipped */ -static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; -static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 }; -static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; -/* Basic pins of the MMC/SD card 0 interface */ -static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, - DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, - DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; -/* Often only 4 bits are used, then these are not needed (only used for MMC) */ -static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, - DB8500_PIN_V3, DB8500_PIN_V2}; -static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 }; -/* MSP1 can only be on these pins, but TXD and RXD can be flipped */ -static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; -static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 }; -/* LCD interface */ -static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, - DB8500_PIN_G3, DB8500_PIN_G2 }; -static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 }; -static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 }; -static const unsigned lcd_d0_d7_a_1_pins[] = { - DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, - DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 }; -/* D8 thru D11 often used as TVOUT lines */ -static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4, - DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 }; -static const unsigned lcd_d12_d23_a_1_pins[] = { - DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5, - DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6, - DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 }; -static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8, - DB8500_PIN_D8, DB8500_PIN_D9 }; -static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 }; -static const unsigned kp_a_2_pins[] = { - DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, - DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; -/* MC2 has 8 data lines and no direction control, so only for (e)MMC */ -static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4, - DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, - DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, - DB8500_PIN_C5 }; -static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, - DB8500_PIN_C12, DB8500_PIN_C11 }; -static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13, - DB8500_PIN_C13, DB8500_PIN_D13 }; -static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 }; -/* - * Image processor GPIO pins are named "ipgpio" and have their own - * numberspace - */ -static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 }; -static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 }; -/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */ -static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23, - DB8500_PIN_D23 }; -/* - * This MSP cannot switch RX and TX, SCK in a separate group since this - * seems to be optional. - */ -static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 }; -static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27, - DB8500_PIN_AG28, DB8500_PIN_AG26 }; -static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25, - DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25, - DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24, - DB8500_PIN_AJ23 }; -/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */ -static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15, - DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, - DB8500_PIN_AH15 }; -static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, - DB8500_PIN_AH12, DB8500_PIN_AH11 }; -static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 }; -static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9, - DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 }; -static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 }; -static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; -static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29, - DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26, - DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27, - DB8500_PIN_AC28, DB8500_PIN_AC27 }; - -/* Altfunction B column */ -static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 }; -static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; -static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; -static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; -static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; -static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; -static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; -/* Just RX and TX for UART2 */ -static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 }; -static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 }; -static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 }; -static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 }; -static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4, - DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; -static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 }; -static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, - DB8500_PIN_V3, DB8500_PIN_V2 }; -static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; -static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, - DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2, - DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, - DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1, - DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2, - DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 }; -static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, - DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, - DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, - DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8, - DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9, - DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5, - DB8500_PIN_C9, DB8500_PIN_B14 }; -/* This chip select pin can be "ps0" in alt B so have it separately */ -static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 }; -static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 }; -static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 }; -static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 }; -static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 }; -static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22, - DB8500_PIN_C23, DB8500_PIN_D23 }; -static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, - DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, - DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; -static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 }; -static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 }; -static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13, - DB8500_PIN_AG13, DB8500_PIN_AH15 }; -static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, - DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10, - DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9, - DB8500_PIN_AG8 }; -static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 }; -static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 }; -static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 }; - -/* Altfunction C column */ -static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, - DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 }; -static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 }; -static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 }; -static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 }; -static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 }; -static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 }; -static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; -/* Optional 4-bit Memory Stick interface */ -static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, - DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, - DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; -static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 }; -static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 }; -static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 }; -static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1, - DB8500_PIN_AE2, DB8500_PIN_AG2 }; -static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 }; -static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 }; -static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 }; -static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 }; -static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 }; -static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, - DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 }; -static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 }; -static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 }; -static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 }; -static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 }; -static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 }; -static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, - DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, - DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, - DB8500_PIN_D9 }; -static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 }; -static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, - DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16, - DB8500_PIN_C23, DB8500_PIN_D23 }; -static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 }; -static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 }; -static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 }; -static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 }; -static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 }; -static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 }; -static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 }; -static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 }; -static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 }; -static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 }; -static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9, - DB8500_PIN_AG9, DB8500_PIN_AG8 }; -static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 }; -static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; - -/* Other C1 column */ -static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, - DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, - DB8500_PIN_D6, DB8500_PIN_B7 }; -static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, - DB8500_PIN_AH12, DB8500_PIN_AH11 }; - -#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \ - .npins = ARRAY_SIZE(a##_pins), .altsetting = b } - -static const struct nmk_pingroup nmk_db8500_groups[] = { - /* Altfunction A column */ - DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A), - /* Altfunction B column */ - DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B), - /* Altfunction C column */ - DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C), - /* Other alt C1 column, these are still configured as alt C */ - DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C), -}; - -/* We use this macro to define the groups applicable to a function */ -#define DB8500_FUNC_GROUPS(a, b...) \ -static const char * const a##_groups[] = { b }; - -DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1"); -DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1"); -/* - * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however - * only available on two pins in alternative function C - */ -DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1", - "u2rxtx_c_2", "u2rxtx_c_3"); -DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2"); -/* - * MSP0 can only be on a certain set of pins, but the TX/RX pins can be - * switched around by selecting the altfunction A or B. The SCK pin is - * only available on the altfunction B. - */ -DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1", - "msp0txrx_b_1", "msp0sck_b_1"); -DB8500_FUNC_GROUPS(mc0, "mc0_a_1"); -/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */ -DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1"); -DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1"); -DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1", - "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1"); -DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1"); -DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); -DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1"); -DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1"); -DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1"); -/* The image processor has 8 GPIO pins that can be muxed out */ -DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1", - "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1", - "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1", - "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2", - "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2"); -/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */ -DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1"); -DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); -DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1"); -DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1"); -DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1"); -DB8500_FUNC_GROUPS(usb, "usb_a_1"); -DB8500_FUNC_GROUPS(trig, "trig_b_1"); -DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1"); -DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2"); -DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2"); -/* - * The modem UART can output its RX and TX pins in some different places, - * so select one of each. - */ -DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2", - "uartmodrx_c_1", "uartmod_tx_c_1"); -DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1"); -DB8500_FUNC_GROUPS(spi3, "spi3_b_1"); -/* Select between CS0 on alt B or PS1 on alt C */ -DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1"); -DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1"); -DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1"); -DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4"); -DB8500_FUNC_GROUPS(spi1, "spi1_b_1"); -DB8500_FUNC_GROUPS(mc3, "mc3_b_1"); -DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1"); -DB8500_FUNC_GROUPS(slim0, "slim0_c_1"); -DB8500_FUNC_GROUPS(ms, "ms_c_1"); -DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1"); -DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2"); -DB8500_FUNC_GROUPS(mc5, "mc5_c_1"); -DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2"); -DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2"); -DB8500_FUNC_GROUPS(spi0, "spi0_c_1"); -DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1"); - -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -static const struct nmk_function nmk_db8500_functions[] = { - FUNCTION(u0), - FUNCTION(u1), - FUNCTION(u2), - FUNCTION(ipi2c), - FUNCTION(msp0), - FUNCTION(mc0), - FUNCTION(msp1), - FUNCTION(lcdb), - FUNCTION(lcd), - FUNCTION(kp), - FUNCTION(mc2), - FUNCTION(ssp1), - FUNCTION(ssp0), - FUNCTION(i2c0), - FUNCTION(ipgpio), - FUNCTION(msp2), - FUNCTION(mc4), - FUNCTION(mc1), - FUNCTION(hsi), - FUNCTION(clkout), - FUNCTION(usb), - FUNCTION(trig), - FUNCTION(i2c4), - FUNCTION(i2c1), - FUNCTION(i2c2), - FUNCTION(uartmod), - FUNCTION(stmmod), - FUNCTION(spi3), - FUNCTION(sm), - FUNCTION(lcda), - FUNCTION(ddrtrig), - FUNCTION(pwl), - FUNCTION(spi1), - FUNCTION(mc3), - FUNCTION(ipjtag), - FUNCTION(slim0), - FUNCTION(ms), - FUNCTION(iptrigout), - FUNCTION(stmape), - FUNCTION(mc5), - FUNCTION(usbsim), - FUNCTION(i2c3), - FUNCTION(spi0), - FUNCTION(spi2), -}; - -static const struct nmk_pinctrl_soc_data nmk_db8500_soc = { - .gpio_ranges = nmk_db8500_ranges, - .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges), - .pins = nmk_db8500_pins, - .npins = ARRAY_SIZE(nmk_db8500_pins), - .functions = nmk_db8500_functions, - .nfunctions = ARRAY_SIZE(nmk_db8500_functions), - .groups = nmk_db8500_groups, - .ngroups = ARRAY_SIZE(nmk_db8500_groups), -}; - -void __devinit -nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) -{ - *soc = &nmk_db8500_soc; -} diff --git a/trunk/drivers/pinctrl/pinctrl-nomadik.h b/trunk/drivers/pinctrl/pinctrl-nomadik.h deleted file mode 100644 index bc91aed7185d..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-nomadik.h +++ /dev/null @@ -1,77 +0,0 @@ -#ifndef PINCTRL_PINCTRL_NOMADIK_H -#define PINCTRL_PINCTRL_NOMADIK_H - -#include - -/* Package definitions */ -#define PINCTRL_NMK_STN8815 0 -#define PINCTRL_NMK_DB8500 1 - -/** - * struct nmk_function - Nomadik pinctrl mux function - * @name: The name of the function, exported to pinctrl core. - * @groups: An array of pin groups that may select this function. - * @ngroups: The number of entries in @groups. - */ -struct nmk_function { - const char *name; - const char * const *groups; - unsigned ngroups; -}; - -/** - * struct nmk_pingroup - describes a Nomadik pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @num_pins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - * @altsetting: the altsetting to apply to all pins in this group to - * configure them to be used by a function - */ -struct nmk_pingroup { - const char *name; - const unsigned int *pins; - const unsigned npins; - int altsetting; -}; - -/** - * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration - * @gpio_ranges: An array of GPIO ranges for this SoC - * @gpio_num_ranges: The number of GPIO ranges for this SoC - * @pins: An array describing all pins the pin controller affects. - * All pins which are also GPIOs must be listed first within the - * array, and be numbered identically to the GPIO controller's - * numbering. - * @npins: The number of entries in @pins. - * @functions: The functions supported on this SoC. - * @nfunction: The number of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The number of entries in @groups. - */ -struct nmk_pinctrl_soc_data { - struct pinctrl_gpio_range *gpio_ranges; - unsigned gpio_num_ranges; - const struct pinctrl_pin_desc *pins; - unsigned npins; - const struct nmk_function *functions; - unsigned nfunctions; - const struct nmk_pingroup *groups; - unsigned ngroups; -}; - -#ifdef CONFIG_PINCTRL_DB8500 - -void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc); - -#else - -static inline void -nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) -{ -} - -#endif - -#endif /* PINCTRL_PINCTRL_NOMADIK_H */ diff --git a/trunk/drivers/pinctrl/pinctrl-pxa3xx.c b/trunk/drivers/pinctrl/pinctrl-pxa3xx.c index 7644e42ac211..079dce0e93e9 100644 --- a/trunk/drivers/pinctrl/pinctrl-pxa3xx.c +++ b/trunk/drivers/pinctrl/pinctrl-pxa3xx.c @@ -25,18 +25,20 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = { .pin_base = 0, }; -static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev) +static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - - return info->num_grps; + if (selector >= info->num_grps) + return -EINVAL; + return 0; } static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev, unsigned selector) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - + if (selector >= info->num_grps) + return NULL; return info->grps[selector].name; } @@ -46,23 +48,25 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev, unsigned *num_pins) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - + if (selector >= info->num_grps) + return -EINVAL; *pins = info->grps[selector].pins; *num_pins = info->grps[selector].npins; return 0; } static struct pinctrl_ops pxa3xx_pctrl_ops = { - .get_groups_count = pxa3xx_get_groups_count, + .list_groups = pxa3xx_list_groups, .get_group_name = pxa3xx_get_group_name, .get_group_pins = pxa3xx_get_group_pins, }; -static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev) +static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - - return info->num_funcs; + if (func >= info->num_funcs) + return -EINVAL; + return 0; } static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev, @@ -166,7 +170,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev, } static struct pinmux_ops pxa3xx_pmx_ops = { - .get_functions_count = pxa3xx_pmx_get_funcs_count, + .list_functions = pxa3xx_pmx_list_func, .get_function_name = pxa3xx_pmx_get_func_name, .get_function_groups = pxa3xx_pmx_get_groups, .enable = pxa3xx_pmx_enable, diff --git a/trunk/drivers/pinctrl/pinctrl-sirf.c b/trunk/drivers/pinctrl/pinctrl-sirf.c index ba15b1a29e52..6b3534cc051a 100644 --- a/trunk/drivers/pinctrl/pinctrl-sirf.c +++ b/trunk/drivers/pinctrl/pinctrl-sirf.c @@ -853,14 +853,18 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), }; -static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) +static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(sirfsoc_pin_groups); + if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) + return -EINVAL; + return 0; } static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, unsigned selector) { + if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) + return NULL; return sirfsoc_pin_groups[selector].name; } @@ -868,6 +872,8 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector const unsigned **pins, unsigned *num_pins) { + if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) + return -EINVAL; *pins = sirfsoc_pin_groups[selector].pins; *num_pins = sirfsoc_pin_groups[selector].num_pins; return 0; @@ -880,7 +886,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s } static struct pinctrl_ops sirfsoc_pctrl_ops = { - .get_groups_count = sirfsoc_get_groups_count, + .list_groups = sirfsoc_list_groups, .get_group_name = sirfsoc_get_group_name, .get_group_pins = sirfsoc_get_group_pins, .pin_dbg_show = sirfsoc_pin_dbg_show, @@ -1027,9 +1033,11 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector sirfsoc_pinmux_endisable(spmx, selector, false); } -static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) +static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector) { - return ARRAY_SIZE(sirfsoc_pmx_functions); + if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions)) + return -EINVAL; + return 0; } static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, @@ -1066,9 +1074,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, } static struct pinmux_ops sirfsoc_pinmux_ops = { + .list_functions = sirfsoc_pinmux_list_funcs, .enable = sirfsoc_pinmux_enable, .disable = sirfsoc_pinmux_disable, - .get_functions_count = sirfsoc_pinmux_get_funcs_count, .get_function_name = sirfsoc_pinmux_get_func_name, .get_function_groups = sirfsoc_pinmux_get_groups, .gpio_request_enable = sirfsoc_pinmux_request_gpio, diff --git a/trunk/drivers/pinctrl/pinctrl-tegra.c b/trunk/drivers/pinctrl/pinctrl-tegra.c index b6934867d8d3..9b329688120c 100644 --- a/trunk/drivers/pinctrl/pinctrl-tegra.c +++ b/trunk/drivers/pinctrl/pinctrl-tegra.c @@ -1,7 +1,7 @@ /* * Driver for the NVIDIA Tegra pinmux * - * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. * * Derived from code: * Copyright (C) 2010 Google, Inc. @@ -22,19 +22,17 @@ #include #include #include -#include -#include -#include +#include #include #include #include -#include #include -#include "core.h" #include "pinctrl-tegra.h" +#define DRIVER_NAME "tegra-pinmux-disabled" + struct tegra_pmx { struct device *dev; struct pinctrl_dev *pctl; @@ -55,11 +53,15 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) writel(val, pmx->regs[bank] + reg); } -static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev, + unsigned group) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->soc->ngroups; + if (group >= pmx->soc->ngroups) + return -EINVAL; + + return 0; } static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, @@ -67,6 +69,9 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + if (group >= pmx->soc->ngroups) + return NULL; + return pmx->soc->groups[group].name; } @@ -77,259 +82,38 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + if (group >= pmx->soc->ngroups) + return -EINVAL; + *pins = pmx->soc->groups[group].pins; *num_pins = pmx->soc->groups[group].npins; return 0; } -#ifdef CONFIG_DEBUG_FS static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset) { - seq_printf(s, " %s", dev_name(pctldev->dev)); -} -#endif - -static int reserve_map(struct device *dev, struct pinctrl_map **map, - unsigned *reserved_maps, unsigned *num_maps, - unsigned reserve) -{ - unsigned old_num = *reserved_maps; - unsigned new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) { - dev_err(dev, "krealloc(map) failed\n"); - return -ENOMEM; - } - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, const char *group, - const char *function) -{ - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -static int add_map_configs(struct device *dev, struct pinctrl_map **map, - unsigned *reserved_maps, unsigned *num_maps, - const char *group, unsigned long *configs, - unsigned num_configs) -{ - unsigned long *dup_configs; - - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) { - dev_err(dev, "kmemdup(configs) failed\n"); - return -ENOMEM; - } - - (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static int add_config(struct device *dev, unsigned long **configs, - unsigned *num_configs, unsigned long config) -{ - unsigned old_num = *num_configs; - unsigned new_num = old_num + 1; - unsigned long *new_configs; - - new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, - GFP_KERNEL); - if (!new_configs) { - dev_err(dev, "krealloc(configs) failed\n"); - return -ENOMEM; - } - - new_configs[old_num] = config; - - *configs = new_configs; - *num_configs = new_num; - - return 0; -} - -void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - - kfree(map); -} - -static const struct cfg_param { - const char *property; - enum tegra_pinconf_param param; -} cfg_params[] = { - {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, - {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, - {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, - {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, - {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, - {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, - {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, - {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, - {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, - {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, - {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, - {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, - {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, -}; - -int tegra_pinctrl_dt_subnode_to_map(struct device *dev, - struct device_node *np, - struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps) -{ - int ret, i; - const char *function; - u32 val; - unsigned long config; - unsigned long *configs = NULL; - unsigned num_configs = 0; - unsigned reserve; - struct property *prop; - const char *group; - - ret = of_property_read_string(np, "nvidia,function", &function); - if (ret < 0) { - /* EINVAL=missing, which is fine since it's optional */ - if (ret != -EINVAL) - dev_err(dev, - "could not parse property nvidia,function\n"); - function = NULL; - } - - for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { - ret = of_property_read_u32(np, cfg_params[i].property, &val); - if (!ret) { - config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); - ret = add_config(dev, &configs, &num_configs, config); - if (ret < 0) - goto exit; - /* EINVAL=missing, which is fine since it's optional */ - } else if (ret != -EINVAL) { - dev_err(dev, "could not parse property %s\n", - cfg_params[i].property); - } - } - - reserve = 0; - if (function != NULL) - reserve++; - if (num_configs) - reserve++; - ret = of_property_count_strings(np, "nvidia,pins"); - if (ret < 0) { - dev_err(dev, "could not parse property nvidia,pins\n"); - goto exit; - } - reserve *= ret; - - ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "nvidia,pins", prop, group) { - if (function) { - ret = add_map_mux(map, reserved_maps, num_maps, - group, function); - if (ret < 0) - goto exit; - } - - if (num_configs) { - ret = add_map_configs(dev, map, reserved_maps, - num_maps, group, configs, - num_configs); - if (ret < 0) - goto exit; - } - } - - ret = 0; - -exit: - kfree(configs); - return ret; -} - -int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - unsigned reserved_maps; - struct device_node *np; - int ret; - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map, - &reserved_maps, num_maps); - if (ret < 0) { - tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; + seq_printf(s, " " DRIVER_NAME); } static struct pinctrl_ops tegra_pinctrl_ops = { - .get_groups_count = tegra_pinctrl_get_groups_count, + .list_groups = tegra_pinctrl_list_groups, .get_group_name = tegra_pinctrl_get_group_name, .get_group_pins = tegra_pinctrl_get_group_pins, -#ifdef CONFIG_DEBUG_FS .pin_dbg_show = tegra_pinctrl_pin_dbg_show, -#endif - .dt_node_to_map = tegra_pinctrl_dt_node_to_map, - .dt_free_map = tegra_pinctrl_dt_free_map, }; -static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev, + unsigned function) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->soc->nfunctions; + if (function >= pmx->soc->nfunctions) + return -EINVAL; + + return 0; } static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, @@ -337,6 +121,9 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + if (function >= pmx->soc->nfunctions) + return NULL; + return pmx->soc->functions[function].name; } @@ -347,6 +134,9 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + if (function >= pmx->soc->nfunctions) + return -EINVAL; + *groups = pmx->soc->functions[function].groups; *num_groups = pmx->soc->functions[function].ngroups; @@ -361,16 +151,18 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, int i; u32 val; + if (group >= pmx->soc->ngroups) + return -EINVAL; g = &pmx->soc->groups[group]; - if (WARN_ON(g->mux_reg < 0)) + if (g->mux_reg < 0) return -EINVAL; for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { if (g->funcs[i] == function) break; } - if (WARN_ON(i == ARRAY_SIZE(g->funcs))) + if (i == ARRAY_SIZE(g->funcs)) return -EINVAL; val = pmx_readl(pmx, g->mux_bank, g->mux_reg); @@ -388,9 +180,11 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, const struct tegra_pingroup *g; u32 val; + if (group >= pmx->soc->ngroups) + return; g = &pmx->soc->groups[group]; - if (WARN_ON(g->mux_reg < 0)) + if (g->mux_reg < 0) return; val = pmx_readl(pmx, g->mux_bank, g->mux_reg); @@ -400,7 +194,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, } static struct pinmux_ops tegra_pinmux_ops = { - .get_functions_count = tegra_pinctrl_get_funcs_count, + .list_functions = tegra_pinctrl_list_funcs, .get_function_name = tegra_pinctrl_get_func_name, .get_function_groups = tegra_pinctrl_get_func_groups, .enable = tegra_pinctrl_enable, @@ -410,7 +204,6 @@ static struct pinmux_ops tegra_pinmux_ops = { static int tegra_pinconf_reg(struct tegra_pmx *pmx, const struct tegra_pingroup *g, enum tegra_pinconf_param param, - bool report_err, s8 *bank, s16 *reg, s8 *bit, s8 *width) { switch (param) { @@ -498,10 +291,9 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, } if (*reg < 0) { - if (report_err) - dev_err(pmx->dev, - "Config param %04x not supported on group %s\n", - param, g->name); + dev_err(pmx->dev, + "Config param %04x not supported on group %s\n", + param, g->name); return -ENOTSUPP; } @@ -511,14 +303,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, static int tegra_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { - dev_err(pctldev->dev, "pin_config_get op not supported\n"); return -ENOTSUPP; } static int tegra_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long config) { - dev_err(pctldev->dev, "pin_config_set op not supported\n"); return -ENOTSUPP; } @@ -534,10 +324,11 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, s16 reg; u32 val, mask; + if (group >= pmx->soc->ngroups) + return -EINVAL; g = &pmx->soc->groups[group]; - ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, - &width); + ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width); if (ret < 0) return ret; @@ -562,10 +353,11 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, s16 reg; u32 val, mask; + if (group >= pmx->soc->ngroups) + return -EINVAL; g = &pmx->soc->groups[group]; - ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, - &width); + ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width); if (ret < 0) return ret; @@ -573,10 +365,8 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, /* LOCK can't be cleared */ if (param == TEGRA_PINCONF_PARAM_LOCK) { - if ((val & BIT(bit)) && !arg) { - dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); + if ((val & BIT(bit)) && !arg) return -EINVAL; - } } /* Special-case Boolean values; allow any non-zero as true */ @@ -585,12 +375,8 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, /* Range-check user-supplied value */ mask = (1 << width) - 1; - if (arg & ~mask) { - dev_err(pctldev->dev, - "config %lx: %x too big for %d bit register\n", - config, arg, width); + if (arg & ~mask) return -EINVAL; - } /* Update register */ val &= ~(mask << bit); @@ -600,78 +386,23 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, return 0; } -#ifdef CONFIG_DEBUG_FS static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset) { } -static const char *strip_prefix(const char *s) -{ - const char *comma = strchr(s, ','); - if (!comma) - return s; - - return comma + 1; -} - static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) + struct seq_file *s, unsigned selector) { - struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tegra_pingroup *g; - int i, ret; - s8 bank, bit, width; - s16 reg; - u32 val; - - g = &pmx->soc->groups[group]; - - for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { - ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, - &bank, ®, &bit, &width); - if (ret < 0) - continue; - - val = pmx_readl(pmx, bank, reg); - val >>= bit; - val &= (1 << width) - 1; - - seq_printf(s, "\n\t%s=%u", - strip_prefix(cfg_params[i].property), val); - } } -static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned long config) -{ - enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); - u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); - const char *pname = "unknown"; - int i; - - for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { - if (cfg_params[i].param == param) { - pname = cfg_params[i].property; - break; - } - } - - seq_printf(s, "%s=%d", strip_prefix(pname), arg); -} -#endif - struct pinconf_ops tegra_pinconf_ops = { .pin_config_get = tegra_pinconf_get, .pin_config_set = tegra_pinconf_set, .pin_config_group_get = tegra_pinconf_group_get, .pin_config_group_set = tegra_pinconf_group_set, -#ifdef CONFIG_DEBUG_FS .pin_config_dbg_show = tegra_pinconf_dbg_show, .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, - .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, -#endif }; static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { @@ -681,29 +412,60 @@ static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { }; static struct pinctrl_desc tegra_pinctrl_desc = { + .name = DRIVER_NAME, .pctlops = &tegra_pinctrl_ops, .pmxops = &tegra_pinmux_ops, .confops = &tegra_pinconf_ops, .owner = THIS_MODULE, }; -int __devinit tegra_pinctrl_probe(struct platform_device *pdev, - const struct tegra_pinctrl_soc_data *soc_data) +static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = { +#ifdef CONFIG_PINCTRL_TEGRA20 + { + .compatible = "nvidia,tegra20-pinmux-disabled", + .data = tegra20_pinctrl_init, + }, +#endif +#ifdef CONFIG_PINCTRL_TEGRA30 + { + .compatible = "nvidia,tegra30-pinmux-disabled", + .data = tegra30_pinctrl_init, + }, +#endif + {}, +}; + +static int __devinit tegra_pinctrl_probe(struct platform_device *pdev) { + const struct of_device_id *match; + tegra_pinctrl_soc_initf initf = NULL; struct tegra_pmx *pmx; struct resource *res; int i; + match = of_match_device(tegra_pinctrl_of_match, &pdev->dev); + if (match) + initf = (tegra_pinctrl_soc_initf)match->data; +#ifdef CONFIG_PINCTRL_TEGRA20 + if (!initf) + initf = tegra20_pinctrl_init; +#endif + if (!initf) { + dev_err(&pdev->dev, + "Could not determine SoC-specific init func\n"); + return -EINVAL; + } + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) { dev_err(&pdev->dev, "Can't alloc tegra_pmx\n"); return -ENOMEM; } pmx->dev = &pdev->dev; - pmx->soc = soc_data; + + (*initf)(&pmx->soc); tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; - tegra_pinctrl_desc.name = dev_name(&pdev->dev); tegra_pinctrl_desc.pins = pmx->soc->pins; tegra_pinctrl_desc.npins = pmx->soc->npins; @@ -758,9 +520,8 @@ int __devinit tegra_pinctrl_probe(struct platform_device *pdev, return 0; } -EXPORT_SYMBOL_GPL(tegra_pinctrl_probe); -int __devexit tegra_pinctrl_remove(struct platform_device *pdev) +static int __devexit tegra_pinctrl_remove(struct platform_device *pdev) { struct tegra_pmx *pmx = platform_get_drvdata(pdev); @@ -769,4 +530,30 @@ int __devexit tegra_pinctrl_remove(struct platform_device *pdev) return 0; } -EXPORT_SYMBOL_GPL(tegra_pinctrl_remove); + +static struct platform_driver tegra_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = tegra_pinctrl_of_match, + }, + .probe = tegra_pinctrl_probe, + .remove = __devexit_p(tegra_pinctrl_remove), +}; + +static int __init tegra_pinctrl_init(void) +{ + return platform_driver_register(&tegra_pinctrl_driver); +} +arch_initcall(tegra_pinctrl_init); + +static void __exit tegra_pinctrl_exit(void) +{ + platform_driver_unregister(&tegra_pinctrl_driver); +} +module_exit(tegra_pinctrl_exit); + +MODULE_AUTHOR("Stephen Warren "); +MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/pinctrl-tegra.h b/trunk/drivers/pinctrl/pinctrl-tegra.h index 705c007a38cc..782c795326ef 100644 --- a/trunk/drivers/pinctrl/pinctrl-tegra.h +++ b/trunk/drivers/pinctrl/pinctrl-tegra.h @@ -139,8 +139,25 @@ struct tegra_pinctrl_soc_data { unsigned ngroups; }; -int tegra_pinctrl_probe(struct platform_device *pdev, - const struct tegra_pinctrl_soc_data *soc_data); -int tegra_pinctrl_remove(struct platform_device *pdev); +/** + * tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC. + * @soc_data: This pointer must be updated to point at a struct containing + * details of the SoC. + */ +typedef void (*tegra_pinctrl_soc_initf)( + const struct tegra_pinctrl_soc_data **soc_data); + +/** + * tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20 + * @soc_data: This pointer will be updated to point at a struct containing + * details of Tegra20's pin controller. + */ +void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data); +/** + * tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20 + * @soc_data: This pointer will be updated to point at a struct containing + * details of Tegra30's pin controller. + */ +void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data); #endif diff --git a/trunk/drivers/pinctrl/pinctrl-tegra20.c b/trunk/drivers/pinctrl/pinctrl-tegra20.c index a74f9a568536..f69ff96aa292 100644 --- a/trunk/drivers/pinctrl/pinctrl-tegra20.c +++ b/trunk/drivers/pinctrl/pinctrl-tegra20.c @@ -1,7 +1,7 @@ /* * Pinctrl data for the NVIDIA Tegra20 pinmux * - * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. * * Derived from code: * Copyright (C) 2010 Google, Inc. @@ -17,8 +17,6 @@ * more details. */ -#include -#include #include #include #include @@ -2856,39 +2854,7 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = { .ngroups = ARRAY_SIZE(tegra20_groups), }; -static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev) +void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) { - return tegra_pinctrl_probe(pdev, &tegra20_pinctrl); + *soc = &tegra20_pinctrl; } - -static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = { - { .compatible = "nvidia,tegra20-pinmux", }, - { }, -}; - -static struct platform_driver tegra20_pinctrl_driver = { - .driver = { - .name = "tegra20-pinctrl", - .owner = THIS_MODULE, - .of_match_table = tegra20_pinctrl_of_match, - }, - .probe = tegra20_pinctrl_probe, - .remove = __devexit_p(tegra_pinctrl_remove), -}; - -static int __init tegra20_pinctrl_init(void) -{ - return platform_driver_register(&tegra20_pinctrl_driver); -} -arch_initcall(tegra20_pinctrl_init); - -static void __exit tegra20_pinctrl_exit(void) -{ - platform_driver_unregister(&tegra20_pinctrl_driver); -} -module_exit(tegra20_pinctrl_exit); - -MODULE_AUTHOR("Stephen Warren "); -MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/pinctrl-tegra30.c b/trunk/drivers/pinctrl/pinctrl-tegra30.c index 0386fdf0da16..4d7571d4a431 100644 --- a/trunk/drivers/pinctrl/pinctrl-tegra30.c +++ b/trunk/drivers/pinctrl/pinctrl-tegra30.c @@ -1,7 +1,7 @@ /* * Pinctrl data for the NVIDIA Tegra30 pinmux * - * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -13,8 +13,6 @@ * more details. */ -#include -#include #include #include #include @@ -3722,39 +3720,7 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = { .ngroups = ARRAY_SIZE(tegra30_groups), }; -static int __devinit tegra30_pinctrl_probe(struct platform_device *pdev) +void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) { - return tegra_pinctrl_probe(pdev, &tegra30_pinctrl); + *soc = &tegra30_pinctrl; } - -static struct of_device_id tegra30_pinctrl_of_match[] __devinitdata = { - { .compatible = "nvidia,tegra30-pinmux", }, - { }, -}; - -static struct platform_driver tegra30_pinctrl_driver = { - .driver = { - .name = "tegra30-pinctrl", - .owner = THIS_MODULE, - .of_match_table = tegra30_pinctrl_of_match, - }, - .probe = tegra30_pinctrl_probe, - .remove = __devexit_p(tegra_pinctrl_remove), -}; - -static int __init tegra30_pinctrl_init(void) -{ - return platform_driver_register(&tegra30_pinctrl_driver); -} -arch_initcall(tegra30_pinctrl_init); - -static void __exit tegra30_pinctrl_exit(void) -{ - platform_driver_unregister(&tegra30_pinctrl_driver); -} -module_exit(tegra30_pinctrl_exit); - -MODULE_AUTHOR("Stephen Warren "); -MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/pinctrl-u300.c b/trunk/drivers/pinctrl/pinctrl-u300.c index 05d029911be6..26eb8ccd72d5 100644 --- a/trunk/drivers/pinctrl/pinctrl-u300.c +++ b/trunk/drivers/pinctrl/pinctrl-u300.c @@ -836,14 +836,18 @@ static const struct u300_pin_group u300_pin_groups[] = { }, }; -static int u300_get_groups_count(struct pinctrl_dev *pctldev) +static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(u300_pin_groups); + if (selector >= ARRAY_SIZE(u300_pin_groups)) + return -EINVAL; + return 0; } static const char *u300_get_group_name(struct pinctrl_dev *pctldev, unsigned selector) { + if (selector >= ARRAY_SIZE(u300_pin_groups)) + return NULL; return u300_pin_groups[selector].name; } @@ -851,6 +855,8 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins) { + if (selector >= ARRAY_SIZE(u300_pin_groups)) + return -EINVAL; *pins = u300_pin_groups[selector].pins; *num_pins = u300_pin_groups[selector].num_pins; return 0; @@ -863,7 +869,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, } static struct pinctrl_ops u300_pctrl_ops = { - .get_groups_count = u300_get_groups_count, + .list_groups = u300_list_groups, .get_group_name = u300_get_group_name, .get_group_pins = u300_get_group_pins, .pin_dbg_show = u300_pin_dbg_show, @@ -985,9 +991,11 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, u300_pmx_endisable(upmx, selector, false); } -static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(u300_pmx_functions); + if (selector >= ARRAY_SIZE(u300_pmx_functions)) + return -EINVAL; + return 0; } static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev, @@ -1006,7 +1014,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, } static struct pinmux_ops u300_pmx_ops = { - .get_functions_count = u300_pmx_get_funcs_count, + .list_functions = u300_pmx_list_funcs, .get_function_name = u300_pmx_get_func_name, .get_function_groups = u300_pmx_get_groups, .enable = u300_pmx_enable, diff --git a/trunk/drivers/pinctrl/pinmux.c b/trunk/drivers/pinctrl/pinmux.c index 220fa492c9f0..4e62783a573a 100644 --- a/trunk/drivers/pinctrl/pinmux.c +++ b/trunk/drivers/pinctrl/pinmux.c @@ -33,26 +33,22 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev) { const struct pinmux_ops *ops = pctldev->desc->pmxops; - unsigned nfuncs; unsigned selector = 0; /* Check that we implement required operations */ - if (!ops || - !ops->get_functions_count || + if (!ops->list_functions || !ops->get_function_name || !ops->get_function_groups || !ops->enable || - !ops->disable) { - dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); + !ops->disable) return -EINVAL; - } + /* Check that all functions registered have names */ - nfuncs = ops->get_functions_count(pctldev); - while (selector < nfuncs) { + while (ops->list_functions(pctldev, selector) >= 0) { const char *fname = ops->get_function_name(pctldev, selector); if (!fname) { - dev_err(pctldev->dev, "pinmux ops has no name for function%u\n", + pr_err("pinmux ops has no name for function%u\n", selector); return -EINVAL; } @@ -89,23 +85,20 @@ static int pin_request(struct pinctrl_dev *pctldev, const struct pinmux_ops *ops = pctldev->desc->pmxops; int status = -EINVAL; + dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner); + desc = pin_desc_get(pctldev, pin); if (desc == NULL) { dev_err(pctldev->dev, - "pin %d is not registered so it cannot be requested\n", - pin); + "pin is not registered so it cannot be requested\n"); goto out; } - dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n", - pin, desc->name, owner); - if (gpio_range) { /* There's no need to support multiple GPIO requests */ if (desc->gpio_owner) { dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->gpio_owner, owner); + "pin already requested\n"); goto out; } @@ -113,8 +106,7 @@ static int pin_request(struct pinctrl_dev *pctldev, } else { if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) { dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->mux_owner, owner); + "pin already requested\n"); goto out; } @@ -147,7 +139,8 @@ static int pin_request(struct pinctrl_dev *pctldev, status = 0; if (status) { - dev_err(pctldev->dev, "request() failed for pin %d\n", pin); + dev_err(pctldev->dev, "->request on device %s failed for pin %d\n", + pctldev->desc->name, pin); module_put(pctldev->owner); } @@ -164,7 +157,7 @@ static int pin_request(struct pinctrl_dev *pctldev, out: if (status) dev_err(pctldev->dev, "pin-%d (%s) status %d\n", - pin, owner, status); + pin, owner, status); return status; } @@ -294,11 +287,10 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, const char *function) { const struct pinmux_ops *ops = pctldev->desc->pmxops; - unsigned nfuncs = ops->get_functions_count(pctldev); unsigned selector = 0; /* See if this pctldev has this function */ - while (selector < nfuncs) { + while (ops->list_functions(pctldev, selector) >= 0) { const char *fname = ops->get_function_name(pctldev, selector); @@ -327,32 +319,18 @@ int pinmux_map_to_setting(struct pinctrl_map const *map, const unsigned *pins; unsigned num_pins; - if (!pmxops) { - dev_err(pctldev->dev, "does not support mux function\n"); - return -EINVAL; - } - - ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function); - if (ret < 0) { - dev_err(pctldev->dev, "invalid function %s in map table\n", - map->data.mux.function); - return ret; - } - setting->data.mux.func = ret; + setting->data.mux.func = + pinmux_func_name_to_selector(pctldev, map->data.mux.function); + if (setting->data.mux.func < 0) + return setting->data.mux.func; ret = pmxops->get_function_groups(pctldev, setting->data.mux.func, &groups, &num_groups); - if (ret < 0) { - dev_err(pctldev->dev, "can't query groups for function %s\n", - map->data.mux.function); + if (ret < 0) return ret; - } - if (!num_groups) { - dev_err(pctldev->dev, - "function %s can't be selected on any group\n", - map->data.mux.function); + if (!num_groups) return -EINVAL; - } + if (map->data.mux.group) { bool found = false; group = map->data.mux.group; @@ -362,23 +340,15 @@ int pinmux_map_to_setting(struct pinctrl_map const *map, break; } } - if (!found) { - dev_err(pctldev->dev, - "invalid group \"%s\" for function \"%s\"\n", - group, map->data.mux.function); + if (!found) return -EINVAL; - } } else { group = groups[0]; } - ret = pinctrl_get_group_selector(pctldev, group); - if (ret < 0) { - dev_err(pctldev->dev, "invalid group %s in map table\n", - map->data.mux.group); - return ret; - } - setting->data.mux.group = ret; + setting->data.mux.group = pinctrl_get_group_selector(pctldev, group); + if (setting->data.mux.group < 0) + return setting->data.mux.group; ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins, &num_pins); @@ -394,7 +364,7 @@ int pinmux_map_to_setting(struct pinctrl_map const *map, ret = pin_request(pctldev, pins[i], map->dev_name, NULL); if (ret) { dev_err(pctldev->dev, - "could not request pin %d on device %s\n", + "could not get request pin %d on device %s\n", pins[i], pinctrl_dev_get_name(pctldev)); /* On error release all taken pins */ i--; /* this pin just failed */ @@ -507,15 +477,11 @@ static int pinmux_functions_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; const struct pinmux_ops *pmxops = pctldev->desc->pmxops; - unsigned nfuncs; unsigned func_selector = 0; - if (!pmxops) - return 0; - mutex_lock(&pinctrl_mutex); - nfuncs = pmxops->get_functions_count(pctldev); - while (func_selector < nfuncs) { + + while (pmxops->list_functions(pctldev, func_selector) >= 0) { const char *func = pmxops->get_function_name(pctldev, func_selector); const char * const *groups; @@ -549,9 +515,6 @@ static int pinmux_pins_show(struct seq_file *s, void *what) const struct pinmux_ops *pmxops = pctldev->desc->pmxops; unsigned i, pin; - if (!pmxops) - return 0; - seq_puts(s, "Pinmux settings per pin\n"); seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n"); diff --git a/trunk/drivers/pinctrl/pinmux.h b/trunk/drivers/pinctrl/pinmux.h index d1a98b1c9fce..6fc47003e95d 100644 --- a/trunk/drivers/pinctrl/pinmux.h +++ b/trunk/drivers/pinctrl/pinmux.h @@ -31,6 +31,12 @@ void pinmux_free_setting(struct pinctrl_setting const *setting); int pinmux_enable_setting(struct pinctrl_setting const *setting); void pinmux_disable_setting(struct pinctrl_setting const *setting); +void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map); +void pinmux_show_setting(struct seq_file *s, + struct pinctrl_setting const *setting); +void pinmux_init_device_debugfs(struct dentry *devroot, + struct pinctrl_dev *pctldev); + #else static inline int pinmux_check_ops(struct pinctrl_dev *pctldev) @@ -83,18 +89,6 @@ static inline void pinmux_disable_setting( { } -#endif - -#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS) - -void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map); -void pinmux_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting); -void pinmux_init_device_debugfs(struct dentry *devroot, - struct pinctrl_dev *pctldev); - -#else - static inline void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map) { diff --git a/trunk/drivers/pinctrl/spear/Kconfig b/trunk/drivers/pinctrl/spear/Kconfig deleted file mode 100644 index 6a2596b4f359..000000000000 --- a/trunk/drivers/pinctrl/spear/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -# -# ST Microelectronics SPEAr PINCTRL drivers -# - -if PLAT_SPEAR - -config PINCTRL_SPEAR - bool - depends on OF - select PINMUX - help - This enables pin control drivers for SPEAr Platform - -config PINCTRL_SPEAR3XX - bool - depends on ARCH_SPEAR3XX - select PINCTRL_SPEAR - -config PINCTRL_SPEAR300 - bool "ST Microelectronics SPEAr300 SoC pin controller driver" - depends on MACH_SPEAR300 - select PINCTRL_SPEAR3XX - -config PINCTRL_SPEAR310 - bool "ST Microelectronics SPEAr310 SoC pin controller driver" - depends on MACH_SPEAR310 - select PINCTRL_SPEAR3XX - -config PINCTRL_SPEAR320 - bool "ST Microelectronics SPEAr320 SoC pin controller driver" - depends on MACH_SPEAR320 - select PINCTRL_SPEAR3XX - -endif diff --git a/trunk/drivers/pinctrl/spear/Makefile b/trunk/drivers/pinctrl/spear/Makefile deleted file mode 100644 index 15dcb85da22d..000000000000 --- a/trunk/drivers/pinctrl/spear/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPEAr pinmux support - -obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o -obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o -obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o -obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o -obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear.c b/trunk/drivers/pinctrl/spear/pinctrl-spear.c deleted file mode 100644 index 5ae50aadf885..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * Inspired from: - * - U300 Pinctl drivers - * - Tegra Pinctl drivers - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-spear.h" - -#define DRIVER_NAME "spear-pinmux" - -static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) -{ - return readl_relaxed(pmx->vbase + reg); -} - -static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) -{ - writel_relaxed(val, pmx->vbase + reg); -} - -static int set_mode(struct spear_pmx *pmx, int mode) -{ - struct spear_pmx_mode *pmx_mode = NULL; - int i; - u32 val; - - if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes) - return -EINVAL; - - for (i = 0; i < pmx->machdata->npmx_modes; i++) { - if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) { - pmx_mode = pmx->machdata->pmx_modes[i]; - break; - } - } - - if (!pmx_mode) - return -EINVAL; - - val = pmx_readl(pmx, pmx_mode->reg); - val &= ~pmx_mode->mask; - val |= pmx_mode->val; - pmx_writel(pmx, val, pmx_mode->reg); - - pmx->machdata->mode = pmx_mode->mode; - dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n", - pmx_mode->name ? pmx_mode->name : "no_name", - pmx_mode->reg); - - return 0; -} - -void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg) -{ - struct spear_pingroup *pgroup; - struct spear_modemux *modemux; - int i, j, group; - - for (group = 0; group < machdata->ngroups; group++) { - pgroup = machdata->groups[group]; - - for (i = 0; i < pgroup->nmodemuxs; i++) { - modemux = &pgroup->modemuxs[i]; - - for (j = 0; j < modemux->nmuxregs; j++) - if (modemux->muxregs[j].reg == 0xFFFF) - modemux->muxregs[j].reg = reg; - } - } -} - -static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->machdata->ngroups; -} - -static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->machdata->groups[group]->name; -} - -static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, const unsigned **pins, unsigned *num_pins) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - *pins = pmx->machdata->groups[group]->pins; - *num_pins = pmx->machdata->groups[group]->npins; - - return 0; -} - -static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned offset) -{ - seq_printf(s, " " DRIVER_NAME); -} - -int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct device_node *np; - struct property *prop; - const char *function, *group; - int ret, index = 0, count = 0; - - /* calculate number of maps required */ - for_each_child_of_node(np_config, np) { - ret = of_property_read_string(np, "st,function", &function); - if (ret < 0) - return ret; - - ret = of_property_count_strings(np, "st,pins"); - if (ret < 0) - return ret; - - count += ret; - } - - if (!count) { - dev_err(pmx->dev, "No child nodes passed via DT\n"); - return -ENODEV; - } - - *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); - if (!*map) - return -ENOMEM; - - for_each_child_of_node(np_config, np) { - of_property_read_string(np, "st,function", &function); - of_property_for_each_string(np, "st,pins", prop, group) { - (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[index].data.mux.group = group; - (*map)[index].data.mux.function = function; - index++; - } - } - - *num_maps = count; - - return 0; -} - -void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - kfree(map); -} - -static struct pinctrl_ops spear_pinctrl_ops = { - .get_groups_count = spear_pinctrl_get_groups_cnt, - .get_group_name = spear_pinctrl_get_group_name, - .get_group_pins = spear_pinctrl_get_group_pins, - .pin_dbg_show = spear_pinctrl_pin_dbg_show, - .dt_node_to_map = spear_pinctrl_dt_node_to_map, - .dt_free_map = spear_pinctrl_dt_free_map, -}; - -static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->machdata->nfunctions; -} - -static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->machdata->functions[function]->name; -} - -static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned function, const char *const **groups, - unsigned * const ngroups) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - *groups = pmx->machdata->functions[function]->groups; - *ngroups = pmx->machdata->functions[function]->ngroups; - - return 0; -} - -static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group, bool enable) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct spear_pingroup *pgroup; - const struct spear_modemux *modemux; - struct spear_muxreg *muxreg; - u32 val, temp; - int i, j; - bool found = false; - - pgroup = pmx->machdata->groups[group]; - - for (i = 0; i < pgroup->nmodemuxs; i++) { - modemux = &pgroup->modemuxs[i]; - - /* SoC have any modes */ - if (pmx->machdata->modes_supported) { - if (!(pmx->machdata->mode & modemux->modes)) - continue; - } - - found = true; - for (j = 0; j < modemux->nmuxregs; j++) { - muxreg = &modemux->muxregs[j]; - - val = pmx_readl(pmx, muxreg->reg); - val &= ~muxreg->mask; - - if (enable) - temp = muxreg->val; - else - temp = ~muxreg->val; - - val |= temp; - pmx_writel(pmx, val, muxreg->reg); - } - } - - if (!found) { - dev_err(pmx->dev, "pinmux group: %s not supported\n", - pgroup->name); - return -ENODEV; - } - - return 0; -} - -static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) -{ - return spear_pinctrl_endisable(pctldev, function, group, true); -} - -static void spear_pinctrl_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - spear_pinctrl_endisable(pctldev, function, group, false); -} - -static struct pinmux_ops spear_pinmux_ops = { - .get_functions_count = spear_pinctrl_get_funcs_count, - .get_function_name = spear_pinctrl_get_func_name, - .get_function_groups = spear_pinctrl_get_func_groups, - .enable = spear_pinctrl_enable, - .disable = spear_pinctrl_disable, -}; - -static struct pinctrl_desc spear_pinctrl_desc = { - .name = DRIVER_NAME, - .pctlops = &spear_pinctrl_ops, - .pmxops = &spear_pinmux_ops, - .owner = THIS_MODULE, -}; - -int __devinit spear_pinctrl_probe(struct platform_device *pdev, - struct spear_pinctrl_machdata *machdata) -{ - struct device_node *np = pdev->dev.of_node; - struct resource *res; - struct spear_pmx *pmx; - - if (!machdata) - return -ENODEV; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; - - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); - if (!pmx) { - dev_err(&pdev->dev, "Can't alloc spear_pmx\n"); - return -ENOMEM; - } - - pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!pmx->vbase) { - dev_err(&pdev->dev, "Couldn't ioremap at index 0\n"); - return -ENODEV; - } - - pmx->dev = &pdev->dev; - pmx->machdata = machdata; - - /* configure mode, if supported by SoC */ - if (machdata->modes_supported) { - int mode = 0; - - if (of_property_read_u32(np, "st,pinmux-mode", &mode)) { - dev_err(&pdev->dev, "OF: pinmux mode not passed\n"); - return -EINVAL; - } - - if (set_mode(pmx, mode)) { - dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n", - mode); - return -EINVAL; - } - } - - platform_set_drvdata(pdev, pmx); - - spear_pinctrl_desc.pins = machdata->pins; - spear_pinctrl_desc.npins = machdata->npins; - - pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx); - if (IS_ERR(pmx->pctl)) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(pmx->pctl); - } - - return 0; -} - -int __devexit spear_pinctrl_remove(struct platform_device *pdev) -{ - struct spear_pmx *pmx = platform_get_drvdata(pdev); - - pinctrl_unregister(pmx->pctl); - - return 0; -} diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear.h b/trunk/drivers/pinctrl/spear/pinctrl-spear.h deleted file mode 100644 index 47a6b5b72f90..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Driver header file for the ST Microelectronics SPEAr pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PINMUX_SPEAR_H__ -#define __PINMUX_SPEAR_H__ - -#include -#include - -struct platform_device; -struct device; - -/** - * struct spear_pmx_mode - SPEAr pmx mode - * @name: name of pmx mode - * @mode: mode id - * @reg: register for configuring this mode - * @mask: mask of this mode in reg - * @val: val to be configured at reg after doing (val & mask) - */ -struct spear_pmx_mode { - const char *const name; - u16 mode; - u16 reg; - u16 mask; - u32 val; -}; - -/** - * struct spear_muxreg - SPEAr mux reg configuration - * @reg: register offset - * @mask: mask bits - * @val: val to be written on mask bits - */ -struct spear_muxreg { - u16 reg; - u32 mask; - u32 val; -}; - -/** - * struct spear_modemux - SPEAr mode mux configuration - * @modes: mode ids supported by this group of muxregs - * @nmuxregs: number of muxreg configurations to be done for modes - * @muxregs: array of muxreg configurations to be done for modes - */ -struct spear_modemux { - u16 modes; - u8 nmuxregs; - struct spear_muxreg *muxregs; -}; - -/** - * struct spear_pingroup - SPEAr pin group configurations - * @name: name of pin group - * @pins: array containing pin numbers - * @npins: size of pins array - * @modemuxs: array of modemux configurations for this pin group - * @nmodemuxs: size of array modemuxs - * - * A representation of a group of pins in the SPEAr pin controller. Each group - * allows some parameter or parameters to be configured. - */ -struct spear_pingroup { - const char *name; - const unsigned *pins; - unsigned npins; - struct spear_modemux *modemuxs; - unsigned nmodemuxs; -}; - -/** - * struct spear_function - SPEAr pinctrl mux function - * @name: The name of the function, exported to pinctrl core. - * @groups: An array of pin groups that may select this function. - * @ngroups: The number of entries in @groups. - */ -struct spear_function { - const char *name; - const char *const *groups; - unsigned ngroups; -}; - -/** - * struct spear_pinctrl_machdata - SPEAr pin controller machine driver - * configuration - * @pins: An array describing all pins the pin controller affects. - * All pins which are also GPIOs must be listed first within the *array, - * and be numbered identically to the GPIO controller's *numbering. - * @npins: The numbmer of entries in @pins. - * @functions: An array describing all mux functions the SoC supports. - * @nfunctions: The numbmer of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The numbmer of entries in @groups. - * - * @modes_supported: Does SoC support modes - * @mode: mode configured from probe - * @pmx_modes: array of modes supported by SoC - * @npmx_modes: number of entries in pmx_modes. - */ -struct spear_pinctrl_machdata { - const struct pinctrl_pin_desc *pins; - unsigned npins; - struct spear_function **functions; - unsigned nfunctions; - struct spear_pingroup **groups; - unsigned ngroups; - - bool modes_supported; - u16 mode; - struct spear_pmx_mode **pmx_modes; - unsigned npmx_modes; -}; - -/** - * struct spear_pmx - SPEAr pinctrl mux - * @dev: pointer to struct dev of platform_device registered - * @pctl: pointer to struct pinctrl_dev - * @machdata: pointer to SoC or machine specific structure - * @vbase: virtual base address of pinmux controller - */ -struct spear_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - struct spear_pinctrl_machdata *machdata; - void __iomem *vbase; -}; - -/* exported routines */ -void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); -int __devinit spear_pinctrl_probe(struct platform_device *pdev, - struct spear_pinctrl_machdata *machdata); -int __devexit spear_pinctrl_remove(struct platform_device *pdev); -#endif /* __PINMUX_SPEAR_H__ */ diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear300.c b/trunk/drivers/pinctrl/spear/pinctrl-spear300.c deleted file mode 100644 index 9c82a35e4e78..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear300.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr300 pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "pinctrl-spear3xx.h" - -#define DRIVER_NAME "spear300-pinmux" - -/* addresses */ -#define PMX_CONFIG_REG 0x00 -#define MODE_CONFIG_REG 0x04 - -/* modes */ -#define NAND_MODE (1 << 0) -#define NOR_MODE (1 << 1) -#define PHOTO_FRAME_MODE (1 << 2) -#define LEND_IP_PHONE_MODE (1 << 3) -#define HEND_IP_PHONE_MODE (1 << 4) -#define LEND_WIFI_PHONE_MODE (1 << 5) -#define HEND_WIFI_PHONE_MODE (1 << 6) -#define ATA_PABX_WI2S_MODE (1 << 7) -#define ATA_PABX_I2S_MODE (1 << 8) -#define CAML_LCDW_MODE (1 << 9) -#define CAMU_LCD_MODE (1 << 10) -#define CAMU_WLCD_MODE (1 << 11) -#define CAML_LCD_MODE (1 << 12) - -static struct spear_pmx_mode pmx_mode_nand = { - .name = "nand", - .mode = NAND_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x00, -}; - -static struct spear_pmx_mode pmx_mode_nor = { - .name = "nor", - .mode = NOR_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x01, -}; - -static struct spear_pmx_mode pmx_mode_photo_frame = { - .name = "photo frame mode", - .mode = PHOTO_FRAME_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x02, -}; - -static struct spear_pmx_mode pmx_mode_lend_ip_phone = { - .name = "lend ip phone mode", - .mode = LEND_IP_PHONE_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x03, -}; - -static struct spear_pmx_mode pmx_mode_hend_ip_phone = { - .name = "hend ip phone mode", - .mode = HEND_IP_PHONE_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x04, -}; - -static struct spear_pmx_mode pmx_mode_lend_wifi_phone = { - .name = "lend wifi phone mode", - .mode = LEND_WIFI_PHONE_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x05, -}; - -static struct spear_pmx_mode pmx_mode_hend_wifi_phone = { - .name = "hend wifi phone mode", - .mode = HEND_WIFI_PHONE_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x06, -}; - -static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = { - .name = "ata pabx wi2s mode", - .mode = ATA_PABX_WI2S_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x07, -}; - -static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = { - .name = "ata pabx i2s mode", - .mode = ATA_PABX_I2S_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x08, -}; - -static struct spear_pmx_mode pmx_mode_caml_lcdw = { - .name = "caml lcdw mode", - .mode = CAML_LCDW_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x0C, -}; - -static struct spear_pmx_mode pmx_mode_camu_lcd = { - .name = "camu lcd mode", - .mode = CAMU_LCD_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x0D, -}; - -static struct spear_pmx_mode pmx_mode_camu_wlcd = { - .name = "camu wlcd mode", - .mode = CAMU_WLCD_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0xE, -}; - -static struct spear_pmx_mode pmx_mode_caml_lcd = { - .name = "caml lcd mode", - .mode = CAML_LCD_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x0F, -}; - -static struct spear_pmx_mode *spear300_pmx_modes[] = { - &pmx_mode_nand, - &pmx_mode_nor, - &pmx_mode_photo_frame, - &pmx_mode_lend_ip_phone, - &pmx_mode_hend_ip_phone, - &pmx_mode_lend_wifi_phone, - &pmx_mode_hend_wifi_phone, - &pmx_mode_ata_pabx_wi2s, - &pmx_mode_ata_pabx_i2s, - &pmx_mode_caml_lcdw, - &pmx_mode_camu_lcd, - &pmx_mode_camu_wlcd, - &pmx_mode_caml_lcd, -}; - -/* fsmc_2chips_pins */ -static const unsigned fsmc_2chips_pins[] = { 1, 97 }; -static struct spear_muxreg fsmc_2chips_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK, - .val = 0, - }, -}; - -static struct spear_modemux fsmc_2chips_modemux[] = { - { - .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | - ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, - .muxregs = fsmc_2chips_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg), - }, -}; - -static struct spear_pingroup fsmc_2chips_pingroup = { - .name = "fsmc_2chips_grp", - .pins = fsmc_2chips_pins, - .npins = ARRAY_SIZE(fsmc_2chips_pins), - .modemuxs = fsmc_2chips_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux), -}; - -/* fsmc_4chips_pins */ -static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 }; -static struct spear_muxreg fsmc_4chips_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, - .val = 0, - }, -}; - -static struct spear_modemux fsmc_4chips_modemux[] = { - { - .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | - ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, - .muxregs = fsmc_4chips_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg), - }, -}; - -static struct spear_pingroup fsmc_4chips_pingroup = { - .name = "fsmc_4chips_grp", - .pins = fsmc_4chips_pins, - .npins = ARRAY_SIZE(fsmc_4chips_pins), - .modemuxs = fsmc_4chips_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux), -}; - -static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp" -}; -static struct spear_function fsmc_function = { - .name = "fsmc", - .groups = fsmc_grps, - .ngroups = ARRAY_SIZE(fsmc_grps), -}; - -/* clcd_lcdmode_pins */ -static const unsigned clcd_lcdmode_pins[] = { 49, 50 }; -static struct spear_muxreg clcd_lcdmode_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux clcd_lcdmode_modemux[] = { - { - .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | - CAMU_LCD_MODE | CAML_LCD_MODE, - .muxregs = clcd_lcdmode_muxreg, - .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg), - }, -}; - -static struct spear_pingroup clcd_lcdmode_pingroup = { - .name = "clcd_lcdmode_grp", - .pins = clcd_lcdmode_pins, - .npins = ARRAY_SIZE(clcd_lcdmode_pins), - .modemuxs = clcd_lcdmode_modemux, - .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux), -}; - -/* clcd_pfmode_pins */ -static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 }; -static struct spear_muxreg clcd_pfmode_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux clcd_pfmode_modemux[] = { - { - .modes = PHOTO_FRAME_MODE, - .muxregs = clcd_pfmode_muxreg, - .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg), - }, -}; - -static struct spear_pingroup clcd_pfmode_pingroup = { - .name = "clcd_pfmode_grp", - .pins = clcd_pfmode_pins, - .npins = ARRAY_SIZE(clcd_pfmode_pins), - .modemuxs = clcd_pfmode_modemux, - .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux), -}; - -static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp" -}; -static struct spear_function clcd_function = { - .name = "clcd", - .groups = clcd_grps, - .ngroups = ARRAY_SIZE(clcd_grps), -}; - -/* tdm_pins */ -static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 }; -static struct spear_muxreg tdm_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_modemux tdm_modemux[] = { - { - .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE - | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE - | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .muxregs = tdm_muxreg, - .nmuxregs = ARRAY_SIZE(tdm_muxreg), - }, -}; - -static struct spear_pingroup tdm_pingroup = { - .name = "tdm_grp", - .pins = tdm_pins, - .npins = ARRAY_SIZE(tdm_pins), - .modemuxs = tdm_modemux, - .nmodemuxs = ARRAY_SIZE(tdm_modemux), -}; - -static const char *const tdm_grps[] = { "tdm_grp" }; -static struct spear_function tdm_function = { - .name = "tdm", - .groups = tdm_grps, - .ngroups = ARRAY_SIZE(tdm_grps), -}; - -/* i2c_clk_pins */ -static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 }; -static struct spear_muxreg i2c_clk_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux i2c_clk_modemux[] = { - { - .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | - LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | - ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE - | CAML_LCD_MODE, - .muxregs = i2c_clk_muxreg, - .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg), - }, -}; - -static struct spear_pingroup i2c_clk_pingroup = { - .name = "i2c_clk_grp_grp", - .pins = i2c_clk_pins, - .npins = ARRAY_SIZE(i2c_clk_pins), - .modemuxs = i2c_clk_modemux, - .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux), -}; - -static const char *const i2c_grps[] = { "i2c_clk_grp" }; -static struct spear_function i2c_function = { - .name = "i2c1", - .groups = i2c_grps, - .ngroups = ARRAY_SIZE(i2c_grps), -}; - -/* caml_pins */ -static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 }; -static struct spear_muxreg caml_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux caml_modemux[] = { - { - .modes = CAML_LCDW_MODE | CAML_LCD_MODE, - .muxregs = caml_muxreg, - .nmuxregs = ARRAY_SIZE(caml_muxreg), - }, -}; - -static struct spear_pingroup caml_pingroup = { - .name = "caml_grp", - .pins = caml_pins, - .npins = ARRAY_SIZE(caml_pins), - .modemuxs = caml_modemux, - .nmodemuxs = ARRAY_SIZE(caml_modemux), -}; - -/* camu_pins */ -static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 }; -static struct spear_muxreg camu_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux camu_modemux[] = { - { - .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE, - .muxregs = camu_muxreg, - .nmuxregs = ARRAY_SIZE(camu_muxreg), - }, -}; - -static struct spear_pingroup camu_pingroup = { - .name = "camu_grp", - .pins = camu_pins, - .npins = ARRAY_SIZE(camu_pins), - .modemuxs = camu_modemux, - .nmodemuxs = ARRAY_SIZE(camu_modemux), -}; - -static const char *const cam_grps[] = { "caml_grp", "camu_grp" }; -static struct spear_function cam_function = { - .name = "cam", - .groups = cam_grps, - .ngroups = ARRAY_SIZE(cam_grps), -}; - -/* dac_pins */ -static const unsigned dac_pins[] = { 43, 44 }; -static struct spear_muxreg dac_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK, - .val = 0, - }, -}; - -static struct spear_modemux dac_modemux[] = { - { - .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .muxregs = dac_muxreg, - .nmuxregs = ARRAY_SIZE(dac_muxreg), - }, -}; - -static struct spear_pingroup dac_pingroup = { - .name = "dac_grp", - .pins = dac_pins, - .npins = ARRAY_SIZE(dac_pins), - .modemuxs = dac_modemux, - .nmodemuxs = ARRAY_SIZE(dac_modemux), -}; - -static const char *const dac_grps[] = { "dac_grp" }; -static struct spear_function dac_function = { - .name = "dac", - .groups = dac_grps, - .ngroups = ARRAY_SIZE(dac_grps), -}; - -/* i2s_pins */ -static const unsigned i2s_pins[] = { 39, 40, 41, 42 }; -static struct spear_muxreg i2s_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux i2s_modemux[] = { - { - .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE - | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | - ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .muxregs = i2s_muxreg, - .nmuxregs = ARRAY_SIZE(i2s_muxreg), - }, -}; - -static struct spear_pingroup i2s_pingroup = { - .name = "i2s_grp", - .pins = i2s_pins, - .npins = ARRAY_SIZE(i2s_pins), - .modemuxs = i2s_modemux, - .nmodemuxs = ARRAY_SIZE(i2s_modemux), -}; - -static const char *const i2s_grps[] = { "i2s_grp" }; -static struct spear_function i2s_function = { - .name = "i2s", - .groups = i2s_grps, - .ngroups = ARRAY_SIZE(i2s_grps), -}; - -/* sdhci_4bit_pins */ -static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 }; -static struct spear_muxreg sdhci_4bit_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | - PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | - PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, - .val = 0, - }, -}; - -static struct spear_modemux sdhci_4bit_modemux[] = { - { - .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | - HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | - CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE, - .muxregs = sdhci_4bit_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg), - }, -}; - -static struct spear_pingroup sdhci_4bit_pingroup = { - .name = "sdhci_4bit_grp", - .pins = sdhci_4bit_pins, - .npins = ARRAY_SIZE(sdhci_4bit_pins), - .modemuxs = sdhci_4bit_modemux, - .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux), -}; - -/* sdhci_8bit_pins */ -static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, - 33 }; -static struct spear_muxreg sdhci_8bit_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | - PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | - PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux sdhci_8bit_modemux[] = { - { - .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | - HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | - CAMU_WLCD_MODE | CAML_LCD_MODE, - .muxregs = sdhci_8bit_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg), - }, -}; - -static struct spear_pingroup sdhci_8bit_pingroup = { - .name = "sdhci_8bit_grp", - .pins = sdhci_8bit_pins, - .npins = ARRAY_SIZE(sdhci_8bit_pins), - .modemuxs = sdhci_8bit_modemux, - .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux), -}; - -static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" }; -static struct spear_function sdhci_function = { - .name = "sdhci", - .groups = sdhci_grps, - .ngroups = ARRAY_SIZE(sdhci_grps), -}; - -/* gpio1_0_to_3_pins */ -static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 }; -static struct spear_muxreg gpio1_0_to_3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux gpio1_0_to_3_modemux[] = { - { - .modes = PHOTO_FRAME_MODE, - .muxregs = gpio1_0_to_3_muxreg, - .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg), - }, -}; - -static struct spear_pingroup gpio1_0_to_3_pingroup = { - .name = "gpio1_0_to_3_grp", - .pins = gpio1_0_to_3_pins, - .npins = ARRAY_SIZE(gpio1_0_to_3_pins), - .modemuxs = gpio1_0_to_3_modemux, - .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux), -}; - -/* gpio1_4_to_7_pins */ -static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 }; - -static struct spear_muxreg gpio1_4_to_7_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux gpio1_4_to_7_modemux[] = { - { - .modes = PHOTO_FRAME_MODE, - .muxregs = gpio1_4_to_7_muxreg, - .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg), - }, -}; - -static struct spear_pingroup gpio1_4_to_7_pingroup = { - .name = "gpio1_4_to_7_grp", - .pins = gpio1_4_to_7_pins, - .npins = ARRAY_SIZE(gpio1_4_to_7_pins), - .modemuxs = gpio1_4_to_7_modemux, - .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux), -}; - -static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" -}; -static struct spear_function gpio1_function = { - .name = "gpio1", - .groups = gpio1_grps, - .ngroups = ARRAY_SIZE(gpio1_grps), -}; - -/* pingroups */ -static struct spear_pingroup *spear300_pingroups[] = { - SPEAR3XX_COMMON_PINGROUPS, - &fsmc_2chips_pingroup, - &fsmc_4chips_pingroup, - &clcd_lcdmode_pingroup, - &clcd_pfmode_pingroup, - &tdm_pingroup, - &i2c_clk_pingroup, - &caml_pingroup, - &camu_pingroup, - &dac_pingroup, - &i2s_pingroup, - &sdhci_4bit_pingroup, - &sdhci_8bit_pingroup, - &gpio1_0_to_3_pingroup, - &gpio1_4_to_7_pingroup, -}; - -/* functions */ -static struct spear_function *spear300_functions[] = { - SPEAR3XX_COMMON_FUNCTIONS, - &fsmc_function, - &clcd_function, - &tdm_function, - &i2c_function, - &cam_function, - &dac_function, - &i2s_function, - &sdhci_function, - &gpio1_function, -}; - -static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = { - { - .compatible = "st,spear300-pinmux", - }, - {}, -}; - -static int __devinit spear300_pinctrl_probe(struct platform_device *pdev) -{ - int ret; - - spear3xx_machdata.groups = spear300_pingroups; - spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups); - spear3xx_machdata.functions = spear300_functions; - spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions); - - spear3xx_machdata.modes_supported = true; - spear3xx_machdata.pmx_modes = spear300_pmx_modes; - spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes); - - pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); - - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; -} - -static int __devexit spear300_pinctrl_remove(struct platform_device *pdev) -{ - return spear_pinctrl_remove(pdev); -} - -static struct platform_driver spear300_pinctrl_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = spear300_pinctrl_of_match, - }, - .probe = spear300_pinctrl_probe, - .remove = __devexit_p(spear300_pinctrl_remove), -}; - -static int __init spear300_pinctrl_init(void) -{ - return platform_driver_register(&spear300_pinctrl_driver); -} -arch_initcall(spear300_pinctrl_init); - -static void __exit spear300_pinctrl_exit(void) -{ - platform_driver_unregister(&spear300_pinctrl_driver); -} -module_exit(spear300_pinctrl_exit); - -MODULE_AUTHOR("Viresh Kumar "); -MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear310.c b/trunk/drivers/pinctrl/spear/pinctrl-spear310.c deleted file mode 100644 index 1a9707605125..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear310.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr310 pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "pinctrl-spear3xx.h" - -#define DRIVER_NAME "spear310-pinmux" - -/* addresses */ -#define PMX_CONFIG_REG 0x08 - -/* emi_cs_0_to_5_pins */ -static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 }; -static struct spear_muxreg emi_cs_0_to_5_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux emi_cs_0_to_5_modemux[] = { - { - .muxregs = emi_cs_0_to_5_muxreg, - .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg), - }, -}; - -static struct spear_pingroup emi_cs_0_to_5_pingroup = { - .name = "emi_cs_0_to_5_grp", - .pins = emi_cs_0_to_5_pins, - .npins = ARRAY_SIZE(emi_cs_0_to_5_pins), - .modemuxs = emi_cs_0_to_5_modemux, - .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux), -}; - -static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" }; -static struct spear_function emi_cs_0_to_5_function = { - .name = "emi", - .groups = emi_cs_0_to_5_grps, - .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps), -}; - -/* uart1_pins */ -static const unsigned uart1_pins[] = { 0, 1 }; -static struct spear_muxreg uart1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart1_modemux[] = { - { - .muxregs = uart1_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_muxreg), - }, -}; - -static struct spear_pingroup uart1_pingroup = { - .name = "uart1_grp", - .pins = uart1_pins, - .npins = ARRAY_SIZE(uart1_pins), - .modemuxs = uart1_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modemux), -}; - -static const char *const uart1_grps[] = { "uart1_grp" }; -static struct spear_function uart1_function = { - .name = "uart1", - .groups = uart1_grps, - .ngroups = ARRAY_SIZE(uart1_grps), -}; - -/* uart2_pins */ -static const unsigned uart2_pins[] = { 43, 44 }; -static struct spear_muxreg uart2_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart2_modemux[] = { - { - .muxregs = uart2_muxreg, - .nmuxregs = ARRAY_SIZE(uart2_muxreg), - }, -}; - -static struct spear_pingroup uart2_pingroup = { - .name = "uart2_grp", - .pins = uart2_pins, - .npins = ARRAY_SIZE(uart2_pins), - .modemuxs = uart2_modemux, - .nmodemuxs = ARRAY_SIZE(uart2_modemux), -}; - -static const char *const uart2_grps[] = { "uart2_grp" }; -static struct spear_function uart2_function = { - .name = "uart2", - .groups = uart2_grps, - .ngroups = ARRAY_SIZE(uart2_grps), -}; - -/* uart3_pins */ -static const unsigned uart3_pins[] = { 37, 38 }; -static struct spear_muxreg uart3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart3_modemux[] = { - { - .muxregs = uart3_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_muxreg), - }, -}; - -static struct spear_pingroup uart3_pingroup = { - .name = "uart3_grp", - .pins = uart3_pins, - .npins = ARRAY_SIZE(uart3_pins), - .modemuxs = uart3_modemux, - .nmodemuxs = ARRAY_SIZE(uart3_modemux), -}; - -static const char *const uart3_grps[] = { "uart3_grp" }; -static struct spear_function uart3_function = { - .name = "uart3", - .groups = uart3_grps, - .ngroups = ARRAY_SIZE(uart3_grps), -}; - -/* uart4_pins */ -static const unsigned uart4_pins[] = { 39, 40 }; -static struct spear_muxreg uart4_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart4_modemux[] = { - { - .muxregs = uart4_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_muxreg), - }, -}; - -static struct spear_pingroup uart4_pingroup = { - .name = "uart4_grp", - .pins = uart4_pins, - .npins = ARRAY_SIZE(uart4_pins), - .modemuxs = uart4_modemux, - .nmodemuxs = ARRAY_SIZE(uart4_modemux), -}; - -static const char *const uart4_grps[] = { "uart4_grp" }; -static struct spear_function uart4_function = { - .name = "uart4", - .groups = uart4_grps, - .ngroups = ARRAY_SIZE(uart4_grps), -}; - -/* uart5_pins */ -static const unsigned uart5_pins[] = { 41, 42 }; -static struct spear_muxreg uart5_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart5_modemux[] = { - { - .muxregs = uart5_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_muxreg), - }, -}; - -static struct spear_pingroup uart5_pingroup = { - .name = "uart5_grp", - .pins = uart5_pins, - .npins = ARRAY_SIZE(uart5_pins), - .modemuxs = uart5_modemux, - .nmodemuxs = ARRAY_SIZE(uart5_modemux), -}; - -static const char *const uart5_grps[] = { "uart5_grp" }; -static struct spear_function uart5_function = { - .name = "uart5", - .groups = uart5_grps, - .ngroups = ARRAY_SIZE(uart5_grps), -}; - -/* fsmc_pins */ -static const unsigned fsmc_pins[] = { 34, 35, 36 }; -static struct spear_muxreg fsmc_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_modemux fsmc_modemux[] = { - { - .muxregs = fsmc_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_muxreg), - }, -}; - -static struct spear_pingroup fsmc_pingroup = { - .name = "fsmc_grp", - .pins = fsmc_pins, - .npins = ARRAY_SIZE(fsmc_pins), - .modemuxs = fsmc_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_modemux), -}; - -static const char *const fsmc_grps[] = { "fsmc_grp" }; -static struct spear_function fsmc_function = { - .name = "fsmc", - .groups = fsmc_grps, - .ngroups = ARRAY_SIZE(fsmc_grps), -}; - -/* rs485_0_pins */ -static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 }; -static struct spear_muxreg rs485_0_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux rs485_0_modemux[] = { - { - .muxregs = rs485_0_muxreg, - .nmuxregs = ARRAY_SIZE(rs485_0_muxreg), - }, -}; - -static struct spear_pingroup rs485_0_pingroup = { - .name = "rs485_0_grp", - .pins = rs485_0_pins, - .npins = ARRAY_SIZE(rs485_0_pins), - .modemuxs = rs485_0_modemux, - .nmodemuxs = ARRAY_SIZE(rs485_0_modemux), -}; - -static const char *const rs485_0_grps[] = { "rs485_0" }; -static struct spear_function rs485_0_function = { - .name = "rs485_0", - .groups = rs485_0_grps, - .ngroups = ARRAY_SIZE(rs485_0_grps), -}; - -/* rs485_1_pins */ -static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 }; -static struct spear_muxreg rs485_1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux rs485_1_modemux[] = { - { - .muxregs = rs485_1_muxreg, - .nmuxregs = ARRAY_SIZE(rs485_1_muxreg), - }, -}; - -static struct spear_pingroup rs485_1_pingroup = { - .name = "rs485_1_grp", - .pins = rs485_1_pins, - .npins = ARRAY_SIZE(rs485_1_pins), - .modemuxs = rs485_1_modemux, - .nmodemuxs = ARRAY_SIZE(rs485_1_modemux), -}; - -static const char *const rs485_1_grps[] = { "rs485_1" }; -static struct spear_function rs485_1_function = { - .name = "rs485_1", - .groups = rs485_1_grps, - .ngroups = ARRAY_SIZE(rs485_1_grps), -}; - -/* tdm_pins */ -static const unsigned tdm_pins[] = { 10, 11, 12, 13 }; -static struct spear_muxreg tdm_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux tdm_modemux[] = { - { - .muxregs = tdm_muxreg, - .nmuxregs = ARRAY_SIZE(tdm_muxreg), - }, -}; - -static struct spear_pingroup tdm_pingroup = { - .name = "tdm_grp", - .pins = tdm_pins, - .npins = ARRAY_SIZE(tdm_pins), - .modemuxs = tdm_modemux, - .nmodemuxs = ARRAY_SIZE(tdm_modemux), -}; - -static const char *const tdm_grps[] = { "tdm_grp" }; -static struct spear_function tdm_function = { - .name = "tdm", - .groups = tdm_grps, - .ngroups = ARRAY_SIZE(tdm_grps), -}; - -/* pingroups */ -static struct spear_pingroup *spear310_pingroups[] = { - SPEAR3XX_COMMON_PINGROUPS, - &emi_cs_0_to_5_pingroup, - &uart1_pingroup, - &uart2_pingroup, - &uart3_pingroup, - &uart4_pingroup, - &uart5_pingroup, - &fsmc_pingroup, - &rs485_0_pingroup, - &rs485_1_pingroup, - &tdm_pingroup, -}; - -/* functions */ -static struct spear_function *spear310_functions[] = { - SPEAR3XX_COMMON_FUNCTIONS, - &emi_cs_0_to_5_function, - &uart1_function, - &uart2_function, - &uart3_function, - &uart4_function, - &uart5_function, - &fsmc_function, - &rs485_0_function, - &rs485_1_function, - &tdm_function, -}; - -static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = { - { - .compatible = "st,spear310-pinmux", - }, - {}, -}; - -static int __devinit spear310_pinctrl_probe(struct platform_device *pdev) -{ - int ret; - - spear3xx_machdata.groups = spear310_pingroups; - spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups); - spear3xx_machdata.functions = spear310_functions; - spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions); - - pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); - - spear3xx_machdata.modes_supported = false; - - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; -} - -static int __devexit spear310_pinctrl_remove(struct platform_device *pdev) -{ - return spear_pinctrl_remove(pdev); -} - -static struct platform_driver spear310_pinctrl_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = spear310_pinctrl_of_match, - }, - .probe = spear310_pinctrl_probe, - .remove = __devexit_p(spear310_pinctrl_remove), -}; - -static int __init spear310_pinctrl_init(void) -{ - return platform_driver_register(&spear310_pinctrl_driver); -} -arch_initcall(spear310_pinctrl_init); - -static void __exit spear310_pinctrl_exit(void) -{ - platform_driver_unregister(&spear310_pinctrl_driver); -} -module_exit(spear310_pinctrl_exit); - -MODULE_AUTHOR("Viresh Kumar "); -MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear320.c b/trunk/drivers/pinctrl/spear/pinctrl-spear320.c deleted file mode 100644 index de726e6c283a..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear320.c +++ /dev/null @@ -1,3468 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr320 pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "pinctrl-spear3xx.h" - -#define DRIVER_NAME "spear320-pinmux" - -/* addresses */ -#define PMX_CONFIG_REG 0x0C -#define MODE_CONFIG_REG 0x10 -#define MODE_EXT_CONFIG_REG 0x18 - -/* modes */ -#define AUTO_NET_SMII_MODE (1 << 0) -#define AUTO_NET_MII_MODE (1 << 1) -#define AUTO_EXP_MODE (1 << 2) -#define SMALL_PRINTERS_MODE (1 << 3) -#define EXTENDED_MODE (1 << 4) - -static struct spear_pmx_mode pmx_mode_auto_net_smii = { - .name = "Automation Networking SMII mode", - .mode = AUTO_NET_SMII_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x00000007, - .val = 0x0, -}; - -static struct spear_pmx_mode pmx_mode_auto_net_mii = { - .name = "Automation Networking MII mode", - .mode = AUTO_NET_MII_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x00000007, - .val = 0x1, -}; - -static struct spear_pmx_mode pmx_mode_auto_exp = { - .name = "Automation Expanded mode", - .mode = AUTO_EXP_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x00000007, - .val = 0x2, -}; - -static struct spear_pmx_mode pmx_mode_small_printers = { - .name = "Small Printers mode", - .mode = SMALL_PRINTERS_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x00000007, - .val = 0x3, -}; - -static struct spear_pmx_mode pmx_mode_extended = { - .name = "extended mode", - .mode = EXTENDED_MODE, - .reg = MODE_EXT_CONFIG_REG, - .mask = 0x00000001, - .val = 0x1, -}; - -static struct spear_pmx_mode *spear320_pmx_modes[] = { - &pmx_mode_auto_net_smii, - &pmx_mode_auto_net_mii, - &pmx_mode_auto_exp, - &pmx_mode_small_printers, - &pmx_mode_extended, -}; - -/* Extended mode registers and their offsets */ -#define EXT_CTRL_REG 0x0018 - #define MII_MDIO_MASK (1 << 4) - #define MII_MDIO_10_11_VAL 0 - #define MII_MDIO_81_VAL (1 << 4) - #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5) - #define MAC_MODE_MII 0 - #define MAC_MODE_RMII 1 - #define MAC_MODE_SMII 2 - #define MAC_MODE_SS_SMII 3 - #define MAC_MODE_MASK 0x3 - #define MAC1_MODE_SHIFT 16 - #define MAC2_MODE_SHIFT 18 - -#define IP_SEL_PAD_0_9_REG 0x00A4 - #define PMX_PL_0_1_MASK (0x3F << 0) - #define PMX_UART2_PL_0_1_VAL 0x0 - #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3)) - - #define PMX_PL_2_3_MASK (0x3F << 6) - #define PMX_I2C2_PL_2_3_VAL 0x0 - #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9)) - #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9)) - - #define PMX_PL_4_5_MASK (0x3F << 12) - #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15)) - #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15)) - #define PMX_PL_5_MASK (0x7 << 15) - #define PMX_TOUCH_Y_PL_5_VAL 0x0 - - #define PMX_PL_6_7_MASK (0x3F << 18) - #define PMX_PL_6_MASK (0x7 << 18) - #define PMX_PL_7_MASK (0x7 << 21) - #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21)) - #define PMX_PWM_3_PL_6_VAL (0x2 << 18) - #define PMX_PWM_2_PL_7_VAL (0x2 << 21) - #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21)) - - #define PMX_PL_8_9_MASK (0x3F << 24) - #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27)) - #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27)) - #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27)) - -#define IP_SEL_PAD_10_19_REG 0x00A8 - #define PMX_PL_10_11_MASK (0x3F << 0) - #define PMX_SMII_PL_10_11_VAL 0 - #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3)) - - #define PMX_PL_12_MASK (0x7 << 6) - #define PMX_PWM3_PL_12_VAL 0 - #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6) - - #define PMX_PL_13_14_MASK (0x3F << 9) - #define PMX_PL_13_MASK (0x7 << 9) - #define PMX_PL_14_MASK (0x7 << 12) - #define PMX_SSP2_PL_13_14_15_16_VAL 0 - #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12)) - #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12)) - #define PMX_PWM2_PL_13_VAL (0x2 << 9) - #define PMX_PWM1_PL_14_VAL (0x2 << 12) - - #define PMX_PL_15_MASK (0x7 << 15) - #define PMX_PWM0_PL_15_VAL (0x2 << 15) - #define PMX_PL_15_16_MASK (0x3F << 15) - #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18)) - #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18)) - - #define PMX_PL_17_18_MASK (0x3F << 21) - #define PMX_SSP1_PL_17_18_19_20_VAL 0 - #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24)) - - #define PMX_PL_19_MASK (0x7 << 27) - #define PMX_I2C2_PL_19_VAL (0x1 << 27) - #define PMX_RMII_PL_19_VAL (0x4 << 27) - -#define IP_SEL_PAD_20_29_REG 0x00AC - #define PMX_PL_20_MASK (0x7 << 0) - #define PMX_I2C2_PL_20_VAL (0x1 << 0) - #define PMX_RMII_PL_20_VAL (0x4 << 0) - - #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3) - #define PMX_SMII_PL_21_TO_27_VAL 0 - #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21)) - - #define PMX_PL_28_29_MASK (0x3F << 24) - #define PMX_PL_28_MASK (0x7 << 24) - #define PMX_PL_29_MASK (0x7 << 27) - #define PMX_UART1_PL_28_29_VAL 0 - #define PMX_PWM_3_PL_28_VAL (0x4 << 24) - #define PMX_PWM_2_PL_29_VAL (0x4 << 27) - -#define IP_SEL_PAD_30_39_REG 0x00B0 - #define PMX_PL_30_31_MASK (0x3F << 0) - #define PMX_CAN1_PL_30_31_VAL (0) - #define PMX_PL_30_MASK (0x7 << 0) - #define PMX_PL_31_MASK (0x7 << 3) - #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0) - #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3) - #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3) - - #define PMX_PL_32_33_MASK (0x3F << 6) - #define PMX_CAN0_PL_32_33_VAL 0 - #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9)) - #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9)) - - #define PMX_PL_34_MASK (0x7 << 12) - #define PMX_PWM2_PL_34_VAL 0 - #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12) - #define PMX_SSP2_PL_34_VAL (0x4 << 12) - - #define PMX_PL_35_MASK (0x7 << 15) - #define PMX_I2S_REF_CLK_PL_35_VAL 0 - #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15) - #define PMX_SSP2_PL_35_VAL (0x4 << 15) - - #define PMX_PL_36_MASK (0x7 << 18) - #define PMX_TOUCH_X_PL_36_VAL 0 - #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18) - #define PMX_SSP1_PL_36_VAL (0x4 << 18) - - #define PMX_PL_37_38_MASK (0x3F << 21) - #define PMX_PWM0_1_PL_37_38_VAL 0 - #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24)) - #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24)) - - #define PMX_PL_39_MASK (0x7 << 27) - #define PMX_I2S_PL_39_VAL 0 - #define PMX_UART4_PL_39_VAL (0x2 << 27) - #define PMX_SSP1_PL_39_VAL (0x4 << 27) - -#define IP_SEL_PAD_40_49_REG 0x00B4 - #define PMX_PL_40_MASK (0x7 << 0) - #define PMX_I2S_PL_40_VAL 0 - #define PMX_UART4_PL_40_VAL (0x2 << 0) - #define PMX_PWM3_PL_40_VAL (0x4 << 0) - - #define PMX_PL_41_42_MASK (0x3F << 3) - #define PMX_PL_41_MASK (0x7 << 3) - #define PMX_PL_42_MASK (0x7 << 6) - #define PMX_I2S_PL_41_42_VAL 0 - #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6)) - #define PMX_PWM2_PL_41_VAL (0x4 << 3) - #define PMX_PWM1_PL_42_VAL (0x4 << 6) - - #define PMX_PL_43_MASK (0x7 << 9) - #define PMX_SDHCI_PL_43_VAL 0 - #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9) - #define PMX_PWM0_PL_43_VAL (0x4 << 9) - - #define PMX_PL_44_45_MASK (0x3F << 12) - #define PMX_SDHCI_PL_44_45_VAL 0 - #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15)) - #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15)) - - #define PMX_PL_46_47_MASK (0x3F << 18) - #define PMX_SDHCI_PL_46_47_VAL 0 - #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21)) - #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21)) - - #define PMX_PL_48_49_MASK (0x3F << 24) - #define PMX_SDHCI_PL_48_49_VAL 0 - #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27)) - #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27)) - -#define IP_SEL_PAD_50_59_REG 0x00B8 - #define PMX_PL_50_51_MASK (0x3F << 0) - #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3)) - #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3)) - #define PMX_PL_50_MASK (0x7 << 0) - #define PMX_PL_51_MASK (0x7 << 3) - #define PMX_SDHCI_PL_50_VAL 0 - #define PMX_SDHCI_CD_PL_51_VAL 0 - - #define PMX_PL_52_53_MASK (0x3F << 6) - #define PMX_FSMC_PL_52_53_VAL 0 - #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9)) - #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9)) - - #define PMX_PL_54_55_56_MASK (0x1FF << 12) - #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18)) - - #define PMX_PL_57_MASK (0x7 << 21) - #define PMX_FSMC_PL_57_VAL 0 - #define PMX_PWM3_PL_57_VAL (0x4 << 21) - - #define PMX_PL_58_59_MASK (0x3F << 24) - #define PMX_PL_58_MASK (0x7 << 24) - #define PMX_PL_59_MASK (0x7 << 27) - #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27)) - #define PMX_PWM2_PL_58_VAL (0x4 << 24) - #define PMX_PWM1_PL_59_VAL (0x4 << 27) - -#define IP_SEL_PAD_60_69_REG 0x00BC - #define PMX_PL_60_MASK (0x7 << 0) - #define PMX_FSMC_PL_60_VAL 0 - #define PMX_PWM0_PL_60_VAL (0x4 << 0) - - #define PMX_PL_61_TO_64_MASK (0xFFF << 3) - #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12)) - #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12)) - - #define PMX_PL_65_TO_68_MASK (0xFFF << 15) - #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24)) - #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24)) - - #define PMX_PL_69_MASK (0x7 << 27) - #define PMX_CLCD_PL_69_VAL (0) - #define PMX_EMI_PL_69_VAL (0x2 << 27) - #define PMX_SPP_PL_69_VAL (0x3 << 27) - #define PMX_UART5_PL_69_VAL (0x4 << 27) - -#define IP_SEL_PAD_70_79_REG 0x00C0 - #define PMX_PL_70_MASK (0x7 << 0) - #define PMX_CLCD_PL_70_VAL (0) - #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0) - #define PMX_SPP_PL_70_VAL (0x3 << 0) - #define PMX_UART5_PL_70_VAL (0x4 << 0) - - #define PMX_PL_71_72_MASK (0x3F << 3) - #define PMX_CLCD_PL_71_72_VAL (0) - #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6)) - #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6)) - #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6)) - - #define PMX_PL_73_MASK (0x7 << 9) - #define PMX_CLCD_PL_73_VAL (0) - #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9) - #define PMX_SPP_PL_73_VAL (0x3 << 9) - #define PMX_UART3_PL_73_VAL (0x4 << 9) - - #define PMX_PL_74_MASK (0x7 << 12) - #define PMX_CLCD_PL_74_VAL (0) - #define PMX_EMI_PL_74_VAL (0x2 << 12) - #define PMX_SPP_PL_74_VAL (0x3 << 12) - #define PMX_UART3_PL_74_VAL (0x4 << 12) - - #define PMX_PL_75_76_MASK (0x3F << 15) - #define PMX_CLCD_PL_75_76_VAL (0) - #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18)) - #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18)) - #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18)) - - #define PMX_PL_77_78_79_MASK (0x1FF << 21) - #define PMX_CLCD_PL_77_78_79_VAL (0) - #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27)) - #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27)) - #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27)) - -#define IP_SEL_PAD_80_89_REG 0x00C4 - #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0) - #define PMX_CLCD_PL_80_TO_85_VAL 0 - #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15)) - #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15)) - #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15)) - #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15)) - - #define PMX_PL_86_87_MASK (0x3F << 18) - #define PMX_PL_86_MASK (0x7 << 18) - #define PMX_PL_87_MASK (0x7 << 21) - #define PMX_CLCD_PL_86_87_VAL 0 - #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21)) - #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21)) - #define PMX_PWM3_PL_86_VAL (0x4 << 18) - #define PMX_PWM2_PL_87_VAL (0x4 << 21) - - #define PMX_PL_88_89_MASK (0x3F << 24) - #define PMX_CLCD_PL_88_89_VAL 0 - #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27)) - #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27)) - #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27)) - #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27)) - -#define IP_SEL_PAD_90_99_REG 0x00C8 - #define PMX_PL_90_91_MASK (0x3F << 0) - #define PMX_CLCD_PL_90_91_VAL 0 - #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3)) - #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3)) - #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3)) - #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3)) - - #define PMX_PL_92_93_MASK (0x3F << 6) - #define PMX_CLCD_PL_92_93_VAL 0 - #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9)) - #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9)) - #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9)) - #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9)) - - #define PMX_PL_94_95_MASK (0x3F << 12) - #define PMX_CLCD_PL_94_95_VAL 0 - #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15)) - #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15)) - #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15)) - #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15)) - - #define PMX_PL_96_97_MASK (0x3F << 18) - #define PMX_CLCD_PL_96_97_VAL 0 - #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21)) - #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21)) - #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21)) - #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21)) - - #define PMX_PL_98_MASK (0x7 << 24) - #define PMX_CLCD_PL_98_VAL 0 - #define PMX_I2C1_PL_98_VAL (0x2 << 24) - #define PMX_UART3_PL_98_VAL (0x4 << 24) - - #define PMX_PL_99_MASK (0x7 << 27) - #define PMX_SDHCI_PL_99_VAL 0 - #define PMX_I2C1_PL_99_VAL (0x2 << 27) - #define PMX_UART3_PL_99_VAL (0x4 << 27) - -#define IP_SEL_MIX_PAD_REG 0x00CC - #define PMX_PL_100_101_MASK (0x3F << 0) - #define PMX_SDHCI_PL_100_101_VAL 0 - #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3)) - - #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8) - #define PMX_SSP1_PORT_94_TO_97_VAL 0 - #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8) - #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8) - #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8) - #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8) - - #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11) - #define PMX_SSP2_PORT_90_TO_93_VAL 0 - #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11) - #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11) - #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11) - #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11) - - #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14) - #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0 - #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14) - #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14) - #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14) - - #define PMX_UART3_PORT_SEL_MASK (0x7 << 16) - #define PMX_UART3_PORT_94_VAL 0 - #define PMX_UART3_PORT_73_VAL (0x1 << 16) - #define PMX_UART3_PORT_52_VAL (0x2 << 16) - #define PMX_UART3_PORT_41_VAL (0x3 << 16) - #define PMX_UART3_PORT_15_VAL (0x4 << 16) - #define PMX_UART3_PORT_8_VAL (0x5 << 16) - #define PMX_UART3_PORT_99_VAL (0x6 << 16) - - #define PMX_UART4_PORT_SEL_MASK (0x7 << 19) - #define PMX_UART4_PORT_92_VAL 0 - #define PMX_UART4_PORT_71_VAL (0x1 << 19) - #define PMX_UART4_PORT_39_VAL (0x2 << 19) - #define PMX_UART4_PORT_13_VAL (0x3 << 19) - #define PMX_UART4_PORT_6_VAL (0x4 << 19) - #define PMX_UART4_PORT_101_VAL (0x5 << 19) - - #define PMX_UART5_PORT_SEL_MASK (0x3 << 22) - #define PMX_UART5_PORT_90_VAL 0 - #define PMX_UART5_PORT_69_VAL (0x1 << 22) - #define PMX_UART5_PORT_37_VAL (0x2 << 22) - #define PMX_UART5_PORT_4_VAL (0x3 << 22) - - #define PMX_UART6_PORT_SEL_MASK (0x1 << 24) - #define PMX_UART6_PORT_88_VAL 0 - #define PMX_UART6_PORT_2_VAL (0x1 << 24) - - #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25) - #define PMX_I2C1_PORT_8_9_VAL 0 - #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25) - - #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26) - #define PMX_I2C2_PORT_96_97_VAL 0 - #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26) - #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26) - #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26) - #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26) - - #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29) - #define PMX_SDHCI_CD_PORT_12_VAL 0 - #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29) - -/* Pad multiplexing for CLCD device */ -static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, - 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, - 97 }; -static struct spear_muxreg clcd_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_69_MASK, - .val = PMX_CLCD_PL_69_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | - PMX_PL_74_MASK | PMX_PL_75_76_MASK | - PMX_PL_77_78_79_MASK, - .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL | - PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL | - PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL, - }, { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | - PMX_PL_88_89_MASK, - .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL | - PMX_CLCD_PL_88_89_VAL, - }, { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | - PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK, - .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL | - PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL | - PMX_CLCD_PL_98_VAL, - }, -}; - -static struct spear_modemux clcd_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = clcd_muxreg, - .nmuxregs = ARRAY_SIZE(clcd_muxreg), - }, -}; - -static struct spear_pingroup clcd_pingroup = { - .name = "clcd_grp", - .pins = clcd_pins, - .npins = ARRAY_SIZE(clcd_pins), - .modemuxs = clcd_modemux, - .nmodemuxs = ARRAY_SIZE(clcd_modemux), -}; - -static const char *const clcd_grps[] = { "clcd_grp" }; -static struct spear_function clcd_function = { - .name = "clcd", - .groups = clcd_grps, - .ngroups = ARRAY_SIZE(clcd_grps), -}; - -/* Pad multiplexing for EMI (Parallel NOR flash) device */ -static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, - 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, - 93, 94, 95, 96, 97 }; -static struct spear_muxreg emi_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg emi_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, - .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, - }, { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK | - PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK, - .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL | - PMX_FSMC_EMI_PL_54_55_56_VAL | - PMX_FSMC_EMI_PL_58_59_VAL, - }, { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_69_MASK, - .val = PMX_EMI_PL_69_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | - PMX_PL_74_MASK | PMX_PL_75_76_MASK | - PMX_PL_77_78_79_MASK, - .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | - PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL | - PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL, - }, { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | - PMX_PL_88_89_MASK, - .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL | - PMX_EMI_PL_88_89_VAL, - }, { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | - PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, - .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL | - PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = EMI_FSMC_DYNAMIC_MUX_MASK, - .val = EMI_FSMC_DYNAMIC_MUX_MASK, - }, -}; - -static struct spear_modemux emi_modemux[] = { - { - .modes = AUTO_EXP_MODE | EXTENDED_MODE, - .muxregs = emi_muxreg, - .nmuxregs = ARRAY_SIZE(emi_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = emi_ext_muxreg, - .nmuxregs = ARRAY_SIZE(emi_ext_muxreg), - }, -}; - -static struct spear_pingroup emi_pingroup = { - .name = "emi_grp", - .pins = emi_pins, - .npins = ARRAY_SIZE(emi_pins), - .modemuxs = emi_modemux, - .nmodemuxs = ARRAY_SIZE(emi_modemux), -}; - -static const char *const emi_grps[] = { "emi_grp" }; -static struct spear_function emi_function = { - .name = "emi", - .groups = emi_grps, - .ngroups = ARRAY_SIZE(emi_grps), -}; - -/* Pad multiplexing for FSMC (NAND flash) device */ -static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60, - 61, 62, 63, 64, 65, 66, 67, 68 }; -static struct spear_muxreg fsmc_8bit_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK | - PMX_PL_57_MASK | PMX_PL_58_59_MASK, - .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL | - PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL, - }, { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK | - PMX_PL_65_TO_68_MASK, - .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL | - PMX_FSMC_PL_65_TO_68_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = EMI_FSMC_DYNAMIC_MUX_MASK, - .val = EMI_FSMC_DYNAMIC_MUX_MASK, - }, -}; - -static struct spear_modemux fsmc_8bit_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = fsmc_8bit_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), - }, -}; - -static struct spear_pingroup fsmc_8bit_pingroup = { - .name = "fsmc_8bit_grp", - .pins = fsmc_8bit_pins, - .npins = ARRAY_SIZE(fsmc_8bit_pins), - .modemuxs = fsmc_8bit_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), -}; - -static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 }; -static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg fsmc_16bit_muxreg[] = { - { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, - .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK, - .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | - PMX_FSMC_EMI_PL_73_VAL, - } -}; - -static struct spear_modemux fsmc_16bit_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = fsmc_8bit_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), - }, { - .modes = AUTO_EXP_MODE | EXTENDED_MODE, - .muxregs = fsmc_16bit_autoexp_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = fsmc_16bit_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), - }, -}; - -static struct spear_pingroup fsmc_16bit_pingroup = { - .name = "fsmc_16bit_grp", - .pins = fsmc_16bit_pins, - .npins = ARRAY_SIZE(fsmc_16bit_pins), - .modemuxs = fsmc_16bit_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), -}; - -static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" }; -static struct spear_function fsmc_function = { - .name = "fsmc", - .groups = fsmc_grps, - .ngroups = ARRAY_SIZE(fsmc_grps), -}; - -/* Pad multiplexing for SPP device */ -static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, - 80, 81, 82, 83, 84, 85 }; -static struct spear_muxreg spp_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_69_MASK, - .val = PMX_SPP_PL_69_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | - PMX_PL_74_MASK | PMX_PL_75_76_MASK | - PMX_PL_77_78_79_MASK, - .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL | - PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL | - PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL, - }, { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK, - .val = PMX_SPP_PL_80_TO_85_VAL, - }, -}; - -static struct spear_modemux spp_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = spp_muxreg, - .nmuxregs = ARRAY_SIZE(spp_muxreg), - }, -}; - -static struct spear_pingroup spp_pingroup = { - .name = "spp_grp", - .pins = spp_pins, - .npins = ARRAY_SIZE(spp_pins), - .modemuxs = spp_modemux, - .nmodemuxs = ARRAY_SIZE(spp_modemux), -}; - -static const char *const spp_grps[] = { "spp_grp" }; -static struct spear_function spp_function = { - .name = "spp", - .groups = spp_grps, - .ngroups = ARRAY_SIZE(spp_grps), -}; - -/* Pad multiplexing for SDHCI device */ -static const unsigned sdhci_led_pins[] = { 34 }; -static struct spear_muxreg sdhci_led_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg sdhci_led_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_34_MASK, - .val = PMX_PWM2_PL_34_VAL, - }, -}; - -static struct spear_modemux sdhci_led_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, - .muxregs = sdhci_led_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = sdhci_led_ext_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg), - }, -}; - -static struct spear_pingroup sdhci_led_pingroup = { - .name = "sdhci_led_grp", - .pins = sdhci_led_pins, - .npins = ARRAY_SIZE(sdhci_led_pins), - .modemuxs = sdhci_led_modemux, - .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux), -}; - -static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49, - 50}; -static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51 -}; -static struct spear_muxreg sdhci_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg sdhci_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK | - PMX_PL_48_49_MASK, - .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL | - PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL, - }, { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_50_MASK, - .val = PMX_SDHCI_PL_50_VAL, - }, { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_99_MASK, - .val = PMX_SDHCI_PL_99_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_PL_100_101_MASK, - .val = PMX_SDHCI_PL_100_101_VAL, - }, -}; - -static struct spear_muxreg sdhci_cd_12_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_12_MASK, - .val = PMX_SDHCI_CD_PL_12_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SDHCI_CD_PORT_SEL_MASK, - .val = PMX_SDHCI_CD_PORT_12_VAL, - }, -}; - -static struct spear_muxreg sdhci_cd_51_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_51_MASK, - .val = PMX_SDHCI_CD_PL_51_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SDHCI_CD_PORT_SEL_MASK, - .val = PMX_SDHCI_CD_PORT_51_VAL, - }, -}; - -#define pmx_sdhci_common_modemux \ - { \ - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \ - SMALL_PRINTERS_MODE | EXTENDED_MODE, \ - .muxregs = sdhci_muxreg, \ - .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \ - }, { \ - .modes = EXTENDED_MODE, \ - .muxregs = sdhci_ext_muxreg, \ - .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \ - } - -static struct spear_modemux sdhci_modemux[][3] = { - { - /* select pin 12 for cd */ - pmx_sdhci_common_modemux, - { - .modes = EXTENDED_MODE, - .muxregs = sdhci_cd_12_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg), - }, - }, { - /* select pin 51 for cd */ - pmx_sdhci_common_modemux, - { - .modes = EXTENDED_MODE, - .muxregs = sdhci_cd_51_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg), - }, - } -}; - -static struct spear_pingroup sdhci_pingroup[] = { - { - .name = "sdhci_cd_12_grp", - .pins = sdhci_cd_12_pins, - .npins = ARRAY_SIZE(sdhci_cd_12_pins), - .modemuxs = sdhci_modemux[0], - .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]), - }, { - .name = "sdhci_cd_51_grp", - .pins = sdhci_cd_51_pins, - .npins = ARRAY_SIZE(sdhci_cd_51_pins), - .modemuxs = sdhci_modemux[1], - .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]), - }, -}; - -static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp", - "sdhci_led_grp" }; - -static struct spear_function sdhci_function = { - .name = "sdhci", - .groups = sdhci_grps, - .ngroups = ARRAY_SIZE(sdhci_grps), -}; - -/* Pad multiplexing for I2S device */ -static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 }; -static struct spear_muxreg i2s_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg i2s_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_35_MASK | PMX_PL_39_MASK, - .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK, - .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL, - }, -}; - -static struct spear_modemux i2s_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, - .muxregs = i2s_muxreg, - .nmuxregs = ARRAY_SIZE(i2s_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = i2s_ext_muxreg, - .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg), - }, -}; - -static struct spear_pingroup i2s_pingroup = { - .name = "i2s_grp", - .pins = i2s_pins, - .npins = ARRAY_SIZE(i2s_pins), - .modemuxs = i2s_modemux, - .nmodemuxs = ARRAY_SIZE(i2s_modemux), -}; - -static const char *const i2s_grps[] = { "i2s_grp" }; -static struct spear_function i2s_function = { - .name = "i2s", - .groups = i2s_grps, - .ngroups = ARRAY_SIZE(i2s_grps), -}; - -/* Pad multiplexing for UART1 device */ -static const unsigned uart1_pins[] = { 28, 29 }; -static struct spear_muxreg uart1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg uart1_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_28_29_MASK, - .val = PMX_UART1_PL_28_29_VAL, - }, -}; - -static struct spear_modemux uart1_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE - | SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = uart1_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = uart1_ext_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg), - }, -}; - -static struct spear_pingroup uart1_pingroup = { - .name = "uart1_grp", - .pins = uart1_pins, - .npins = ARRAY_SIZE(uart1_pins), - .modemuxs = uart1_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modemux), -}; - -static const char *const uart1_grps[] = { "uart1_grp" }; -static struct spear_function uart1_function = { - .name = "uart1", - .groups = uart1_grps, - .ngroups = ARRAY_SIZE(uart1_grps), -}; - -/* Pad multiplexing for UART1 Modem device */ -static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 }; -static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 }; -static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 }; -static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 }; - -static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK, - .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL | - PMX_UART1_ENH_PL_6_7_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART1_ENH_PORT_SEL_MASK, - .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL, - }, -}; - -static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | - PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK | - PMX_PL_35_MASK | PMX_PL_36_MASK, - .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL | - PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | - PMX_UART1_ENH_PL_36_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART1_ENH_PORT_SEL_MASK, - .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL, - }, -}; - -static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | - PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK, - .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | - PMX_UART1_ENH_PL_36_VAL, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, - .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART1_ENH_PORT_SEL_MASK, - .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL, - }, -}; - -static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK, - .val = PMX_UART1_ENH_PL_80_TO_85_VAL, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, - .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART1_ENH_PORT_SEL_MASK, - .val = PMX_UART1_ENH_PORT_81_TO_85_VAL, - }, -}; - -static struct spear_modemux uart1_modem_2_to_7_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = uart1_modem_ext_2_to_7_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg), - }, -}; - -static struct spear_modemux uart1_modem_31_to_36_modemux[] = { - { - .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = uart1_modem_31_to_36_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = uart1_modem_ext_31_to_36_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg), - }, -}; - -static struct spear_modemux uart1_modem_34_to_45_modemux[] = { - { - .modes = AUTO_EXP_MODE | EXTENDED_MODE, - .muxregs = uart1_modem_34_to_45_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = uart1_modem_ext_34_to_45_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg), - }, -}; - -static struct spear_modemux uart1_modem_80_to_85_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = uart1_modem_ext_80_to_85_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg), - }, -}; - -static struct spear_pingroup uart1_modem_pingroup[] = { - { - .name = "uart1_modem_2_to_7_grp", - .pins = uart1_modem_2_to_7_pins, - .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins), - .modemuxs = uart1_modem_2_to_7_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux), - }, { - .name = "uart1_modem_31_to_36_grp", - .pins = uart1_modem_31_to_36_pins, - .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins), - .modemuxs = uart1_modem_31_to_36_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux), - }, { - .name = "uart1_modem_34_to_45_grp", - .pins = uart1_modem_34_to_45_pins, - .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins), - .modemuxs = uart1_modem_34_to_45_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux), - }, { - .name = "uart1_modem_80_to_85_grp", - .pins = uart1_modem_80_to_85_pins, - .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins), - .modemuxs = uart1_modem_80_to_85_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux), - }, -}; - -static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp", - "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp", - "uart1_modem_80_to_85_grp" }; -static struct spear_function uart1_modem_function = { - .name = "uart1_modem", - .groups = uart1_modem_grps, - .ngroups = ARRAY_SIZE(uart1_modem_grps), -}; - -/* Pad multiplexing for UART2 device */ -static const unsigned uart2_pins[] = { 0, 1 }; -static struct spear_muxreg uart2_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg uart2_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_0_1_MASK, - .val = PMX_UART2_PL_0_1_VAL, - }, -}; - -static struct spear_modemux uart2_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE - | SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = uart2_muxreg, - .nmuxregs = ARRAY_SIZE(uart2_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = uart2_ext_muxreg, - .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg), - }, -}; - -static struct spear_pingroup uart2_pingroup = { - .name = "uart2_grp", - .pins = uart2_pins, - .npins = ARRAY_SIZE(uart2_pins), - .modemuxs = uart2_modemux, - .nmodemuxs = ARRAY_SIZE(uart2_modemux), -}; - -static const char *const uart2_grps[] = { "uart2_grp" }; -static struct spear_function uart2_function = { - .name = "uart2", - .groups = uart2_grps, - .ngroups = ARRAY_SIZE(uart2_grps), -}; - -/* Pad multiplexing for uart3 device */ -static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 }, - { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } }; - -static struct spear_muxreg uart3_ext_8_9_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_8_9_MASK, - .val = PMX_UART3_PL_8_9_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_8_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_15_16_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_15_16_MASK, - .val = PMX_UART3_PL_15_16_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_15_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_41_42_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_41_42_MASK, - .val = PMX_UART3_PL_41_42_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_41_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_52_53_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_52_53_MASK, - .val = PMX_UART3_PL_52_53_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_52_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_73_74_muxreg[] = { - { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_73_MASK | PMX_PL_74_MASK, - .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_73_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_94_95_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_94_95_MASK, - .val = PMX_UART3_PL_94_95_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_94_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_98_99_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, - .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_99_VAL, - }, -}; - -static struct spear_modemux uart3_modemux[][1] = { - { - /* Select signals on pins 8_9 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_8_9_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg), - }, - }, { - /* Select signals on pins 15_16 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_15_16_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg), - }, - }, { - /* Select signals on pins 41_42 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_41_42_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg), - }, - }, { - /* Select signals on pins 52_53 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_52_53_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg), - }, - }, { - /* Select signals on pins 73_74 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_73_74_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg), - }, - }, { - /* Select signals on pins 94_95 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_94_95_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg), - }, - }, { - /* Select signals on pins 98_99 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_98_99_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg), - }, - }, -}; - -static struct spear_pingroup uart3_pingroup[] = { - { - .name = "uart3_8_9_grp", - .pins = uart3_pins[0], - .npins = ARRAY_SIZE(uart3_pins[0]), - .modemuxs = uart3_modemux[0], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]), - }, { - .name = "uart3_15_16_grp", - .pins = uart3_pins[1], - .npins = ARRAY_SIZE(uart3_pins[1]), - .modemuxs = uart3_modemux[1], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]), - }, { - .name = "uart3_41_42_grp", - .pins = uart3_pins[2], - .npins = ARRAY_SIZE(uart3_pins[2]), - .modemuxs = uart3_modemux[2], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]), - }, { - .name = "uart3_52_53_grp", - .pins = uart3_pins[3], - .npins = ARRAY_SIZE(uart3_pins[3]), - .modemuxs = uart3_modemux[3], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]), - }, { - .name = "uart3_73_74_grp", - .pins = uart3_pins[4], - .npins = ARRAY_SIZE(uart3_pins[4]), - .modemuxs = uart3_modemux[4], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]), - }, { - .name = "uart3_94_95_grp", - .pins = uart3_pins[5], - .npins = ARRAY_SIZE(uart3_pins[5]), - .modemuxs = uart3_modemux[5], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]), - }, { - .name = "uart3_98_99_grp", - .pins = uart3_pins[6], - .npins = ARRAY_SIZE(uart3_pins[6]), - .modemuxs = uart3_modemux[6], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]), - }, -}; - -static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp", - "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp", - "uart3_94_95_grp", "uart3_98_99_grp" }; - -static struct spear_function uart3_function = { - .name = "uart3", - .groups = uart3_grps, - .ngroups = ARRAY_SIZE(uart3_grps), -}; - -/* Pad multiplexing for uart4 device */ -static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 }, - { 71, 72 }, { 92, 93 }, { 100, 101 } }; - -static struct spear_muxreg uart4_ext_6_7_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_6_7_MASK, - .val = PMX_UART4_PL_6_7_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_6_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_13_14_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_13_14_MASK, - .val = PMX_UART4_PL_13_14_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_13_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_39_40_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_39_MASK, - .val = PMX_UART4_PL_39_VAL, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_40_MASK, - .val = PMX_UART4_PL_40_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_39_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_71_72_muxreg[] = { - { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_71_72_MASK, - .val = PMX_UART4_PL_71_72_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_71_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_92_93_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_92_93_MASK, - .val = PMX_UART4_PL_92_93_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_92_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_100_101_muxreg[] = { - { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_PL_100_101_MASK | - PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PL_100_101_VAL | - PMX_UART4_PORT_101_VAL, - }, -}; - -static struct spear_modemux uart4_modemux[][1] = { - { - /* Select signals on pins 6_7 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_6_7_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg), - }, - }, { - /* Select signals on pins 13_14 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_13_14_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg), - }, - }, { - /* Select signals on pins 39_40 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_39_40_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg), - }, - }, { - /* Select signals on pins 71_72 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_71_72_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg), - }, - }, { - /* Select signals on pins 92_93 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_92_93_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg), - }, - }, { - /* Select signals on pins 100_101_ */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_100_101_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg), - }, - }, -}; - -static struct spear_pingroup uart4_pingroup[] = { - { - .name = "uart4_6_7_grp", - .pins = uart4_pins[0], - .npins = ARRAY_SIZE(uart4_pins[0]), - .modemuxs = uart4_modemux[0], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]), - }, { - .name = "uart4_13_14_grp", - .pins = uart4_pins[1], - .npins = ARRAY_SIZE(uart4_pins[1]), - .modemuxs = uart4_modemux[1], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]), - }, { - .name = "uart4_39_40_grp", - .pins = uart4_pins[2], - .npins = ARRAY_SIZE(uart4_pins[2]), - .modemuxs = uart4_modemux[2], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]), - }, { - .name = "uart4_71_72_grp", - .pins = uart4_pins[3], - .npins = ARRAY_SIZE(uart4_pins[3]), - .modemuxs = uart4_modemux[3], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]), - }, { - .name = "uart4_92_93_grp", - .pins = uart4_pins[4], - .npins = ARRAY_SIZE(uart4_pins[4]), - .modemuxs = uart4_modemux[4], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]), - }, { - .name = "uart4_100_101_grp", - .pins = uart4_pins[5], - .npins = ARRAY_SIZE(uart4_pins[5]), - .modemuxs = uart4_modemux[5], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]), - }, -}; - -static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp", - "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", - "uart4_100_101_grp" }; - -static struct spear_function uart4_function = { - .name = "uart4", - .groups = uart4_grps, - .ngroups = ARRAY_SIZE(uart4_grps), -}; - -/* Pad multiplexing for uart5 device */ -static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 }, - { 90, 91 } }; - -static struct spear_muxreg uart5_ext_4_5_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_I2C_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_4_5_MASK, - .val = PMX_UART5_PL_4_5_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART5_PORT_SEL_MASK, - .val = PMX_UART5_PORT_4_VAL, - }, -}; - -static struct spear_muxreg uart5_ext_37_38_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_37_38_MASK, - .val = PMX_UART5_PL_37_38_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART5_PORT_SEL_MASK, - .val = PMX_UART5_PORT_37_VAL, - }, -}; - -static struct spear_muxreg uart5_ext_69_70_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_69_MASK, - .val = PMX_UART5_PL_69_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK, - .val = PMX_UART5_PL_70_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART5_PORT_SEL_MASK, - .val = PMX_UART5_PORT_69_VAL, - }, -}; - -static struct spear_muxreg uart5_ext_90_91_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK, - .val = PMX_UART5_PL_90_91_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART5_PORT_SEL_MASK, - .val = PMX_UART5_PORT_90_VAL, - }, -}; - -static struct spear_modemux uart5_modemux[][1] = { - { - /* Select signals on pins 4_5 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart5_ext_4_5_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg), - }, - }, { - /* Select signals on pins 37_38 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart5_ext_37_38_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg), - }, - }, { - /* Select signals on pins 69_70 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart5_ext_69_70_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg), - }, - }, { - /* Select signals on pins 90_91 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart5_ext_90_91_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg), - }, - }, -}; - -static struct spear_pingroup uart5_pingroup[] = { - { - .name = "uart5_4_5_grp", - .pins = uart5_pins[0], - .npins = ARRAY_SIZE(uart5_pins[0]), - .modemuxs = uart5_modemux[0], - .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]), - }, { - .name = "uart5_37_38_grp", - .pins = uart5_pins[1], - .npins = ARRAY_SIZE(uart5_pins[1]), - .modemuxs = uart5_modemux[1], - .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]), - }, { - .name = "uart5_69_70_grp", - .pins = uart5_pins[2], - .npins = ARRAY_SIZE(uart5_pins[2]), - .modemuxs = uart5_modemux[2], - .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]), - }, { - .name = "uart5_90_91_grp", - .pins = uart5_pins[3], - .npins = ARRAY_SIZE(uart5_pins[3]), - .modemuxs = uart5_modemux[3], - .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]), - }, -}; - -static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp", - "uart5_69_70_grp", "uart5_90_91_grp" }; -static struct spear_function uart5_function = { - .name = "uart5", - .groups = uart5_grps, - .ngroups = ARRAY_SIZE(uart5_grps), -}; - -/* Pad multiplexing for uart6 device */ -static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } }; -static struct spear_muxreg uart6_ext_2_3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_2_3_MASK, - .val = PMX_UART6_PL_2_3_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART6_PORT_SEL_MASK, - .val = PMX_UART6_PORT_2_VAL, - }, -}; - -static struct spear_muxreg uart6_ext_88_89_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_88_89_MASK, - .val = PMX_UART6_PL_88_89_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART6_PORT_SEL_MASK, - .val = PMX_UART6_PORT_88_VAL, - }, -}; - -static struct spear_modemux uart6_modemux[][1] = { - { - /* Select signals on pins 2_3 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart6_ext_2_3_muxreg, - .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg), - }, - }, { - /* Select signals on pins 88_89 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart6_ext_88_89_muxreg, - .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg), - }, - }, -}; - -static struct spear_pingroup uart6_pingroup[] = { - { - .name = "uart6_2_3_grp", - .pins = uart6_pins[0], - .npins = ARRAY_SIZE(uart6_pins[0]), - .modemuxs = uart6_modemux[0], - .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]), - }, { - .name = "uart6_88_89_grp", - .pins = uart6_pins[1], - .npins = ARRAY_SIZE(uart6_pins[1]), - .modemuxs = uart6_modemux[1], - .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]), - }, -}; - -static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" }; -static struct spear_function uart6_function = { - .name = "uart6", - .groups = uart6_grps, - .ngroups = ARRAY_SIZE(uart6_grps), -}; - -/* UART - RS485 pmx */ -static const unsigned rs485_pins[] = { 77, 78, 79 }; -static struct spear_muxreg rs485_muxreg[] = { - { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_77_78_79_MASK, - .val = PMX_RS485_PL_77_78_79_VAL, - }, -}; - -static struct spear_modemux rs485_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = rs485_muxreg, - .nmuxregs = ARRAY_SIZE(rs485_muxreg), - }, -}; - -static struct spear_pingroup rs485_pingroup = { - .name = "rs485_grp", - .pins = rs485_pins, - .npins = ARRAY_SIZE(rs485_pins), - .modemuxs = rs485_modemux, - .nmodemuxs = ARRAY_SIZE(rs485_modemux), -}; - -static const char *const rs485_grps[] = { "rs485_grp" }; -static struct spear_function rs485_function = { - .name = "rs485", - .groups = rs485_grps, - .ngroups = ARRAY_SIZE(rs485_grps), -}; - -/* Pad multiplexing for Touchscreen device */ -static const unsigned touchscreen_pins[] = { 5, 36 }; -static struct spear_muxreg touchscreen_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg touchscreen_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_5_MASK, - .val = PMX_TOUCH_Y_PL_5_VAL, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_36_MASK, - .val = PMX_TOUCH_X_PL_36_VAL, - }, -}; - -static struct spear_modemux touchscreen_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, - .muxregs = touchscreen_muxreg, - .nmuxregs = ARRAY_SIZE(touchscreen_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = touchscreen_ext_muxreg, - .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg), - }, -}; - -static struct spear_pingroup touchscreen_pingroup = { - .name = "touchscreen_grp", - .pins = touchscreen_pins, - .npins = ARRAY_SIZE(touchscreen_pins), - .modemuxs = touchscreen_modemux, - .nmodemuxs = ARRAY_SIZE(touchscreen_modemux), -}; - -static const char *const touchscreen_grps[] = { "touchscreen_grp" }; -static struct spear_function touchscreen_function = { - .name = "touchscreen", - .groups = touchscreen_grps, - .ngroups = ARRAY_SIZE(touchscreen_grps), -}; - -/* Pad multiplexing for CAN device */ -static const unsigned can0_pins[] = { 32, 33 }; -static struct spear_muxreg can0_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg can0_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_32_33_MASK, - .val = PMX_CAN0_PL_32_33_VAL, - }, -}; - -static struct spear_modemux can0_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE - | EXTENDED_MODE, - .muxregs = can0_muxreg, - .nmuxregs = ARRAY_SIZE(can0_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = can0_ext_muxreg, - .nmuxregs = ARRAY_SIZE(can0_ext_muxreg), - }, -}; - -static struct spear_pingroup can0_pingroup = { - .name = "can0_grp", - .pins = can0_pins, - .npins = ARRAY_SIZE(can0_pins), - .modemuxs = can0_modemux, - .nmodemuxs = ARRAY_SIZE(can0_modemux), -}; - -static const char *const can0_grps[] = { "can0_grp" }; -static struct spear_function can0_function = { - .name = "can0", - .groups = can0_grps, - .ngroups = ARRAY_SIZE(can0_grps), -}; - -static const unsigned can1_pins[] = { 30, 31 }; -static struct spear_muxreg can1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg can1_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_30_31_MASK, - .val = PMX_CAN1_PL_30_31_VAL, - }, -}; - -static struct spear_modemux can1_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE - | EXTENDED_MODE, - .muxregs = can1_muxreg, - .nmuxregs = ARRAY_SIZE(can1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = can1_ext_muxreg, - .nmuxregs = ARRAY_SIZE(can1_ext_muxreg), - }, -}; - -static struct spear_pingroup can1_pingroup = { - .name = "can1_grp", - .pins = can1_pins, - .npins = ARRAY_SIZE(can1_pins), - .modemuxs = can1_modemux, - .nmodemuxs = ARRAY_SIZE(can1_modemux), -}; - -static const char *const can1_grps[] = { "can1_grp" }; -static struct spear_function can1_function = { - .name = "can1", - .groups = can1_grps, - .ngroups = ARRAY_SIZE(can1_grps), -}; - -/* Pad multiplexing for PWM0_1 device */ -static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 }, - { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } }; - -static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_8_9_MASK, - .val = PMX_PWM_0_1_PL_8_9_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_14_MASK | PMX_PL_15_MASK, - .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_30_MASK | PMX_PL_31_MASK, - .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_net_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_37_38_MASK, - .val = PMX_PWM0_1_PL_37_38_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK , - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_42_MASK | PMX_PL_43_MASK, - .val = PMX_PWM1_PL_42_VAL | - PMX_PWM0_PL_43_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_59_MASK, - .val = PMX_PWM1_PL_59_VAL, - }, { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_60_MASK, - .val = PMX_PWM0_PL_60_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_88_89_MASK, - .val = PMX_PWM0_1_PL_88_89_VAL, - }, -}; - -static struct spear_modemux pwm0_1_pin_8_9_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_8_9_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_14_15_modemux[] = { - { - .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = pwm0_1_autoexpsmallpri_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_14_15_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_30_31_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_30_31_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_37_38_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, - .muxregs = pwm0_1_net_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_37_38_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_42_43_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_42_43_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_59_60_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_59_60_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_88_89_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_88_89_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg), - }, -}; - -static struct spear_pingroup pwm0_1_pingroup[] = { - { - .name = "pwm0_1_pin_8_9_grp", - .pins = pwm0_1_pins[0], - .npins = ARRAY_SIZE(pwm0_1_pins[0]), - .modemuxs = pwm0_1_pin_8_9_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux), - }, { - .name = "pwm0_1_pin_14_15_grp", - .pins = pwm0_1_pins[1], - .npins = ARRAY_SIZE(pwm0_1_pins[1]), - .modemuxs = pwm0_1_pin_14_15_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux), - }, { - .name = "pwm0_1_pin_30_31_grp", - .pins = pwm0_1_pins[2], - .npins = ARRAY_SIZE(pwm0_1_pins[2]), - .modemuxs = pwm0_1_pin_30_31_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux), - }, { - .name = "pwm0_1_pin_37_38_grp", - .pins = pwm0_1_pins[3], - .npins = ARRAY_SIZE(pwm0_1_pins[3]), - .modemuxs = pwm0_1_pin_37_38_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux), - }, { - .name = "pwm0_1_pin_42_43_grp", - .pins = pwm0_1_pins[4], - .npins = ARRAY_SIZE(pwm0_1_pins[4]), - .modemuxs = pwm0_1_pin_42_43_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux), - }, { - .name = "pwm0_1_pin_59_60_grp", - .pins = pwm0_1_pins[5], - .npins = ARRAY_SIZE(pwm0_1_pins[5]), - .modemuxs = pwm0_1_pin_59_60_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux), - }, { - .name = "pwm0_1_pin_88_89_grp", - .pins = pwm0_1_pins[6], - .npins = ARRAY_SIZE(pwm0_1_pins[6]), - .modemuxs = pwm0_1_pin_88_89_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux), - }, -}; - -static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp", - "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", - "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp" -}; - -static struct spear_function pwm0_1_function = { - .name = "pwm0_1", - .groups = pwm0_1_grps, - .ngroups = ARRAY_SIZE(pwm0_1_grps), -}; - -/* Pad multiplexing for PWM2 device */ -static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 }, - { 58 }, { 87 } }; -static struct spear_muxreg pwm2_net_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm2_pin_7_muxreg[] = { - { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_7_MASK, - .val = PMX_PWM_2_PL_7_VAL, - }, -}; - -static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm2_pin_13_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_13_MASK, - .val = PMX_PWM2_PL_13_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_29_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN1_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_29_MASK, - .val = PMX_PWM_2_PL_29_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_34_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_34_MASK, - .val = PMX_PWM2_PL_34_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_41_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_41_MASK, - .val = PMX_PWM2_PL_41_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_58_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_58_MASK, - .val = PMX_PWM2_PL_58_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_87_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_87_MASK, - .val = PMX_PWM2_PL_87_VAL, - }, -}; - -static struct spear_modemux pwm2_pin_7_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, - .muxregs = pwm2_net_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_7_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg), - }, -}; -static struct spear_modemux pwm2_pin_13_modemux[] = { - { - .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = pwm2_autoexpsmallpri_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_13_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg), - }, -}; -static struct spear_modemux pwm2_pin_29_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_29_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg), - }, -}; -static struct spear_modemux pwm2_pin_34_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_34_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg), - }, -}; - -static struct spear_modemux pwm2_pin_41_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_41_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg), - }, -}; - -static struct spear_modemux pwm2_pin_58_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_58_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg), - }, -}; - -static struct spear_modemux pwm2_pin_87_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_87_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg), - }, -}; - -static struct spear_pingroup pwm2_pingroup[] = { - { - .name = "pwm2_pin_7_grp", - .pins = pwm2_pins[0], - .npins = ARRAY_SIZE(pwm2_pins[0]), - .modemuxs = pwm2_pin_7_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux), - }, { - .name = "pwm2_pin_13_grp", - .pins = pwm2_pins[1], - .npins = ARRAY_SIZE(pwm2_pins[1]), - .modemuxs = pwm2_pin_13_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux), - }, { - .name = "pwm2_pin_29_grp", - .pins = pwm2_pins[2], - .npins = ARRAY_SIZE(pwm2_pins[2]), - .modemuxs = pwm2_pin_29_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux), - }, { - .name = "pwm2_pin_34_grp", - .pins = pwm2_pins[3], - .npins = ARRAY_SIZE(pwm2_pins[3]), - .modemuxs = pwm2_pin_34_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux), - }, { - .name = "pwm2_pin_41_grp", - .pins = pwm2_pins[4], - .npins = ARRAY_SIZE(pwm2_pins[4]), - .modemuxs = pwm2_pin_41_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux), - }, { - .name = "pwm2_pin_58_grp", - .pins = pwm2_pins[5], - .npins = ARRAY_SIZE(pwm2_pins[5]), - .modemuxs = pwm2_pin_58_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux), - }, { - .name = "pwm2_pin_87_grp", - .pins = pwm2_pins[6], - .npins = ARRAY_SIZE(pwm2_pins[6]), - .modemuxs = pwm2_pin_87_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux), - }, -}; - -static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp", - "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp", - "pwm2_pin_58_grp", "pwm2_pin_87_grp" }; -static struct spear_function pwm2_function = { - .name = "pwm2", - .groups = pwm2_grps, - .ngroups = ARRAY_SIZE(pwm2_grps), -}; - -/* Pad multiplexing for PWM3 device */ -static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 }, - { 86 } }; -static struct spear_muxreg pwm3_pin_6_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_6_MASK, - .val = PMX_PWM_3_PL_6_VAL, - }, -}; - -static struct spear_muxreg pwm3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm3_pin_12_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_12_MASK, - .val = PMX_PWM3_PL_12_VAL, - }, -}; - -static struct spear_muxreg pwm3_pin_28_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN0_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_28_MASK, - .val = PMX_PWM_3_PL_28_VAL, - }, -}; - -static struct spear_muxreg pwm3_pin_40_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_40_MASK, - .val = PMX_PWM3_PL_40_VAL, - }, -}; - -static struct spear_muxreg pwm3_pin_57_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_57_MASK, - .val = PMX_PWM3_PL_57_VAL, - }, -}; - -static struct spear_muxreg pwm3_pin_86_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_86_MASK, - .val = PMX_PWM3_PL_86_VAL, - }, -}; - -static struct spear_modemux pwm3_pin_6_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_6_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_12_modemux[] = { - { - .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | - AUTO_NET_SMII_MODE | EXTENDED_MODE, - .muxregs = pwm3_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_12_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_28_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_28_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_40_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_40_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_57_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_57_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_86_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_86_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg), - }, -}; - -static struct spear_pingroup pwm3_pingroup[] = { - { - .name = "pwm3_pin_6_grp", - .pins = pwm3_pins[0], - .npins = ARRAY_SIZE(pwm3_pins[0]), - .modemuxs = pwm3_pin_6_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux), - }, { - .name = "pwm3_pin_12_grp", - .pins = pwm3_pins[1], - .npins = ARRAY_SIZE(pwm3_pins[1]), - .modemuxs = pwm3_pin_12_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux), - }, { - .name = "pwm3_pin_28_grp", - .pins = pwm3_pins[2], - .npins = ARRAY_SIZE(pwm3_pins[2]), - .modemuxs = pwm3_pin_28_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux), - }, { - .name = "pwm3_pin_40_grp", - .pins = pwm3_pins[3], - .npins = ARRAY_SIZE(pwm3_pins[3]), - .modemuxs = pwm3_pin_40_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux), - }, { - .name = "pwm3_pin_57_grp", - .pins = pwm3_pins[4], - .npins = ARRAY_SIZE(pwm3_pins[4]), - .modemuxs = pwm3_pin_57_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux), - }, { - .name = "pwm3_pin_86_grp", - .pins = pwm3_pins[5], - .npins = ARRAY_SIZE(pwm3_pins[5]), - .modemuxs = pwm3_pin_86_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux), - }, -}; - -static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp", - "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp", - "pwm3_pin_86_grp" }; -static struct spear_function pwm3_function = { - .name = "pwm3", - .groups = pwm3_grps, - .ngroups = ARRAY_SIZE(pwm3_grps), -}; - -/* Pad multiplexing for SSP1 device */ -static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 }, - { 65, 68 }, { 94, 97 } }; -static struct spear_muxreg ssp1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg ssp1_ext_17_20_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK, - .val = PMX_SSP1_PL_17_18_19_20_VAL, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_20_MASK, - .val = PMX_SSP1_PL_17_18_19_20_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_17_TO_20_VAL, - }, -}; - -static struct spear_muxreg ssp1_ext_36_39_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK, - .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL | - PMX_SSP1_PL_39_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_36_TO_39_VAL, - }, -}; - -static struct spear_muxreg ssp1_ext_48_51_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_48_49_MASK, - .val = PMX_SSP1_PL_48_49_VAL, - }, { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_50_51_MASK, - .val = PMX_SSP1_PL_50_51_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_48_TO_51_VAL, - }, -}; - -static struct spear_muxreg ssp1_ext_65_68_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_65_TO_68_MASK, - .val = PMX_SSP1_PL_65_TO_68_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_65_TO_68_VAL, - }, -}; - -static struct spear_muxreg ssp1_ext_94_97_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, - .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_94_TO_97_VAL, - }, -}; - -static struct spear_modemux ssp1_17_20_modemux[] = { - { - .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE | - EXTENDED_MODE, - .muxregs = ssp1_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_17_20_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg), - }, -}; - -static struct spear_modemux ssp1_36_39_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_36_39_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg), - }, -}; - -static struct spear_modemux ssp1_48_51_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_48_51_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg), - }, -}; -static struct spear_modemux ssp1_65_68_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_65_68_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg), - }, -}; - -static struct spear_modemux ssp1_94_97_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_94_97_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg), - }, -}; - -static struct spear_pingroup ssp1_pingroup[] = { - { - .name = "ssp1_17_20_grp", - .pins = ssp1_pins[0], - .npins = ARRAY_SIZE(ssp1_pins[0]), - .modemuxs = ssp1_17_20_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux), - }, { - .name = "ssp1_36_39_grp", - .pins = ssp1_pins[1], - .npins = ARRAY_SIZE(ssp1_pins[1]), - .modemuxs = ssp1_36_39_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux), - }, { - .name = "ssp1_48_51_grp", - .pins = ssp1_pins[2], - .npins = ARRAY_SIZE(ssp1_pins[2]), - .modemuxs = ssp1_48_51_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux), - }, { - .name = "ssp1_65_68_grp", - .pins = ssp1_pins[3], - .npins = ARRAY_SIZE(ssp1_pins[3]), - .modemuxs = ssp1_65_68_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux), - }, { - .name = "ssp1_94_97_grp", - .pins = ssp1_pins[4], - .npins = ARRAY_SIZE(ssp1_pins[4]), - .modemuxs = ssp1_94_97_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux), - }, -}; - -static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp", - "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp" -}; -static struct spear_function ssp1_function = { - .name = "ssp1", - .groups = ssp1_grps, - .ngroups = ARRAY_SIZE(ssp1_grps), -}; - -/* Pad multiplexing for SSP2 device */ -static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 }, - { 61, 64 }, { 90, 93 } }; -static struct spear_muxreg ssp2_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg ssp2_ext_13_16_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK, - .val = PMX_SSP2_PL_13_14_15_16_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_13_TO_16_VAL, - }, -}; - -static struct spear_muxreg ssp2_ext_32_35_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK | - PMX_GPIO_PIN5_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK, - .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL | - PMX_SSP2_PL_35_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_32_TO_35_VAL, - }, -}; - -static struct spear_muxreg ssp2_ext_44_47_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK, - .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_44_TO_47_VAL, - }, -}; - -static struct spear_muxreg ssp2_ext_61_64_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_61_TO_64_MASK, - .val = PMX_SSP2_PL_61_TO_64_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_61_TO_64_VAL, - }, -}; - -static struct spear_muxreg ssp2_ext_90_93_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK, - .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_90_TO_93_VAL, - }, -}; - -static struct spear_modemux ssp2_13_16_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, - .muxregs = ssp2_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_13_16_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg), - }, -}; - -static struct spear_modemux ssp2_32_35_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_32_35_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg), - }, -}; - -static struct spear_modemux ssp2_44_47_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_44_47_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg), - }, -}; - -static struct spear_modemux ssp2_61_64_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_61_64_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg), - }, -}; - -static struct spear_modemux ssp2_90_93_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_90_93_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg), - }, -}; - -static struct spear_pingroup ssp2_pingroup[] = { - { - .name = "ssp2_13_16_grp", - .pins = ssp2_pins[0], - .npins = ARRAY_SIZE(ssp2_pins[0]), - .modemuxs = ssp2_13_16_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux), - }, { - .name = "ssp2_32_35_grp", - .pins = ssp2_pins[1], - .npins = ARRAY_SIZE(ssp2_pins[1]), - .modemuxs = ssp2_32_35_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux), - }, { - .name = "ssp2_44_47_grp", - .pins = ssp2_pins[2], - .npins = ARRAY_SIZE(ssp2_pins[2]), - .modemuxs = ssp2_44_47_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux), - }, { - .name = "ssp2_61_64_grp", - .pins = ssp2_pins[3], - .npins = ARRAY_SIZE(ssp2_pins[3]), - .modemuxs = ssp2_61_64_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux), - }, { - .name = "ssp2_90_93_grp", - .pins = ssp2_pins[4], - .npins = ARRAY_SIZE(ssp2_pins[4]), - .modemuxs = ssp2_90_93_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux), - }, -}; - -static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp", - "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" }; -static struct spear_function ssp2_function = { - .name = "ssp2", - .groups = ssp2_grps, - .ngroups = ARRAY_SIZE(ssp2_grps), -}; - -/* Pad multiplexing for cadence mii2 as mii device */ -static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, - 90, 91, 92, 93, 94, 95, 96, 97 }; -static struct spear_muxreg mii2_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | - PMX_PL_88_89_MASK, - .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL | - PMX_MII2_PL_88_89_VAL, - }, { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | - PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, - .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL | - PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | - (MAC_MODE_MASK << MAC1_MODE_SHIFT) | - MII_MDIO_MASK, - .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) | - (MAC_MODE_MII << MAC1_MODE_SHIFT) | - MII_MDIO_81_VAL, - }, -}; - -static struct spear_modemux mii2_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = mii2_muxreg, - .nmuxregs = ARRAY_SIZE(mii2_muxreg), - }, -}; - -static struct spear_pingroup mii2_pingroup = { - .name = "mii2_grp", - .pins = mii2_pins, - .npins = ARRAY_SIZE(mii2_pins), - .modemuxs = mii2_modemux, - .nmodemuxs = ARRAY_SIZE(mii2_modemux), -}; - -static const char *const mii2_grps[] = { "mii2_grp" }; -static struct spear_function mii2_function = { - .name = "mii2", - .groups = mii2_grps, - .ngroups = ARRAY_SIZE(mii2_grps), -}; - -/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ -static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27 }; -static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; -static struct spear_muxreg mii0_1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg smii0_1_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_10_11_MASK, - .val = PMX_SMII_PL_10_11_VAL, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_21_TO_27_MASK, - .val = PMX_SMII_PL_21_TO_27_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | - (MAC_MODE_MASK << MAC1_MODE_SHIFT) | - MII_MDIO_MASK, - .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT) - | (MAC_MODE_SMII << MAC1_MODE_SHIFT) - | MII_MDIO_10_11_VAL, - }, -}; - -static struct spear_muxreg rmii0_1_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK | - PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK, - .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL | - PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL | - PMX_RMII_PL_19_VAL, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK, - .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | - (MAC_MODE_MASK << MAC1_MODE_SHIFT) | - MII_MDIO_MASK, - .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT) - | (MAC_MODE_RMII << MAC1_MODE_SHIFT) - | MII_MDIO_10_11_VAL, - }, -}; - -static struct spear_modemux mii0_1_modemux[][2] = { - { - /* configure as smii */ - { - .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | - SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = mii0_1_muxreg, - .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = smii0_1_ext_muxreg, - .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg), - }, - }, { - /* configure as rmii */ - { - .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | - SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = mii0_1_muxreg, - .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = rmii0_1_ext_muxreg, - .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg), - }, - }, -}; - -static struct spear_pingroup mii0_1_pingroup[] = { - { - .name = "smii0_1_grp", - .pins = smii0_1_pins, - .npins = ARRAY_SIZE(smii0_1_pins), - .modemuxs = mii0_1_modemux[0], - .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]), - }, { - .name = "rmii0_1_grp", - .pins = rmii0_1_pins, - .npins = ARRAY_SIZE(rmii0_1_pins), - .modemuxs = mii0_1_modemux[1], - .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]), - }, -}; - -static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" }; -static struct spear_function mii0_1_function = { - .name = "mii0_1", - .groups = mii0_1_grps, - .ngroups = ARRAY_SIZE(mii0_1_grps), -}; - -/* Pad multiplexing for i2c1 device */ -static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } }; -static struct spear_muxreg i2c1_ext_8_9_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_8_9_MASK, - .val = PMX_I2C1_PL_8_9_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C1_PORT_SEL_MASK, - .val = PMX_I2C1_PORT_8_9_VAL, - }, -}; - -static struct spear_muxreg i2c1_ext_98_99_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, - .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C1_PORT_SEL_MASK, - .val = PMX_I2C1_PORT_98_99_VAL, - }, -}; - -static struct spear_modemux i2c1_modemux[][1] = { - { - /* Select signals on pins 8-9 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c1_ext_8_9_muxreg, - .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg), - }, - }, { - /* Select signals on pins 98-99 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c1_ext_98_99_muxreg, - .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg), - }, - }, -}; - -static struct spear_pingroup i2c1_pingroup[] = { - { - .name = "i2c1_8_9_grp", - .pins = i2c1_pins[0], - .npins = ARRAY_SIZE(i2c1_pins[0]), - .modemuxs = i2c1_modemux[0], - .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]), - }, { - .name = "i2c1_98_99_grp", - .pins = i2c1_pins[1], - .npins = ARRAY_SIZE(i2c1_pins[1]), - .modemuxs = i2c1_modemux[1], - .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]), - }, -}; - -static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" }; -static struct spear_function i2c1_function = { - .name = "i2c1", - .groups = i2c1_grps, - .ngroups = ARRAY_SIZE(i2c1_grps), -}; - -/* Pad multiplexing for i2c2 device */ -static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 }, - { 75, 76 }, { 96, 97 } }; -static struct spear_muxreg i2c2_ext_0_1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_0_1_MASK, - .val = PMX_I2C2_PL_0_1_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_0_1_VAL, - }, -}; - -static struct spear_muxreg i2c2_ext_2_3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_2_3_MASK, - .val = PMX_I2C2_PL_2_3_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_2_3_VAL, - }, -}; - -static struct spear_muxreg i2c2_ext_19_20_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_19_MASK, - .val = PMX_I2C2_PL_19_VAL, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_20_MASK, - .val = PMX_I2C2_PL_20_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_19_20_VAL, - }, -}; - -static struct spear_muxreg i2c2_ext_75_76_muxreg[] = { - { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_75_76_MASK, - .val = PMX_I2C2_PL_75_76_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_75_76_VAL, - }, -}; - -static struct spear_muxreg i2c2_ext_96_97_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_96_97_MASK, - .val = PMX_I2C2_PL_96_97_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_96_97_VAL, - }, -}; - -static struct spear_modemux i2c2_modemux[][1] = { - { - /* Select signals on pins 0_1 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_0_1_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg), - }, - }, { - /* Select signals on pins 2_3 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_2_3_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg), - }, - }, { - /* Select signals on pins 19_20 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_19_20_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg), - }, - }, { - /* Select signals on pins 75_76 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_75_76_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg), - }, - }, { - /* Select signals on pins 96_97 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_96_97_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg), - }, - }, -}; - -static struct spear_pingroup i2c2_pingroup[] = { - { - .name = "i2c2_0_1_grp", - .pins = i2c2_pins[0], - .npins = ARRAY_SIZE(i2c2_pins[0]), - .modemuxs = i2c2_modemux[0], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]), - }, { - .name = "i2c2_2_3_grp", - .pins = i2c2_pins[1], - .npins = ARRAY_SIZE(i2c2_pins[1]), - .modemuxs = i2c2_modemux[1], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]), - }, { - .name = "i2c2_19_20_grp", - .pins = i2c2_pins[2], - .npins = ARRAY_SIZE(i2c2_pins[2]), - .modemuxs = i2c2_modemux[2], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]), - }, { - .name = "i2c2_75_76_grp", - .pins = i2c2_pins[3], - .npins = ARRAY_SIZE(i2c2_pins[3]), - .modemuxs = i2c2_modemux[3], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]), - }, { - .name = "i2c2_96_97_grp", - .pins = i2c2_pins[4], - .npins = ARRAY_SIZE(i2c2_pins[4]), - .modemuxs = i2c2_modemux[4], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]), - }, -}; - -static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp", - "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" }; -static struct spear_function i2c2_function = { - .name = "i2c2", - .groups = i2c2_grps, - .ngroups = ARRAY_SIZE(i2c2_grps), -}; - -/* pingroups */ -static struct spear_pingroup *spear320_pingroups[] = { - SPEAR3XX_COMMON_PINGROUPS, - &clcd_pingroup, - &emi_pingroup, - &fsmc_8bit_pingroup, - &fsmc_16bit_pingroup, - &spp_pingroup, - &sdhci_led_pingroup, - &sdhci_pingroup[0], - &sdhci_pingroup[1], - &i2s_pingroup, - &uart1_pingroup, - &uart1_modem_pingroup[0], - &uart1_modem_pingroup[1], - &uart1_modem_pingroup[2], - &uart1_modem_pingroup[3], - &uart2_pingroup, - &uart3_pingroup[0], - &uart3_pingroup[1], - &uart3_pingroup[2], - &uart3_pingroup[3], - &uart3_pingroup[4], - &uart3_pingroup[5], - &uart3_pingroup[6], - &uart4_pingroup[0], - &uart4_pingroup[1], - &uart4_pingroup[2], - &uart4_pingroup[3], - &uart4_pingroup[4], - &uart4_pingroup[5], - &uart5_pingroup[0], - &uart5_pingroup[1], - &uart5_pingroup[2], - &uart5_pingroup[3], - &uart6_pingroup[0], - &uart6_pingroup[1], - &rs485_pingroup, - &touchscreen_pingroup, - &can0_pingroup, - &can1_pingroup, - &pwm0_1_pingroup[0], - &pwm0_1_pingroup[1], - &pwm0_1_pingroup[2], - &pwm0_1_pingroup[3], - &pwm0_1_pingroup[4], - &pwm0_1_pingroup[5], - &pwm0_1_pingroup[6], - &pwm2_pingroup[0], - &pwm2_pingroup[1], - &pwm2_pingroup[2], - &pwm2_pingroup[3], - &pwm2_pingroup[4], - &pwm2_pingroup[5], - &pwm2_pingroup[6], - &pwm3_pingroup[0], - &pwm3_pingroup[1], - &pwm3_pingroup[2], - &pwm3_pingroup[3], - &pwm3_pingroup[4], - &pwm3_pingroup[5], - &ssp1_pingroup[0], - &ssp1_pingroup[1], - &ssp1_pingroup[2], - &ssp1_pingroup[3], - &ssp1_pingroup[4], - &ssp2_pingroup[0], - &ssp2_pingroup[1], - &ssp2_pingroup[2], - &ssp2_pingroup[3], - &ssp2_pingroup[4], - &mii2_pingroup, - &mii0_1_pingroup[0], - &mii0_1_pingroup[1], - &i2c1_pingroup[0], - &i2c1_pingroup[1], - &i2c2_pingroup[0], - &i2c2_pingroup[1], - &i2c2_pingroup[2], - &i2c2_pingroup[3], - &i2c2_pingroup[4], -}; - -/* functions */ -static struct spear_function *spear320_functions[] = { - SPEAR3XX_COMMON_FUNCTIONS, - &clcd_function, - &emi_function, - &fsmc_function, - &spp_function, - &sdhci_function, - &i2s_function, - &uart1_function, - &uart1_modem_function, - &uart2_function, - &uart3_function, - &uart4_function, - &uart5_function, - &uart6_function, - &rs485_function, - &touchscreen_function, - &can0_function, - &can1_function, - &pwm0_1_function, - &pwm2_function, - &pwm3_function, - &ssp1_function, - &ssp2_function, - &mii2_function, - &mii0_1_function, - &i2c1_function, - &i2c2_function, -}; - -static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = { - { - .compatible = "st,spear320-pinmux", - }, - {}, -}; - -static int __devinit spear320_pinctrl_probe(struct platform_device *pdev) -{ - int ret; - - spear3xx_machdata.groups = spear320_pingroups; - spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups); - spear3xx_machdata.functions = spear320_functions; - spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions); - - spear3xx_machdata.modes_supported = true; - spear3xx_machdata.pmx_modes = spear320_pmx_modes; - spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes); - - pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); - - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; -} - -static int __devexit spear320_pinctrl_remove(struct platform_device *pdev) -{ - return spear_pinctrl_remove(pdev); -} - -static struct platform_driver spear320_pinctrl_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = spear320_pinctrl_of_match, - }, - .probe = spear320_pinctrl_probe, - .remove = __devexit_p(spear320_pinctrl_remove), -}; - -static int __init spear320_pinctrl_init(void) -{ - return platform_driver_register(&spear320_pinctrl_driver); -} -arch_initcall(spear320_pinctrl_init); - -static void __exit spear320_pinctrl_exit(void) -{ - platform_driver_unregister(&spear320_pinctrl_driver); -} -module_exit(spear320_pinctrl_exit); - -MODULE_AUTHOR("Viresh Kumar "); -MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.c b/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.c deleted file mode 100644 index 832049a8b1c9..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.c +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr3xx pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - -#include "pinctrl-spear3xx.h" - -/* pins */ -static const struct pinctrl_pin_desc spear3xx_pins[] = { - PINCTRL_PIN(0, "PLGPIO0"), - PINCTRL_PIN(1, "PLGPIO1"), - PINCTRL_PIN(2, "PLGPIO2"), - PINCTRL_PIN(3, "PLGPIO3"), - PINCTRL_PIN(4, "PLGPIO4"), - PINCTRL_PIN(5, "PLGPIO5"), - PINCTRL_PIN(6, "PLGPIO6"), - PINCTRL_PIN(7, "PLGPIO7"), - PINCTRL_PIN(8, "PLGPIO8"), - PINCTRL_PIN(9, "PLGPIO9"), - PINCTRL_PIN(10, "PLGPIO10"), - PINCTRL_PIN(11, "PLGPIO11"), - PINCTRL_PIN(12, "PLGPIO12"), - PINCTRL_PIN(13, "PLGPIO13"), - PINCTRL_PIN(14, "PLGPIO14"), - PINCTRL_PIN(15, "PLGPIO15"), - PINCTRL_PIN(16, "PLGPIO16"), - PINCTRL_PIN(17, "PLGPIO17"), - PINCTRL_PIN(18, "PLGPIO18"), - PINCTRL_PIN(19, "PLGPIO19"), - PINCTRL_PIN(20, "PLGPIO20"), - PINCTRL_PIN(21, "PLGPIO21"), - PINCTRL_PIN(22, "PLGPIO22"), - PINCTRL_PIN(23, "PLGPIO23"), - PINCTRL_PIN(24, "PLGPIO24"), - PINCTRL_PIN(25, "PLGPIO25"), - PINCTRL_PIN(26, "PLGPIO26"), - PINCTRL_PIN(27, "PLGPIO27"), - PINCTRL_PIN(28, "PLGPIO28"), - PINCTRL_PIN(29, "PLGPIO29"), - PINCTRL_PIN(30, "PLGPIO30"), - PINCTRL_PIN(31, "PLGPIO31"), - PINCTRL_PIN(32, "PLGPIO32"), - PINCTRL_PIN(33, "PLGPIO33"), - PINCTRL_PIN(34, "PLGPIO34"), - PINCTRL_PIN(35, "PLGPIO35"), - PINCTRL_PIN(36, "PLGPIO36"), - PINCTRL_PIN(37, "PLGPIO37"), - PINCTRL_PIN(38, "PLGPIO38"), - PINCTRL_PIN(39, "PLGPIO39"), - PINCTRL_PIN(40, "PLGPIO40"), - PINCTRL_PIN(41, "PLGPIO41"), - PINCTRL_PIN(42, "PLGPIO42"), - PINCTRL_PIN(43, "PLGPIO43"), - PINCTRL_PIN(44, "PLGPIO44"), - PINCTRL_PIN(45, "PLGPIO45"), - PINCTRL_PIN(46, "PLGPIO46"), - PINCTRL_PIN(47, "PLGPIO47"), - PINCTRL_PIN(48, "PLGPIO48"), - PINCTRL_PIN(49, "PLGPIO49"), - PINCTRL_PIN(50, "PLGPIO50"), - PINCTRL_PIN(51, "PLGPIO51"), - PINCTRL_PIN(52, "PLGPIO52"), - PINCTRL_PIN(53, "PLGPIO53"), - PINCTRL_PIN(54, "PLGPIO54"), - PINCTRL_PIN(55, "PLGPIO55"), - PINCTRL_PIN(56, "PLGPIO56"), - PINCTRL_PIN(57, "PLGPIO57"), - PINCTRL_PIN(58, "PLGPIO58"), - PINCTRL_PIN(59, "PLGPIO59"), - PINCTRL_PIN(60, "PLGPIO60"), - PINCTRL_PIN(61, "PLGPIO61"), - PINCTRL_PIN(62, "PLGPIO62"), - PINCTRL_PIN(63, "PLGPIO63"), - PINCTRL_PIN(64, "PLGPIO64"), - PINCTRL_PIN(65, "PLGPIO65"), - PINCTRL_PIN(66, "PLGPIO66"), - PINCTRL_PIN(67, "PLGPIO67"), - PINCTRL_PIN(68, "PLGPIO68"), - PINCTRL_PIN(69, "PLGPIO69"), - PINCTRL_PIN(70, "PLGPIO70"), - PINCTRL_PIN(71, "PLGPIO71"), - PINCTRL_PIN(72, "PLGPIO72"), - PINCTRL_PIN(73, "PLGPIO73"), - PINCTRL_PIN(74, "PLGPIO74"), - PINCTRL_PIN(75, "PLGPIO75"), - PINCTRL_PIN(76, "PLGPIO76"), - PINCTRL_PIN(77, "PLGPIO77"), - PINCTRL_PIN(78, "PLGPIO78"), - PINCTRL_PIN(79, "PLGPIO79"), - PINCTRL_PIN(80, "PLGPIO80"), - PINCTRL_PIN(81, "PLGPIO81"), - PINCTRL_PIN(82, "PLGPIO82"), - PINCTRL_PIN(83, "PLGPIO83"), - PINCTRL_PIN(84, "PLGPIO84"), - PINCTRL_PIN(85, "PLGPIO85"), - PINCTRL_PIN(86, "PLGPIO86"), - PINCTRL_PIN(87, "PLGPIO87"), - PINCTRL_PIN(88, "PLGPIO88"), - PINCTRL_PIN(89, "PLGPIO89"), - PINCTRL_PIN(90, "PLGPIO90"), - PINCTRL_PIN(91, "PLGPIO91"), - PINCTRL_PIN(92, "PLGPIO92"), - PINCTRL_PIN(93, "PLGPIO93"), - PINCTRL_PIN(94, "PLGPIO94"), - PINCTRL_PIN(95, "PLGPIO95"), - PINCTRL_PIN(96, "PLGPIO96"), - PINCTRL_PIN(97, "PLGPIO97"), - PINCTRL_PIN(98, "PLGPIO98"), - PINCTRL_PIN(99, "PLGPIO99"), - PINCTRL_PIN(100, "PLGPIO100"), - PINCTRL_PIN(101, "PLGPIO101"), -}; - -/* firda_pins */ -static const unsigned firda_pins[] = { 0, 1 }; -static struct spear_muxreg firda_muxreg[] = { - { - .reg = -1, - .mask = PMX_FIRDA_MASK, - .val = PMX_FIRDA_MASK, - }, -}; - -static struct spear_modemux firda_modemux[] = { - { - .modes = ~0, - .muxregs = firda_muxreg, - .nmuxregs = ARRAY_SIZE(firda_muxreg), - }, -}; - -struct spear_pingroup spear3xx_firda_pingroup = { - .name = "firda_grp", - .pins = firda_pins, - .npins = ARRAY_SIZE(firda_pins), - .modemuxs = firda_modemux, - .nmodemuxs = ARRAY_SIZE(firda_modemux), -}; - -static const char *const firda_grps[] = { "firda_grp" }; -struct spear_function spear3xx_firda_function = { - .name = "firda", - .groups = firda_grps, - .ngroups = ARRAY_SIZE(firda_grps), -}; - -/* i2c_pins */ -static const unsigned i2c_pins[] = { 4, 5 }; -static struct spear_muxreg i2c_muxreg[] = { - { - .reg = -1, - .mask = PMX_I2C_MASK, - .val = PMX_I2C_MASK, - }, -}; - -static struct spear_modemux i2c_modemux[] = { - { - .modes = ~0, - .muxregs = i2c_muxreg, - .nmuxregs = ARRAY_SIZE(i2c_muxreg), - }, -}; - -struct spear_pingroup spear3xx_i2c_pingroup = { - .name = "i2c0_grp", - .pins = i2c_pins, - .npins = ARRAY_SIZE(i2c_pins), - .modemuxs = i2c_modemux, - .nmodemuxs = ARRAY_SIZE(i2c_modemux), -}; - -static const char *const i2c_grps[] = { "i2c0_grp" }; -struct spear_function spear3xx_i2c_function = { - .name = "i2c0", - .groups = i2c_grps, - .ngroups = ARRAY_SIZE(i2c_grps), -}; - -/* ssp_cs_pins */ -static const unsigned ssp_cs_pins[] = { 34, 35, 36 }; -static struct spear_muxreg ssp_cs_muxreg[] = { - { - .reg = -1, - .mask = PMX_SSP_CS_MASK, - .val = PMX_SSP_CS_MASK, - }, -}; - -static struct spear_modemux ssp_cs_modemux[] = { - { - .modes = ~0, - .muxregs = ssp_cs_muxreg, - .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg), - }, -}; - -struct spear_pingroup spear3xx_ssp_cs_pingroup = { - .name = "ssp_cs_grp", - .pins = ssp_cs_pins, - .npins = ARRAY_SIZE(ssp_cs_pins), - .modemuxs = ssp_cs_modemux, - .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux), -}; - -static const char *const ssp_cs_grps[] = { "ssp_cs_grp" }; -struct spear_function spear3xx_ssp_cs_function = { - .name = "ssp_cs", - .groups = ssp_cs_grps, - .ngroups = ARRAY_SIZE(ssp_cs_grps), -}; - -/* ssp_pins */ -static const unsigned ssp_pins[] = { 6, 7, 8, 9 }; -static struct spear_muxreg ssp_muxreg[] = { - { - .reg = -1, - .mask = PMX_SSP_MASK, - .val = PMX_SSP_MASK, - }, -}; - -static struct spear_modemux ssp_modemux[] = { - { - .modes = ~0, - .muxregs = ssp_muxreg, - .nmuxregs = ARRAY_SIZE(ssp_muxreg), - }, -}; - -struct spear_pingroup spear3xx_ssp_pingroup = { - .name = "ssp0_grp", - .pins = ssp_pins, - .npins = ARRAY_SIZE(ssp_pins), - .modemuxs = ssp_modemux, - .nmodemuxs = ARRAY_SIZE(ssp_modemux), -}; - -static const char *const ssp_grps[] = { "ssp0_grp" }; -struct spear_function spear3xx_ssp_function = { - .name = "ssp0", - .groups = ssp_grps, - .ngroups = ARRAY_SIZE(ssp_grps), -}; - -/* mii_pins */ -static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27 }; -static struct spear_muxreg mii_muxreg[] = { - { - .reg = -1, - .mask = PMX_MII_MASK, - .val = PMX_MII_MASK, - }, -}; - -static struct spear_modemux mii_modemux[] = { - { - .modes = ~0, - .muxregs = mii_muxreg, - .nmuxregs = ARRAY_SIZE(mii_muxreg), - }, -}; - -struct spear_pingroup spear3xx_mii_pingroup = { - .name = "mii0_grp", - .pins = mii_pins, - .npins = ARRAY_SIZE(mii_pins), - .modemuxs = mii_modemux, - .nmodemuxs = ARRAY_SIZE(mii_modemux), -}; - -static const char *const mii_grps[] = { "mii0_grp" }; -struct spear_function spear3xx_mii_function = { - .name = "mii0", - .groups = mii_grps, - .ngroups = ARRAY_SIZE(mii_grps), -}; - -/* gpio0_pin0_pins */ -static const unsigned gpio0_pin0_pins[] = { 28 }; -static struct spear_muxreg gpio0_pin0_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN0_MASK, - .val = PMX_GPIO_PIN0_MASK, - }, -}; - -static struct spear_modemux gpio0_pin0_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin0_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin0_pingroup = { - .name = "gpio0_pin0_grp", - .pins = gpio0_pin0_pins, - .npins = ARRAY_SIZE(gpio0_pin0_pins), - .modemuxs = gpio0_pin0_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux), -}; - -/* gpio0_pin1_pins */ -static const unsigned gpio0_pin1_pins[] = { 29 }; -static struct spear_muxreg gpio0_pin1_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN1_MASK, - .val = PMX_GPIO_PIN1_MASK, - }, -}; - -static struct spear_modemux gpio0_pin1_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin1_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin1_pingroup = { - .name = "gpio0_pin1_grp", - .pins = gpio0_pin1_pins, - .npins = ARRAY_SIZE(gpio0_pin1_pins), - .modemuxs = gpio0_pin1_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux), -}; - -/* gpio0_pin2_pins */ -static const unsigned gpio0_pin2_pins[] = { 30 }; -static struct spear_muxreg gpio0_pin2_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN2_MASK, - .val = PMX_GPIO_PIN2_MASK, - }, -}; - -static struct spear_modemux gpio0_pin2_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin2_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin2_pingroup = { - .name = "gpio0_pin2_grp", - .pins = gpio0_pin2_pins, - .npins = ARRAY_SIZE(gpio0_pin2_pins), - .modemuxs = gpio0_pin2_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux), -}; - -/* gpio0_pin3_pins */ -static const unsigned gpio0_pin3_pins[] = { 31 }; -static struct spear_muxreg gpio0_pin3_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN3_MASK, - .val = PMX_GPIO_PIN3_MASK, - }, -}; - -static struct spear_modemux gpio0_pin3_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin3_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin3_pingroup = { - .name = "gpio0_pin3_grp", - .pins = gpio0_pin3_pins, - .npins = ARRAY_SIZE(gpio0_pin3_pins), - .modemuxs = gpio0_pin3_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux), -}; - -/* gpio0_pin4_pins */ -static const unsigned gpio0_pin4_pins[] = { 32 }; -static struct spear_muxreg gpio0_pin4_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN4_MASK, - .val = PMX_GPIO_PIN4_MASK, - }, -}; - -static struct spear_modemux gpio0_pin4_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin4_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin4_pingroup = { - .name = "gpio0_pin4_grp", - .pins = gpio0_pin4_pins, - .npins = ARRAY_SIZE(gpio0_pin4_pins), - .modemuxs = gpio0_pin4_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux), -}; - -/* gpio0_pin5_pins */ -static const unsigned gpio0_pin5_pins[] = { 33 }; -static struct spear_muxreg gpio0_pin5_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN5_MASK, - .val = PMX_GPIO_PIN5_MASK, - }, -}; - -static struct spear_modemux gpio0_pin5_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin5_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin5_pingroup = { - .name = "gpio0_pin5_grp", - .pins = gpio0_pin5_pins, - .npins = ARRAY_SIZE(gpio0_pin5_pins), - .modemuxs = gpio0_pin5_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux), -}; - -static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp", - "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp", -}; -struct spear_function spear3xx_gpio0_function = { - .name = "gpio0", - .groups = gpio0_grps, - .ngroups = ARRAY_SIZE(gpio0_grps), -}; - -/* uart0_ext_pins */ -static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 }; -static struct spear_muxreg uart0_ext_muxreg[] = { - { - .reg = -1, - .mask = PMX_UART0_MODEM_MASK, - .val = PMX_UART0_MODEM_MASK, - }, -}; - -static struct spear_modemux uart0_ext_modemux[] = { - { - .modes = ~0, - .muxregs = uart0_ext_muxreg, - .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg), - }, -}; - -struct spear_pingroup spear3xx_uart0_ext_pingroup = { - .name = "uart0_ext_grp", - .pins = uart0_ext_pins, - .npins = ARRAY_SIZE(uart0_ext_pins), - .modemuxs = uart0_ext_modemux, - .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux), -}; - -static const char *const uart0_ext_grps[] = { "uart0_ext_grp" }; -struct spear_function spear3xx_uart0_ext_function = { - .name = "uart0_ext", - .groups = uart0_ext_grps, - .ngroups = ARRAY_SIZE(uart0_ext_grps), -}; - -/* uart0_pins */ -static const unsigned uart0_pins[] = { 2, 3 }; -static struct spear_muxreg uart0_muxreg[] = { - { - .reg = -1, - .mask = PMX_UART0_MASK, - .val = PMX_UART0_MASK, - }, -}; - -static struct spear_modemux uart0_modemux[] = { - { - .modes = ~0, - .muxregs = uart0_muxreg, - .nmuxregs = ARRAY_SIZE(uart0_muxreg), - }, -}; - -struct spear_pingroup spear3xx_uart0_pingroup = { - .name = "uart0_grp", - .pins = uart0_pins, - .npins = ARRAY_SIZE(uart0_pins), - .modemuxs = uart0_modemux, - .nmodemuxs = ARRAY_SIZE(uart0_modemux), -}; - -static const char *const uart0_grps[] = { "uart0_grp" }; -struct spear_function spear3xx_uart0_function = { - .name = "uart0", - .groups = uart0_grps, - .ngroups = ARRAY_SIZE(uart0_grps), -}; - -/* timer_0_1_pins */ -static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 }; -static struct spear_muxreg timer_0_1_muxreg[] = { - { - .reg = -1, - .mask = PMX_TIMER_0_1_MASK, - .val = PMX_TIMER_0_1_MASK, - }, -}; - -static struct spear_modemux timer_0_1_modemux[] = { - { - .modes = ~0, - .muxregs = timer_0_1_muxreg, - .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg), - }, -}; - -struct spear_pingroup spear3xx_timer_0_1_pingroup = { - .name = "timer_0_1_grp", - .pins = timer_0_1_pins, - .npins = ARRAY_SIZE(timer_0_1_pins), - .modemuxs = timer_0_1_modemux, - .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux), -}; - -static const char *const timer_0_1_grps[] = { "timer_0_1_grp" }; -struct spear_function spear3xx_timer_0_1_function = { - .name = "timer_0_1", - .groups = timer_0_1_grps, - .ngroups = ARRAY_SIZE(timer_0_1_grps), -}; - -/* timer_2_3_pins */ -static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 }; -static struct spear_muxreg timer_2_3_muxreg[] = { - { - .reg = -1, - .mask = PMX_TIMER_2_3_MASK, - .val = PMX_TIMER_2_3_MASK, - }, -}; - -static struct spear_modemux timer_2_3_modemux[] = { - { - .modes = ~0, - .muxregs = timer_2_3_muxreg, - .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg), - }, -}; - -struct spear_pingroup spear3xx_timer_2_3_pingroup = { - .name = "timer_2_3_grp", - .pins = timer_2_3_pins, - .npins = ARRAY_SIZE(timer_2_3_pins), - .modemuxs = timer_2_3_modemux, - .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux), -}; - -static const char *const timer_2_3_grps[] = { "timer_2_3_grp" }; -struct spear_function spear3xx_timer_2_3_function = { - .name = "timer_2_3", - .groups = timer_2_3_grps, - .ngroups = ARRAY_SIZE(timer_2_3_grps), -}; - -struct spear_pinctrl_machdata spear3xx_machdata = { - .pins = spear3xx_pins, - .npins = ARRAY_SIZE(spear3xx_pins), -}; diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.h b/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.h deleted file mode 100644 index 5d5fdd8df7b8..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Header file for the ST Microelectronics SPEAr3xx pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PINMUX_SPEAR3XX_H__ -#define __PINMUX_SPEAR3XX_H__ - -#include "pinctrl-spear.h" - -/* pad mux declarations */ -#define PMX_FIRDA_MASK (1 << 14) -#define PMX_I2C_MASK (1 << 13) -#define PMX_SSP_CS_MASK (1 << 12) -#define PMX_SSP_MASK (1 << 11) -#define PMX_MII_MASK (1 << 10) -#define PMX_GPIO_PIN0_MASK (1 << 9) -#define PMX_GPIO_PIN1_MASK (1 << 8) -#define PMX_GPIO_PIN2_MASK (1 << 7) -#define PMX_GPIO_PIN3_MASK (1 << 6) -#define PMX_GPIO_PIN4_MASK (1 << 5) -#define PMX_GPIO_PIN5_MASK (1 << 4) -#define PMX_UART0_MODEM_MASK (1 << 3) -#define PMX_UART0_MASK (1 << 2) -#define PMX_TIMER_2_3_MASK (1 << 1) -#define PMX_TIMER_0_1_MASK (1 << 0) - -extern struct spear_pingroup spear3xx_firda_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup; -extern struct spear_pingroup spear3xx_i2c_pingroup; -extern struct spear_pingroup spear3xx_mii_pingroup; -extern struct spear_pingroup spear3xx_ssp_cs_pingroup; -extern struct spear_pingroup spear3xx_ssp_pingroup; -extern struct spear_pingroup spear3xx_timer_0_1_pingroup; -extern struct spear_pingroup spear3xx_timer_2_3_pingroup; -extern struct spear_pingroup spear3xx_uart0_ext_pingroup; -extern struct spear_pingroup spear3xx_uart0_pingroup; - -#define SPEAR3XX_COMMON_PINGROUPS \ - &spear3xx_firda_pingroup, \ - &spear3xx_gpio0_pin0_pingroup, \ - &spear3xx_gpio0_pin1_pingroup, \ - &spear3xx_gpio0_pin2_pingroup, \ - &spear3xx_gpio0_pin3_pingroup, \ - &spear3xx_gpio0_pin4_pingroup, \ - &spear3xx_gpio0_pin5_pingroup, \ - &spear3xx_i2c_pingroup, \ - &spear3xx_mii_pingroup, \ - &spear3xx_ssp_cs_pingroup, \ - &spear3xx_ssp_pingroup, \ - &spear3xx_timer_0_1_pingroup, \ - &spear3xx_timer_2_3_pingroup, \ - &spear3xx_uart0_ext_pingroup, \ - &spear3xx_uart0_pingroup - -extern struct spear_function spear3xx_firda_function; -extern struct spear_function spear3xx_gpio0_function; -extern struct spear_function spear3xx_i2c_function; -extern struct spear_function spear3xx_mii_function; -extern struct spear_function spear3xx_ssp_cs_function; -extern struct spear_function spear3xx_ssp_function; -extern struct spear_function spear3xx_timer_0_1_function; -extern struct spear_function spear3xx_timer_2_3_function; -extern struct spear_function spear3xx_uart0_ext_function; -extern struct spear_function spear3xx_uart0_function; - -#define SPEAR3XX_COMMON_FUNCTIONS \ - &spear3xx_firda_function, \ - &spear3xx_gpio0_function, \ - &spear3xx_i2c_function, \ - &spear3xx_mii_function, \ - &spear3xx_ssp_cs_function, \ - &spear3xx_ssp_function, \ - &spear3xx_timer_0_1_function, \ - &spear3xx_timer_2_3_function, \ - &spear3xx_uart0_ext_function, \ - &spear3xx_uart0_function - -extern struct spear_pinctrl_machdata spear3xx_machdata; - -#endif /* __PINMUX_SPEAR3XX_H__ */ diff --git a/trunk/drivers/usb/host/ehci-tegra.c b/trunk/drivers/usb/host/ehci-tegra.c index 826c2fd8c402..86183366647f 100644 --- a/trunk/drivers/usb/host/ehci-tegra.c +++ b/trunk/drivers/usb/host/ehci-tegra.c @@ -581,16 +581,15 @@ static const struct hc_driver tegra_ehci_hc_driver = { .port_handed_over = ehci_port_handed_over, }; -static int setup_vbus_gpio(struct platform_device *pdev, - struct tegra_ehci_platform_data *pdata) +static int setup_vbus_gpio(struct platform_device *pdev) { int err = 0; int gpio; - gpio = pdata->vbus_gpio; - if (!gpio_is_valid(gpio)) - gpio = of_get_named_gpio(pdev->dev.of_node, - "nvidia,vbus-gpio", 0); + if (!pdev->dev.of_node) + return 0; + + gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0); if (!gpio_is_valid(gpio)) return 0; @@ -634,7 +633,7 @@ static int tegra_ehci_probe(struct platform_device *pdev) if (!pdev->dev.dma_mask) pdev->dev.dma_mask = &tegra_ehci_dma_mask; - setup_vbus_gpio(pdev, pdata); + setup_vbus_gpio(pdev); tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); if (!tegra) diff --git a/trunk/include/linux/clk.h b/trunk/include/linux/clk.h index 70cf722ac3af..b0252726df61 100644 --- a/trunk/include/linux/clk.h +++ b/trunk/include/linux/clk.h @@ -100,26 +100,6 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb); */ struct clk *clk_get(struct device *dev, const char *id); -/** - * devm_clk_get - lookup and obtain a managed reference to a clock producer. - * @dev: device for clock "consumer" - * @id: clock comsumer ID - * - * Returns a struct clk corresponding to the clock producer, or - * valid IS_ERR() condition containing errno. The implementation - * uses @dev and @id to determine the clock consumer, and thereby - * the clock producer. (IOW, @id may be identical strings, but - * clk_get may return different clock producers depending on @dev.) - * - * Drivers must assume that the clock source is not enabled. - * - * devm_clk_get should not be called from within interrupt context. - * - * The clock will automatically be freed when the device is unbound - * from the bus. - */ -struct clk *devm_clk_get(struct device *dev, const char *id); - /** * clk_prepare - prepare a clock source * @clk: clock source @@ -226,18 +206,6 @@ unsigned long clk_get_rate(struct clk *clk); */ void clk_put(struct clk *clk); -/** - * devm_clk_put - "free" a managed clock source - * @dev: device used to acuqire the clock - * @clk: clock source acquired with devm_clk_get() - * - * Note: drivers must ensure that all clk_enable calls made on this - * clock source are balanced by clk_disable calls prior to calling - * this function. - * - * clk_put should not be called from within interrupt context. - */ -void devm_clk_put(struct device *dev, struct clk *clk); /* * The remaining APIs are optional for machine class support. diff --git a/trunk/include/linux/clkdev.h b/trunk/include/linux/clkdev.h index a6a6f603103b..d9a4fd028c9d 100644 --- a/trunk/include/linux/clkdev.h +++ b/trunk/include/linux/clkdev.h @@ -40,7 +40,4 @@ void clkdev_drop(struct clk_lookup *cl); void clkdev_add_table(struct clk_lookup *, size_t); int clk_add_alias(const char *, const char *, char *, struct device *); -int clk_register_clkdev(struct clk *, const char *, const char *, ...); -int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t); - #endif diff --git a/trunk/include/linux/of.h b/trunk/include/linux/of.h index 2ec1083af7ff..fa7fb1d97458 100644 --- a/trunk/include/linux/of.h +++ b/trunk/include/linux/of.h @@ -193,17 +193,6 @@ extern struct device_node *of_get_next_child(const struct device_node *node, for (child = of_get_next_child(parent, NULL); child != NULL; \ child = of_get_next_child(parent, child)) -static inline int of_get_child_count(const struct device_node *np) -{ - struct device_node *child; - int num = 0; - - for_each_child_of_node(np, child) - num++; - - return num; -} - extern struct device_node *of_find_node_with_property( struct device_node *from, const char *prop_name); #define for_each_node_with_property(dn, prop_name) \ @@ -270,37 +259,6 @@ extern void of_detach_node(struct device_node *); #endif #define of_match_ptr(_ptr) (_ptr) - -/* - * struct property *prop; - * const __be32 *p; - * u32 u; - * - * of_property_for_each_u32(np, "propname", prop, p, u) - * printk("U32 value: %x\n", u); - */ -const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur, - u32 *pu); -#define of_property_for_each_u32(np, propname, prop, p, u) \ - for (prop = of_find_property(np, propname, NULL), \ - p = of_prop_next_u32(prop, NULL, &u); \ - p; \ - p = of_prop_next_u32(prop, p, &u)) - -/* - * struct property *prop; - * const char *s; - * - * of_property_for_each_string(np, "propname", prop, s) - * printk("String value: %s\n", s); - */ -const char *of_prop_next_string(struct property *prop, const char *cur); -#define of_property_for_each_string(np, propname, prop, s) \ - for (prop = of_find_property(np, propname, NULL), \ - s = of_prop_next_string(prop, NULL); \ - s; \ - s = of_prop_next_string(prop, s)) - #else /* CONFIG_OF */ static inline bool of_have_populated_dt(void) @@ -311,11 +269,6 @@ static inline bool of_have_populated_dt(void) #define for_each_child_of_node(parent, child) \ while (0) -static inline int of_get_child_count(const struct device_node *np) -{ - return 0; -} - static inline int of_device_is_compatible(const struct device_node *device, const char *name) { @@ -396,10 +349,6 @@ static inline int of_machine_is_compatible(const char *compat) #define of_match_ptr(_ptr) NULL #define of_match_node(_matches, _node) NULL -#define of_property_for_each_u32(np, propname, prop, p, u) \ - while (0) -#define of_property_for_each_string(np, propname, prop, s) \ - while (0) #endif /* CONFIG_OF */ /** diff --git a/trunk/include/linux/pinctrl/consumer.h b/trunk/include/linux/pinctrl/consumer.h index 6dd96fb45482..191e72688481 100644 --- a/trunk/include/linux/pinctrl/consumer.h +++ b/trunk/include/linux/pinctrl/consumer.h @@ -36,9 +36,6 @@ extern struct pinctrl_state * __must_check pinctrl_lookup_state( const char *name); extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s); -extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev); -extern void devm_pinctrl_put(struct pinctrl *p); - #else /* !CONFIG_PINCTRL */ static inline int pinctrl_request_gpio(unsigned gpio) @@ -82,15 +79,6 @@ static inline int pinctrl_select_state(struct pinctrl *p, return 0; } -static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev) -{ - return NULL; -} - -static inline void devm_pinctrl_put(struct pinctrl *p) -{ -} - #endif /* CONFIG_PINCTRL */ static inline struct pinctrl * __must_check pinctrl_get_select( @@ -125,38 +113,6 @@ static inline struct pinctrl * __must_check pinctrl_get_select_default( return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); } -static inline struct pinctrl * __must_check devm_pinctrl_get_select( - struct device *dev, const char *name) -{ - struct pinctrl *p; - struct pinctrl_state *s; - int ret; - - p = devm_pinctrl_get(dev); - if (IS_ERR(p)) - return p; - - s = pinctrl_lookup_state(p, name); - if (IS_ERR(s)) { - devm_pinctrl_put(p); - return ERR_PTR(PTR_ERR(s)); - } - - ret = pinctrl_select_state(p, s); - if (ret < 0) { - devm_pinctrl_put(p); - return ERR_PTR(ret); - } - - return p; -} - -static inline struct pinctrl * __must_check devm_pinctrl_get_select_default( - struct device *dev) -{ - return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); -} - #ifdef CONFIG_PINCONF extern int pin_config_get(const char *dev_name, const char *name, diff --git a/trunk/include/linux/pinctrl/machine.h b/trunk/include/linux/pinctrl/machine.h index 7d22ab00343f..e4d1de742502 100644 --- a/trunk/include/linux/pinctrl/machine.h +++ b/trunk/include/linux/pinctrl/machine.h @@ -154,7 +154,7 @@ struct pinctrl_map { extern int pinctrl_register_mappings(struct pinctrl_map const *map, unsigned num_maps); -extern void pinctrl_provide_dummies(void); + #else static inline int pinctrl_register_mappings(struct pinctrl_map const *map, @@ -163,8 +163,5 @@ static inline int pinctrl_register_mappings(struct pinctrl_map const *map, return 0; } -static inline void pinctrl_provide_dummies(void) -{ -} -#endif /* !CONFIG_PINCTRL */ +#endif /* !CONFIG_PINMUX */ #endif diff --git a/trunk/include/linux/pinctrl/pinconf.h b/trunk/include/linux/pinctrl/pinconf.h index e7a720104a47..ec431f03362d 100644 --- a/trunk/include/linux/pinctrl/pinconf.h +++ b/trunk/include/linux/pinctrl/pinconf.h @@ -25,6 +25,7 @@ struct seq_file; * @pin_config_get: get the config of a certain pin, if the requested config * is not available on this controller this should return -ENOTSUPP * and if it is available but disabled it should return -EINVAL + * @pin_config_get: get the config of a certain pin * @pin_config_set: configure an individual pin * @pin_config_group_get: get configurations for an entire pin group * @pin_config_group_set: configure all pins in a group @@ -32,8 +33,6 @@ struct seq_file; * per-device info for a certain pin in debugfs * @pin_config_group_dbg_show: optional debugfs display hook that will provide * per-device info for a certain group in debugfs - * @pin_config_config_dbg_show: optional debugfs display hook that will decode - * and display a driver's pin configuration parameter */ struct pinconf_ops { #ifdef CONFIG_GENERIC_PINCONF @@ -57,9 +56,6 @@ struct pinconf_ops { void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s, unsigned selector); - void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned long config); }; #endif diff --git a/trunk/include/linux/pinctrl/pinctrl-state.h b/trunk/include/linux/pinctrl/pinctrl-state.h index 634608dc6c89..3920e28b4da7 100644 --- a/trunk/include/linux/pinctrl/pinctrl-state.h +++ b/trunk/include/linux/pinctrl/pinctrl-state.h @@ -2,18 +2,5 @@ * Standard pin control state definitions */ -/** - * @PINCTRL_STATE_DEFAULT: the state the pinctrl handle shall be put - * into as default, usually this means the pins are up and ready to - * be used by the device driver. This state is commonly used by - * hogs to configure muxing and pins at boot. - * @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into - * when the pins are idle. Could typically be set from a - * pm_runtime_suspend() operation. - * @PINCTRL_STATE_SLEEP: the state the pinctrl handle shall be put into - * when the pins are sleeping. Could typically be set from a - * common suspend() function. - */ #define PINCTRL_STATE_DEFAULT "default" #define PINCTRL_STATE_IDLE "idle" -#define PINCTRL_STATE_SLEEP "sleep" diff --git a/trunk/include/linux/pinctrl/pinctrl.h b/trunk/include/linux/pinctrl/pinctrl.h index 3b894a668d32..4e9f0788c221 100644 --- a/trunk/include/linux/pinctrl/pinctrl.h +++ b/trunk/include/linux/pinctrl/pinctrl.h @@ -21,11 +21,9 @@ struct device; struct pinctrl_dev; -struct pinctrl_map; struct pinmux_ops; struct pinconf_ops; struct gpio_chip; -struct device_node; /** * struct pinctrl_pin_desc - boards/machines provide information on their @@ -66,24 +64,17 @@ struct pinctrl_gpio_range { /** * struct pinctrl_ops - global pin control operations, to be implemented by * pin controller drivers. - * @get_groups_count: Returns the count of total number of groups registered. + * @list_groups: list the number of selectable named groups available + * in this pinmux driver, the core will begin on 0 and call this + * repeatedly as long as it returns >= 0 to enumerate the groups * @get_group_name: return the group name of the pin group * @get_group_pins: return an array of pins corresponding to a certain * group selector @pins, and the size of the array in @num_pins * @pin_dbg_show: optional debugfs display hook that will provide per-device * info for a certain pin in debugfs - * @dt_node_to_map: parse a device tree "pin configuration node", and create - * mapping table entries for it. These are returned through the @map and - * @num_maps output parameters. This function is optional, and may be - * omitted for pinctrl drivers that do not support device tree. - * @dt_free_map: free mapping table entries created via @dt_node_to_map. The - * top-level @map pointer must be freed, along with any dynamically - * allocated members of the mapping table entries themselves. This - * function is optional, and may be omitted for pinctrl drivers that do - * not support device tree. */ struct pinctrl_ops { - int (*get_groups_count) (struct pinctrl_dev *pctldev); + int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector); const char *(*get_group_name) (struct pinctrl_dev *pctldev, unsigned selector); int (*get_group_pins) (struct pinctrl_dev *pctldev, @@ -92,11 +83,6 @@ struct pinctrl_ops { unsigned *num_pins); void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset); - int (*dt_node_to_map) (struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps); - void (*dt_free_map) (struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps); }; /** diff --git a/trunk/include/linux/pinctrl/pinmux.h b/trunk/include/linux/pinctrl/pinmux.h index 1818dcbdd9ab..47e9237edd47 100644 --- a/trunk/include/linux/pinctrl/pinmux.h +++ b/trunk/include/linux/pinctrl/pinmux.h @@ -23,14 +23,15 @@ struct pinctrl_dev; /** * struct pinmux_ops - pinmux operations, to be implemented by pin controller * drivers that support pinmuxing - * @request: called by the core to see if a certain pin can be made + * @request: called by the core to see if a certain pin can be made available * available for muxing. This is called by the core to acquire the pins * before selecting any actual mux setting across a function. The driver * is allowed to answer "no" by returning a negative error code * @free: the reverse function of the request() callback, frees a pin after * being requested - * @get_functions_count: returns number of selectable named functions available - * in this pinmux driver + * @list_functions: list the number of selectable named functions available + * in this pinmux driver, the core will begin on 0 and call this + * repeatedly as long as it returns >= 0 to enumerate mux settings * @get_function_name: return the function name of the muxing selector, * called by the core to figure out which mux setting it shall map a * certain device to @@ -61,7 +62,7 @@ struct pinctrl_dev; struct pinmux_ops { int (*request) (struct pinctrl_dev *pctldev, unsigned offset); int (*free) (struct pinctrl_dev *pctldev, unsigned offset); - int (*get_functions_count) (struct pinctrl_dev *pctldev); + int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector); const char *(*get_function_name) (struct pinctrl_dev *pctldev, unsigned selector); int (*get_function_groups) (struct pinctrl_dev *pctldev, diff --git a/trunk/include/linux/platform_data/tegra_usb.h b/trunk/include/linux/platform_data/tegra_usb.h index 66c673fef408..6bca5b569acb 100644 --- a/trunk/include/linux/platform_data/tegra_usb.h +++ b/trunk/include/linux/platform_data/tegra_usb.h @@ -26,7 +26,6 @@ struct tegra_ehci_platform_data { /* power down the phy on bus suspend */ int power_down_on_bus_suspend; void *phy_config; - int vbus_gpio; }; #endif /* _TEGRA_USB_H_ */