From 992ecb4a6e0df4395d2864e2f3c76185cccea1cb Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 27 May 2011 15:50:59 +1000 Subject: [PATCH] --- yaml --- r: 260104 b: refs/heads/master c: 752ab0a0927add86c8b6604e01147041509b2af4 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 8434aa13ce7e..56860f0d3471 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2b6f1c5f17305dd5d9b1c566be31101a66fae4c9 +refs/heads/master: 752ab0a0927add86c8b6604e01147041509b2af4 diff --git a/trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c b/trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c index f2f9825ab0a6..31018eaf5279 100644 --- a/trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c +++ b/trunk/drivers/gpu/drm/nouveau/nvc0_grctx.c @@ -1783,10 +1783,11 @@ nvc0_grctx_generate(struct nouveau_channel *chan) nv_wr32(dev, 0x40587c, 0x00000000); if (1) { - const u8 chipset_tp_max[] = { 16, 0, 0, 4, 8 }; + const u8 chipset_tp_max[] = { 16, 4, 0, 4, 8, 0, 0, 0, + 16, 0, 0, 0, 0, 0, 8, 0 }; u8 max = chipset_tp_max[dev_priv->chipset & 0x0f]; u8 tpnr[GPC_MAX]; - u8 data[32]; + u8 data[TP_MAX]; memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr)); memset(data, 0x1f, sizeof(data));