From 99f5e3cabadf3806c066e46a0420bdff8fb7a28c Mon Sep 17 00:00:00 2001 From: Muli Ben-Yehuda Date: Tue, 26 Sep 2006 10:52:33 +0200 Subject: [PATCH] --- yaml --- r: 35863 b: refs/heads/master c: de684652f34f57cb60d4d78d09139a0e0c5e7b1b h: refs/heads/master i: 35861: 5fe339ebe6ee098cd6b469fabf43fe5d237bad8c 35859: 59a093bf9af8c8fa665479fbec5a9c4d9b6a3780 35855: 78ff09ce066fa74fba72e70c9c54411daab79658 v: v3 --- [refs] | 2 +- trunk/arch/x86_64/kernel/pci-calgary.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index a996542bd6cb..443a1b46c2c1 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2ade2920dcefdf5595c6380ebed131c964190855 +refs/heads/master: de684652f34f57cb60d4d78d09139a0e0c5e7b1b diff --git a/trunk/arch/x86_64/kernel/pci-calgary.c b/trunk/arch/x86_64/kernel/pci-calgary.c index caf84e4e4ca9..ebe4e930b64d 100644 --- a/trunk/arch/x86_64/kernel/pci-calgary.c +++ b/trunk/arch/x86_64/kernel/pci-calgary.c @@ -127,15 +127,19 @@ static void tce_cache_blast(struct iommu_table *tbl); /* enable this to stress test the chip's TCE cache */ #ifdef CONFIG_IOMMU_DEBUG +int debugging __read_mostly = 1; + static inline void tce_cache_blast_stress(struct iommu_table *tbl) { tce_cache_blast(tbl); } -#else +#else /* debugging is disabled */ +int debugging __read_mostly = 0; + static inline void tce_cache_blast_stress(struct iommu_table *tbl) { } -#endif /* BLAST_TCE_CACHE_ON_UNMAP */ +#endif /* CONFIG_IOMMU_DEBUG */ static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen) { @@ -944,8 +948,10 @@ void __init detect_calgary(void) if (calgary_found) { iommu_detected = 1; calgary_detected = 1; - printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected. " - "TCE table spec is %d.\n", specified_table_size); + printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); + printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " + "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, + debugging ? "enabled" : "disabled"); } return;