From 9a258f38036b2028971f40f3f1c74ace4dcce8e3 Mon Sep 17 00:00:00 2001 From: Krzysztof Helt Date: Sat, 10 Jun 2006 22:03:43 -0700 Subject: [PATCH] --- yaml --- r: 27182 b: refs/heads/master c: 650fb8382287f7990d5127a82a54295139224606 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/sparc/kernel/smp.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 387a86aa3e0c..3f29fd86bb80 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9145bcf63575a8b78590a5beaf604001e9c8d2ef +refs/heads/master: 650fb8382287f7990d5127a82a54295139224606 diff --git a/trunk/arch/sparc/kernel/smp.c b/trunk/arch/sparc/kernel/smp.c index a93f5da6855d..40b42c88e6a7 100644 --- a/trunk/arch/sparc/kernel/smp.c +++ b/trunk/arch/sparc/kernel/smp.c @@ -69,6 +69,17 @@ void __init smp_store_cpu_info(int id) "clock-frequency", 0); cpu_data(id).prom_node = cpu_node; cpu_data(id).mid = cpu_get_hwmid(cpu_node); + + /* this is required to tune the scheduler correctly */ + /* is it possible to have CPUs with different cache sizes? */ + if (id == boot_cpu_id) { + int cache_line,cache_nlines; + cache_line = 0x20; + cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line); + cache_nlines = 0x8000; + cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines); + max_cache_size = cache_line * cache_nlines; + } if (cpu_data(id).mid < 0) panic("No MID found for CPU%d at node 0x%08d", id, cpu_node); }