From 9a44836b0554dc56aa3a001ffa38721363388c50 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 8 Apr 2008 17:41:58 -0700 Subject: [PATCH] --- yaml --- r: 88207 b: refs/heads/master c: 6395bee7e92bf34e95dc67c1da5acc30e8b98244 h: refs/heads/master i: 88205: cd2c3a9b1e42a69bc126f3132aa1042f926b1c32 88203: 2f9d839a1dfe321c882841559112d07b66960a7a 88199: 3868f627639866b257daad1be3b612249e3efcad 88191: 4dc3125d74f3dfb5af7f365fbcb4cc5d50148ed7 v: v3 --- [refs] | 2 +- trunk/Documentation/spi/spi-summary | 15 ++++++++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index e465457d9b26..6f8c324bb3ea 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f9e522caece074b9a985436d611127e8e96ad446 +refs/heads/master: 6395bee7e92bf34e95dc67c1da5acc30e8b98244 diff --git a/trunk/Documentation/spi/spi-summary b/trunk/Documentation/spi/spi-summary index 8861e47e5a2d..6d5f18143c50 100644 --- a/trunk/Documentation/spi/spi-summary +++ b/trunk/Documentation/spi/spi-summary @@ -116,6 +116,13 @@ low order bit. So when a chip's timing diagram shows the clock starting low (CPOL=0) and data stabilized for sampling during the trailing clock edge (CPHA=1), that's SPI mode 1. +Note that the clock mode is relevant as soon as the chipselect goes +active. So the master must set the clock to inactive before selecting +a slave, and the slave can tell the chosen polarity by sampling the +clock level when its select line goes active. That's why many devices +support for example both modes 0 and 3: they don't care about polarity, +and alway clock data in/out on rising clock edges. + How do these driver programming interfaces work? ------------------------------------------------ @@ -379,8 +386,14 @@ any more such messages. + when bidirectional reads and writes start ... by how its sequence of spi_transfer requests is arranged; + + which I/O buffers are used ... each spi_transfer wraps a + buffer for each transfer direction, supporting full duplex + (two pointers, maybe the same one in both cases) and half + duplex (one pointer is NULL) transfers; + + optionally defining short delays after transfers ... using - the spi_transfer.delay_usecs setting; + the spi_transfer.delay_usecs setting (this delay can be the + only protocol effect, if the buffer length is zero); + whether the chipselect becomes inactive after a transfer and any delay ... by using the spi_transfer.cs_change flag;