From 9a5795deb8a926a75617556f0c5140a3eb0020fc Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 20 Jan 2012 12:10:18 +0100 Subject: [PATCH] --- yaml --- r: 286899 b: refs/heads/master c: 612539e81f655f6ac73c7af1da8701c1ee618aee h: refs/heads/master i: 286897: e40afbda54516ae6b9fc7b66f7b38b8598059a5f 286895: 1cf0ecec2eb72334c7e8fe68d227aca4560fc174 v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/proc-v7.S | 6 ------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/[refs] b/[refs] index 874b00f62a0c..c071b679e974 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 868dbf905245a524496a0535982ed21ad3be5585 +refs/heads/master: 612539e81f655f6ac73c7af1da8701c1ee618aee diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S index b15597400105..0404ccbb8aa3 100644 --- a/trunk/arch/arm/mm/proc-v7.S +++ b/trunk/arch/arm/mm/proc-v7.S @@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume) * Initialise TLB, Caches, and MMU state ready to switch the MMU * on. Return in r0 the new CP15 C1 control register setting. * - * We automatically detect if we have a Harvard cache, and use the - * Harvard cache control instructions insead of the unified cache - * control instructions. - * * This should be able to cover all ARMv7 cores. * * It is assumed that: @@ -251,9 +247,7 @@ __v7_setup: #endif 3: mov r10, #0 -#ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate -#endif dsb #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs