From 9b4666a1054dd107ba93f45e9a3c6d192e33d93f Mon Sep 17 00:00:00 2001 From: Inderpal Singh Date: Wed, 17 Oct 2012 11:48:55 +0530 Subject: [PATCH] --- yaml --- r: 345031 b: refs/heads/master c: 5e393a2227ba97408ffb98d62cf362dfe2a59baa h: refs/heads/master i: 345029: 7ff9e0e9c5637d0ee6b38c6e08bfad8c62201ccd 345027: 02d817975a0a4e06c185bbd1c0a5e4436d9e596b 345023: e8e0d794cee99ccf99451dbc8c2891de1731e1ca v: v3 --- [refs] | 2 +- trunk/drivers/mfd/sec-irq.c | 102 ++++++++++++++++++------------------ 2 files changed, 52 insertions(+), 52 deletions(-) diff --git a/[refs] b/[refs] index bebdb6f85782..26495749cc2d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fee546ce8cfd9dea1f53175f627e17ef5ff05df4 +refs/heads/master: 5e393a2227ba97408ffb98d62cf362dfe2a59baa diff --git a/trunk/drivers/mfd/sec-irq.c b/trunk/drivers/mfd/sec-irq.c index c901fa50fea1..0dd84e99081e 100644 --- a/trunk/drivers/mfd/sec-irq.c +++ b/trunk/drivers/mfd/sec-irq.c @@ -24,67 +24,67 @@ static struct regmap_irq s2mps11_irqs[] = { [S2MPS11_IRQ_PWRONF] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S2MPS11_IRQ_PWRONF_MASK, }, [S2MPS11_IRQ_PWRONR] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S2MPS11_IRQ_PWRONR_MASK, }, [S2MPS11_IRQ_JIGONBF] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S2MPS11_IRQ_JIGONBF_MASK, }, [S2MPS11_IRQ_JIGONBR] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S2MPS11_IRQ_JIGONBR_MASK, }, [S2MPS11_IRQ_ACOKBF] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S2MPS11_IRQ_ACOKBF_MASK, }, [S2MPS11_IRQ_ACOKBR] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S2MPS11_IRQ_ACOKBR_MASK, }, [S2MPS11_IRQ_PWRON1S] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S2MPS11_IRQ_PWRON1S_MASK, }, [S2MPS11_IRQ_MRB] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S2MPS11_IRQ_MRB_MASK, }, [S2MPS11_IRQ_RTC60S] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S2MPS11_IRQ_RTC60S_MASK, }, [S2MPS11_IRQ_RTCA1] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S2MPS11_IRQ_RTCA1_MASK, }, [S2MPS11_IRQ_RTCA2] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S2MPS11_IRQ_RTCA2_MASK, }, [S2MPS11_IRQ_SMPL] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S2MPS11_IRQ_SMPL_MASK, }, [S2MPS11_IRQ_RTC1S] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S2MPS11_IRQ_RTC1S_MASK, }, [S2MPS11_IRQ_WTSR] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S2MPS11_IRQ_WTSR_MASK, }, [S2MPS11_IRQ_INT120C] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S2MPS11_IRQ_INT120C_MASK, }, [S2MPS11_IRQ_INT140C] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S2MPS11_IRQ_INT140C_MASK, }, }; @@ -92,146 +92,146 @@ static struct regmap_irq s2mps11_irqs[] = { static struct regmap_irq s5m8767_irqs[] = { [S5M8767_IRQ_PWRR] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8767_IRQ_PWRR_MASK, }, [S5M8767_IRQ_PWRF] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8767_IRQ_PWRF_MASK, }, [S5M8767_IRQ_PWR1S] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8767_IRQ_PWR1S_MASK, }, [S5M8767_IRQ_JIGR] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8767_IRQ_JIGR_MASK, }, [S5M8767_IRQ_JIGF] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8767_IRQ_JIGF_MASK, }, [S5M8767_IRQ_LOWBAT2] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8767_IRQ_LOWBAT2_MASK, }, [S5M8767_IRQ_LOWBAT1] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8767_IRQ_LOWBAT1_MASK, }, [S5M8767_IRQ_MRB] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S5M8767_IRQ_MRB_MASK, }, [S5M8767_IRQ_DVSOK2] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S5M8767_IRQ_DVSOK2_MASK, }, [S5M8767_IRQ_DVSOK3] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S5M8767_IRQ_DVSOK3_MASK, }, [S5M8767_IRQ_DVSOK4] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S5M8767_IRQ_DVSOK4_MASK, }, [S5M8767_IRQ_RTC60S] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8767_IRQ_RTC60S_MASK, }, [S5M8767_IRQ_RTCA1] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8767_IRQ_RTCA1_MASK, }, [S5M8767_IRQ_RTCA2] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8767_IRQ_RTCA2_MASK, }, [S5M8767_IRQ_SMPL] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8767_IRQ_SMPL_MASK, }, [S5M8767_IRQ_RTC1S] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8767_IRQ_RTC1S_MASK, }, [S5M8767_IRQ_WTSR] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8767_IRQ_WTSR_MASK, }, }; static struct regmap_irq s5m8763_irqs[] = { [S5M8763_IRQ_DCINF] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8763_IRQ_DCINF_MASK, }, [S5M8763_IRQ_DCINR] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8763_IRQ_DCINR_MASK, }, [S5M8763_IRQ_JIGF] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8763_IRQ_JIGF_MASK, }, [S5M8763_IRQ_JIGR] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8763_IRQ_JIGR_MASK, }, [S5M8763_IRQ_PWRONF] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8763_IRQ_PWRONF_MASK, }, [S5M8763_IRQ_PWRONR] = { - .reg_offset = 1, + .reg_offset = 0, .mask = S5M8763_IRQ_PWRONR_MASK, }, [S5M8763_IRQ_WTSREVNT] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S5M8763_IRQ_WTSREVNT_MASK, }, [S5M8763_IRQ_SMPLEVNT] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S5M8763_IRQ_SMPLEVNT_MASK, }, [S5M8763_IRQ_ALARM1] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S5M8763_IRQ_ALARM1_MASK, }, [S5M8763_IRQ_ALARM0] = { - .reg_offset = 2, + .reg_offset = 1, .mask = S5M8763_IRQ_ALARM0_MASK, }, [S5M8763_IRQ_ONKEY1S] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8763_IRQ_ONKEY1S_MASK, }, [S5M8763_IRQ_TOPOFFR] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8763_IRQ_TOPOFFR_MASK, }, [S5M8763_IRQ_DCINOVPR] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8763_IRQ_DCINOVPR_MASK, }, [S5M8763_IRQ_CHGRSTF] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8763_IRQ_CHGRSTF_MASK, }, [S5M8763_IRQ_DONER] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8763_IRQ_DONER_MASK, }, [S5M8763_IRQ_CHGFAULT] = { - .reg_offset = 3, + .reg_offset = 2, .mask = S5M8763_IRQ_CHGFAULT_MASK, }, [S5M8763_IRQ_LOBAT1] = { - .reg_offset = 4, + .reg_offset = 3, .mask = S5M8763_IRQ_LOBAT1_MASK, }, [S5M8763_IRQ_LOBAT2] = { - .reg_offset = 4, + .reg_offset = 3, .mask = S5M8763_IRQ_LOBAT2_MASK, }, };