From 9ba3380659ca48f949868c078d4497947ba130a3 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 27 Jul 2010 15:06:58 +0300 Subject: [PATCH] --- yaml --- r: 212573 b: refs/heads/master c: 69f22be7b10684ade3808de22db87c536ed135f3 h: refs/heads/master i: 212571: e05fdf2fdd24f3cefc268bf1eac8a4a58f25ce40 v: v3 --- [refs] | 2 +- trunk/MAINTAINERS | 7 - trunk/arch/arm/Kconfig | 25 - trunk/arch/arm/Kconfig.debug | 14 - trunk/arch/arm/Makefile | 9 +- trunk/arch/arm/common/gic.c | 14 + .../arch/arm/configs/at91sam9g20ek_defconfig | 1 - trunk/arch/arm/configs/kirkwood_defconfig | 1 - trunk/arch/arm/configs/mx27_defconfig | 15 +- trunk/arch/arm/configs/mx31pdk_defconfig | 44 + trunk/arch/arm/configs/mx3_defconfig | 2 +- trunk/arch/arm/configs/mx51_defconfig | 9 +- trunk/arch/arm/include/asm/elf.h | 4 - trunk/arch/arm/include/asm/io.h | 1 - trunk/arch/arm/include/asm/mmu_context.h | 29 +- trunk/arch/arm/include/asm/seccomp.h | 11 - trunk/arch/arm/include/asm/thread_info.h | 2 - trunk/arch/arm/kernel/entry-common.S | 15 +- trunk/arch/arm/kernel/process.c | 21 - .../arm/mach-aaec2000/include/mach/vmalloc.h | 2 +- trunk/arch/arm/mach-at91/Kconfig | 9 +- trunk/arch/arm/mach-at91/Makefile | 3 +- .../arch/arm/mach-at91/board-at572d940hf_ek.c | 2 +- .../arm/mach-at91/board-sam9g20ek-2slot-mmc.c | 329 +++++++ trunk/arch/arm/mach-at91/board-sam9g20ek.c | 74 +- trunk/arch/arm/mach-at91/board-sam9m10g45ek.c | 4 +- .../arch/arm/mach-at91/include/mach/at91x40.h | 6 - .../arch/arm/mach-at91/include/mach/system.h | 4 - .../arm/mach-bcmring/include/mach/vmalloc.h | 2 +- .../arm/mach-clps711x/include/mach/vmalloc.h | 2 +- .../arm/mach-ebsa110/include/mach/vmalloc.h | 2 +- .../mach-footbridge/include/mach/vmalloc.h | 2 +- .../arm/mach-h720x/include/mach/vmalloc.h | 2 +- trunk/arch/arm/mach-imx/Kconfig | 14 +- trunk/arch/arm/mach-imx/Makefile | 1 - trunk/arch/arm/mach-imx/clock-imx1.c | 2 +- trunk/arch/arm/mach-imx/clock-imx21.c | 6 +- trunk/arch/arm/mach-imx/clock-imx27.c | 48 +- trunk/arch/arm/mach-imx/devices-imx1.h | 14 +- trunk/arch/arm/mach-imx/devices-imx21.h | 36 +- trunk/arch/arm/mach-imx/devices-imx27.h | 51 +- trunk/arch/arm/mach-imx/devices.c | 56 ++ trunk/arch/arm/mach-imx/devices.h | 3 + .../arm/mach-imx/eukrea_mbimx27-baseboard.c | 8 +- trunk/arch/arm/mach-imx/mach-cpuimx27.c | 6 +- .../arm/mach-imx/mach-imx27_visstrim_m10.c | 263 ------ trunk/arch/arm/mach-imx/mach-imx27lite.c | 8 +- trunk/arch/arm/mach-imx/mach-mx1ads.c | 4 +- trunk/arch/arm/mach-imx/mach-mx21ads.c | 2 +- trunk/arch/arm/mach-imx/mach-mx27_3ds.c | 8 +- trunk/arch/arm/mach-imx/mach-mx27ads.c | 6 +- trunk/arch/arm/mach-imx/mach-mxt_td60.c | 13 +- trunk/arch/arm/mach-imx/mach-pca100.c | 15 +- trunk/arch/arm/mach-imx/mach-pcm038.c | 8 +- trunk/arch/arm/mach-imx/mach-scb9328.c | 2 +- trunk/arch/arm/mach-imx/pcm970-baseboard.c | 4 +- .../mach-integrator/include/mach/vmalloc.h | 2 +- trunk/arch/arm/mach-kirkwood/Kconfig | 12 - trunk/arch/arm/mach-kirkwood/Makefile | 12 +- trunk/arch/arm/mach-kirkwood/d2net_v2-setup.c | 231 ----- trunk/arch/arm/mach-kirkwood/dockstar-setup.c | 112 --- .../mach-kirkwood/include/mach/leds-netxbig.h | 55 -- .../arch/arm/mach-kirkwood/lacie_v2-common.c | 127 --- .../arch/arm/mach-kirkwood/lacie_v2-common.h | 18 - .../arm/mach-kirkwood/netspace_v2-setup.c | 122 ++- .../arch/arm/mach-kirkwood/netxbig_v2-setup.c | 269 +++--- trunk/arch/arm/mach-kirkwood/openrd-setup.c | 101 +-- .../arch/arm/mach-msm/include/mach/vmalloc.h | 2 +- trunk/arch/arm/mach-mx25/Kconfig | 6 +- trunk/arch/arm/mach-mx25/clock.c | 28 +- trunk/arch/arm/mach-mx25/devices-imx25.h | 62 +- trunk/arch/arm/mach-mx25/devices.c | 58 ++ trunk/arch/arm/mach-mx25/devices.h | 3 + .../arm/mach-mx25/eukrea_mbimxsd-baseboard.c | 12 +- trunk/arch/arm/mach-mx25/mach-cpuimx25.c | 5 +- trunk/arch/arm/mach-mx25/mach-mx25_3ds.c | 5 +- trunk/arch/arm/mach-mx3/Kconfig | 11 +- trunk/arch/arm/mach-mx3/Makefile | 1 + trunk/arch/arm/mach-mx3/clock-imx31.c | 10 +- trunk/arch/arm/mach-mx3/clock-imx35.c | 28 +- trunk/arch/arm/mach-mx3/cpu.c | 47 +- trunk/arch/arm/mach-mx3/devices-imx31.h | 49 +- trunk/arch/arm/mach-mx3/devices-imx35.h | 51 +- trunk/arch/arm/mach-mx3/devices.c | 63 ++ trunk/arch/arm/mach-mx3/devices.h | 4 + .../arm/mach-mx3/eukrea_mbimxsd-baseboard.c | 19 +- trunk/arch/arm/mach-mx3/mach-cpuimx35.c | 38 +- trunk/arch/arm/mach-mx3/mach-mx31ads.c | 2 +- trunk/arch/arm/mach-mx3/mach-mx35_3ds.c | 51 +- trunk/arch/arm/mach-mx3/mach-pcm043.c | 15 +- trunk/arch/arm/mach-mx3/mm.c | 18 - trunk/arch/arm/mach-mx5/Kconfig | 14 - trunk/arch/arm/mach-mx5/Makefile | 1 - trunk/arch/arm/mach-mx5/board-cpuimx51.c | 14 +- trunk/arch/arm/mach-mx5/board-mx51_3ds.c | 42 +- trunk/arch/arm/mach-mx5/board-mx51_babbage.c | 72 +- trunk/arch/arm/mach-mx5/board-mx51_efikamx.c | 121 --- trunk/arch/arm/mach-mx5/clock-mx51.c | 231 +---- trunk/arch/arm/mach-mx5/cpu.c | 19 - trunk/arch/arm/mach-mx5/devices-imx51.h | 38 - trunk/arch/arm/mach-mx5/devices.c | 114 +++ trunk/arch/arm/mach-mx5/devices.h | 6 + .../arm/mach-mx5/eukrea_mbimx51-baseboard.c | 7 +- .../arch/arm/mach-netx/include/mach/vmalloc.h | 2 +- .../arm/mach-omap1/include/mach/vmalloc.h | 2 +- .../arm/mach-omap2/include/mach/vmalloc.h | 2 +- .../arm/mach-pnx4008/include/mach/vmalloc.h | 2 +- trunk/arch/arm/mach-pxa/Kconfig | 4 + trunk/arch/arm/mach-pxa/Makefile | 2 +- trunk/arch/arm/mach-pxa/devices.c | 28 + trunk/arch/arm/mach-pxa/devices.h | 1 + .../arm/mach-pxa/include/mach/pxa3xx-u2d.h | 35 + trunk/arch/arm/mach-pxa/pxa3xx-ulpi.c | 392 +++++++++ trunk/arch/arm/mach-pxa/pxa3xx.c | 2 +- .../arch/arm/mach-rpc/include/mach/vmalloc.h | 2 +- .../arm/mach-shark/include/mach/vmalloc.h | 2 +- trunk/arch/arm/mach-tcc8k/Kconfig | 11 - trunk/arch/arm/mach-tcc8k/Makefile | 9 - trunk/arch/arm/mach-tcc8k/Makefile.boot | 3 - trunk/arch/arm/mach-tcc8k/board-tcc8000-sdk.c | 64 -- trunk/arch/arm/mach-tcc8k/clock.c | 567 ------------ trunk/arch/arm/mach-tcc8k/common.h | 15 - trunk/arch/arm/mach-tcc8k/devices.c | 239 ------ trunk/arch/arm/mach-tcc8k/io.c | 62 -- trunk/arch/arm/mach-tcc8k/irq.c | 111 --- trunk/arch/arm/mach-tcc8k/time.c | 149 ---- .../arm/mach-versatile/include/mach/vmalloc.h | 2 +- trunk/arch/arm/mm/mmap.c | 22 - trunk/arch/arm/plat-mxc/Kconfig | 12 - trunk/arch/arm/plat-mxc/Makefile | 1 - trunk/arch/arm/plat-mxc/audmux-v2.c | 8 +- trunk/arch/arm/plat-mxc/devices/Kconfig | 10 - trunk/arch/arm/plat-mxc/devices/Makefile | 9 +- .../arm/plat-mxc/devices/platform-esdhc.c | 31 - .../arch/arm/plat-mxc/devices/platform-fec.c | 58 -- .../arm/plat-mxc/devices/platform-imx-dma.c | 129 --- .../arm/plat-mxc/devices/platform-imx-i2c.c | 84 +- .../arm/plat-mxc/devices/platform-imx-ssi.c | 107 --- .../arm/plat-mxc/devices/platform-imx-uart.c | 137 +-- .../arm/plat-mxc/devices/platform-mxc_nand.c | 85 +- .../arm/plat-mxc/devices/platform-spi_imx.c | 89 +- trunk/arch/arm/plat-mxc/ehci.c | 4 +- trunk/arch/arm/plat-mxc/epit.c | 242 ------ trunk/arch/arm/plat-mxc/gpio.c | 2 +- trunk/arch/arm/plat-mxc/include/mach/common.h | 1 - .../plat-mxc/include/mach/devices-common.h | 108 +-- trunk/arch/arm/plat-mxc/include/mach/esdhc.h | 16 - .../arm/plat-mxc/include/mach/iomux-mx51.h | 61 +- trunk/arch/arm/plat-mxc/include/mach/mx21.h | 2 +- trunk/arch/arm/plat-mxc/include/mach/mx25.h | 15 +- trunk/arch/arm/plat-mxc/include/mach/mx27.h | 2 +- trunk/arch/arm/plat-mxc/include/mach/mx31.h | 11 +- trunk/arch/arm/plat-mxc/include/mach/mx35.h | 32 +- trunk/arch/arm/plat-mxc/include/mach/mx3x.h | 23 +- trunk/arch/arm/plat-mxc/include/mach/mx51.h | 657 +++++++------- trunk/arch/arm/plat-tcc/Kconfig | 20 - trunk/arch/arm/plat-tcc/Makefile | 3 - trunk/arch/arm/plat-tcc/clock.c | 179 ---- trunk/arch/arm/plat-tcc/include/mach/clkdev.h | 7 - trunk/arch/arm/plat-tcc/include/mach/clock.h | 48 -- .../arm/plat-tcc/include/mach/debug-macro.S | 33 - .../arm/plat-tcc/include/mach/entry-macro.S | 68 -- .../arch/arm/plat-tcc/include/mach/hardware.h | 43 - trunk/arch/arm/plat-tcc/include/mach/io.h | 23 - trunk/arch/arm/plat-tcc/include/mach/irqs.h | 83 -- trunk/arch/arm/plat-tcc/include/mach/memory.h | 18 - trunk/arch/arm/plat-tcc/include/mach/system.h | 31 - .../arm/plat-tcc/include/mach/tcc8k-regs.h | 807 ------------------ trunk/arch/arm/plat-tcc/include/mach/timex.h | 5 - .../arm/plat-tcc/include/mach/uncompress.h | 34 - .../arch/arm/plat-tcc/include/mach/vmalloc.h | 10 - trunk/arch/arm/plat-tcc/system.c | 25 - trunk/arch/avr32/Kconfig | 1 - trunk/drivers/leds/Kconfig | 11 +- trunk/drivers/leds/Makefile | 1 - trunk/drivers/leds/leds-netxbig.c | 449 ---------- trunk/drivers/leds/leds-ns2.c | 9 +- trunk/drivers/net/Kconfig | 5 +- trunk/drivers/spi/Kconfig | 16 - trunk/drivers/spi/spi_imx.c | 402 ++------- 180 files changed, 2339 insertions(+), 7233 deletions(-) create mode 100644 trunk/arch/arm/configs/mx31pdk_defconfig delete mode 100644 trunk/arch/arm/include/asm/seccomp.h create mode 100644 trunk/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c delete mode 100644 trunk/arch/arm/mach-imx/mach-imx27_visstrim_m10.c delete mode 100644 trunk/arch/arm/mach-kirkwood/d2net_v2-setup.c delete mode 100644 trunk/arch/arm/mach-kirkwood/dockstar-setup.c delete mode 100644 trunk/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h delete mode 100644 trunk/arch/arm/mach-kirkwood/lacie_v2-common.c delete mode 100644 trunk/arch/arm/mach-kirkwood/lacie_v2-common.h delete mode 100644 trunk/arch/arm/mach-mx5/board-mx51_efikamx.c delete mode 100644 trunk/arch/arm/mach-mx5/devices-imx51.h create mode 100644 trunk/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h create mode 100644 trunk/arch/arm/mach-pxa/pxa3xx-ulpi.c delete mode 100644 trunk/arch/arm/mach-tcc8k/Kconfig delete mode 100644 trunk/arch/arm/mach-tcc8k/Makefile delete mode 100644 trunk/arch/arm/mach-tcc8k/Makefile.boot delete mode 100644 trunk/arch/arm/mach-tcc8k/board-tcc8000-sdk.c delete mode 100644 trunk/arch/arm/mach-tcc8k/clock.c delete mode 100644 trunk/arch/arm/mach-tcc8k/common.h delete mode 100644 trunk/arch/arm/mach-tcc8k/devices.c delete mode 100644 trunk/arch/arm/mach-tcc8k/io.c delete mode 100644 trunk/arch/arm/mach-tcc8k/irq.c delete mode 100644 trunk/arch/arm/mach-tcc8k/time.c delete mode 100644 trunk/arch/arm/plat-mxc/devices/platform-esdhc.c delete mode 100644 trunk/arch/arm/plat-mxc/devices/platform-fec.c delete mode 100644 trunk/arch/arm/plat-mxc/devices/platform-imx-dma.c delete mode 100644 trunk/arch/arm/plat-mxc/devices/platform-imx-ssi.c delete mode 100644 trunk/arch/arm/plat-mxc/epit.c delete mode 100644 trunk/arch/arm/plat-mxc/include/mach/esdhc.h delete mode 100644 trunk/arch/arm/plat-tcc/Kconfig delete mode 100644 trunk/arch/arm/plat-tcc/Makefile delete mode 100644 trunk/arch/arm/plat-tcc/clock.c delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/clkdev.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/clock.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/debug-macro.S delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/entry-macro.S delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/hardware.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/io.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/irqs.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/memory.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/system.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/tcc8k-regs.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/timex.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/uncompress.h delete mode 100644 trunk/arch/arm/plat-tcc/include/mach/vmalloc.h delete mode 100644 trunk/arch/arm/plat-tcc/system.c delete mode 100644 trunk/drivers/leds/leds-netxbig.c diff --git a/[refs] b/[refs] index c16b4f63547f..92270eecd610 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4af8f24d99d119ed68b27d1b0bd6f2ab2b23ed1b +refs/heads/master: 69f22be7b10684ade3808de22db87c536ed135f3 diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 0c737460f7e9..f46d8e66333f 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -980,13 +980,6 @@ S: Supported F: arch/arm/mach-shmobile/ F: drivers/sh/ -ARM/TELECHIPS ARM ARCHITECTURE -M: "Hans J. Koch" -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/plat-tcc/ -F: arch/arm/mach-tcc8k/ - ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index ca5aa5aa39e0..88c97bc7a6f5 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -747,15 +747,6 @@ config ARCH_SHARK Support for the StrongARM based Digital DNARD machine, also known as "Shark" (). -config ARCH_TCC_926 - bool "Telechips TCC ARM926-based systems" - select CPU_ARM926T - select HAVE_CLK - select COMMON_CLKDEV - select GENERIC_CLOCKEVENTS - help - Support for Telechips TCC ARM926-based systems. - config ARCH_LH7A40X bool "Sharp LH7A40X" select CPU_ARM922T @@ -924,8 +915,6 @@ source "arch/arm/plat-s5p/Kconfig" source "arch/arm/plat-spear/Kconfig" -source "arch/arm/plat-tcc/Kconfig" - if ARCH_S3C2410 source "arch/arm/mach-s3c2400/Kconfig" source "arch/arm/mach-s3c2410/Kconfig" @@ -1474,20 +1463,6 @@ config UACCESS_WITH_MEMCPY However, if the CPU data cache is using a write-allocate mode, this option is unlikely to provide any performance gain. -config SECCOMP - bool - prompt "Enable seccomp to safely compute untrusted bytecode" - ---help--- - This kernel feature is useful for number crunching applications - that may need to compute untrusted bytecode during their - execution. By using pipes or other transports made available to - the process as file descriptors supporting the read/write - syscalls, it's possible to isolate those applications in - their own address space using seccomp. Once seccomp is - enabled via prctl(PR_SET_SECCOMP), it cannot be disabled - and the task is only allowed to execute a few safe syscalls - defined by each seccomp mode. - config CC_STACKPROTECTOR bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" help diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug index c29fb382aeee..91344af75f39 100644 --- a/trunk/arch/arm/Kconfig.debug +++ b/trunk/arch/arm/Kconfig.debug @@ -2,20 +2,6 @@ menu "Kernel hacking" source "lib/Kconfig.debug" -config STRICT_DEVMEM - bool "Filter access to /dev/mem" - depends on MMU - ---help--- - If this option is disabled, you allow userspace (root) access to all - of memory, including kernel and userspace memory. Accidental - access to this is obviously disastrous, but specific access can - be used by people debugging the kernel. - - If this option is switched on, the /dev/mem file only allows - userspace access to memory mapped peripherals. - - If in doubt, say Y. - # RMK wants arm kernels compiled with frame pointers or stack unwinding. # If you know what you are doing and are willing to live without stack # traces, you can get a slightly smaller kernel by setting this option to diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index 502255905c4e..59c1ce858fc8 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -183,7 +183,6 @@ machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_STMP378X) := stmp378x machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx -machine-$(CONFIG_ARCH_TCC8K) := tcc8k machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_U300) := u300 machine-$(CONFIG_ARCH_U8500) := ux500 @@ -203,7 +202,6 @@ plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_S3C64XX) := samsung plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx -plat-$(CONFIG_ARCH_TCC_926) := tcc plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_ORION) := orion @@ -247,13 +245,12 @@ ifeq ($(FASTFPE),$(wildcard $(FASTFPE))) FASTFPE_OBJ :=$(FASTFPE)/ endif -core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ -core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) -core-$(CONFIG_VFP) += arch/arm/vfp/ - # If we have a machine-specific directory, then include it in the build. core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ core-y += $(machdirs) $(platdirs) +core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ +core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) +core-$(CONFIG_VFP) += arch/arm/vfp/ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ diff --git a/trunk/arch/arm/common/gic.c b/trunk/arch/arm/common/gic.c index ada6359160eb..7dfa9a85bc0c 100644 --- a/trunk/arch/arm/common/gic.c +++ b/trunk/arch/arm/common/gic.c @@ -67,11 +67,25 @@ static inline unsigned int gic_irq(unsigned int irq) /* * Routines to acknowledge, disable and enable interrupts + * + * Linux assumes that when we're done with an interrupt we need to + * unmask it, in the same way we need to unmask an interrupt when + * we first enable it. + * + * The GIC has a separate notion of "end of interrupt" to re-enable + * an interrupt after handling, in order to support hardware + * prioritisation. + * + * We can make the GIC behave in the way that Linux expects by making + * our "acknowledge" routine disable the interrupt, then mark it as + * complete. */ static void gic_ack_irq(unsigned int irq) { + u32 mask = 1 << (irq % 32); spin_lock(&irq_controller_lock); + writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); spin_unlock(&irq_controller_lock); } diff --git a/trunk/arch/arm/configs/at91sam9g20ek_defconfig b/trunk/arch/arm/configs/at91sam9g20ek_defconfig index 9e90e6d79297..f1bac70d6ce9 100644 --- a/trunk/arch/arm/configs/at91sam9g20ek_defconfig +++ b/trunk/arch/arm/configs/at91sam9g20ek_defconfig @@ -13,7 +13,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9G20=y CONFIG_MACH_AT91SAM9G20EK=y -CONFIG_MACH_AT91SAM9G20EK_2MMC=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y diff --git a/trunk/arch/arm/configs/kirkwood_defconfig b/trunk/arch/arm/configs/kirkwood_defconfig index 2f7042813765..ccc9c9959b82 100644 --- a/trunk/arch/arm/configs/kirkwood_defconfig +++ b/trunk/arch/arm/configs/kirkwood_defconfig @@ -15,7 +15,6 @@ CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_ESATA_SHEEVAPLUG=y CONFIG_MACH_GURUPLUG=y -CONFIG_MACH_DOCKSTAR=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y CONFIG_MACH_OPENRD_BASE=y diff --git a/trunk/arch/arm/configs/mx27_defconfig b/trunk/arch/arm/configs/mx27_defconfig index 813cfb366c18..b2038b0e266f 100644 --- a/trunk/arch/arm/configs/mx27_defconfig +++ b/trunk/arch/arm/configs/mx27_defconfig @@ -21,14 +21,8 @@ CONFIG_ARCH_MX2=y CONFIG_MACH_MX27=y CONFIG_MACH_MX27ADS=y CONFIG_MACH_PCM038=y -CONFIG_MACH_CPUIMX27=y -CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y -CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y CONFIG_MACH_MX27_3DS=y -CONFIG_MACH_IMX27_VISSTRIM_M10=y CONFIG_MACH_IMX27LITE=y -CONFIG_MACH_PCA100=y -CONFIG_MACH_MXT_TD60=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y CONFIG_NO_HZ=y @@ -82,9 +76,7 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_SERIO is not set -CONFIG_SERIAL_8250=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y # CONFIG_LEGACY_PTYS is not set @@ -93,20 +85,19 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_IMX=y CONFIG_SPI=y -CONFIG_SPI_IMX=y +CONFIG_SPI_BITBANG=y CONFIG_W1=y CONFIG_W1_MASTER_MXC=y CONFIG_W1_SLAVE_THERM=y # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_IMX=y +# CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y CONFIG_FONT_8x8=y # CONFIG_HID_SUPPORT is not set -CONFIG_USB=m -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_ULPI=y +# CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_MXC=y CONFIG_RTC_CLASS=y diff --git a/trunk/arch/arm/configs/mx31pdk_defconfig b/trunk/arch/arm/configs/mx31pdk_defconfig new file mode 100644 index 000000000000..2d29329749e4 --- /dev/null +++ b/trunk/arch/arm/configs/mx31pdk_defconfig @@ -0,0 +1,44 @@ +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_MXC=y +# CONFIG_MACH_MX31ADS is not set +CONFIG_MACH_MX31_3DS=y +CONFIG_AEABI=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_LRO is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_DNOTIFY is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRC32 is not set diff --git a/trunk/arch/arm/configs/mx3_defconfig b/trunk/arch/arm/configs/mx3_defconfig index f0c339fd5d21..161f907b611f 100644 --- a/trunk/arch/arm/configs/mx3_defconfig +++ b/trunk/arch/arm/configs/mx3_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_PCM043=y CONFIG_MACH_ARMADILLO5X0=y CONFIG_MACH_MX35_3DS=y CONFIG_MACH_KZM_ARM11_01=y -CONFIG_MACH_EUKREA_CPUIMX35=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y CONFIG_NO_HZ=y @@ -109,6 +108,7 @@ CONFIG_MMC=y CONFIG_MMC_MXC=y CONFIG_DMADEVICES=y # CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_UBIFS_FS=y diff --git a/trunk/arch/arm/configs/mx51_defconfig b/trunk/arch/arm/configs/mx51_defconfig index 163cfee7644c..a665ecbbe2bc 100644 --- a/trunk/arch/arm/configs/mx51_defconfig +++ b/trunk/arch/arm/configs/mx51_defconfig @@ -15,8 +15,6 @@ CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_ARCH_MXC=y CONFIG_ARCH_MX5=y CONFIG_MACH_MX51_BABBAGE=y -CONFIG_MACH_MX51_3DS=y -CONFIG_MACH_EUKREA_CPUIMX51=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT_VOLUNTARY=y @@ -71,6 +69,7 @@ CONFIG_REALTEK_PHY=y CONFIG_NATIONAL_PHY=y CONFIG_STE10XP=y CONFIG_LSI_ET1011C_PHY=y +CONFIG_FIXED_PHY=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_GPIO=y CONFIG_NET_ETHERNET=y @@ -101,6 +100,7 @@ CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCA=m CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set # CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -117,11 +117,13 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y +CONFIG_INOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set @@ -134,7 +136,6 @@ CONFIG_ZISOFS=y CONFIG_UDF_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=y -CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=m CONFIG_NFS_FS=y CONFIG_NFS_V3=y @@ -150,6 +151,7 @@ CONFIG_NLS_UTF8=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y +# CONFIG_DETECT_SOFTLOCKUP is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set @@ -157,6 +159,7 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_ARM_UNWIND is not set CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y +CONFIG_KEYS=y CONFIG_SECURITYFS=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y diff --git a/trunk/arch/arm/include/asm/elf.h b/trunk/arch/arm/include/asm/elf.h index 8bb66bca2e3e..5747a8baa413 100644 --- a/trunk/arch/arm/include/asm/elf.h +++ b/trunk/arch/arm/include/asm/elf.h @@ -127,8 +127,4 @@ struct mm_struct; extern unsigned long arch_randomize_brk(struct mm_struct *mm); #define arch_randomize_brk arch_randomize_brk -extern int vectors_user_mapping(void); -#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping() -#define ARCH_HAS_SETUP_ADDITIONAL_PAGES - #endif diff --git a/trunk/arch/arm/include/asm/io.h b/trunk/arch/arm/include/asm/io.h index 815efa2d4e07..1261b1f928d9 100644 --- a/trunk/arch/arm/include/asm/io.h +++ b/trunk/arch/arm/include/asm/io.h @@ -294,7 +294,6 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); #define ARCH_HAS_VALID_PHYS_ADDR_RANGE extern int valid_phys_addr_range(unsigned long addr, size_t size); extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); -extern int devmem_is_allowed(unsigned long pfn); #endif /* diff --git a/trunk/arch/arm/include/asm/mmu_context.h b/trunk/arch/arm/include/asm/mmu_context.h index 71605d9f8e42..a0b3cac0547c 100644 --- a/trunk/arch/arm/include/asm/mmu_context.h +++ b/trunk/arch/arm/include/asm/mmu_context.h @@ -18,6 +18,7 @@ #include #include #include +#include void __check_kvm_seq(struct mm_struct *mm); @@ -133,32 +134,4 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #define deactivate_mm(tsk,mm) do { } while (0) #define activate_mm(prev,next) switch_mm(prev, next, NULL) -/* - * We are inserting a "fake" vma for the user-accessible vector page so - * gdb and friends can get to it through ptrace and /proc//mem. - * But we also want to remove it before the generic code gets to see it - * during process exit or the unmapping of it would cause total havoc. - * (the macro is used as remove_vma() is static to mm/mmap.c) - */ -#define arch_exit_mmap(mm) \ -do { \ - struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \ - if (high_vma) { \ - BUG_ON(high_vma->vm_next); /* it should be last */ \ - if (high_vma->vm_prev) \ - high_vma->vm_prev->vm_next = NULL; \ - else \ - mm->mmap = NULL; \ - rb_erase(&high_vma->vm_rb, &mm->mm_rb); \ - mm->mmap_cache = NULL; \ - mm->map_count--; \ - remove_vma(high_vma); \ - } \ -} while (0) - -static inline void arch_dup_mmap(struct mm_struct *oldmm, - struct mm_struct *mm) -{ -} - #endif diff --git a/trunk/arch/arm/include/asm/seccomp.h b/trunk/arch/arm/include/asm/seccomp.h deleted file mode 100644 index 52b156b341f5..000000000000 --- a/trunk/arch/arm/include/asm/seccomp.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _ASM_ARM_SECCOMP_H -#define _ASM_ARM_SECCOMP_H - -#include - -#define __NR_seccomp_read __NR_read -#define __NR_seccomp_write __NR_write -#define __NR_seccomp_exit __NR_exit -#define __NR_seccomp_sigreturn __NR_rt_sigreturn - -#endif /* _ASM_ARM_SECCOMP_H */ diff --git a/trunk/arch/arm/include/asm/thread_info.h b/trunk/arch/arm/include/asm/thread_info.h index 7b5cc8dae06e..763e29fa8530 100644 --- a/trunk/arch/arm/include/asm/thread_info.h +++ b/trunk/arch/arm/include/asm/thread_info.h @@ -144,7 +144,6 @@ extern void vfp_flush_hwstate(struct thread_info *); #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_FREEZE 19 #define TIF_RESTORE_SIGMASK 20 -#define TIF_SECCOMP 21 #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) @@ -154,7 +153,6 @@ extern void vfp_flush_hwstate(struct thread_info *); #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) #define _TIF_FREEZE (1 << TIF_FREEZE) #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) -#define _TIF_SECCOMP (1 << TIF_SECCOMP) /* * Change these and you break ASM code in entry-common.S diff --git a/trunk/arch/arm/kernel/entry-common.S b/trunk/arch/arm/kernel/entry-common.S index 0385a8207b67..7885722bdf4e 100644 --- a/trunk/arch/arm/kernel/entry-common.S +++ b/trunk/arch/arm/kernel/entry-common.S @@ -295,6 +295,7 @@ ENTRY(vector_swi) get_thread_info tsk adr tbl, sys_call_table @ load syscall table pointer + ldr ip, [tsk, #TI_FLAGS] @ check for syscall tracing #if defined(CONFIG_OABI_COMPAT) /* @@ -311,20 +312,8 @@ ENTRY(vector_swi) eor scno, scno, #__NR_SYSCALL_BASE @ check OS number #endif - ldr r10, [tsk, #TI_FLAGS] @ check for syscall tracing stmdb sp!, {r4, r5} @ push fifth and sixth args - -#ifdef CONFIG_SECCOMP - tst r10, #_TIF_SECCOMP - beq 1f - mov r0, scno - bl __secure_computing - add r0, sp, #S_R0 + S_OFF @ pointer to regs - ldmia r0, {r0 - r3} @ have to reload r0 - r3 -1: -#endif - - tst r10, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? + tst ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? bne __sys_trace cmp scno, #NR_syscalls @ check upper syscall limit diff --git a/trunk/arch/arm/kernel/process.c b/trunk/arch/arm/kernel/process.c index 66ac9c926200..401e38be1f78 100644 --- a/trunk/arch/arm/kernel/process.c +++ b/trunk/arch/arm/kernel/process.c @@ -458,24 +458,3 @@ unsigned long arch_randomize_brk(struct mm_struct *mm) unsigned long range_end = mm->brk + 0x02000000; return randomize_range(mm->brk, range_end, 0) ? : mm->brk; } - -/* - * The vectors page is always readable from user space for the - * atomic helpers and the signal restart code. Let's declare a mapping - * for it so it is visible through ptrace and /proc//mem. - */ - -int vectors_user_mapping(void) -{ - struct mm_struct *mm = current->mm; - return install_special_mapping(mm, 0xffff0000, PAGE_SIZE, - VM_READ | VM_EXEC | - VM_MAYREAD | VM_MAYEXEC | - VM_ALWAYSDUMP | VM_RESERVED, - NULL); -} - -const char *arch_vma_name(struct vm_area_struct *vma) -{ - return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL; -} diff --git a/trunk/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/trunk/arch/arm/mach-aaec2000/include/mach/vmalloc.h index cff4e0a996ce..551f68f666bf 100644 --- a/trunk/arch/arm/mach-aaec2000/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-aaec2000/include/mach/vmalloc.h @@ -11,6 +11,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/trunk/arch/arm/mach-at91/Kconfig b/trunk/arch/arm/mach-at91/Kconfig index bbd5efa65099..939bccd70569 100644 --- a/trunk/arch/arm/mach-at91/Kconfig +++ b/trunk/arch/arm/mach-at91/Kconfig @@ -33,7 +33,6 @@ config ARCH_AT91SAM9260 select HAVE_AT91_USART3 select HAVE_AT91_USART4 select HAVE_AT91_USART5 - select HAVE_NET_MACB config ARCH_AT91SAM9261 bool "AT91SAM9261" @@ -52,7 +51,6 @@ config ARCH_AT91SAM9263 select CPU_ARM926T select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL - select HAVE_NET_MACB config ARCH_AT91SAM9RL bool "AT91SAM9RL" @@ -68,7 +66,6 @@ config ARCH_AT91SAM9G20 select HAVE_AT91_USART3 select HAVE_AT91_USART4 select HAVE_AT91_USART5 - select HAVE_NET_MACB config ARCH_AT91SAM9G45 bool "AT91SAM9G45" @@ -76,7 +73,6 @@ config ARCH_AT91SAM9G45 select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 select HAVE_FB_ATMEL - select HAVE_NET_MACB config ARCH_AT91CAP9 bool "AT91CAP9" @@ -342,7 +338,6 @@ config MACH_AT91SAM9G20EK that embeds only one SD/MMC slot. config MACH_AT91SAM9G20EK_2MMC - depends on MACH_AT91SAM9G20EK bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" select HAVE_NAND_ATMEL_BUSWIDTH_16 help @@ -388,8 +383,8 @@ if ARCH_AT91SAM9G45 comment "AT91SAM9G45 Board Type" -config MACH_AT91SAM9M10G45EK - bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" +config MACH_AT91SAM9G45EKES + bool "Atmel AT91SAM9G45-EKES Evaluation Kit" select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. diff --git a/trunk/arch/arm/mach-at91/Makefile b/trunk/arch/arm/mach-at91/Makefile index 3a07a3696441..ca2ac003f41f 100644 --- a/trunk/arch/arm/mach-at91/Makefile +++ b/trunk/arch/arm/mach-at91/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o # AT91SAM9G20 board-specific support obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o +obj-$(CONFIG_MACH_AT91SAM9G20EK_2MMC) += board-sam9g20ek-2slot-mmc.o obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o @@ -69,7 +70,7 @@ obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o # AT91SAM9G45 board-specific support -obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o +obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o # AT91CAP9 board-specific support obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o diff --git a/trunk/arch/arm/mach-at91/board-at572d940hf_ek.c b/trunk/arch/arm/mach-at91/board-at572d940hf_ek.c index 46651623f208..5daff277f53e 100644 --- a/trunk/arch/arm/mach-at91/board-at572d940hf_ek.c +++ b/trunk/arch/arm/mach-at91/board-at572d940hf_ek.c @@ -216,7 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = { /* .rdy_pin = AT91_PIN_PC16, */ .enable_pin = AT91_PIN_PA15, .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) .bus_width_16 = 1, #else .bus_width_16 = 0, diff --git a/trunk/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/trunk/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c new file mode 100644 index 000000000000..c49f5c003ee1 --- /dev/null +++ b/trunk/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c @@ -0,0 +1,329 @@ +/* + * Copyright (C) 2005 SAN People + * Copyright (C) 2008 Atmel + * Copyright (C) 2009 Rob Emanuele + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "sam9_smc.h" +#include "generic.h" + + +static void __init ek_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + +static void __init ek_init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata ek_usbh_data = { + .ports = 2, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata ek_udc_data = { + .vbus_pin = AT91_PIN_PC5, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + + +/* + * SPI devices. + */ +static struct spi_board_info ek_spi_devices[] = { +#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91)) + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 1, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) + { /* DataFlash card */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#endif +#endif +}; + + +/* + * MACB Ethernet device + */ +static struct at91_eth_data __initdata ek_macb_data = { + .phy_irq_pin = AT91_PIN_PB0, + .is_rmii = 1, +}; + + +/* + * NAND flash + */ +static struct mtd_partition __initdata ek_nand_partition[] = { + { + .name = "Bootstrap", + .offset = 0, + .size = 4 * SZ_1M, + }, + { + .name = "Partition 1", + .offset = MTDPART_OFS_NXTBLK, + .size = 60 * SZ_1M, + }, + { + .name = "Partition 2", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(ek_nand_partition); + return ek_nand_partition; +} + +/* det_pin is not connected */ +static struct atmel_nand_data __initdata ek_nand_data = { + .ale = 21, + .cle = 22, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .partition_info = nand_partitions, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 3, +}; + +static void __init ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (ek_nand_data.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + + +/* + * MCI (SD/MMC) + * wp_pin is not connected + */ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) +static struct mci_platform_data __initdata ek_mmc_data = { + .slot[0] = { + .bus_width = 4, + .detect_pin = AT91_PIN_PC2, + .wp_pin = -ENODEV, + }, + .slot[1] = { + .bus_width = 4, + .detect_pin = AT91_PIN_PC9, + .wp_pin = -ENODEV, + }, + +}; +#else +static struct at91_mmc_data __initdata ek_mmc_data = { + .slot_b = 1, /* Only one slot so use slot B */ + .wire4 = 1, + .det_pin = AT91_PIN_PC9, +}; +#endif + +/* + * LEDs + */ +static struct gpio_led ek_leds[] = { + { /* "bottom" led, green, userled1 to be defined */ + .name = "ds5", + .gpio = AT91_PIN_PB8, + .active_low = 1, + .default_trigger = "none", + }, + { /* "power" led, yellow */ + .name = "ds1", + .gpio = AT91_PIN_PB9, + .default_trigger = "heartbeat", + } +}; + +#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) +static struct regulator_consumer_supply ek_audio_consumer_supplies[] = { + REGULATOR_SUPPLY("AVDD", "0-001b"), + REGULATOR_SUPPLY("HPVDD", "0-001b"), + REGULATOR_SUPPLY("DBVDD", "0-001b"), + REGULATOR_SUPPLY("DCVDD", "0-001b"), +}; + +static struct regulator_init_data ek_avdd_reg_init_data = { + .constraints = { + .name = "3V3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .consumer_supplies = ek_audio_consumer_supplies, + .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies), +}; + +static struct fixed_voltage_config ek_vdd_pdata = { + .supply_name = "board-3V3", + .microvolts = 3300000, + .gpio = -EINVAL, + .enabled_at_boot = 0, + .init_data = &ek_avdd_reg_init_data, +}; +static struct platform_device ek_voltage_regulator = { + .name = "reg-fixed-voltage", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &ek_vdd_pdata, + }, +}; +static void __init ek_add_regulators(void) +{ + platform_device_register(&ek_voltage_regulator); +} +#else +static void __init ek_add_regulators(void) {} +#endif + +static struct i2c_board_info __initdata ek_i2c_devices[] = { + { + I2C_BOARD_INFO("24c512", 0x50), + }, +}; + + +static void __init ek_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); + /* USB Device */ + at91_add_device_udc(&ek_udc_data); + /* SPI */ + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + /* NAND */ + ek_add_device_nand(); + /* Ethernet */ + at91_add_device_eth(&ek_macb_data); + /* Regulators */ + ek_add_regulators(); + /* MMC */ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) + at91_add_device_mci(0, &ek_mmc_data); +#else + at91_add_device_mmc(0, &ek_mmc_data); +#endif + /* I2C */ + at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); + /* LEDs */ + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); + /* PCK0 provides MCLK to the WM8731 */ + at91_set_B_periph(AT91_PIN_PC1, 0); + /* SSC (for WM8731) */ + at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); +} + +MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") + /* Maintainer: Rob Emanuele */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = ek_map_io, + .init_irq = ek_init_irq, + .init_machine = ek_board_init, +MACHINE_END diff --git a/trunk/arch/arm/mach-at91/board-sam9g20ek.c b/trunk/arch/arm/mach-at91/board-sam9g20ek.c index b463e340c4a0..6ea9808b8868 100644 --- a/trunk/arch/arm/mach-at91/board-sam9g20ek.c +++ b/trunk/arch/arm/mach-at91/board-sam9g20ek.c @@ -47,18 +47,6 @@ #include "sam9_smc.h" #include "generic.h" -/* - * board revision encoding - * bit 0: - * 0 => 1 sd/mmc slot - * 1 => 2 sd/mmc slots connectors (board from revision C) - */ -#define HAVE_2MMC (1 << 0) -static int inline ek_have_2mmc(void) -{ - return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC); -} - static void __init ek_map_io(void) { @@ -106,7 +94,7 @@ static struct at91_udc_data __initdata ek_udc_data = { * SPI devices. */ static struct spi_board_info ek_spi_devices[] = { -#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91)) +#if !defined(CONFIG_MMC_AT91) { /* DataFlash chip */ .modalias = "mtd_dataflash", .chip_select = 1, @@ -133,13 +121,6 @@ static struct at91_eth_data __initdata ek_macb_data = { .is_rmii = 1, }; -static void __init ek_add_device_macb(void) -{ - if (ek_have_2mmc()) - ek_macb_data.phy_irq_pin = AT91_PIN_PB0; - - at91_add_device_eth(&ek_macb_data); -} /* * NAND flash @@ -217,36 +198,13 @@ static void __init ek_add_device_nand(void) /* * MCI (SD/MMC) - * wp_pin and vcc_pin are not connected + * det_pin, wp_pin and vcc_pin are not connected */ -#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) -static struct mci_platform_data __initdata ek_mmc_data = { - .slot[1] = { - .bus_width = 4, - .detect_pin = AT91_PIN_PC9, - }, - -}; -#else static struct at91_mmc_data __initdata ek_mmc_data = { - .slot_b = 1, /* Only one slot so use slot B */ + .slot_b = 1, .wire4 = 1, - .det_pin = AT91_PIN_PC9, }; -#endif -static void __init ek_add_device_mmc(void) -{ -#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) - if (ek_have_2mmc()) { - ek_mmc_data.slot[0].bus_width = 4; - ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2; - } - at91_add_device_mci(0, &ek_mmc_data); -#else - at91_add_device_mmc(0, &ek_mmc_data); -#endif -} /* * LEDs @@ -265,15 +223,6 @@ static struct gpio_led ek_leds[] = { } }; -static void __init ek_add_device_gpio_leds(void) -{ - if (ek_have_2mmc()) { - ek_leds[0].gpio = AT91_PIN_PB8; - ek_leds[1].gpio = AT91_PIN_PB9; - } - - at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); -} /* * GPIO Buttons @@ -387,15 +336,15 @@ static void __init ek_board_init(void) /* NAND */ ek_add_device_nand(); /* Ethernet */ - ek_add_device_macb(); + at91_add_device_eth(&ek_macb_data); /* Regulators */ ek_add_regulators(); /* MMC */ - ek_add_device_mmc(); + at91_add_device_mmc(0, &ek_mmc_data); /* I2C */ at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); /* LEDs */ - ek_add_device_gpio_leds(); + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); /* Push Buttons */ ek_add_device_buttons(); /* PCK0 provides MCLK to the WM8731 */ @@ -414,14 +363,3 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") .init_irq = ek_init_irq, .init_machine = ek_board_init, MACHINE_END - -MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") - /* Maintainer: Atmel */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, - .map_io = ek_map_io, - .init_irq = ek_init_irq, - .init_machine = ek_board_init, -MACHINE_END diff --git a/trunk/arch/arm/mach-at91/board-sam9m10g45ek.c b/trunk/arch/arm/mach-at91/board-sam9m10g45ek.c index ae0e0843e5f5..ee800595594d 100644 --- a/trunk/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/trunk/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -135,7 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = { .rdy_pin = AT91_PIN_PC8, .enable_pin = AT91_PIN_PC14, .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) .bus_width_16 = 1, #else .bus_width_16 = 0, @@ -399,7 +399,7 @@ static void __init ek_board_init(void) at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led)); } -MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") +MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES") /* Maintainer: Atmel */ .phys_io = AT91_BASE_SYS, .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, diff --git a/trunk/arch/arm/mach-at91/include/mach/at91x40.h b/trunk/arch/arm/mach-at91/include/mach/at91x40.h index 063ac44a0204..d34cdb8abdca 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91x40.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91x40.h @@ -52,10 +52,4 @@ #define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ #define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ -/* - * Support defines for the simple Power Controller module. - */ -#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */ -#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */ - #endif /* AT91X40_H */ diff --git a/trunk/arch/arm/mach-at91/include/mach/system.h b/trunk/arch/arm/mach-at91/include/mach/system.h index bfbb612265d6..c80e090b3670 100644 --- a/trunk/arch/arm/mach-at91/include/mach/system.h +++ b/trunk/arch/arm/mach-at91/include/mach/system.h @@ -33,11 +33,7 @@ static inline void arch_idle(void) * Disable the processor clock. The processor will be automatically * re-enabled by an interrupt or by a reset. */ -#ifdef AT91_PS - at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU); -#else at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); -#endif #else /* * Set the processor (CP15) into 'Wait for Interrupt' mode. diff --git a/trunk/arch/arm/mach-bcmring/include/mach/vmalloc.h b/trunk/arch/arm/mach-bcmring/include/mach/vmalloc.h index 3db3a09fd398..35e2ead8395c 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/vmalloc.h @@ -22,4 +22,4 @@ * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles * larger physical memory designs better. */ -#define VMALLOC_END 0xf0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x30000000) diff --git a/trunk/arch/arm/mach-clps711x/include/mach/vmalloc.h b/trunk/arch/arm/mach-clps711x/include/mach/vmalloc.h index 30b3a287ed88..ea6cc7beff28 100644 --- a/trunk/arch/arm/mach-clps711x/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-clps711x/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/trunk/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/trunk/arch/arm/mach-ebsa110/include/mach/vmalloc.h index 60bde56fba4c..9b44c19e95ec 100644 --- a/trunk/arch/arm/mach-ebsa110/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-ebsa110/include/mach/vmalloc.h @@ -7,4 +7,4 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#define VMALLOC_END 0xdf000000 +#define VMALLOC_END (PAGE_OFFSET + 0x1f000000) diff --git a/trunk/arch/arm/mach-footbridge/include/mach/vmalloc.h b/trunk/arch/arm/mach-footbridge/include/mach/vmalloc.h index 0ffbb7c85e59..d0958d860a3c 100644 --- a/trunk/arch/arm/mach-footbridge/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-footbridge/include/mach/vmalloc.h @@ -7,4 +7,4 @@ */ -#define VMALLOC_END 0xf0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x30000000) diff --git a/trunk/arch/arm/mach-h720x/include/mach/vmalloc.h b/trunk/arch/arm/mach-h720x/include/mach/vmalloc.h index a45915b88756..ff1460d6841b 100644 --- a/trunk/arch/arm/mach-h720x/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-h720x/include/mach/vmalloc.h @@ -5,6 +5,6 @@ #ifndef __ARCH_ARM_VMALLOC_H #define __ARCH_ARM_VMALLOC_H -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) #endif diff --git a/trunk/arch/arm/mach-imx/Kconfig b/trunk/arch/arm/mach-imx/Kconfig index 9b45f1f523fa..c5c0369bb481 100644 --- a/trunk/arch/arm/mach-imx/Kconfig +++ b/trunk/arch/arm/mach-imx/Kconfig @@ -146,8 +146,8 @@ choice default MACH_EUKREA_MBIMX27_BASEBOARD config MACH_EUKREA_MBIMX27_BASEBOARD - bool "Eukrea MBIMX27 development board" - select IMX_HAVE_PLATFORM_IMX_SSI + prompt "Eukrea MBIMX27 development board" + bool select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SPI_IMX help @@ -163,15 +163,6 @@ config MACH_MX27_3DS Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. -config MACH_IMX27_VISSTRIM_M10 - bool "Vista Silicon i.MX27 Visstrim_m10" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - help - Include support for Visstrim_m10 platform and its different variants. - This includes specific configurations for the board and its - peripherals. - config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" select IMX_HAVE_PLATFORM_IMX_UART @@ -182,7 +173,6 @@ config MACH_IMX27LITE config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX diff --git a/trunk/arch/arm/mach-imx/Makefile b/trunk/arch/arm/mach-imx/Makefile index 5582692bb176..46a9fdfbbd15 100644 --- a/trunk/arch/arm/mach-imx/Makefile +++ b/trunk/arch/arm/mach-imx/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o -obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_PCA100) += mach-pca100.o diff --git a/trunk/arch/arm/mach-imx/clock-imx1.c b/trunk/arch/arm/mach-imx/clock-imx1.c index daca30b2d5b1..c05096c38301 100644 --- a/trunk/arch/arm/mach-imx/clock-imx1.c +++ b/trunk/arch/arm/mach-imx/clock-imx1.c @@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) - _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk) + _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk) _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) _REGISTER_CLOCK(NULL, "mshc", mshc_clk) diff --git a/trunk/arch/arm/mach-imx/clock-imx21.c b/trunk/arch/arm/mach-imx/clock-imx21.c index cf15ea516a72..bb419ef4d133 100644 --- a/trunk/arch/arm/mach-imx/clock-imx21.c +++ b/trunk/arch/arm/mach-imx/clock-imx21.c @@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0]) _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0]) _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1]) - _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0]) - _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1]) - _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2]) + _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0]) + _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1]) + _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2]) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0]) _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0]) diff --git a/trunk/arch/arm/mach-imx/clock-imx27.c b/trunk/arch/arm/mach-imx/clock-imx27.c index 98a25bada783..5a1aa15c8a16 100644 --- a/trunk/arch/arm/mach-imx/clock-imx27.c +++ b/trunk/arch/arm/mach-imx/clock-imx27.c @@ -594,27 +594,27 @@ DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk); DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk); /* Clocks we cannot directly gate, but drivers need their rates */ -DEFINE_CLOCK(cspi1_clk, 0, NULL, 0, NULL, &cspi1_clk1, &per2_clk); -DEFINE_CLOCK(cspi2_clk, 1, NULL, 0, NULL, &cspi2_clk1, &per2_clk); -DEFINE_CLOCK(cspi3_clk, 2, NULL, 0, NULL, &cspi13_clk1, &per2_clk); -DEFINE_CLOCK(sdhc1_clk, 0, NULL, 0, NULL, &sdhc1_clk1, &per2_clk); -DEFINE_CLOCK(sdhc2_clk, 1, NULL, 0, NULL, &sdhc2_clk1, &per2_clk); -DEFINE_CLOCK(sdhc3_clk, 2, NULL, 0, NULL, &sdhc3_clk1, &per2_clk); -DEFINE_CLOCK(pwm_clk, 0, NULL, 0, NULL, &pwm_clk1, &per1_clk); -DEFINE_CLOCK(gpt1_clk, 0, NULL, 0, NULL, &gpt1_clk1, &per1_clk); -DEFINE_CLOCK(gpt2_clk, 1, NULL, 0, NULL, &gpt2_clk1, &per1_clk); -DEFINE_CLOCK(gpt3_clk, 2, NULL, 0, NULL, &gpt3_clk1, &per1_clk); -DEFINE_CLOCK(gpt4_clk, 3, NULL, 0, NULL, &gpt4_clk1, &per1_clk); -DEFINE_CLOCK(gpt5_clk, 4, NULL, 0, NULL, &gpt5_clk1, &per1_clk); -DEFINE_CLOCK(gpt6_clk, 5, NULL, 0, NULL, &gpt6_clk1, &per1_clk); -DEFINE_CLOCK(uart1_clk, 0, NULL, 0, NULL, &uart1_clk1, &per1_clk); -DEFINE_CLOCK(uart2_clk, 1, NULL, 0, NULL, &uart2_clk1, &per1_clk); -DEFINE_CLOCK(uart3_clk, 2, NULL, 0, NULL, &uart3_clk1, &per1_clk); -DEFINE_CLOCK(uart4_clk, 3, NULL, 0, NULL, &uart4_clk1, &per1_clk); -DEFINE_CLOCK(uart5_clk, 4, NULL, 0, NULL, &uart5_clk1, &per1_clk); -DEFINE_CLOCK(uart6_clk, 5, NULL, 0, NULL, &uart6_clk1, &per1_clk); -DEFINE_CLOCK1(lcdc_clk, 0, NULL, 0, parent, &lcdc_clk1, &per3_clk); -DEFINE_CLOCK1(csi_clk, 0, NULL, 0, parent, &csi_clk1, &per4_clk); +DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk); +DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk); +DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk); +DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk); +DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk); +DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk); +DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk); +DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk); +DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk); +DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk); +DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk); +DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk); +DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk); +DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk); +DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk); +DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk); +DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk); +DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk); +DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk); +DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk); +DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk) - _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk) - _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk) - _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk) + _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) + _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) + _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) diff --git a/trunk/arch/arm/mach-imx/devices-imx1.h b/trunk/arch/arm/mach-imx/devices-imx1.h index 81979486218e..a8d94f078196 100644 --- a/trunk/arch/arm/mach-imx/devices-imx1.h +++ b/trunk/arch/arm/mach-imx/devices-imx1.h @@ -9,12 +9,10 @@ #include #include -extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst; -#define imx1_add_imx_i2c(pdata) \ - imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) +#define imx1_add_i2c_imx(pdata) \ + imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata) -extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst; -#define imx1_add_imx_uart(id, pdata) \ - imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) -#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) -#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) +#define imx1_add_imx_uart0(pdata) \ + imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata) +#define imx1_add_imx_uart1(pdata) \ + imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata) diff --git a/trunk/arch/arm/mach-imx/devices-imx21.h b/trunk/arch/arm/mach-imx/devices-imx21.h index d189039749b0..42788e99d127 100644 --- a/trunk/arch/arm/mach-imx/devices-imx21.h +++ b/trunk/arch/arm/mach-imx/devices-imx21.h @@ -9,28 +9,22 @@ #include #include -extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; -#define imx21_add_imx_i2c(pdata) \ - imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) +#define imx21_add_i2c_imx(pdata) \ + imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata) -extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; -#define imx21_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) +#define imx21_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata) +#define imx21_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata) +#define imx21_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata) +#define imx21_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata) -extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; -#define imx21_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata) -#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata) -#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata) -#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) -#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) - -extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; #define imx21_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) + imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata) -extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; -#define imx21_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx21_cspi_data[id], pdata) -#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata) -#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata) +#define imx21_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata) +#define imx21_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata) diff --git a/trunk/arch/arm/mach-imx/devices-imx27.h b/trunk/arch/arm/mach-imx/devices-imx27.h index 7011690364f2..65e7bb7ec2e8 100644 --- a/trunk/arch/arm/mach-imx/devices-imx27.h +++ b/trunk/arch/arm/mach-imx/devices-imx27.h @@ -9,35 +9,30 @@ #include #include -extern const struct imx_fec_data imx27_fec_data __initconst; -#define imx27_add_fec(pdata) \ - imx_add_fec(&imx27_fec_data, pdata) +#define imx27_add_i2c_imx0(pdata) \ + imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata) +#define imx27_add_i2c_imx1(pdata) \ + imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata) -extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; -#define imx27_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) +#define imx27_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata) +#define imx27_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata) +#define imx27_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata) +#define imx27_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata) +#define imx27_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata) +#define imx27_add_imx_uart5(pdata) \ + imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata) -extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; -#define imx27_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; -#define imx27_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata) -#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata) -#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata) -#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata) -#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata) -#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) -#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) - -extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; #define imx27_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) + imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata) -extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; -#define imx27_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx27_cspi_data[id], pdata) -#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) -#define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata) -#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata) +#define imx27_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata) +#define imx27_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata) +#define imx27_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata) diff --git a/trunk/arch/arm/mach-imx/devices.c b/trunk/arch/arm/mach-imx/devices.c index fba5047de8b1..9c271a752b84 100644 --- a/trunk/arch/arm/mach-imx/devices.c +++ b/trunk/arch/arm/mach-imx/devices.c @@ -314,6 +314,27 @@ struct platform_device mxc_fb_device = { }, }; +#ifdef CONFIG_MACH_MX27 +static struct resource mxc_fec_resources[] = { + { + .start = MX27_FEC_BASE_ADDR, + .end = MX27_FEC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX27_INT_FEC, + .end = MX27_INT_FEC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_fec_device = { + .name = "fec", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_fec_resources), + .resource = mxc_fec_resources, +}; +#endif + static struct resource mxc_pwm_resources[] = { { .start = MX2x_PWM_BASE_ADDR, @@ -459,6 +480,41 @@ struct platform_device mxc_usbh2 = { }; #endif +#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \ + { \ + .name = _name, \ + .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .flags = IORESOURCE_DMA, \ + } + +#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \ + static struct resource imx_ssi_resources ## n[] = { \ + { \ + .start = MX2x_SSI ## ssin ## _BASE_ADDR, \ + .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = MX2x_INT_SSI1, \ + .end = MX2x_INT_SSI1, \ + .flags = IORESOURCE_IRQ, \ + }, \ + DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \ + DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \ + DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \ + DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \ + }; \ + \ + struct platform_device imx_ssi_device ## n = { \ + .name = "imx-ssi", \ + .id = n, \ + .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ + .resource = imx_ssi_resources ## n, \ + } + +DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); +DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); + /* GPIO port description */ #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ { \ diff --git a/trunk/arch/arm/mach-imx/devices.h b/trunk/arch/arm/mach-imx/devices.h index 807f02a031c9..efd4527506a5 100644 --- a/trunk/arch/arm/mach-imx/devices.h +++ b/trunk/arch/arm/mach-imx/devices.h @@ -16,6 +16,7 @@ extern struct platform_device mxc_gpt5; extern struct platform_device mxc_wdt; extern struct platform_device mxc_w1_master_device; extern struct platform_device mxc_fb_device; +extern struct platform_device mxc_fec_device; extern struct platform_device mxc_pwm_device; extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device1; @@ -25,5 +26,7 @@ extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mx21_usbhc_device; +extern struct platform_device imx_ssi_device0; +extern struct platform_device imx_ssi_device1; extern struct platform_device imx_kpp_device; #endif diff --git a/trunk/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/trunk/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 026263c665ca..4edc5f439201 100644 --- a/trunk/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/trunk/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -36,12 +36,13 @@ #include #include #include +#include #include #include "devices-imx27.h" #include "devices.h" -static const int eukrea_mbimx27_pins[] __initconst = { +static int eukrea_mbimx27_pins[] = { /* UART2 */ PE3_PF_UART2_CTS, PE4_PF_UART2_RTS, @@ -310,8 +311,7 @@ static struct imxmmc_platform_data sdhc_pdata = { .dat3_card_detect = 1, }; -static const -struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = { +struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = { .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE, }; @@ -357,7 +357,7 @@ void __init eukrea_mbimx27_baseboard_init(void) i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); - imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata); + mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata); #if defined(CONFIG_TOUCHSCREEN_ADS7846) \ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) diff --git a/trunk/arch/arm/mach-imx/mach-cpuimx27.c b/trunk/arch/arm/mach-imx/mach-cpuimx27.c index 28f73a1c79f7..339150ab0ea5 100644 --- a/trunk/arch/arm/mach-imx/mach-cpuimx27.c +++ b/trunk/arch/arm/mach-imx/mach-cpuimx27.c @@ -46,7 +46,7 @@ #include "devices-imx27.h" #include "devices.h" -static const int eukrea_cpuimx27_pins[] __initconst = { +static int eukrea_cpuimx27_pins[] = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, @@ -157,6 +157,7 @@ cpuimx27_nand_board_info __initconst = { static struct platform_device *platform_devices[] __initdata = { &eukrea_cpuimx27_nor_mtd_device, + &mxc_fec_device, &mxc_wdt, &mxc_w1_master_device, }; @@ -258,9 +259,8 @@ static void __init eukrea_cpuimx27_init(void) i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); - imx27_add_imx_i2c(1, &cpuimx27_i2c1_data); + imx27_add_i2c_imx1(&cpuimx27_i2c1_data); - imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) diff --git a/trunk/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/trunk/arch/arm/mach-imx/mach-imx27_visstrim_m10.c deleted file mode 100644 index a0d78faa08e8..000000000000 --- a/trunk/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * mach-imx27_visstrim_m10.c - * - * Copyright 2010 Javier Martin - * - * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "devices-imx27.h" -#include "devices.h" - -#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) -#define SDHC1_IRQ IRQ_GPIOB(25) - -static const int visstrim_m10_pins[] __initconst = { - /* UART1 (console) */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SDHC1 */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* Both I2Cs */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* USB OTG */ - OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PC9_PF_USBOTG_DATA0, - PC11_PF_USBOTG_DATA1, - PC10_PF_USBOTG_DATA2, - PC13_PF_USBOTG_DATA3, - PC12_PF_USBOTG_DATA4, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PE25_PF_USBOTG_DATA7, - PE24_PF_USBOTG_CLK, - PE2_PF_USBOTG_DIR, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PB23_PF_USB_PWR, - PB24_PF_USB_OC, -}; - -/* GPIOs used as events for applications */ -static struct gpio_keys_button visstrim_gpio_keys[] = { - { - .type = EV_KEY, - .code = KEY_RESTART, - .gpio = (GPIO_PORTC + 15), - .desc = "Default config", - .active_low = 0, - .wakeup = 1, - }, - { - .type = EV_KEY, - .code = KEY_RECORD, - .gpio = (GPIO_PORTF + 14), - .desc = "Record", - .active_low = 0, - .wakeup = 1, - }, - { - .type = EV_KEY, - .code = KEY_STOP, - .gpio = (GPIO_PORTF + 13), - .desc = "Stop", - .active_low = 0, - .wakeup = 1, - } -}; - -static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = { - .buttons = visstrim_gpio_keys, - .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), -}; - -static struct platform_device visstrim_gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &visstrim_gpio_keys_platform_data, - }, -}; - -/* Visstrim_SM10 has a microSD slot connected to sdhc1 */ -static int visstrim_m10_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING, - "mmc-detect", data); - return ret; -} - -static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(SDHC1_IRQ, data); -} - -static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = { - .init = visstrim_m10_sdhc1_init, - .exit = visstrim_m10_sdhc1_exit, -}; - -/* Visstrim_SM10 NOR flash */ -static struct physmap_flash_data visstrim_m10_flash_data = { - .width = 2, -}; - -static struct resource visstrim_m10_flash_resource = { - .start = 0xc0000000, - .end = 0xc0000000 + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device visstrim_m10_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &visstrim_m10_flash_data, - }, - .num_resources = 1, - .resource = &visstrim_m10_flash_resource, -}; - -static struct platform_device *platform_devices[] __initdata = { - &visstrim_gpio_keys_device, - &visstrim_m10_nor_mtd_device, -}; - -/* Visstrim_M10 uses UART0 as console */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* I2C */ -static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct pca953x_platform_data visstrim_m10_pca9555_pdata = { - .gpio_base = 240, /* After MX27 internal GPIOs */ - .invert = 0, -}; - -static struct i2c_board_info visstrim_m10_i2c_devices[] = { - { - I2C_BOARD_INFO("pca9555", 0x20), - .platform_data = &visstrim_m10_pca9555_pdata, - }, -}; - -/* USB OTG */ -static int otg_phy_init(struct platform_device *pdev) -{ - gpio_set_value(OTG_PHY_CS_GPIO, 0); - return 0; -} - -static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = { - .init = otg_phy_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED, -}; - -static void __init visstrim_m10_board_init(void) -{ - int ret; - - ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins, - ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10"); - if (ret) - pr_err("Failed to setup pins (%d)\n", ret); - - imx27_add_imx_uart0(&uart_pdata); - - i2c_register_board_info(0, visstrim_m10_i2c_devices, - ARRAY_SIZE(visstrim_m10_i2c_devices)); - imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); - imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); - mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata); - mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata); - imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); -} - -static void __init visstrim_m10_timer_init(void) -{ - mx27_clocks_init((unsigned long)25000000); -} - -static struct sys_timer visstrim_m10_timer = { - .init = visstrim_m10_timer_init, -}; - -MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") - .phys_io = MX27_AIPI_BASE_ADDR, - .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = visstrim_m10_board_init, - .timer = &visstrim_m10_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-imx/mach-imx27lite.c b/trunk/arch/arm/mach-imx/mach-imx27lite.c index 60d4d0ac4939..22a2b5d91213 100644 --- a/trunk/arch/arm/mach-imx/mach-imx27lite.c +++ b/trunk/arch/arm/mach-imx/mach-imx27lite.c @@ -27,7 +27,7 @@ #include "devices-imx27.h" #include "devices.h" -static const int mx27lite_pins[] __initconst = { +static unsigned int mx27lite_pins[] = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, @@ -58,12 +58,16 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static struct platform_device *platform_devices[] __initdata = { + &mxc_fec_device, +}; + static void __init mx27lite_init(void) { mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), "imx27lite"); imx27_add_imx_uart0(&uart_pdata); - imx27_add_fec(NULL); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } static void __init mx27lite_timer_init(void) diff --git a/trunk/arch/arm/mach-imx/mach-mx1ads.c b/trunk/arch/arm/mach-imx/mach-mx1ads.c index 85e2877572b5..77a760cfadc0 100644 --- a/trunk/arch/arm/mach-imx/mach-mx1ads.c +++ b/trunk/arch/arm/mach-imx/mach-mx1ads.c @@ -32,7 +32,7 @@ #include "devices-imx1.h" #include "devices.h" -static const int mx1ads_pins[] __initconst = { +static int mx1ads_pins[] = { /* UART1 */ PC9_PF_UART1_CTS, PC10_PF_UART1_RTS, @@ -131,7 +131,7 @@ static void __init mx1ads_init(void) i2c_register_board_info(0, mx1ads_i2c_devices, ARRAY_SIZE(mx1ads_i2c_devices)); - imx1_add_imx_i2c(&mx1ads_i2c_data); + imx1_add_i2c_imx(&mx1ads_i2c_data); } static void __init mx1ads_timer_init(void) diff --git a/trunk/arch/arm/mach-imx/mach-mx21ads.c b/trunk/arch/arm/mach-imx/mach-mx21ads.c index 7f021e6f6acd..96d7f8189f32 100644 --- a/trunk/arch/arm/mach-imx/mach-mx21ads.c +++ b/trunk/arch/arm/mach-imx/mach-mx21ads.c @@ -67,7 +67,7 @@ #define MX21ADS_IO_LED4_ON 0x4000 #define MX21ADS_IO_LED3_ON 0x8000 -static const int mx21ads_pins[] __initconst = { +static unsigned int mx21ads_pins[] = { /* CS8900A */ (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), diff --git a/trunk/arch/arm/mach-imx/mach-mx27_3ds.c b/trunk/arch/arm/mach-imx/mach-mx27_3ds.c index a69dba252658..e66ffaa1c26c 100644 --- a/trunk/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/trunk/arch/arm/mach-imx/mach-mx27_3ds.c @@ -33,7 +33,7 @@ #include "devices-imx27.h" #include "devices.h" -static const int mx27pdk_pins[] __initconst = { +static unsigned int mx27pdk_pins[] = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, @@ -64,6 +64,10 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static struct platform_device *platform_devices[] __initdata = { + &mxc_fec_device, +}; + /* * Matrix keyboard */ @@ -90,7 +94,7 @@ static void __init mx27pdk_init(void) mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), "mx27pdk"); imx27_add_imx_uart0(&uart_pdata); - imx27_add_fec(NULL); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data); } diff --git a/trunk/arch/arm/mach-imx/mach-mx27ads.c b/trunk/arch/arm/mach-imx/mach-mx27ads.c index ffb39a42f240..9c77da98a10e 100644 --- a/trunk/arch/arm/mach-imx/mach-mx27ads.c +++ b/trunk/arch/arm/mach-imx/mach-mx27ads.c @@ -66,7 +66,7 @@ /* to determine the correct external crystal reference */ #define CKIH_27MHZ_BIT_SET (1 << 3) -static const int mx27ads_pins[] __initconst = { +static unsigned int mx27ads_pins[] = { /* UART0 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, @@ -284,6 +284,7 @@ static struct imxmmc_platform_data sdhc2_pdata = { static struct platform_device *platform_devices[] __initdata = { &mx27ads_nor_mtd_device, + &mxc_fec_device, &mxc_w1_master_device, }; @@ -307,12 +308,11 @@ static void __init mx27ads_board_init(void) /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, mx27ads_i2c_devices, ARRAY_SIZE(mx27ads_i2c_devices)); - imx27_add_imx_i2c(1, &mx27ads_i2c1_data); + imx27_add_i2c_imx1(&mx27ads_i2c1_data); mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); - imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/trunk/arch/arm/mach-imx/mach-mxt_td60.c b/trunk/arch/arm/mach-imx/mach-mxt_td60.c index f4c397dec794..a3a1e452d4c5 100644 --- a/trunk/arch/arm/mach-imx/mach-mxt_td60.c +++ b/trunk/arch/arm/mach-imx/mach-mxt_td60.c @@ -37,7 +37,7 @@ #include "devices-imx27.h" #include "devices.h" -static const int mxt_td60_pins[] __initconst = { +static unsigned int mxt_td60_pins[] __initdata = { /* UART0 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, @@ -231,6 +231,10 @@ static struct imxmmc_platform_data sdhc1_pdata = { .exit = mxt_td60_sdhc1_exit, }; +static struct platform_device *platform_devices[] __initdata = { + &mxc_fec_device, +}; + static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -251,11 +255,12 @@ static void __init mxt_td60_board_init(void) i2c_register_board_info(1, mxt_td60_i2c2_devices, ARRAY_SIZE(mxt_td60_i2c2_devices)); - imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); - imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); + imx27_add_i2c_imx0(&mxt_td60_i2c0_data); + imx27_add_i2c_imx1(&mxt_td60_i2c1_data); mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); - imx27_add_fec(NULL); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } static void __init mxt_td60_timer_init(void) diff --git a/trunk/arch/arm/mach-imx/mach-pca100.c b/trunk/arch/arm/mach-imx/mach-pca100.c index 223c31c48db6..23c9e1f37b9c 100644 --- a/trunk/arch/arm/mach-imx/mach-pca100.c +++ b/trunk/arch/arm/mach-imx/mach-pca100.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -54,7 +55,7 @@ #define SPI1_SS1 (GPIO_PORTD + 27) #define SD2_CD (GPIO_PORTC + 29) -static const int pca100_pins[] __initconst = { +static int pca100_pins[] = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, @@ -173,6 +174,7 @@ pca100_nand_board_info __initconst = { static struct platform_device *platform_devices[] __initdata = { &mxc_w1_master_device, + &mxc_fec_device, &mxc_wdt, }; @@ -191,9 +193,11 @@ static struct i2c_board_info pca100_i2c_devices[] = { I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ .platform_data = &board_eeprom, }, { - I2C_BOARD_INFO("pcf8563", 0x51), + I2C_BOARD_INFO("rtc-pcf8563", 0x51), + .type = "pcf8563" }, { I2C_BOARD_INFO("lm75", 0x4a), + .type = "lm75" } }; @@ -248,7 +252,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) msleep(2); } -static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = { +static struct imx_ssi_platform_data pca100_ssi_pdata = { .ac97_reset = pca100_ac97_cold_reset, .ac97_warm_reset = pca100_ac97_warm_reset, .flags = IMX_SSI_USE_AC97, @@ -385,7 +389,7 @@ static void __init pca100_init(void) if (ret) printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); - imx27_add_imx_ssi(0, &pca100_ssi_pdata); + mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata); imx27_add_imx_uart0(&uart_pdata); @@ -397,7 +401,7 @@ static void __init pca100_init(void) i2c_register_board_info(1, pca100_i2c_devices, ARRAY_SIZE(pca100_i2c_devices)); - imx27_add_imx_i2c(1, &pca100_i2c1_data); + imx27_add_i2c_imx1(&pca100_i2c1_data); #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); @@ -432,7 +436,6 @@ static void __init pca100_init(void) mxc_register_device(&mxc_fb_device, &pca100_fb_data); - imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/trunk/arch/arm/mach-imx/mach-pcm038.c b/trunk/arch/arm/mach-imx/mach-pcm038.c index b9888a8defc1..9212e8f37001 100644 --- a/trunk/arch/arm/mach-imx/mach-pcm038.c +++ b/trunk/arch/arm/mach-imx/mach-pcm038.c @@ -43,7 +43,7 @@ #include "devices-imx27.h" #include "devices.h" -static const int pcm038_pins[] __initconst = { +static int pcm038_pins[] = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, @@ -173,6 +173,7 @@ pcm038_nand_board_info __initconst = { static struct platform_device *platform_devices[] __initdata = { &pcm038_nor_mtd_device, &mxc_w1_master_device, + &mxc_fec_device, &pcm038_sram_mtd_device, &mxc_wdt, }; @@ -256,7 +257,7 @@ static struct regulator_init_data cam_data = { .consumer_supplies = cam_consumers, }; -static struct mc13783_regulator_init_data pcm038_regulators[] = { +struct mc13783_regulator_init_data pcm038_regulators[] = { { .id = MC13783_REGU_VCAM, .init_data = &cam_data, @@ -308,7 +309,7 @@ static void __init pcm038_init(void) i2c_register_board_info(1, pcm038_i2c_devices, ARRAY_SIZE(pcm038_i2c_devices)); - imx27_add_imx_i2c(1, &pcm038_i2c1_data); + imx27_add_i2c_imx1(&pcm038_i2c1_data); /* PE18 for user-LED D40 */ mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT); @@ -324,7 +325,6 @@ static void __init pcm038_init(void) mxc_register_device(&mxc_usbh2, &usbh2_pdata); - imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); #ifdef CONFIG_MACH_PCM970_BASEBOARD diff --git a/trunk/arch/arm/mach-imx/mach-scb9328.c b/trunk/arch/arm/mach-imx/mach-scb9328.c index fb2e5f3d37f6..88bf0d1e26e6 100644 --- a/trunk/arch/arm/mach-imx/mach-scb9328.c +++ b/trunk/arch/arm/mach-imx/mach-scb9328.c @@ -95,7 +95,7 @@ static struct platform_device dm9000x_device = { } }; -static const int mxc_uart1_pins[] = { +static int mxc_uart1_pins[] = { PC9_PF_UART1_CTS, PC10_PF_UART1_RTS, PC11_PF_UART1_TXD, diff --git a/trunk/arch/arm/mach-imx/pcm970-baseboard.c b/trunk/arch/arm/mach-imx/pcm970-baseboard.c index 9110d9cca7a2..f490a406d57e 100644 --- a/trunk/arch/arm/mach-imx/pcm970-baseboard.c +++ b/trunk/arch/arm/mach-imx/pcm970-baseboard.c @@ -31,7 +31,7 @@ #include "devices.h" -static const int pcm970_pins[] __initconst = { +static int pcm970_pins[] = { /* SDHC */ PB4_PF_SD2_D0, PB5_PF_SD2_D1, @@ -200,7 +200,7 @@ static struct resource pcm970_sja1000_resources[] = { }, }; -static struct sja1000_platform_data pcm970_sja1000_platform_data = { +struct sja1000_platform_data pcm970_sja1000_platform_data = { .osc_freq = 16000000, .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, .cdr = CDR_CBP, diff --git a/trunk/arch/arm/mach-integrator/include/mach/vmalloc.h b/trunk/arch/arm/mach-integrator/include/mach/vmalloc.h index e056e7cf5645..e87ab0b37bdd 100644 --- a/trunk/arch/arm/mach-integrator/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-integrator/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/trunk/arch/arm/mach-kirkwood/Kconfig b/trunk/arch/arm/mach-kirkwood/Kconfig index 34106335c728..cc25501b57fa 100644 --- a/trunk/arch/arm/mach-kirkwood/Kconfig +++ b/trunk/arch/arm/mach-kirkwood/Kconfig @@ -58,12 +58,6 @@ config MACH_TS41X QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS devices. -config MACH_DOCKSTAR - bool "Seagate FreeAgent DockStar" - help - Say 'Y' here if you want your kernel to support the - Seagate FreeAgent DockStar. - config MACH_OPENRD bool @@ -106,12 +100,6 @@ config MACH_NETSPACE_MAX_V2 Say 'Y' here if you want your kernel to support the LaCie Network Space Max v2 NAS. -config MACH_D2NET_V2 - bool "LaCie d2 Network v2 NAS Board" - help - Say 'Y' here if you want your kernel to support the - LaCie d2 Network v2 NAS. - config MACH_NET2BIG_V2 bool "LaCie 2Big Network v2 NAS Board" help diff --git a/trunk/arch/arm/mach-kirkwood/Makefile b/trunk/arch/arm/mach-kirkwood/Makefile index 5dcaa81a2ec3..295d7baa6ae1 100644 --- a/trunk/arch/arm/mach-kirkwood/Makefile +++ b/trunk/arch/arm/mach-kirkwood/Makefile @@ -7,16 +7,14 @@ obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o -obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o -obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o +obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o +obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o +obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o +obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o +obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o obj-$(CONFIG_MACH_T5325) += t5325-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/trunk/arch/arm/mach-kirkwood/d2net_v2-setup.c b/trunk/arch/arm/mach-kirkwood/d2net_v2-setup.c deleted file mode 100644 index cd62d0f82a73..000000000000 --- a/trunk/arch/arm/mach-kirkwood/d2net_v2-setup.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * arch/arm/mach-kirkwood/d2net_v2-setup.c - * - * LaCie d2 Network Space v2 Board Setup - * - * Copyright (C) 2010 Simon Guinot - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "lacie_v2-common.h" - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data d2net_v2_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ - -static struct mv_sata_platform_data d2net_v2_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * GPIO keys - ****************************************************************************/ - -#define D2NET_V2_GPIO_PUSH_BUTTON 34 -#define D2NET_V2_GPIO_POWER_SWITCH_ON 13 -#define D2NET_V2_GPIO_POWER_SWITCH_OFF 15 - -#define D2NET_V2_SWITCH_POWER_ON 0x1 -#define D2NET_V2_SWITCH_POWER_OFF 0x2 - -static struct gpio_keys_button d2net_v2_buttons[] = { - [0] = { - .type = EV_SW, - .code = D2NET_V2_SWITCH_POWER_ON, - .gpio = D2NET_V2_GPIO_POWER_SWITCH_ON, - .desc = "Back power switch (on|auto)", - .active_low = 0, - }, - [1] = { - .type = EV_SW, - .code = D2NET_V2_SWITCH_POWER_OFF, - .gpio = D2NET_V2_GPIO_POWER_SWITCH_OFF, - .desc = "Back power switch (auto|off)", - .active_low = 0, - }, - [2] = { - .code = KEY_POWER, - .gpio = D2NET_V2_GPIO_PUSH_BUTTON, - .desc = "Front Push Button", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data d2net_v2_button_data = { - .buttons = d2net_v2_buttons, - .nbuttons = ARRAY_SIZE(d2net_v2_buttons), -}; - -static struct platform_device d2net_v2_gpio_buttons = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &d2net_v2_button_data, - }, -}; - -/***************************************************************************** - * GPIO LEDs - ****************************************************************************/ - -#define D2NET_V2_GPIO_RED_LED 12 - -static struct gpio_led d2net_v2_gpio_led_pins[] = { - { - .name = "d2net_v2:red:fail", - .gpio = D2NET_V2_GPIO_RED_LED, - }, -}; - -static struct gpio_led_platform_data d2net_v2_gpio_leds_data = { - .num_leds = ARRAY_SIZE(d2net_v2_gpio_led_pins), - .leds = d2net_v2_gpio_led_pins, -}; - -static struct platform_device d2net_v2_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &d2net_v2_gpio_leds_data, - }, -}; - -/***************************************************************************** - * Dual-GPIO CPLD LEDs - ****************************************************************************/ - -#define D2NET_V2_GPIO_BLUE_LED_SLOW 29 -#define D2NET_V2_GPIO_BLUE_LED_CMD 30 - -static struct ns2_led d2net_v2_led_pins[] = { - { - .name = "d2net_v2:blue:sata", - .cmd = D2NET_V2_GPIO_BLUE_LED_CMD, - .slow = D2NET_V2_GPIO_BLUE_LED_SLOW, - }, -}; - -static struct ns2_led_platform_data d2net_v2_leds_data = { - .num_leds = ARRAY_SIZE(d2net_v2_led_pins), - .leds = d2net_v2_led_pins, -}; - -static struct platform_device d2net_v2_leds = { - .name = "leds-ns2", - .id = -1, - .dev = { - .platform_data = &d2net_v2_leds_data, - }, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -static unsigned int d2net_v2_mpp_config[] __initdata = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* Request power-off */ - MPP8_TW0_SDA, - MPP9_TW0_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, /* Red led */ - MPP13_GPIO, /* Rear power switch (on|auto) */ - MPP14_GPIO, /* USB fuse */ - MPP15_GPIO, /* Rear power switch (auto|off) */ - MPP16_GPIO, /* SATA 0 power */ - MPP21_SATA0_ACTn, - MPP24_GPIO, /* USB mode select */ - MPP26_GPIO, /* USB device vbus */ - MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* Blue led (slow register) */ - MPP30_GPIO, /* Blue led (command register) */ - MPP34_GPIO, /* Power button (1 = Released, 0 = Pushed) */ - MPP35_GPIO, /* Inhibit power-off */ - 0 -}; - -#define D2NET_V2_GPIO_POWER_OFF 7 - -static void d2net_v2_power_off(void) -{ - gpio_set_value(D2NET_V2_GPIO_POWER_OFF, 1); -} - -static void __init d2net_v2_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(d2net_v2_mpp_config); - - lacie_v2_hdd_power_init(1); - - kirkwood_ehci_init(); - kirkwood_ge00_init(&d2net_v2_ge00_data); - kirkwood_sata_init(&d2net_v2_sata_data); - kirkwood_uart0_init(); - lacie_v2_register_flash(); - lacie_v2_register_i2c_devices(); - - platform_device_register(&d2net_v2_leds); - platform_device_register(&d2net_v2_gpio_leds); - platform_device_register(&d2net_v2_gpio_buttons); - - if (gpio_request(D2NET_V2_GPIO_POWER_OFF, "power-off") == 0 && - gpio_direction_output(D2NET_V2_GPIO_POWER_OFF, 0) == 0) - pm_power_off = d2net_v2_power_off; - else - pr_err("d2net_v2: failed to configure power-off GPIO\n"); -} - -MACHINE_START(D2NET_V2, "LaCie d2 Network v2") - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = d2net_v2_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &lacie_v2_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-kirkwood/dockstar-setup.c b/trunk/arch/arm/mach-kirkwood/dockstar-setup.c deleted file mode 100644 index a90475d5059c..000000000000 --- a/trunk/arch/arm/mach-kirkwood/dockstar-setup.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * arch/arm/mach-kirkwood/dockstar-setup.c - * - * Seagate FreeAgent DockStar Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" - -static struct mtd_partition dockstar_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data dockstar_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -static struct gpio_led dockstar_led_pins[] = { - { - .name = "dockstar:green:health", - .default_trigger = "default-on", - .gpio = 46, - .active_low = 1, - }, - { - .name = "dockstar:orange:misc", - .default_trigger = "none", - .gpio = 47, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data dockstar_led_data = { - .leds = dockstar_led_pins, - .num_leds = ARRAY_SIZE(dockstar_led_pins), -}; - -static struct platform_device dockstar_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &dockstar_led_data, - } -}; - -static unsigned int dockstar_mpp_config[] __initdata = { - MPP29_GPIO, /* USB Power Enable */ - MPP46_GPIO, /* LED green */ - MPP47_GPIO, /* LED orange */ - 0 -}; - -static void __init dockstar_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - - /* setup gpio pin select */ - kirkwood_mpp_conf(dockstar_mpp_config); - - kirkwood_uart0_init(); - kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25); - - if (gpio_request(29, "USB Power Enable") != 0 || - gpio_direction_output(29, 1) != 0) - printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n"); - kirkwood_ehci_init(); - - kirkwood_ge00_init(&dockstar_ge00_data); - - platform_device_register(&dockstar_leds); -} - -MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar") - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = dockstar_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h b/trunk/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h deleted file mode 100644 index 24b536ebdf13..000000000000 --- a/trunk/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * arch/arm/mach-kirkwood/include/mach/leds-netxbig.h - * - * Platform data structure for netxbig LED driver - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_LEDS_NETXBIG_H -#define __MACH_LEDS_NETXBIG_H - -struct netxbig_gpio_ext { - unsigned *addr; - int num_addr; - unsigned *data; - int num_data; - unsigned enable; -}; - -enum netxbig_led_mode { - NETXBIG_LED_OFF, - NETXBIG_LED_ON, - NETXBIG_LED_SATA, - NETXBIG_LED_TIMER1, - NETXBIG_LED_TIMER2, - NETXBIG_LED_MODE_NUM, -}; - -#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM - -struct netxbig_led_timer { - unsigned long delay_on; - unsigned long delay_off; - enum netxbig_led_mode mode; -}; - -struct netxbig_led { - const char *name; - const char *default_trigger; - int mode_addr; - int *mode_val; - int bright_addr; -}; - -struct netxbig_led_platform_data { - struct netxbig_gpio_ext *gpio_ext; - struct netxbig_led_timer *timer; - int num_timer; - struct netxbig_led *leds; - int num_leds; -}; - -#endif /* __MACH_LEDS_NETXBIG_H */ diff --git a/trunk/arch/arm/mach-kirkwood/lacie_v2-common.c b/trunk/arch/arm/mach-kirkwood/lacie_v2-common.c deleted file mode 100644 index d3ea1b6c8a02..000000000000 --- a/trunk/arch/arm/mach-kirkwood/lacie_v2-common.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * arch/arm/mach-kirkwood/lacie_v2-common.c - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -/***************************************************************************** - * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005) - ****************************************************************************/ - -static struct mtd_partition lacie_v2_flash_parts[] = { - { - .name = "u-boot", - .size = MTDPART_SIZ_FULL, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, -}; - -static const struct flash_platform_data lacie_v2_flash = { - .type = "mx25l4005a", - .name = "spi_flash", - .parts = lacie_v2_flash_parts, - .nr_parts = ARRAY_SIZE(lacie_v2_flash_parts), -}; - -static struct spi_board_info __initdata lacie_v2_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &lacie_v2_flash, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -void __init lacie_v2_register_flash(void) -{ - spi_register_board_info(lacie_v2_spi_slave_info, - ARRAY_SIZE(lacie_v2_spi_slave_info)); - kirkwood_spi_init(); -} - -/***************************************************************************** - * I2C devices - ****************************************************************************/ - -static struct at24_platform_data at24c04 = { - .byte_len = SZ_4K / 8, - .page_size = 16, -}; - -/* - * i2c addr | chip | description - * 0x50 | HT24LC04 | eeprom (512B) - */ - -static struct i2c_board_info __initdata lacie_v2_i2c_info[] = { - { - I2C_BOARD_INFO("24c04", 0x50), - .platform_data = &at24c04, - } -}; - -void __init lacie_v2_register_i2c_devices(void) -{ - kirkwood_i2c_init(); - i2c_register_board_info(0, lacie_v2_i2c_info, - ARRAY_SIZE(lacie_v2_i2c_info)); -} - -/***************************************************************************** - * Hard Disk power - ****************************************************************************/ - -static int __initdata lacie_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 }; - -void __init lacie_v2_hdd_power_init(int hdd_num) -{ - int i; - int err; - - /* Power up all hard disks. */ - for (i = 0; i < hdd_num; i++) { - err = gpio_request(lacie_v2_gpio_hdd_power[i], NULL); - if (err == 0) { - err = gpio_direction_output( - lacie_v2_gpio_hdd_power[i], 1); - /* Free the HDD power GPIOs. This allow user-space to - * configure them via the gpiolib sysfs interface. */ - gpio_free(lacie_v2_gpio_hdd_power[i]); - } - if (err) - pr_err("Failed to power up HDD%d\n", i + 1); - } -} - -/***************************************************************************** - * Timer - ****************************************************************************/ - -static void lacie_v2_timer_init(void) -{ - kirkwood_tclk = 166666667; - orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); -} - -struct sys_timer lacie_v2_timer = { - .init = lacie_v2_timer_init, -}; diff --git a/trunk/arch/arm/mach-kirkwood/lacie_v2-common.h b/trunk/arch/arm/mach-kirkwood/lacie_v2-common.h deleted file mode 100644 index af521315b87b..000000000000 --- a/trunk/arch/arm/mach-kirkwood/lacie_v2-common.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * arch/arm/mach-kirkwood/lacie_v2-common.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ARCH_KIRKWOOD_LACIE_V2_COMMON_H -#define __ARCH_KIRKWOOD_LACIE_V2_COMMON_H - -void lacie_v2_register_flash(void); -void lacie_v2_register_i2c_devices(void); -void lacie_v2_hdd_power_init(int hdd_num); - -extern struct sys_timer lacie_v2_timer; - -#endif diff --git a/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c b/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c index fed264d28f4a..d26bf324738b 100644 --- a/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -24,19 +24,56 @@ #include #include #include +#include +#include +#include #include #include +#include +#include #include #include #include #include #include #include +#include #include #include +#include #include "common.h" #include "mpp.h" -#include "lacie_v2-common.h" + +/***************************************************************************** + * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005) + ****************************************************************************/ + +static struct mtd_partition netspace_v2_flash_parts[] = { + { + .name = "u-boot", + .size = MTDPART_SIZ_FULL, + .offset = 0, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, +}; + +static const struct flash_platform_data netspace_v2_flash = { + .type = "mx25l4005a", + .name = "spi_flash", + .parts = netspace_v2_flash_parts, + .nr_parts = ARRAY_SIZE(netspace_v2_flash_parts), +}; + +static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &netspace_v2_flash, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; /***************************************************************************** * Ethernet @@ -46,6 +83,27 @@ static struct mv643xx_eth_platform_data netspace_v2_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; +/***************************************************************************** + * I2C devices + ****************************************************************************/ + +static struct at24_platform_data at24c04 = { + .byte_len = SZ_4K / 8, + .page_size = 16, +}; + +/* + * i2c addr | chip | description + * 0x50 | HT24LC04 | eeprom (512B) + */ + +static struct i2c_board_info __initdata netspace_v2_i2c_info[] = { + { + I2C_BOARD_INFO("24c04", 0x50), + .platform_data = &at24c04, + } +}; + /***************************************************************************** * SATA ****************************************************************************/ @@ -54,6 +112,35 @@ static struct mv_sata_platform_data netspace_v2_sata_data = { .n_ports = 2, }; +#define NETSPACE_V2_GPIO_SATA0_POWER 16 +#define NETSPACE_V2_GPIO_SATA1_POWER 17 + +static void __init netspace_v2_sata_power_init(void) +{ + int err; + + err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power"); + if (err == 0) { + err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1); + if (err) + gpio_free(NETSPACE_V2_GPIO_SATA0_POWER); + } + if (err) + pr_err("netspace_v2: failed to setup SATA0 power\n"); + + if (machine_is_netspace_max_v2()) { + err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power"); + if (err == 0) { + err = gpio_direction_output( + NETSPACE_V2_GPIO_SATA1_POWER, 1); + if (err) + gpio_free(NETSPACE_V2_GPIO_SATA1_POWER); + } + if (err) + pr_err("netspace_v2: failed to setup SATA1 power\n"); + } +} + /***************************************************************************** * GPIO keys ****************************************************************************/ @@ -136,6 +223,20 @@ static struct platform_device netspace_v2_leds = { }, }; +/***************************************************************************** + * Timer + ****************************************************************************/ + +static void netspace_v2_timer_init(void) +{ + kirkwood_tclk = 166666667; + orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); +} + +struct sys_timer netspace_v2_timer = { + .init = netspace_v2_timer_init, +}; + /***************************************************************************** * General Setup ****************************************************************************/ @@ -190,17 +291,18 @@ static void __init netspace_v2_init(void) kirkwood_init(); kirkwood_mpp_conf(netspace_v2_mpp_config); - if (machine_is_netspace_max_v2()) - lacie_v2_hdd_power_init(2); - else - lacie_v2_hdd_power_init(1); + netspace_v2_sata_power_init(); kirkwood_ehci_init(); kirkwood_ge00_init(&netspace_v2_ge00_data); kirkwood_sata_init(&netspace_v2_sata_data); kirkwood_uart0_init(); - lacie_v2_register_flash(); - lacie_v2_register_i2c_devices(); + spi_register_board_info(netspace_v2_spi_slave_info, + ARRAY_SIZE(netspace_v2_spi_slave_info)); + kirkwood_spi_init(); + kirkwood_i2c_init(); + i2c_register_board_info(0, netspace_v2_i2c_info, + ARRAY_SIZE(netspace_v2_i2c_info)); platform_device_register(&netspace_v2_leds); platform_device_register(&netspace_v2_gpio_leds); @@ -221,7 +323,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") .init_machine = netspace_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &lacie_v2_timer, + .timer = &netspace_v2_timer, MACHINE_END #endif @@ -233,7 +335,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") .init_machine = netspace_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &lacie_v2_timer, + .timer = &netspace_v2_timer, MACHINE_END #endif @@ -245,6 +347,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2") .init_machine = netspace_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &lacie_v2_timer, + .timer = &netspace_v2_timer, MACHINE_END #endif diff --git a/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c index d970e1eee37d..2bd14c5079de 100644 --- a/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c +++ b/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c @@ -23,19 +23,55 @@ #include #include #include +#include +#include +#include #include #include +#include +#include #include #include #include #include #include #include +#include #include -#include +#include #include "common.h" #include "mpp.h" -#include "lacie_v2-common.h" + +/***************************************************************************** + * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005) + ****************************************************************************/ + +static struct mtd_partition netxbig_v2_flash_parts[] = { + { + .name = "u-boot", + .size = MTDPART_SIZ_FULL, + .offset = 0, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, +}; + +static const struct flash_platform_data netxbig_v2_flash = { + .type = "mx25l4005a", + .name = "spi_flash", + .parts = netxbig_v2_flash_parts, + .nr_parts = ARRAY_SIZE(netxbig_v2_flash_parts), +}; + +static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &netxbig_v2_flash, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; /***************************************************************************** * Ethernet @@ -49,6 +85,27 @@ static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; +/***************************************************************************** + * I2C devices + ****************************************************************************/ + +static struct at24_platform_data at24c04 = { + .byte_len = SZ_4K / 8, + .page_size = 16, +}; + +/* + * i2c addr | chip | description + * 0x50 | HT24LC04 | eeprom (512B) + */ + +static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = { + { + I2C_BOARD_INFO("24c04", 0x50), + .platform_data = &at24c04, + } +}; + /***************************************************************************** * SATA ****************************************************************************/ @@ -57,6 +114,34 @@ static struct mv_sata_platform_data netxbig_v2_sata_data = { .n_ports = 2, }; +static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 }; + +static void __init netxbig_v2_sata_power_init(void) +{ + int i; + int err; + int hdd_nb; + + if (machine_is_net2big_v2()) + hdd_nb = 2; + else + hdd_nb = 5; + + /* Power up all hard disks. */ + for (i = 0; i < hdd_nb; i++) { + err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL); + if (err == 0) { + err = gpio_direction_output( + netxbig_v2_gpio_hdd_power[i], 1); + /* Free the HDD power GPIOs. This allow user-space to + * configure them via the gpiolib sysfs interface. */ + gpio_free(netxbig_v2_gpio_hdd_power[i]); + } + if (err) + pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1); + } +} + /***************************************************************************** * GPIO keys ****************************************************************************/ @@ -105,7 +190,7 @@ static struct platform_device netxbig_v2_gpio_buttons = { }; /***************************************************************************** - * GPIO extension LEDs + * GPIO LEDs ****************************************************************************/ /* @@ -115,32 +200,19 @@ static struct platform_device netxbig_v2_gpio_buttons = { * - address register : bit [0-2] -> GPIO [47-49] * - data register : bit [0-2] -> GPIO [44-46] * - enable register : GPIO 29 - */ - -static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 }; -static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 }; - -static struct netxbig_gpio_ext netxbig_v2_gpio_ext = { - .addr = netxbig_v2_gpio_ext_addr, - .num_addr = ARRAY_SIZE(netxbig_v2_gpio_ext_addr), - .data = netxbig_v2_gpio_ext_data, - .num_data = ARRAY_SIZE(netxbig_v2_gpio_ext_data), - .enable = 29, -}; - -/* + * * Address register selection: * * addr | register * ---------------------------- * 0 | front LED * 1 | front LED brightness - * 2 | SATA LED brightness - * 3 | SATA0 LED - * 4 | SATA1 LED - * 5 | SATA2 LED - * 6 | SATA3 LED - * 7 | SATA4 LED + * 2 | HDD LED brightness + * 3 | HDD1 LED + * 4 | HDD2 LED + * 5 | HDD3 LED + * 6 | HDD4 LED + * 7 | HDD5 LED * * Data register configuration: * @@ -161,107 +233,30 @@ static struct netxbig_gpio_ext netxbig_v2_gpio_ext = { * 6 | blink blue on=1 sec and red on=1 sec * 7 | blink blue on=0.5 sec and blue off=2.5 sec * - * data | SATA LED mode + * data | HDD LED mode * ------------------------------------------------- - * 0 | fix off + * 0 | fix blue on * 1 | SATA activity blink * 2 | fix red on * 3 | blink blue on=1 sec and blue off=1 sec * 4 | blink red on=1 sec and red off=1 sec * 5 | blink blue on=2.5 sec and red on=0.5 sec * 6 | blink blue on=1 sec and red on=1 sec - * 7 | fix blue on + * 7 | blink blue on=0.5 sec and blue off=2.5 sec */ -static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = { - [NETXBIG_LED_OFF] = 0, - [NETXBIG_LED_ON] = 2, - [NETXBIG_LED_SATA] = NETXBIG_LED_INVALID_MODE, - [NETXBIG_LED_TIMER1] = 4, - [NETXBIG_LED_TIMER2] = NETXBIG_LED_INVALID_MODE, -}; - -static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = { - [NETXBIG_LED_OFF] = 0, - [NETXBIG_LED_ON] = 1, - [NETXBIG_LED_SATA] = NETXBIG_LED_INVALID_MODE, - [NETXBIG_LED_TIMER1] = 3, - [NETXBIG_LED_TIMER2] = 7, -}; - -static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = { - [NETXBIG_LED_OFF] = 0, - [NETXBIG_LED_ON] = 7, - [NETXBIG_LED_SATA] = 1, - [NETXBIG_LED_TIMER1] = 3, - [NETXBIG_LED_TIMER2] = NETXBIG_LED_INVALID_MODE, -}; - -static struct netxbig_led_timer netxbig_v2_led_timer[] = { - [0] = { - .delay_on = 500, - .delay_off = 500, - .mode = NETXBIG_LED_TIMER1, - }, - [1] = { - .delay_on = 500, - .delay_off = 1000, - .mode = NETXBIG_LED_TIMER2, - }, -}; - -#define NETXBIG_LED(_name, maddr, mval, baddr) \ - { .name = _name, \ - .mode_addr = maddr, \ - .mode_val = mval, \ - .bright_addr = baddr } - -static struct netxbig_led net2big_v2_leds_ctrl[] = { - NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled, 1), - NETXBIG_LED("net2big-v2:red:power", 0, netxbig_v2_red_mled, 1), - NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2), - NETXBIG_LED("net2big-v2:red:sata0", 3, netxbig_v2_red_mled, 2), - NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2), - NETXBIG_LED("net2big-v2:red:sata1", 4, netxbig_v2_red_mled, 2), -}; - -static struct netxbig_led_platform_data net2big_v2_leds_data = { - .gpio_ext = &netxbig_v2_gpio_ext, - .timer = netxbig_v2_led_timer, - .num_timer = ARRAY_SIZE(netxbig_v2_led_timer), - .leds = net2big_v2_leds_ctrl, - .num_leds = ARRAY_SIZE(net2big_v2_leds_ctrl), -}; - -static struct netxbig_led net5big_v2_leds_ctrl[] = { - NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled, 1), - NETXBIG_LED("net5big-v2:red:power", 0, netxbig_v2_red_mled, 1), - NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2), - NETXBIG_LED("net5big-v2:red:sata0", 3, netxbig_v2_red_mled, 2), - NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2), - NETXBIG_LED("net5big-v2:red:sata1", 4, netxbig_v2_red_mled, 2), - NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2), - NETXBIG_LED("net5big-v2:red:sata2", 5, netxbig_v2_red_mled, 2), - NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2), - NETXBIG_LED("net5big-v2:red:sata3", 6, netxbig_v2_red_mled, 2), - NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2), - NETXBIG_LED("net5big-v2:red:sata5", 7, netxbig_v2_red_mled, 2), -}; +/***************************************************************************** + * Timer + ****************************************************************************/ -static struct netxbig_led_platform_data net5big_v2_leds_data = { - .gpio_ext = &netxbig_v2_gpio_ext, - .timer = netxbig_v2_led_timer, - .num_timer = ARRAY_SIZE(netxbig_v2_led_timer), - .leds = net5big_v2_leds_ctrl, - .num_leds = ARRAY_SIZE(net5big_v2_leds_ctrl), -}; +static void netxbig_v2_timer_init(void) +{ + kirkwood_tclk = 166666667; + orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); +} -static struct platform_device netxbig_v2_leds = { - .name = "leds-netxbig", - .id = -1, - .dev = { - .platform_data = &net2big_v2_leds_data, - }, +struct sys_timer netxbig_v2_timer = { + .init = netxbig_v2_timer_init, }; /***************************************************************************** @@ -289,18 +284,18 @@ static unsigned int net2big_v2_mpp_config[] __initdata = { MPP24_GPIO, /* USB mode select */ MPP26_GPIO, /* USB device vbus */ MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* GPIO extension ALE */ + MPP29_GPIO, /* CPLD extension ALE */ MPP34_GPIO, /* Rear Push button */ MPP35_GPIO, /* Inhibit switch power-off */ MPP36_GPIO, /* SATA HDD1 presence */ MPP37_GPIO, /* SATA HDD2 presence */ MPP40_GPIO, /* eSATA presence */ - MPP44_GPIO, /* GPIO extension (data 0) */ - MPP45_GPIO, /* GPIO extension (data 1) */ - MPP46_GPIO, /* GPIO extension (data 2) */ - MPP47_GPIO, /* GPIO extension (addr 0) */ - MPP48_GPIO, /* GPIO extension (addr 1) */ - MPP49_GPIO, /* GPIO extension (addr 2) */ + MPP44_GPIO, /* CPLD extension (data 0) */ + MPP45_GPIO, /* CPLD extension (data 1) */ + MPP46_GPIO, /* CPLD extension (data 2) */ + MPP47_GPIO, /* CPLD extension (addr 0) */ + MPP48_GPIO, /* CPLD extension (addr 1) */ + MPP49_GPIO, /* CPLD extension (addr 2) */ 0 }; @@ -329,7 +324,7 @@ static unsigned int net5big_v2_mpp_config[] __initdata = { MPP26_GE1_RXD2, MPP27_GE1_RXD3, MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* GPIO extension ALE */ + MPP29_GPIO, /* CPLD extension ALE */ MPP30_GE1_RXCTL, MPP31_GE1_RXCLK, MPP32_GE1_TCLKOUT, @@ -344,12 +339,12 @@ static unsigned int net5big_v2_mpp_config[] __initdata = { MPP41_GPIO, /* SATA HDD3 power */ MPP42_GPIO, /* SATA HDD4 power */ MPP43_GPIO, /* SATA HDD5 power */ - MPP44_GPIO, /* GPIO extension (data 0) */ - MPP45_GPIO, /* GPIO extension (data 1) */ - MPP46_GPIO, /* GPIO extension (data 2) */ - MPP47_GPIO, /* GPIO extension (addr 0) */ - MPP48_GPIO, /* GPIO extension (addr 1) */ - MPP49_GPIO, /* GPIO extension (addr 2) */ + MPP44_GPIO, /* CPLD extension (data 0) */ + MPP45_GPIO, /* CPLD extension (data 1) */ + MPP46_GPIO, /* CPLD extension (data 2) */ + MPP47_GPIO, /* CPLD extension (addr 0) */ + MPP48_GPIO, /* CPLD extension (addr 1) */ + MPP49_GPIO, /* CPLD extension (addr 2) */ 0 }; @@ -371,10 +366,7 @@ static void __init netxbig_v2_init(void) else kirkwood_mpp_conf(net5big_v2_mpp_config); - if (machine_is_net2big_v2()) - lacie_v2_hdd_power_init(2); - else - lacie_v2_hdd_power_init(5); + netxbig_v2_sata_power_init(); kirkwood_ehci_init(); kirkwood_ge00_init(&netxbig_v2_ge00_data); @@ -382,12 +374,13 @@ static void __init netxbig_v2_init(void) kirkwood_ge01_init(&netxbig_v2_ge01_data); kirkwood_sata_init(&netxbig_v2_sata_data); kirkwood_uart0_init(); - lacie_v2_register_flash(); - lacie_v2_register_i2c_devices(); + spi_register_board_info(netxbig_v2_spi_slave_info, + ARRAY_SIZE(netxbig_v2_spi_slave_info)); + kirkwood_spi_init(); + kirkwood_i2c_init(); + i2c_register_board_info(0, netxbig_v2_i2c_info, + ARRAY_SIZE(netxbig_v2_i2c_info)); - if (machine_is_net5big_v2()) - netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data; - platform_device_register(&netxbig_v2_leds); platform_device_register(&netxbig_v2_gpio_buttons); if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 && @@ -405,7 +398,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2") .init_machine = netxbig_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &lacie_v2_timer, + .timer = &netxbig_v2_timer, MACHINE_END #endif @@ -417,6 +410,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2") .init_machine = netxbig_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &lacie_v2_timer, + .timer = &netxbig_v2_timer, MACHINE_END #endif diff --git a/trunk/arch/arm/mach-kirkwood/openrd-setup.c b/trunk/arch/arm/mach-kirkwood/openrd-setup.c index 38017c8ac43f..fd06be618815 100644 --- a/trunk/arch/arm/mach-kirkwood/openrd-setup.c +++ b/trunk/arch/arm/mach-kirkwood/openrd-setup.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -58,22 +57,7 @@ static struct mvsdio_platform_data openrd_mvsdio_data = { }; static unsigned int openrd_mpp_config[] __initdata = { - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP28_GPIO, MPP29_GPIO, - MPP34_GPIO, - 0 -}; - -/* Configure MPP for UART1 */ -static unsigned int openrd_uart1_mpp_config[] __initdata = { - MPP13_UART1_TXD, - MPP14_UART1_RXD, 0 }; @@ -83,68 +67,6 @@ static struct i2c_board_info i2c_board_info[] __initdata = { }, }; -static int __initdata uart1; - -static int __init sd_uart_selection(char *str) -{ - uart1 = -EINVAL; - - /* Default is SD. Change if required, for UART */ - if (!str) - return 0; - - if (!strncmp(str, "232", 3)) { - uart1 = 232; - } else if (!strncmp(str, "485", 3)) { - /* OpenRD-Base doesn't have RS485. Treat is as an - * unknown argument & just have default setting - - * which is SD */ - if (machine_is_openrd_base()) { - uart1 = -ENODEV; - return 1; - } - - uart1 = 485; - } - return 1; -} -/* Parse boot_command_line string kw_openrd_init_uart1=232/485 */ -__setup("kw_openrd_init_uart1=", sd_uart_selection); - -static int __init uart1_mpp_config(void) -{ - kirkwood_mpp_conf(openrd_uart1_mpp_config); - - if (gpio_request(34, "SD_UART1_SEL")) { - printk(KERN_ERR "GPIO request failed for SD/UART1 selection" - ", gpio: 34\n"); - return -EIO; - } - - if (gpio_request(28, "RS232_RS485_SEL")) { - printk(KERN_ERR "GPIO request failed for RS232/RS485 selection" - ", gpio# 28\n"); - gpio_free(34); - return -EIO; - } - - /* Select UART1 - * Pin # 34: 0 => UART1, 1 => SD */ - gpio_direction_output(34, 0); - - /* Select RS232 OR RS485 - * Pin # 28: 0 => RS232, 1 => RS485 */ - if (uart1 == 232) - gpio_direction_output(28, 0); - else - gpio_direction_output(28, 1); - - gpio_free(34); - gpio_free(28); - - return 0; -} - static void __init openrd_init(void) { /* @@ -168,6 +90,7 @@ static void __init openrd_init(void) kirkwood_ge01_init(&openrd_ge01_data); kirkwood_sata_init(&openrd_sata_data); + kirkwood_sdio_init(&openrd_mvsdio_data); kirkwood_i2c_init(); @@ -176,28 +99,6 @@ static void __init openrd_init(void) ARRAY_SIZE(i2c_board_info)); kirkwood_audio_init(); } - - if (uart1 <= 0) { - if (uart1 < 0) - printk(KERN_ERR "Invalid kernel parameter to select " - "UART1. Defaulting to SD. ERROR CODE: %d\n", - uart1); - - /* Select SD - * Pin # 34: 0 => UART1, 1 => SD */ - if (gpio_request(34, "SD_UART1_SEL")) { - printk(KERN_ERR "GPIO request failed for SD/UART1 " - "selection, gpio: 34\n"); - } else { - - gpio_direction_output(34, 1); - gpio_free(34); - kirkwood_sdio_init(&openrd_mvsdio_data); - } - } else { - if (!uart1_mpp_config()) - kirkwood_uart1_init(); - } } static int __init openrd_pci_init(void) diff --git a/trunk/arch/arm/mach-msm/include/mach/vmalloc.h b/trunk/arch/arm/mach-msm/include/mach/vmalloc.h index 31a32ad062dc..05f81fd8623c 100644 --- a/trunk/arch/arm/mach-msm/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-msm/include/mach/vmalloc.h @@ -16,7 +16,7 @@ #ifndef __ASM_ARCH_MSM_VMALLOC_H #define __ASM_ARCH_MSM_VMALLOC_H -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) #endif diff --git a/trunk/arch/arm/mach-mx25/Kconfig b/trunk/arch/arm/mach-mx25/Kconfig index aa57e35ce3cd..c71a7bc19284 100644 --- a/trunk/arch/arm/mach-mx25/Kconfig +++ b/trunk/arch/arm/mach-mx25/Kconfig @@ -12,8 +12,6 @@ config MACH_EUKREA_CPUIMX25 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC select MXC_ULPI if USB_ULPI choice @@ -22,8 +20,8 @@ choice default MACH_EUKREA_MBIMXSD25_BASEBOARD config MACH_EUKREA_MBIMXSD25_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_IMX_SSI + prompt "Eukrea MBIMXSD development board" + bool help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. diff --git a/trunk/arch/arm/mach-mx25/clock.c b/trunk/arch/arm/mach-mx25/clock.c index 2179713873c2..40c7cc41cee3 100644 --- a/trunk/arch/arm/mach-mx25/clock.c +++ b/trunk/arch/arm/mach-mx25/clock.c @@ -139,16 +139,6 @@ static unsigned long get_rate_lcdc(struct clk *clk) return get_rate_per(7); } -static unsigned long get_rate_esdhc1(struct clk *clk) -{ - return get_rate_per(3); -} - -static unsigned long get_rate_esdhc2(struct clk *clk) -{ - return get_rate_per(4); -} - static unsigned long get_rate_csi(struct clk *clk) { return get_rate_per(0); @@ -223,12 +213,6 @@ DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1, NULL, NULL); -DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0, 3, get_rate_esdhc1, NULL, - &esdhc1_ahb_clk); -DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL); -DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL, - &esdhc2_ahb_clk); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); @@ -254,10 +238,6 @@ DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); -DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL, - &esdhc1_per_clk); -DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL, - &esdhc2_per_clk); DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); @@ -281,9 +261,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) - _REGISTER_CLOCK("imx25-cspi.0", NULL, cspi1_clk) - _REGISTER_CLOCK("imx25-cspi.1", NULL, cspi2_clk) - _REGISTER_CLOCK("imx25-cspi.2", NULL, cspi3_clk) + _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) + _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) + _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk) _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) @@ -299,8 +279,6 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) diff --git a/trunk/arch/arm/mach-mx25/devices-imx25.h b/trunk/arch/arm/mach-mx25/devices-imx25.h index 733aaee5bae8..d86a7c3ca8b0 100644 --- a/trunk/arch/arm/mach-mx25/devices-imx25.h +++ b/trunk/arch/arm/mach-mx25/devices-imx25.h @@ -9,47 +9,35 @@ #include #include -extern const struct imx_fec_data imx25_fec_data __initconst; -#define imx25_add_fec(pdata) \ - imx_add_fec(&imx25_fec_data, pdata) - #define imx25_add_flexcan0(pdata) \ imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata) #define imx25_add_flexcan1(pdata) \ imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) -extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; -#define imx25_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata) -#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata) -#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) -#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) - -extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; -#define imx25_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; -#define imx25_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata) -#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata) -#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata) -#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata) -#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) -#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) +#define imx25_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata) +#define imx25_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata) +#define imx25_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata) + +#define imx25_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata) +#define imx25_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata) +#define imx25_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata) +#define imx25_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata) +#define imx25_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata) -extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; #define imx25_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) - -extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst; -#define imx25_add_spi_imx(id, pdata) \ - imx_add_spi_imx(&imx25_spi_imx_data[id], pdata) -#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) -#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) -#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) - -#define imx25_add_esdhc0(pdata) \ - imx_add_esdhc(0, MX25_ESDHC1_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC1, pdata) -#define imx25_add_esdhc1(pdata) \ - imx_add_esdhc(1, MX25_ESDHC2_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC2, pdata) + imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata) + +#define imx25_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata) +#define imx25_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata) +#define imx25_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata) diff --git a/trunk/arch/arm/mach-mx25/devices.c b/trunk/arch/arm/mach-mx25/devices.c index 1d0eb3e85941..3468eb15b236 100644 --- a/trunk/arch/arm/mach-mx25/devices.c +++ b/trunk/arch/arm/mach-mx25/devices.c @@ -208,6 +208,26 @@ int __init imx25_register_gpios(void) return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); } +static struct resource mx25_fec_resources[] = { + { + .start = MX25_FEC_BASE_ADDR, + .end = MX25_FEC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_FEC, + .end = MX25_INT_FEC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mx25_fec_device = { + .name = "fec", + .id = 0, + .num_resources = ARRAY_SIZE(mx25_fec_resources), + .resource = mx25_fec_resources, +}; + static struct resource mx25_rtc_resources[] = { { .start = MX25_DRYICE_BASE_ADDR, @@ -285,6 +305,44 @@ struct platform_device mx25_kpp_device = { .resource = mx25_kpp_resources, }; +static struct resource imx_ssi_resources0[] = { + { + .start = MX25_SSI1_BASE_ADDR, + .end = MX25_SSI1_BASE_ADDR + 0x3fff, + .flags = IORESOURCE_MEM, + }, { + .start = MX25_INT_SSI1, + .end = MX25_INT_SSI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource imx_ssi_resources1[] = { + { + .start = MX25_SSI2_BASE_ADDR, + .end = MX25_SSI2_BASE_ADDR + 0x3fff, + .flags = IORESOURCE_MEM + }, { + .start = MX25_INT_SSI2, + .end = MX25_INT_SSI2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_ssi_device0 = { + .name = "imx-ssi", + .id = 0, + .num_resources = ARRAY_SIZE(imx_ssi_resources0), + .resource = imx_ssi_resources0, +}; + +struct platform_device imx_ssi_device1 = { + .name = "imx-ssi", + .id = 1, + .num_resources = ARRAY_SIZE(imx_ssi_resources1), + .resource = imx_ssi_resources1, +}; + static struct resource mx25_csi_resources[] = { { .start = MX25_CSI_BASE_ADDR, diff --git a/trunk/arch/arm/mach-mx25/devices.h b/trunk/arch/arm/mach-mx25/devices.h index 7b70a43c3a4b..4aceb68e35a7 100644 --- a/trunk/arch/arm/mach-mx25/devices.h +++ b/trunk/arch/arm/mach-mx25/devices.h @@ -6,8 +6,11 @@ extern struct platform_device mxc_pwm_device1; extern struct platform_device mxc_pwm_device2; extern struct platform_device mxc_pwm_device3; extern struct platform_device mxc_keypad_device; +extern struct platform_device mx25_fec_device; extern struct platform_device mx25_rtc_device; extern struct platform_device mx25_fb_device; extern struct platform_device mxc_wdt; extern struct platform_device mx25_kpp_device; +extern struct platform_device imx_ssi_device0; +extern struct platform_device imx_ssi_device1; extern struct platform_device mx25_csi_device; diff --git a/trunk/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/trunk/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c index c1fe048c445e..4aaadc753d3e 100644 --- a/trunk/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c +++ b/trunk/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include "devices-imx25.h" @@ -89,9 +90,6 @@ static struct pad_desc eukrea_mbimxsd_pads[] = { MX25_PAD_KPP_COL2__AUD5_TXC, MX25_PAD_KPP_COL1__AUD5_RXD, MX25_PAD_KPP_COL0__AUD5_TXD, - /* CAN */ - MX25_PAD_GPIO_D__CAN2_RX, - MX25_PAD_GPIO_C__CAN2_TX, }; #define GPIO_LED1 83 @@ -207,8 +205,7 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { }, }; -static const -struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { +struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, }; @@ -242,10 +239,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void) imx25_add_imx_uart1(&uart_pdata); mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); - imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); - - imx25_add_flexcan1(NULL); - imx25_add_esdhc0(NULL); + mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/trunk/arch/arm/mach-mx25/mach-cpuimx25.c b/trunk/arch/arm/mach-mx25/mach-cpuimx25.c index 21d9b9e9c92c..e064bb3d6919 100644 --- a/trunk/arch/arm/mach-mx25/mach-cpuimx25.c +++ b/trunk/arch/arm/mach-mx25/mach-cpuimx25.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -66,7 +67,7 @@ static struct pad_desc eukrea_cpuimx25_pads[] = { MX25_PAD_I2C1_DAT__I2C1_DAT, }; -static const struct fec_platform_data mx25_fec_pdata __initconst = { +static struct fec_platform_data mx25_fec_pdata = { .phy = PHY_INTERFACE_MODE_RMII, }; @@ -128,7 +129,7 @@ static void __init eukrea_cpuimx25_init(void) imx25_add_imx_uart0(&uart_pdata); imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); mxc_register_device(&mx25_rtc_device, NULL); - imx25_add_fec(&mx25_fec_pdata); + mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); diff --git a/trunk/arch/arm/mach-mx25/mach-mx25_3ds.c b/trunk/arch/arm/mach-mx25/mach-mx25_3ds.c index bd1805698631..62bc21f11a71 100644 --- a/trunk/arch/arm/mach-mx25/mach-mx25_3ds.c +++ b/trunk/arch/arm/mach-mx25/mach-mx25_3ds.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -98,7 +99,7 @@ static struct pad_desc mx25pdk_pads[] = { MX25_PAD_KPP_COL3__KPP_COL3, }; -static const struct fec_platform_data mx25_fec_pdata __initconst = { +static struct fec_platform_data mx25_fec_pdata = { .phy = PHY_INTERFACE_MODE_RMII, }; @@ -191,7 +192,7 @@ static void __init mx25pdk_init(void) mxc_register_device(&mxc_wdt, NULL); mx25pdk_fec_reset(); - imx25_add_fec(&mx25_fec_pdata); + mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data); } diff --git a/trunk/arch/arm/mach-mx3/Kconfig b/trunk/arch/arm/mach-mx3/Kconfig index 096fd33f8ab9..85beece802aa 100644 --- a/trunk/arch/arm/mach-mx3/Kconfig +++ b/trunk/arch/arm/mach-mx3/Kconfig @@ -9,7 +9,6 @@ config ARCH_MX35 bool select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 - select HAVE_EPIT comment "MX3 platforms:" @@ -17,7 +16,6 @@ config MACH_MX31ADS bool "Support MX31ADS platforms" select ARCH_MX31 select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART default y help @@ -119,11 +117,9 @@ config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" select ARCH_MX35 select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC select MXC_ULPI if USB_ULPI help Include support for Phytec pcm043 platform. This includes @@ -144,7 +140,6 @@ config MACH_MX35_3DS bool "Support MX35PDK platform" select ARCH_MX35 select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND default n help Include support for MX35PDK platform. This includes specific @@ -164,8 +159,6 @@ config MACH_EUKREA_CPUIMX35 select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC select MXC_ULPI if USB_ULPI help Include support for Eukrea CPUIMX35 platform. This includes @@ -177,8 +170,8 @@ choice default MACH_EUKREA_MBIMXSD35_BASEBOARD config MACH_EUKREA_MBIMXSD35_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_IMX_SSI + prompt "Eukrea MBIMXSD development board" + bool help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. diff --git a/trunk/arch/arm/mach-mx3/Makefile b/trunk/arch/arm/mach-mx3/Makefile index 8a182d0a3fcf..2bd7beceb991 100644 --- a/trunk/arch/arm/mach-mx3/Makefile +++ b/trunk/arch/arm/mach-mx3/Makefile @@ -7,6 +7,7 @@ obj-y := mm.o devices.o cpu.o CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o diff --git a/trunk/arch/arm/mach-mx3/clock-imx31.c b/trunk/arch/arm/mach-mx3/clock-imx31.c index 109e98f323e0..9a9eb6de6127 100644 --- a/trunk/arch/arm/mach-mx3/clock-imx31.c +++ b/trunk/arch/arm/mach-mx3/clock-imx31.c @@ -477,7 +477,7 @@ DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk); DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk); DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk); DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk); DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk); DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk); DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk); @@ -525,9 +525,9 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "emi", emi_clk) - _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk) - _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk) - _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk) + _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) + _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) + _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK(NULL, "pwm", pwm_clk) _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) @@ -564,7 +564,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK(NULL, "rtic", rtic_clk) _REGISTER_CLOCK(NULL, "rng", rng_clk) - _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1) + _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1) _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2) _REGISTER_CLOCK(NULL, "mstick", mstick1_clk) _REGISTER_CLOCK(NULL, "mstick", mstick2_clk) diff --git a/trunk/arch/arm/mach-mx3/clock-imx35.c b/trunk/arch/arm/mach-mx3/clock-imx35.c index 61e4a318980a..7a62e744a8b0 100644 --- a/trunk/arch/arm/mach-mx3/clock-imx35.c +++ b/trunk/arch/arm/mach-mx3/clock-imx35.c @@ -364,8 +364,8 @@ DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL); DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL); DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL); DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL); -DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg, NULL); -DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg, NULL); +DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL); +DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL); DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL); DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL); DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL); @@ -451,17 +451,17 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) - _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk) - _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk) + _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) + _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) _REGISTER_CLOCK(NULL, "ect", ect_clk) _REGISTER_CLOCK(NULL, "edio", edio_clk) _REGISTER_CLOCK(NULL, "emi", emi_clk) - _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk) - _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk) + _REGISTER_CLOCK(NULL, "epit", epit1_clk) + _REGISTER_CLOCK(NULL, "epit", epit2_clk) _REGISTER_CLOCK(NULL, "esai", esai_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk) + _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk) + _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk) + _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK(NULL, "gpio", gpio1_clk) _REGISTER_CLOCK(NULL, "gpio", gpio2_clk) @@ -482,7 +482,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "rtc", rtc_clk) _REGISTER_CLOCK(NULL, "rtic", rtic_clk) _REGISTER_CLOCK(NULL, "scc", scc_clk) - _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) + _REGISTER_CLOCK(NULL, "sdma", sdma_clk) _REGISTER_CLOCK(NULL, "spba", spba_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) @@ -535,16 +535,8 @@ int __init mx35_clocks_init() __raw_writel(cgr2, CCM_BASE + CCM_CGR2); __raw_writel(cgr3, CCM_BASE + CCM_CGR3); - clk_enable(&iim_clk); - mx35_read_cpu_rev(); - -#ifdef CONFIG_MXC_USE_EPIT - epit_timer_init(&epit1_clk, - MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); -#else mxc_timer_init(&gpt_clk, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); -#endif return 0; } diff --git a/trunk/arch/arm/mach-mx3/cpu.c b/trunk/arch/arm/mach-mx3/cpu.c index d00a75457812..861afe0fe3ad 100644 --- a/trunk/arch/arm/mach-mx3/cpu.c +++ b/trunk/arch/arm/mach-mx3/cpu.c @@ -25,15 +25,15 @@ struct mx3_cpu_type { }; static struct mx3_cpu_type mx31_cpu_type[] __initdata = { - { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = MX3x_CHIP_REV_1_0 }, - { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, - { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, - { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, - { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, + { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = CHIP_REV_1_0 }, + { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = CHIP_REV_1_1 }, + { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = CHIP_REV_1_1 }, + { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = CHIP_REV_1_1 }, + { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = CHIP_REV_1_1 }, + { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = CHIP_REV_1_2 }, + { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = CHIP_REV_1_2 }, + { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = CHIP_REV_2_0 }, + { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = CHIP_REV_2_0 }, }; void __init mx31_read_cpu_rev(void) @@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void) u32 i, srev; /* read SREV register from IIM module */ - srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); + srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV)); for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) if (srev == mx31_cpu_type[i].srev) { @@ -55,30 +55,3 @@ void __init mx31_read_cpu_rev(void) printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); } - -unsigned int mx35_cpu_rev; -EXPORT_SYMBOL(mx35_cpu_rev); - -void __init mx35_read_cpu_rev(void) -{ - u32 rev; - char *srev = "unknown"; - - rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); - switch (rev) { - case 0x00: - mx35_cpu_rev = MX3x_CHIP_REV_1_0; - srev = "1.0"; - break; - case 0x10: - mx35_cpu_rev = MX3x_CHIP_REV_2_0; - srev = "2.0"; - break; - case 0x11: - mx35_cpu_rev = MX3x_CHIP_REV_2_1; - srev = "2.1"; - break; - } - - printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); -} diff --git a/trunk/arch/arm/mach-mx3/devices-imx31.h b/trunk/arch/arm/mach-mx3/devices-imx31.h index de9598590eba..3b1a44a20585 100644 --- a/trunk/arch/arm/mach-mx3/devices-imx31.h +++ b/trunk/arch/arm/mach-mx3/devices-imx31.h @@ -9,33 +9,30 @@ #include #include -extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; -#define imx31_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) -#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata) -#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) -#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) +#define imx31_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata) +#define imx31_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata) +#define imx31_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata) -extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; -#define imx31_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) +#define imx31_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata) +#define imx31_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata) +#define imx31_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata) +#define imx31_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata) +#define imx31_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata) -extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; -#define imx31_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) -#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata) -#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata) -#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata) -#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) -#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) - -extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; #define imx31_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) + imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata) -extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; -#define imx31_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx31_cspi_data[id], pdata) -#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) -#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata) -#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata) +#define imx31_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata) +#define imx31_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata) +#define imx31_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata) diff --git a/trunk/arch/arm/mach-mx3/devices-imx35.h b/trunk/arch/arm/mach-mx3/devices-imx35.h index 509b346b7fef..f6a431a4c3d2 100644 --- a/trunk/arch/arm/mach-mx3/devices-imx35.h +++ b/trunk/arch/arm/mach-mx3/devices-imx35.h @@ -9,46 +9,29 @@ #include #include -extern const struct imx_fec_data imx35_fec_data __initconst; -#define imx35_add_fec(pdata) \ - imx_add_fec(&imx35_fec_data, pdata) - #define imx35_add_flexcan0(pdata) \ imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) #define imx35_add_flexcan1(pdata) \ imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) -extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; -#define imx35_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata) -#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata) -#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) -#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) - -extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; -#define imx35_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) +#define imx35_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata) +#define imx35_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata) +#define imx35_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata) -extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; -#define imx35_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) -#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata) -#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) -#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) +#define imx35_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata) +#define imx35_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata) +#define imx35_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata) -extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; #define imx35_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) - -extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; -#define imx35_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx35_cspi_data[id], pdata) -#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) -#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) + imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata) -#define imx35_add_esdhc0(pdata) \ - imx_add_esdhc(0, MX35_ESDHC1_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC1, pdata) -#define imx35_add_esdhc1(pdata) \ - imx_add_esdhc(1, MX35_ESDHC2_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC2, pdata) -#define imx35_add_esdhc2(pdata) \ - imx_add_esdhc(2, MX35_ESDHC3_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC3, pdata) +#define imx35_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata) +#define imx35_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata) diff --git a/trunk/arch/arm/mach-mx3/devices.c b/trunk/arch/arm/mach-mx3/devices.c index f4dff11aaee7..a4fd1a26fc91 100644 --- a/trunk/arch/arm/mach-mx3/devices.c +++ b/trunk/arch/arm/mach-mx3/devices.c @@ -281,6 +281,65 @@ struct platform_device mxc_usbh2 = { .num_resources = ARRAY_SIZE(mxc_usbh2_resources), }; +#if defined(CONFIG_ARCH_MX35) +static struct resource mxc_fec_resources[] = { + { + .start = MXC_FEC_BASE_ADDR, + .end = MXC_FEC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_FEC, + .end = MXC_INT_FEC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_fec_device = { + .name = "fec", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_fec_resources), + .resource = mxc_fec_resources, +}; +#endif + +static struct resource imx_ssi_resources0[] = { + { + .start = SSI1_BASE_ADDR, + .end = SSI1_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX31_INT_SSI1, + .end = MX31_INT_SSI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource imx_ssi_resources1[] = { + { + .start = SSI2_BASE_ADDR, + .end = SSI2_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM + }, { + .start = MX31_INT_SSI2, + .end = MX31_INT_SSI2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_ssi_device0 = { + .name = "imx-ssi", + .id = 0, + .num_resources = ARRAY_SIZE(imx_ssi_resources0), + .resource = imx_ssi_resources0, +}; + +struct platform_device imx_ssi_device1 = { + .name = "imx-ssi", + .id = 1, + .num_resources = ARRAY_SIZE(imx_ssi_resources1), + .resource = imx_ssi_resources1, +}; + static struct resource imx_wdt_resources[] = { { .flags = IORESOURCE_MEM, @@ -351,6 +410,10 @@ static int __init mx3_devices_init(void) mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; mxc_usbh1_resources[1].start = MXC_INT_USBHS; mxc_usbh1_resources[1].end = MXC_INT_USBHS; + imx_ssi_resources0[1].start = MX35_INT_SSI1; + imx_ssi_resources0[1].end = MX35_INT_SSI1; + imx_ssi_resources1[1].start = MX35_INT_SSI2; + imx_ssi_resources1[1].end = MX35_INT_SSI2; imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; } diff --git a/trunk/arch/arm/mach-mx3/devices.h b/trunk/arch/arm/mach-mx3/devices.h index 585f814473d5..e5535234839f 100644 --- a/trunk/arch/arm/mach-mx3/devices.h +++ b/trunk/arch/arm/mach-mx3/devices.h @@ -2,6 +2,7 @@ extern struct platform_device mxc_w1_master_device; extern struct platform_device mx3_ipu; extern struct platform_device mx3_fb; extern struct platform_device mx3_camera; +extern struct platform_device mxc_fec_device; extern struct platform_device mxcsdhc_device0; extern struct platform_device mxcsdhc_device1; extern struct platform_device mxc_otg_udc_device; @@ -9,6 +10,9 @@ extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mxc_rnga_device; +extern struct platform_device imx_ssi_device0; +extern struct platform_device imx_ssi_device1; +extern struct platform_device imx_ssi_device1; extern struct platform_device imx_wdt_device0; extern struct platform_device imx_rtc_device0; extern struct platform_device imx_kpp_device; diff --git a/trunk/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/trunk/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c index 886959906fbc..f8f15e3ac7a0 100644 --- a/trunk/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/trunk/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c @@ -43,6 +43,7 @@ #include #include #include +#include #include "devices-imx35.h" #include "devices.h" @@ -119,16 +120,6 @@ static struct pad_desc eukrea_mbimxsd_pads[] = { MX35_PAD_STXD4__AUDMUX_AUD4_TXD, MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, MX35_PAD_SCK4__AUDMUX_AUD4_TXC, - /* CAN2 */ - MX35_PAD_TX5_RX0__CAN2_TXCAN, - MX35_PAD_TX4_RX1__CAN2_RXCAN, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, }; #define GPIO_LED1 (2 * 32 + 29) @@ -215,8 +206,7 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { }, }; -static const -struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { +struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, }; @@ -252,10 +242,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void) mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); - imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); - - imx35_add_flexcan1(NULL); - imx35_add_esdhc0(NULL); + mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/trunk/arch/arm/mach-mx3/mach-cpuimx35.c b/trunk/arch/arm/mach-mx3/mach-cpuimx35.c index 6024bb958eea..2a4f8b781ba4 100644 --- a/trunk/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/trunk/arch/arm/mach-mx3/mach-cpuimx35.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include @@ -54,16 +53,39 @@ static const struct imxuart_platform_data uart_pdata __initconst = { }; static const struct imxi2c_platform_data - eukrea_cpuimx35_i2c0_data __initconst = { - .bitrate = 100000, +eukrea_cpuimx35_i2c0_data __initconst = { + .bitrate = 50000, }; +#define TSC2007_IRQGPIO (2 * 32 + 2) +static int ts_get_pendown_state(void) +{ + int val = 0; + gpio_free(TSC2007_IRQGPIO); + gpio_request(TSC2007_IRQGPIO, NULL); + gpio_direction_input(TSC2007_IRQGPIO); + + val = gpio_get_value(TSC2007_IRQGPIO); + + gpio_free(TSC2007_IRQGPIO); + gpio_request(TSC2007_IRQGPIO, NULL); + + return val ? 0 : 1; +} + +static int ts_init(void) +{ + gpio_request(TSC2007_IRQGPIO, NULL); + return 0; +} + static struct tsc2007_platform_data tsc2007_info = { .model = 2007, .x_plate_ohms = 180, + .get_pendown_state = ts_get_pendown_state, + .init_platform_hw = ts_init, }; -#define TSC2007_IRQGPIO (2 * 32 + 2) static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { { I2C_BOARD_INFO("pcf8563", 0x51), @@ -76,6 +98,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { }; static struct platform_device *devices[] __initdata = { + &mxc_fec_device, &imx_wdt_device0, }; @@ -112,18 +135,18 @@ static struct pad_desc eukrea_cpuimx35_pads[] = { }; static const struct mxc_nand_platform_data - eukrea_cpuimx35_nand_board_info __initconst = { +eukrea_cpuimx35_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, .flash_bbt = 1, }; -static struct mxc_usbh_platform_data __maybe_unused otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = { +static struct mxc_usbh_platform_data usbh1_pdata = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, @@ -157,7 +180,6 @@ static void __init mxc_board_init(void) mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, ARRAY_SIZE(eukrea_cpuimx35_pads)); - imx35_add_fec(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); imx35_add_imx_uart0(&uart_pdata); diff --git a/trunk/arch/arm/mach-mx3/mach-mx31ads.c b/trunk/arch/arm/mach-mx3/mach-mx31ads.c index 96cedc4a47f5..94b3e7c42404 100644 --- a/trunk/arch/arm/mach-mx3/mach-mx31ads.c +++ b/trunk/arch/arm/mach-mx3/mach-mx31ads.c @@ -517,7 +517,7 @@ static unsigned int ssi_pins[] = { static void mxc_init_audio(void) { - imx31_add_imx_ssi(0, NULL); + mxc_register_device(&imx_ssi_device0, NULL); mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); } diff --git a/trunk/arch/arm/mach-mx3/mach-mx35_3ds.c b/trunk/arch/arm/mach-mx3/mach-mx35_3ds.c index 91bb06552af1..1c30d7212f17 100644 --- a/trunk/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/trunk/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -1,6 +1,5 @@ /* * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix * * Author: Fabio Estevam * @@ -28,8 +27,6 @@ #include #include -#include - #include #include #include @@ -38,7 +35,6 @@ #include #include #include -#include #include "devices-imx35.h" #include "devices.h" @@ -47,34 +43,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct physmap_flash_data mx35pdk_flash_data = { - .width = 2, -}; - -static struct resource mx35pdk_flash_resource = { - .start = MX35_CS0_BASE_ADDR, - .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx35pdk_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx35pdk_flash_data, - }, - .resource = &mx35pdk_flash_resource, - .num_resources = 1, -}; - -static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - static struct platform_device *devices[] __initdata = { - &mx35pdk_flash, + &mxc_fec_device, }; static struct pad_desc mx35pdk_pads[] = { @@ -105,24 +75,14 @@ static struct pad_desc mx35pdk_pads[] = { /* USBOTG */ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - /* USBH1 */ - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, }; /* OTG config */ -static struct fsl_usb2_platform_data usb_otg_pdata = { +static struct fsl_usb2_platform_data usb_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; -/* USB HOST config */ -static struct mxc_usbh_platform_data usb_host_pdata = { - .portsc = MXC_EHCI_MODE_SERIAL, - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY, -}; - /* * Board specific initialization. */ @@ -130,16 +90,11 @@ static void __init mxc_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); - imx35_add_fec(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); imx35_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata); - - mxc_register_device(&mxc_usbh1, &usb_host_pdata); - - imx35_add_mxc_nand(&mx35pdk_nand_board_info); + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } static void __init mx35pdk_timer_init(void) diff --git a/trunk/arch/arm/mach-mx3/mach-pcm043.c b/trunk/arch/arm/mach-mx3/mach-pcm043.c index e790a00cf99f..28886f0e62f9 100644 --- a/trunk/arch/arm/mach-mx3/mach-pcm043.c +++ b/trunk/arch/arm/mach-mx3/mach-pcm043.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "devices-imx35.h" #include "devices.h" @@ -140,6 +141,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = { static struct platform_device *devices[] __initdata = { &pcm043_flash, + &mxc_fec_device, &imx_wdt_device0, }; @@ -215,13 +217,6 @@ static struct pad_desc pcm043_pads[] = { /* CAN2 */ MX35_PAD_TX5_RX0__CAN2_TXCAN, MX35_PAD_TX4_RX1__CAN2_RXCAN, - /* esdhc */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, }; #define AC97_GPIO_TXFS (1 * 32 + 31) @@ -298,7 +293,7 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) mdelay(1); } -static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = { +static struct imx_ssi_platform_data pcm043_ssi_pdata = { .ac97_reset = pcm043_ac97_cold_reset, .ac97_warm_reset = pcm043_ac97_warm_reset, .flags = IMX_SSI_USE_AC97, @@ -362,12 +357,11 @@ static void __init mxc_board_init(void) MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */ MXC_AUDMUX_V2_PDCR_RXDSEL(3)); - imx35_add_fec(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); imx35_add_imx_uart0(&uart_pdata); imx35_add_mxc_nand(&pcm037_nand_board_info); - imx35_add_imx_ssi(0, &pcm043_ssi_pdata); + mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); imx35_add_imx_uart1(&uart_pdata); @@ -395,7 +389,6 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); imx35_add_flexcan1(NULL); - imx35_add_esdhc0(NULL); } static void __init pcm043_timer_init(void) diff --git a/trunk/arch/arm/mach-mx3/mm.c b/trunk/arch/arm/mach-mx3/mm.c index b4ffc531a82c..20e48c0195c4 100644 --- a/trunk/arch/arm/mach-mx3/mm.c +++ b/trunk/arch/arm/mach-mx3/mm.c @@ -110,24 +110,6 @@ void __init mx35_init_irq(void) static int mxc_init_l2x0(void) { void __iomem *l2x0_base; - void __iomem *clkctl_base; -/* - * First of all, we must repair broken chip settings. There are some - * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These - * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. - * Workaraound is to setup the correct register setting prior enabling the - * L2 cache. This should not hurt already working CPUs, as they are using the - * same value - */ -#define L2_MEM_VAL 0x10 - - clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); - if (clkctl_base != NULL) { - writel(0x00000515, clkctl_base + L2_MEM_VAL); - iounmap(clkctl_base); - } else { - pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); - } l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); if (IS_ERR(l2x0_base)) { diff --git a/trunk/arch/arm/mach-mx5/Kconfig b/trunk/arch/arm/mach-mx5/Kconfig index fad31cc5004b..0848db5dd364 100644 --- a/trunk/arch/arm/mach-mx5/Kconfig +++ b/trunk/arch/arm/mach-mx5/Kconfig @@ -5,14 +5,11 @@ config ARCH_MX51 default y select MXC_TZIC select ARCH_MXC_IOMUX_V3 - select ARCH_MXC_AUDMUX_V2 comment "MX5 platforms:" config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX51 Babbage platform, also known as MX51EVK in u-boot. This includes specific configurations for the board and its @@ -20,8 +17,6 @@ config MACH_MX51_BABBAGE config MACH_MX51_3DS bool "Support MX51PDK (3DS)" - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD help Include support for MX51PDK (3DS) platform. This includes specific @@ -29,8 +24,6 @@ config MACH_MX51_3DS config MACH_EUKREA_CPUIMX51 bool "Support Eukrea CPUIMX51 module" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART help Include support for Eukrea CPUIMX51 platform. This includes specific configurations for the module and its peripherals. @@ -49,11 +42,4 @@ config MACH_EUKREA_MBIMX51_BASEBOARD endchoice -config MACH_MX51_EFIKAMX - bool "Support MX51 Genesi Efika MX nettop" - select IMX_HAVE_PLATFORM_IMX_UART - help - Include support for Genesi Efika MX nettop. This includes specific - configurations for the board and its peripherals. - endif diff --git a/trunk/arch/arm/mach-mx5/Makefile b/trunk/arch/arm/mach-mx5/Makefile index d1aac9c3d33c..86c66e7f52f3 100644 --- a/trunk/arch/arm/mach-mx5/Makefile +++ b/trunk/arch/arm/mach-mx5/Makefile @@ -9,4 +9,3 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o -obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o diff --git a/trunk/arch/arm/mach-mx5/board-cpuimx51.c b/trunk/arch/arm/mach-mx5/board-cpuimx51.c index 61f051043bbc..623607a20f57 100644 --- a/trunk/arch/arm/mach-mx5/board-cpuimx51.c +++ b/trunk/arch/arm/mach-mx5/board-cpuimx51.c @@ -28,7 +28,9 @@ #include #include #include +#include #include +#include #include #include @@ -37,7 +39,6 @@ #include #include -#include "devices-imx51.h" #include "devices.h" #define CPUIMX51_USBH1_STP (0*32 + 27) @@ -108,6 +109,7 @@ static struct platform_device serial_device = { #endif static struct platform_device *devices[] __initdata = { + &mxc_fec_device, #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) &serial_device, #endif @@ -146,12 +148,11 @@ static struct pad_desc eukrea_cpuimx51_pads[] = { MX51_PAD_USBH1_STP__USBH1_STP, }; -static const struct imxuart_platform_data uart_pdata __initconst = { +static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -static const -struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = { +static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = { .bitrate = 100000, }; @@ -238,7 +239,7 @@ static void __init eukrea_cpuimx51_init(void) mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads)); - imx51_add_imx_uart(0, &uart_pdata); + mxc_register_device(&mxc_uart_device0, &uart_pdata); gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); gpio_direction_input(CPUIMX51_QUARTA_GPIO); gpio_free(CPUIMX51_QUARTA_GPIO); @@ -252,10 +253,9 @@ static void __init eukrea_cpuimx51_init(void) gpio_direction_input(CPUIMX51_QUARTD_GPIO); gpio_free(CPUIMX51_QUARTD_GPIO); - imx51_add_fec(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); - imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data); + mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data); i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); diff --git a/trunk/arch/arm/mach-mx5/board-mx51_3ds.c b/trunk/arch/arm/mach-mx5/board-mx51_3ds.c index ed08a2352a1a..f95c2fd94667 100644 --- a/trunk/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/trunk/arch/arm/mach-mx5/board-mx51_3ds.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include @@ -22,13 +21,12 @@ #include #include #include +#include #include -#include "devices-imx51.h" #include "devices.h" #define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) -#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) static struct pad_desc mx51_3ds_pads[] = { /* UART1 */ @@ -63,25 +61,19 @@ static struct pad_desc mx51_3ds_pads[] = { MX51_PAD_KEY_COL3__KEY_COL3, MX51_PAD_KEY_COL4__KEY_COL4, MX51_PAD_KEY_COL5__KEY_COL5, - - /* eCSPI2 */ - MX51_PAD_NANDF_RB2__ECSPI2_SCLK, - MX51_PAD_NANDF_RB3__ECSPI2_MISO, - MX51_PAD_NANDF_D15__ECSPI2_MOSI, - MX51_PAD_NANDF_D12__GPIO_3_28, }; /* Serial ports */ #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static const struct imxuart_platform_data uart_pdata __initconst = { +static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; static inline void mxc_init_imx_uart(void) { - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_uart_device1, &uart_pdata); + mxc_register_device(&mxc_uart_device2, &uart_pdata); } #else /* !SERIAL_IMX */ static inline void mxc_init_imx_uart(void) @@ -135,26 +127,6 @@ static inline void mxc_init_keypad(void) } #endif -static int mx51_3ds_spi2_cs[] = { - MXC_SPI_CS(0), - MX51_3DS_ECSPI2_CS, -}; - -static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = { - .chipselect = mx51_3ds_spi2_cs, - .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs), -}; - -static struct spi_board_info mx51_3ds_spi_nor_device[] = { - { - .modalias = "m25p80", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL,}, -}; - /* * Board specific initialization. */ @@ -164,10 +136,6 @@ static void __init mxc_board_init(void) ARRAY_SIZE(mx51_3ds_pads)); mxc_init_imx_uart(); - imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); - spi_register_board_info(mx51_3ds_spi_nor_device, - ARRAY_SIZE(mx51_3ds_spi_nor_device)); - if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT)) printk(KERN_WARNING "Init of the debugboard failed, all " "devices on the board are unusable.\n"); diff --git a/trunk/arch/arm/mach-mx5/board-mx51_babbage.c b/trunk/arch/arm/mach-mx5/board-mx51_babbage.c index 23ee4a447406..6e384d92e625 100644 --- a/trunk/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/trunk/arch/arm/mach-mx5/board-mx51_babbage.c @@ -17,11 +17,12 @@ #include #include #include -#include #include #include +#include #include +#include #include #include @@ -30,13 +31,11 @@ #include #include -#include "devices-imx51.h" #include "devices.h" #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ -#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ -#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ +#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */ /* USB_CTRL_1 */ #define MX51_USB_CTRL_1_OFFSET 0x10 @@ -46,6 +45,10 @@ #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 #define MX51_USB_PLL_DIV_24_MHZ 0x02 +static struct platform_device *devices[] __initdata = { + &mxc_fec_device, +}; + static struct pad_desc mx51babbage_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, @@ -90,41 +93,19 @@ static struct pad_desc mx51babbage_pads[] = { /* USB HUB reset line*/ MX51_PAD_GPIO_1_7__GPIO_1_7, - - /* FEC */ - MX51_PAD_EIM_EB2__FEC_MDIO, - MX51_PAD_EIM_EB3__FEC_RDAT1, - MX51_PAD_EIM_CS2__FEC_RDAT2, - MX51_PAD_EIM_CS3__FEC_RDAT3, - MX51_PAD_EIM_CS4__FEC_RX_ER, - MX51_PAD_EIM_CS5__FEC_CRS, - MX51_PAD_NANDF_RB2__FEC_COL, - MX51_PAD_NANDF_RB3__FEC_RXCLK, - MX51_PAD_NANDF_RB6__FEC_RDAT0, - MX51_PAD_NANDF_RB7__FEC_TDAT0, - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_NANDF_CS3__FEC_MDC, - MX51_PAD_NANDF_CS4__FEC_TDAT1, - MX51_PAD_NANDF_CS5__FEC_TDAT2, - MX51_PAD_NANDF_CS6__FEC_TDAT3, - MX51_PAD_NANDF_CS7__FEC_TX_EN, - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, - - /* FEC PHY reset line */ - MX51_PAD_EIM_A20__GPIO_2_14, }; /* Serial ports */ #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static const struct imxuart_platform_data uart_pdata __initconst = { +static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; static inline void mxc_init_imx_uart(void) { - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_uart_device1, &uart_pdata); + mxc_register_device(&mxc_uart_device2, &uart_pdata); } #else /* !SERIAL_IMX */ static inline void mxc_init_imx_uart(void) @@ -132,7 +113,7 @@ static inline void mxc_init_imx_uart(void) } #endif /* SERIAL_IMX */ -static const struct imxi2c_platform_data babbage_i2c_data __initconst = { +static struct imxi2c_platform_data babbage_i2c_data = { .bitrate = 100000, }; @@ -190,22 +171,6 @@ static inline void babbage_usbhub_reset(void) gpio_set_value(BABBAGE_USB_HUB_RESET, 1); } -static inline void babbage_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); - gpio_set_value(BABBAGE_FEC_PHY_RESET, 0); - msleep(1); - gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); -} - /* This function is board specific as the bit mask for the plldiv will also be different for other Freescale SoCs, thus a common bitmask is not possible and cannot get place in /plat-mxc/ehci.c.*/ @@ -213,7 +178,7 @@ static int initialize_otg_port(struct platform_device *pdev) { u32 v; void __iomem *usb_base; - void __iomem *usbother_base; + u32 usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -231,7 +196,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) { u32 v; void __iomem *usb_base; - void __iomem *usbother_base; + u32 usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -285,11 +250,10 @@ static void __init mxc_board_init(void) mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, ARRAY_SIZE(mx51babbage_pads)); mxc_init_imx_uart(); - babbage_fec_reset(); - imx51_add_fec(NULL); + platform_add_devices(devices, ARRAY_SIZE(devices)); - imx51_add_imx_i2c(0, &babbage_i2c_data); - imx51_add_imx_i2c(1, &babbage_i2c_data); + mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data); + mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data); mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); if (otg_mode_host) @@ -319,7 +283,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") /* Maintainer: Amit Kucheria */ .phys_io = MX51_AIPS1_BASE_ADDR, .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = MX51_PHYS_OFFSET + 0x100, + .boot_params = PHYS_OFFSET + 0x100, .map_io = mx51_map_io, .init_irq = mx51_init_irq, .init_machine = mxc_board_init, diff --git a/trunk/arch/arm/mach-mx5/board-mx51_efikamx.c b/trunk/arch/arm/mach-mx5/board-mx51_efikamx.c deleted file mode 100644 index b00502acdc15..000000000000 --- a/trunk/arch/arm/mach-mx5/board-mx51_efikamx.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 2010 Linaro Limited - * - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices-imx51.h" -#include "devices.h" - -#define MX51_USB_PLL_DIV_24_MHZ 0x01 - -static struct pad_desc mx51efikamx_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, -}; - -/* Serial ports */ -#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static const struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static inline void mxc_init_imx_uart(void) -{ - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); -} -#else /* !SERIAL_IMX */ -static inline void mxc_init_imx_uart(void) -{ -} -#endif /* SERIAL_IMX */ - -/* This function is board specific as the bit mask for the plldiv will also - * be different for other Freescale SoCs, thus a common bitmask is not - * possible and cannot get place in /plat-mxc/ehci.c. - */ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); - usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_24_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - return 0; -} - -static struct mxc_usbh_platform_data dr_utmi_config = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, - .flags = MXC_EHCI_INTERNAL_PHY, -}; - -static void __init mxc_board_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, - ARRAY_SIZE(mx51efikamx_pads)); - mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); - mxc_init_imx_uart(); -} - -static void __init mx51_efikamx_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 24576000); -} - -static struct sys_timer mxc_timer = { - .init = mx51_efikamx_timer_init, -}; - -MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") - /* Maintainer: Amit Kucheria */ - .phys_io = MX51_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = MX51_PHYS_OFFSET + 0x100, - .map_io = mx51_map_io, - .init_irq = mx51_init_irq, - .init_machine = mxc_board_init, - .timer = &mxc_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-mx5/clock-mx51.c b/trunk/arch/arm/mach-mx5/clock-mx51.c index 21cecc040172..57c10a9926cc 100644 --- a/trunk/arch/arm/mach-mx5/clock-mx51.c +++ b/trunk/arch/arm/mach-mx5/clock-mx51.c @@ -41,36 +41,34 @@ static struct clk usboh3_clk; #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ -static void _clk_ccgr_setclk(struct clk *clk, unsigned mode) +static int _clk_ccgr_enable(struct clk *clk) { - u32 reg = __raw_readl(clk->enable_reg); - - reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); - reg |= mode << clk->enable_shift; + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; __raw_writel(reg, clk->enable_reg); -} -static int _clk_ccgr_enable(struct clk *clk) -{ - _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON); return 0; } static void _clk_ccgr_disable(struct clk *clk) { - _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF); -} + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); -static int _clk_ccgr_enable_inrun(struct clk *clk) -{ - _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); - return 0; } static void _clk_ccgr_disable_inwait(struct clk *clk) { - _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); } /* @@ -573,64 +571,6 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) return 0; } -#define clk_nfc_set_parent NULL - -static unsigned long clk_nfc_get_rate(struct clk *clk) -{ - unsigned long rate; - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >> - MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1; - rate = clk_get_rate(clk->parent) / div; - WARN_ON(rate == 0); - return rate; -} - -static unsigned long clk_nfc_round_rate(struct clk *clk, - unsigned long rate) -{ - u32 div; - unsigned long parent_rate = clk_get_rate(clk->parent); - - if (!rate) - return -EINVAL; - - div = parent_rate / rate; - - if (parent_rate % rate) - div++; - - if (div > 8) - return -EINVAL; - - return parent_rate / div; - -} - -static int clk_nfc_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, div; - - div = clk_get_rate(clk->parent) / rate; - if (div == 0) - div++; - if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8)) - return -EINVAL; - - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; - reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; - __raw_writel(reg, MXC_CCM_CBCDR); - - while (__raw_readl(MXC_CCM_CDHIPR) & - MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){ - } - - return 0; -} - static unsigned long clk_usboh3_get_rate(struct clk *clk) { u32 reg, prediv, podf; @@ -680,17 +620,6 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) return ckih2_reference; } -static unsigned long clk_emi_slow_get_rate(struct clk *clk) -{ - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> - MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; - - return clk_get_rate(clk->parent) / div; -} - /* External high frequency clock */ static struct clk ckih_clk = { .get_rate = get_high_reference_clock_rate, @@ -833,105 +762,45 @@ static struct clk kpp_clk = { .id = 0, }; -static struct clk emi_slow_clk = { - .parent = &pll2_sw_clk, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable_inwait, - .get_rate = clk_emi_slow_get_rate, -}; - -#define DEFINE_CLOCK1(name, i, er, es, pfx, p, s) \ +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ static struct clk name = { \ .id = i, \ .enable_reg = er, \ .enable_shift = es, \ - .get_rate = pfx##_get_rate, \ - .set_rate = pfx##_set_rate, \ - .round_rate = pfx##_round_rate, \ - .set_parent = pfx##_set_parent, \ + .get_rate = gr, \ + .set_rate = sr, \ .enable = _clk_ccgr_enable, \ .disable = _clk_ccgr_disable, \ .parent = p, \ .secondary = s, \ } -/* eCSPI */ -static unsigned long clk_ecspi_get_rate(struct clk *clk) -{ - u32 reg, pred, podf; - - reg = __raw_readl(MXC_CCM_CSCDR2); - - pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> - MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; - podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> - MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; - - return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), - (pred + 1) * (podf + 1)); -} - -static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg, mux; - - mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, - &lp_apm_clk); - - reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; - __raw_writel(reg, MXC_CCM_CSCMR1); - - return 0; -} - -static struct clk ecspi_main_clk = { - .parent = &pll3_sw_clk, - .get_rate = clk_ecspi_get_rate, - .set_parent = clk_ecspi_set_parent, -}; - -#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = gr, \ - .set_rate = sr, \ - .enable = e, \ - .disable = d, \ - .parent = p, \ - .secondary = s, \ - } - -#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ - DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s) +/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, + get_rate, set_rate, parent, secondary); */ /* Shared peripheral bus arbiter */ DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, NULL, NULL, &ipg_clk, NULL); /* UART */ +DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, + NULL, NULL, &uart_root_clk, NULL); +DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, + NULL, NULL, &uart_root_clk, NULL); +DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, + NULL, NULL, &uart_root_clk, NULL); DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &ipg_clk, &aips_tz1_clk); DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, &ipg_clk, &aips_tz1_clk); DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, NULL, NULL, &ipg_clk, &spba_clk); -DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, - NULL, NULL, &uart_root_clk, &uart1_ipg_clk); -DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, &uart_root_clk, &uart2_ipg_clk); -DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, - NULL, NULL, &uart_root_clk, &uart3_ipg_clk); /* GPT */ +DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, &ipg_clk, NULL); DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &ipg_clk, &gpt_ipg_clk); /* I2C */ DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, @@ -945,42 +814,6 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, NULL, NULL, &ipg_clk, NULL); -/* NFC */ -DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET, - clk_nfc, &emi_slow_clk, NULL); - -/* SSI */ -DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET, - NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk); -DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET, - NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, - NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); - -/* eCSPI */ -DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, - &ipg_clk, &spba_clk); -DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET, - NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk); -DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET, - NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, - &ipg_clk, &aips_tz2_clk); -DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET, - NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk); - -/* CSPI */ -DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &ipg_clk, &aips_tz2_clk); -DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET, - NULL, NULL, &ipg_clk, &cspi_ipg_clk); - -/* SDMA */ -DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET, - NULL, NULL, &ahb_clk, NULL); - #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@ -1004,16 +837,6 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) - _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) - _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) - _REGISTER_CLOCK(NULL, "ckih", ckih_clk) - _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) - _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk) - _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) - _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) - _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) }; static void clk_tree_init(void) diff --git a/trunk/arch/arm/mach-mx5/cpu.c b/trunk/arch/arm/mach-mx5/cpu.c index eaacb6e9b5d0..2d37785e3857 100644 --- a/trunk/arch/arm/mach-mx5/cpu.c +++ b/trunk/arch/arm/mach-mx5/cpu.c @@ -70,25 +70,6 @@ int mx51_revision(void) } EXPORT_SYMBOL(mx51_revision); -#ifdef CONFIG_NEON - -/* - * All versions of the silicon before Rev. 3 have broken NEON implementations. - * Dependent on link order - so the assumption is that vfp_init is called - * before us. - */ -static int __init mx51_neon_fixup(void) -{ - if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) { - elf_hwcap &= ~HWCAP_NEON; - pr_info("Turning off NEON support, detected broken NEON implementation\n"); - } - return 0; -} - -late_initcall(mx51_neon_fixup); -#endif - static int __init post_cpu_init(void) { unsigned int reg; diff --git a/trunk/arch/arm/mach-mx5/devices-imx51.h b/trunk/arch/arm/mach-mx5/devices-imx51.h deleted file mode 100644 index c233379256b8..000000000000 --- a/trunk/arch/arm/mach-mx5/devices-imx51.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include - -extern const struct imx_fec_data imx51_fec_data __initconst; -#define imx51_add_fec(pdata) \ - imx_add_fec(&imx51_fec_data, pdata) - -extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst; -#define imx51_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) - -extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst; -#define imx51_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst; -#define imx51_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) - -extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst; -#define imx51_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) - -extern const struct imx_spi_imx_data imx51_cspi_data __initconst; -#define imx51_add_cspi(pdata) \ - imx_add_spi_imx(&imx51_cspi_data, pdata) - -extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; -#define imx51_add_ecspi(id, pdata) \ - imx_add_spi_imx(&imx51_ecspi_data[id], pdata) diff --git a/trunk/arch/arm/mach-mx5/devices.c b/trunk/arch/arm/mach-mx5/devices.c index 4c7be87a7c9d..1920ff4963b2 100644 --- a/trunk/arch/arm/mach-mx5/devices.c +++ b/trunk/arch/arm/mach-mx5/devices.c @@ -17,6 +17,120 @@ #include #include +static struct resource uart0[] = { + { + .start = MX51_UART1_BASE_ADDR, + .end = MX51_UART1_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART1, + .end = MX51_MXC_INT_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device0 = { + .name = "imx-uart", + .id = 0, + .resource = uart0, + .num_resources = ARRAY_SIZE(uart0), +}; + +static struct resource uart1[] = { + { + .start = MX51_UART2_BASE_ADDR, + .end = MX51_UART2_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART2, + .end = MX51_MXC_INT_UART2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device1 = { + .name = "imx-uart", + .id = 1, + .resource = uart1, + .num_resources = ARRAY_SIZE(uart1), +}; + +static struct resource uart2[] = { + { + .start = MX51_UART3_BASE_ADDR, + .end = MX51_UART3_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART3, + .end = MX51_MXC_INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device2 = { + .name = "imx-uart", + .id = 2, + .resource = uart2, + .num_resources = ARRAY_SIZE(uart2), +}; + +static struct resource mxc_fec_resources[] = { + { + .start = MX51_MXC_FEC_BASE_ADDR, + .end = MX51_MXC_FEC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_FEC, + .end = MX51_MXC_INT_FEC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_fec_device = { + .name = "fec", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_fec_resources), + .resource = mxc_fec_resources, +}; + +static struct resource mxc_i2c0_resources[] = { + { + .start = MX51_I2C1_BASE_ADDR, + .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_I2C1, + .end = MX51_MXC_INT_I2C1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_i2c_device0 = { + .name = "imx-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_i2c0_resources), + .resource = mxc_i2c0_resources, +}; + +static struct resource mxc_i2c1_resources[] = { + { + .start = MX51_I2C2_BASE_ADDR, + .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_I2C2, + .end = MX51_MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_i2c_device1 = { + .name = "imx-i2c", + .id = 1, + .num_resources = ARRAY_SIZE(mxc_i2c1_resources), + .resource = mxc_i2c1_resources, +}; + static struct resource mxc_hsi2c_resources[] = { { .start = MX51_HSI2C_DMA_BASE_ADDR, diff --git a/trunk/arch/arm/mach-mx5/devices.h b/trunk/arch/arm/mach-mx5/devices.h index af1d07c0bbc1..e509cfaad1d4 100644 --- a/trunk/arch/arm/mach-mx5/devices.h +++ b/trunk/arch/arm/mach-mx5/devices.h @@ -1,6 +1,12 @@ +extern struct platform_device mxc_uart_device0; +extern struct platform_device mxc_uart_device1; +extern struct platform_device mxc_uart_device2; +extern struct platform_device mxc_fec_device; extern struct platform_device mxc_usbdr_host_device; extern struct platform_device mxc_usbh1_device; extern struct platform_device mxc_usbdr_udc_device; extern struct platform_device mxc_wdt; +extern struct platform_device mxc_i2c_device0; +extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_hsi2c_device; extern struct platform_device mxc_keypad_device; diff --git a/trunk/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/trunk/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index d0e417ce2c08..ffa93d1d6ef8 100644 --- a/trunk/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/trunk/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -30,7 +30,6 @@ #include -#include "devices-imx51.h" #include "devices.h" #define MBIMX51_TSC2007_GPIO (2*32 + 30) @@ -115,7 +114,7 @@ static struct pad_desc mbimx51_pads[] = { MX51_PAD_KEY_COL3__KEY_COL3, }; -static const struct imxuart_platform_data uart_pdata __initconst = { +static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -173,8 +172,8 @@ void __init eukrea_mbimx51_baseboard_init(void) mxc_iomux_v3_setup_multiple_pads(mbimx51_pads, ARRAY_SIZE(mbimx51_pads)); - imx51_add_imx_uart(1, NULL); - imx51_add_imx_uart(2, &uart_pdata); + mxc_register_device(&mxc_uart_device1, NULL); + mxc_register_device(&mxc_uart_device2, &uart_pdata); gpio_request(MBIMX51_LED0, "LED0"); gpio_direction_output(MBIMX51_LED0, 1); diff --git a/trunk/arch/arm/mach-netx/include/mach/vmalloc.h b/trunk/arch/arm/mach-netx/include/mach/vmalloc.h index 7cca3574308f..25d5cc676e0f 100644 --- a/trunk/arch/arm/mach-netx/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-netx/include/mach/vmalloc.h @@ -16,4 +16,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/trunk/arch/arm/mach-omap1/include/mach/vmalloc.h b/trunk/arch/arm/mach-omap1/include/mach/vmalloc.h index b001f67d695b..1b2af14df151 100644 --- a/trunk/arch/arm/mach-omap1/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-omap1/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END 0xd8000000 +#define VMALLOC_END (PAGE_OFFSET + 0x18000000) diff --git a/trunk/arch/arm/mach-omap2/include/mach/vmalloc.h b/trunk/arch/arm/mach-omap2/include/mach/vmalloc.h index 4da31e997efe..9ce9b6e8ad23 100644 --- a/trunk/arch/arm/mach-omap2/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-omap2/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END 0xf8000000 +#define VMALLOC_END (PAGE_OFFSET + 0x38000000) diff --git a/trunk/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/trunk/arch/arm/mach-pnx4008/include/mach/vmalloc.h index 31b65ee07b0b..2ad398378aed 100644 --- a/trunk/arch/arm/mach-pnx4008/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-pnx4008/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * The vmalloc() routines leaves a hole of 4kB between each vmalloced * area for the same reason. ;) */ -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/trunk/arch/arm/mach-pxa/Kconfig b/trunk/arch/arm/mach-pxa/Kconfig index 7aefb9074852..3d4926edb675 100644 --- a/trunk/arch/arm/mach-pxa/Kconfig +++ b/trunk/arch/arm/mach-pxa/Kconfig @@ -643,6 +643,7 @@ config CPU_PXA300 config CPU_PXA310 bool select CPU_PXA300 + select PXA310_ULPI if USB_ULPI help PXA310 (codename Monahans-LV) @@ -698,4 +699,7 @@ config PXA_HAVE_BOARD_IRQS config PXA_HAVE_ISA_IRQS bool +config PXA310_ULPI + bool + endif diff --git a/trunk/arch/arm/mach-pxa/Makefile b/trunk/arch/arm/mach-pxa/Makefile index 85c7fb324dbb..a1db59b124f9 100644 --- a/trunk/arch/arm/mach-pxa/Makefile +++ b/trunk/arch/arm/mach-pxa/Makefile @@ -18,7 +18,7 @@ endif # SoC-specific code obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o -obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o +obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o obj-$(CONFIG_CPU_PXA930) += pxa930.o diff --git a/trunk/arch/arm/mach-pxa/devices.c b/trunk/arch/arm/mach-pxa/devices.c index 65447dc736c2..a2fc859251da 100644 --- a/trunk/arch/arm/mach-pxa/devices.c +++ b/trunk/arch/arm/mach-pxa/devices.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -134,6 +135,33 @@ struct platform_device pxa27x_device_udc = { } }; +#ifdef CONFIG_PXA3xx +static struct resource pxa3xx_u2d_resources[] = { + [0] = { + .start = 0x54100000, + .end = 0x54100fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USB2, + .end = IRQ_USB2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa3xx_device_u2d = { + .name = "pxa3xx-u2d", + .id = -1, + .resource = pxa3xx_u2d_resources, + .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources), +}; + +void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info) +{ + pxa_register_device(&pxa3xx_device_u2d, info); +} +#endif /* CONFIG_PXA3xx */ + static struct resource pxafb_resources[] = { [0] = { .start = 0x44000000, diff --git a/trunk/arch/arm/mach-pxa/devices.h b/trunk/arch/arm/mach-pxa/devices.h index 50353ea49ba4..715e8bd02e24 100644 --- a/trunk/arch/arm/mach-pxa/devices.h +++ b/trunk/arch/arm/mach-pxa/devices.h @@ -4,6 +4,7 @@ extern struct platform_device pxa3xx_device_mci2; extern struct platform_device pxa3xx_device_mci3; extern struct platform_device pxa25x_device_udc; extern struct platform_device pxa27x_device_udc; +extern struct platform_device pxa3xx_device_u2d; extern struct platform_device pxa_device_fb; extern struct platform_device pxa_device_ffuart; extern struct platform_device pxa_device_btuart; diff --git a/trunk/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h b/trunk/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h new file mode 100644 index 000000000000..9d82cb65ea56 --- /dev/null +++ b/trunk/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h @@ -0,0 +1,35 @@ +/* + * PXA3xx U2D header + * + * Copyright (C) 2010 CompuLab Ltd. + * + * Igor Grinberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __PXA310_U2D__ +#define __PXA310_U2D__ + +#include + +struct pxa3xx_u2d_platform_data { + +#define ULPI_SER_6PIN (1 << 0) +#define ULPI_SER_3PIN (1 << 1) + unsigned int ulpi_mode; + + int (*init)(struct device *); + void (*exit)(struct device *); +}; + + +/* Start PXA3xx U2D host */ +int pxa3xx_u2d_start_hc(struct usb_bus *host); +/* Stop PXA3xx U2D host */ +void pxa3xx_u2d_stop_hc(struct usb_bus *host); + +extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info); + +#endif /* __PXA310_U2D__ */ diff --git a/trunk/arch/arm/mach-pxa/pxa3xx-ulpi.c b/trunk/arch/arm/mach-pxa/pxa3xx-ulpi.c new file mode 100644 index 000000000000..e57439e01171 --- /dev/null +++ b/trunk/arch/arm/mach-pxa/pxa3xx-ulpi.c @@ -0,0 +1,392 @@ +/* + * linux/arch/arm/mach-pxa/pxa3xx-ulpi.c + * + * code specific to pxa3xx aka Monahans + * + * Copyright (C) 2010 CompuLab Ltd. + * + * 2010-13-07: Igor Grinberg + * initial version: pxa310 USB Host mode support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +struct pxa3xx_u2d_ulpi { + struct clk *clk; + void __iomem *mmio_base; + + struct otg_transceiver *otg; + unsigned int ulpi_mode; +}; + +static struct pxa3xx_u2d_ulpi *u2d; + +static inline u32 u2d_readl(u32 reg) +{ + return __raw_readl(u2d->mmio_base + reg); +} + +static inline void u2d_writel(u32 reg, u32 val) +{ + __raw_writel(val, u2d->mmio_base + reg); +} + +#if defined(CONFIG_PXA310_ULPI) +enum u2d_ulpi_phy_mode { + SYNCH = 0, + CARKIT = (1 << 0), + SER_3PIN = (1 << 1), + SER_6PIN = (1 << 2), + LOWPOWER = (1 << 3), +}; + +static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void) +{ + return (u2d_readl(U2DOTGUSR) >> 28) & 0xF; +} + +static int pxa310_ulpi_poll(void) +{ + int timeout = 50000; + + while (timeout--) { + if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN)) + return 0; + + cpu_relax(); + } + + pr_warning("%s: ULPI access timed out!\n", __func__); + + return -ETIMEDOUT; +} + +static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg) +{ + int err; + + if (pxa310_ulpi_get_phymode() != SYNCH) { + pr_warning("%s: PHY is not in SYNCH mode!\n", __func__); + return -EBUSY; + } + + u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16)); + msleep(5); + + err = pxa310_ulpi_poll(); + if (err) + return err; + + return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA; +} + +static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg) +{ + if (pxa310_ulpi_get_phymode() != SYNCH) { + pr_warning("%s: PHY is not in SYNCH mode!\n", __func__); + return -EBUSY; + } + + u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8)); + msleep(5); + + return pxa310_ulpi_poll(); +} + +struct otg_io_access_ops pxa310_ulpi_access_ops = { + .read = pxa310_ulpi_read, + .write = pxa310_ulpi_write, +}; + +static void pxa310_otg_transceiver_rtsm(void) +{ + u32 u2dotgcr; + + /* put PHY to sync mode */ + u2dotgcr = u2d_readl(U2DOTGCR); + u2dotgcr |= U2DOTGCR_RTSM | U2DOTGCR_UTMID; + u2d_writel(U2DOTGCR, u2dotgcr); + msleep(10); + + /* setup OTG sync mode */ + u2dotgcr = u2d_readl(U2DOTGCR); + u2dotgcr |= U2DOTGCR_ULAF; + u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF); + u2d_writel(U2DOTGCR, u2dotgcr); +} + +static int pxa310_start_otg_host_transcvr(struct usb_bus *host) +{ + int err; + + pxa310_otg_transceiver_rtsm(); + + err = otg_init(u2d->otg); + if (err) { + pr_err("OTG transceiver init failed"); + return err; + } + + err = otg_set_vbus(u2d->otg, 1); + if (err) { + pr_err("OTG transceiver VBUS set failed"); + return err; + } + + err = otg_set_host(u2d->otg, host); + if (err) + pr_err("OTG transceiver Host mode set failed"); + + return err; +} + +static int pxa310_start_otg_hc(struct usb_bus *host) +{ + u32 u2dotgcr; + int err; + + /* disable USB device controller */ + u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE); + u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID); + u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F); + + err = pxa310_start_otg_host_transcvr(host); + if (err) + return err; + + /* set xceiver mode */ + if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL) + u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS); + else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL) + u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS); + + /* start OTG host controller */ + u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF; + u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF)); + + return 0; +} + +static void pxa310_stop_otg_hc(void) +{ + pxa310_otg_transceiver_rtsm(); + + otg_set_host(u2d->otg, NULL); + otg_set_vbus(u2d->otg, 0); + otg_shutdown(u2d->otg); +} + +static void pxa310_u2d_setup_otg_hc(void) +{ + u32 u2dotgcr; + + u2dotgcr = u2d_readl(U2DOTGCR); + u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID; + u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF); + u2d_writel(U2DOTGCR, u2dotgcr); + msleep(5); + u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE); + msleep(5); + u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F); +} + +static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata) +{ + unsigned int ulpi_mode = ULPI_OTG_DRVVBUS; + + if (pdata) { + if (pdata->ulpi_mode & ULPI_SER_6PIN) + ulpi_mode |= ULPI_IC_6PIN_SERIAL; + else if (pdata->ulpi_mode & ULPI_SER_3PIN) + ulpi_mode |= ULPI_IC_3PIN_SERIAL; + } + + u2d->ulpi_mode = ulpi_mode; + + u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode); + if (!u2d->otg) + return -ENOMEM; + + u2d->otg->io_priv = u2d->mmio_base; + + return 0; +} + +static void pxa310_otg_exit(void) +{ + kfree(u2d->otg); +} +#else +static inline void pxa310_u2d_setup_otg_hc(void) {} +static inline int pxa310_start_otg_hc(struct usb_bus *host) +{ + return 0; +} +static inline void pxa310_stop_otg_hc(void) {} +static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata) +{ + return 0; +} +static inline void pxa310_otg_exit(void) {} +#endif /* CONFIG_PXA310_ULPI */ + +int pxa3xx_u2d_start_hc(struct usb_bus *host) +{ + int err = 0; + + clk_enable(u2d->clk); + + if (cpu_is_pxa310()) { + pxa310_u2d_setup_otg_hc(); + err = pxa310_start_otg_hc(host); + } + + return err; +} + +void pxa3xx_u2d_stop_hc(struct usb_bus *host) +{ + if (cpu_is_pxa310()) + pxa310_stop_otg_hc(); + + clk_disable(u2d->clk); +} + +static int pxa3xx_u2d_probe(struct platform_device *pdev) +{ + struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data; + struct resource *r; + int err; + + u2d = kzalloc(sizeof(struct pxa3xx_u2d_ulpi), GFP_KERNEL); + if (!u2d) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + u2d->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(u2d->clk)) { + dev_err(&pdev->dev, "failed to get u2d clock\n"); + err = PTR_ERR(u2d->clk); + goto err_free_mem; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no IO memory resource defined\n"); + err = -ENODEV; + goto err_put_clk; + } + + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (!r) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + err = -EBUSY; + goto err_put_clk; + } + + u2d->mmio_base = ioremap(r->start, resource_size(r)); + if (!u2d->mmio_base) { + dev_err(&pdev->dev, "ioremap() failed\n"); + err = -ENODEV; + goto err_free_res; + } + + if (pdata->init) { + err = pdata->init(&pdev->dev); + if (err) + goto err_free_io; + } + + /* Only PXA310 U2D has OTG functionality */ + if (cpu_is_pxa310()) { + err = pxa310_otg_init(pdata); + if (err) + goto err_free_plat; + } + + platform_set_drvdata(pdev, &u2d); + + return 0; + +err_free_plat: + if (pdata->exit) + pdata->exit(&pdev->dev); +err_free_io: + iounmap(u2d->mmio_base); +err_free_res: + release_mem_region(r->start, resource_size(r)); +err_put_clk: + clk_put(u2d->clk); +err_free_mem: + kfree(u2d); + return err; +} + +static int pxa3xx_u2d_remove(struct platform_device *pdev) +{ + struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data; + struct resource *r; + + if (cpu_is_pxa310()) { + pxa310_stop_otg_hc(); + pxa310_otg_exit(); + } + + if (pdata->exit) + pdata->exit(&pdev->dev); + + platform_set_drvdata(pdev, NULL); + iounmap(u2d->mmio_base); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, resource_size(r)); + + clk_put(u2d->clk); + + kfree(u2d); + + return 0; +} + +static struct platform_driver pxa3xx_u2d_ulpi_driver = { + .driver = { + .name = "pxa3xx-u2d", + .owner = THIS_MODULE, + }, + .probe = pxa3xx_u2d_probe, + .remove = pxa3xx_u2d_remove, +}; + +static int pxa3xx_u2d_ulpi_init(void) +{ + return platform_driver_register(&pxa3xx_u2d_ulpi_driver); +} +module_init(pxa3xx_u2d_ulpi_init); + +static void __exit pxa3xx_u2d_ulpi_exit(void) +{ + platform_driver_unregister(&pxa3xx_u2d_ulpi_driver); +} +module_exit(pxa3xx_u2d_ulpi_exit); + +MODULE_DESCRIPTION("PXA3xx U2D ULPI driver"); +MODULE_AUTHOR("Igor Grinberg"); +MODULE_LICENSE("GPL v2"); diff --git a/trunk/arch/arm/mach-pxa/pxa3xx.c b/trunk/arch/arm/mach-pxa/pxa3xx.c index fa0014847c71..cf2bd26dcbab 100644 --- a/trunk/arch/arm/mach-pxa/pxa3xx.c +++ b/trunk/arch/arm/mach-pxa/pxa3xx.c @@ -265,7 +265,7 @@ static struct clk_lookup pxa3xx_clkregs[] = { INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), - INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"), + INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), diff --git a/trunk/arch/arm/mach-rpc/include/mach/vmalloc.h b/trunk/arch/arm/mach-rpc/include/mach/vmalloc.h index 3bcd86fadb81..9a96fd69e705 100644 --- a/trunk/arch/arm/mach-rpc/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-rpc/include/mach/vmalloc.h @@ -7,4 +7,4 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#define VMALLOC_END 0xdc000000 +#define VMALLOC_END (PAGE_OFFSET + 0x1c000000) diff --git a/trunk/arch/arm/mach-shark/include/mach/vmalloc.h b/trunk/arch/arm/mach-shark/include/mach/vmalloc.h index 8e845b6a7cb5..f6c6837c5451 100644 --- a/trunk/arch/arm/mach-shark/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-shark/include/mach/vmalloc.h @@ -1,4 +1,4 @@ /* * arch/arm/mach-shark/include/mach/vmalloc.h */ -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/trunk/arch/arm/mach-tcc8k/Kconfig b/trunk/arch/arm/mach-tcc8k/Kconfig deleted file mode 100644 index ad86415d1577..000000000000 --- a/trunk/arch/arm/mach-tcc8k/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -if ARCH_TCC8K - -comment "TCC8000 systems:" - -config MACH_TCC8000_SDK - bool "Telechips TCC8000-SDK development kit" - default y - help - Support for the Telechips TCC8000-SDK board. - -endif diff --git a/trunk/arch/arm/mach-tcc8k/Makefile b/trunk/arch/arm/mach-tcc8k/Makefile deleted file mode 100644 index 9bacf31e49ba..000000000000 --- a/trunk/arch/arm/mach-tcc8k/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for TCC8K boards and common files. -# - -# Common support -obj-y += clock.o irq.o time.o io.o devices.o - -# Board specific support -obj-$(CONFIG_MACH_TCC8000_SDK) += board-tcc8000-sdk.o diff --git a/trunk/arch/arm/mach-tcc8k/Makefile.boot b/trunk/arch/arm/mach-tcc8k/Makefile.boot deleted file mode 100644 index f135c9deae10..000000000000 --- a/trunk/arch/arm/mach-tcc8k/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x20008000 -params_phys-y := 0x20000100 -initrd_phys-y := 0x20800000 diff --git a/trunk/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/trunk/arch/arm/mach-tcc8k/board-tcc8000-sdk.c deleted file mode 100644 index 4e42555b2009..000000000000 --- a/trunk/arch/arm/mach-tcc8k/board-tcc8000-sdk.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2009 Hans J. Koch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#include "common.h" - -#define XI_FREQUENCY 12000000 -#define XTI_FREQUENCY 32768 - -#ifdef CONFIG_MTD_NAND_TCC -/* NAND */ -static struct tcc_nand_platform_data tcc8k_sdk_nand_data = { - .width = 1, - .hw_ecc = 0, -}; -#endif - -static void __init tcc8k_init(void) -{ -#ifdef CONFIG_MTD_NAND_TCC - tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data; - platform_device_register(&tcc_nand_device); -#endif -} - -static void __init tcc8k_init_timer(void) -{ - tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY); -} - -static struct sys_timer tcc8k_timer = { - .init = tcc8k_init_timer, -}; - -static void __init tcc8k_map_io(void) -{ - tcc8k_map_common_io(); -} - -MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") - .phys_io = 0x90000000, - .io_pg_offst = ((0xf1000000) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x00000100, - .map_io = tcc8k_map_io, - .init_irq = tcc8k_init_irq, - .init_machine = tcc8k_init, - .timer = &tcc8k_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-tcc8k/clock.c b/trunk/arch/arm/mach-tcc8k/clock.c deleted file mode 100644 index ba32a15127ab..000000000000 --- a/trunk/arch/arm/mach-tcc8k/clock.c +++ /dev/null @@ -1,567 +0,0 @@ -/* - * Lowlevel clock handling for Telechips TCC8xxx SoCs - * - * Copyright (C) 2010 by Hans J. Koch - * - * Licensed under the terms of the GPL v2 - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "common.h" - -#define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS) -#define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS) - -#define ACLKREF (CKC_BASE + ACLKREF_OFFS) -#define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS) -#define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS) -#define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS) -#define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS) -#define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS) -#define ACLKI2C (CKC_BASE + ACLKI2C_OFFS) -#define ACLKADC (CKC_BASE + ACLKADC_OFFS) -#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS) -#define ACLKLCD (CKC_BASE + ACLKLCD_OFFS) -#define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS) -#define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS) -#define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS) -#define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS) -#define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS) -#define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS) -#define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS) -#define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS) -#define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS) -#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS) -#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS) -#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS) -#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS) -#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS) -#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS) -#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS) - -/* Crystal frequencies */ -static unsigned long xi_rate, xti_rate; - -static void __iomem *pll_cfg_addr(int pll) -{ - switch (pll) { - case 0: return (CKC_BASE + PLL0CFG_OFFS); - case 1: return (CKC_BASE + PLL1CFG_OFFS); - case 2: return (CKC_BASE + PLL2CFG_OFFS); - default: - BUG(); - } -} - -static int pll_enable(int pll, int enable) -{ - u32 reg; - void __iomem *addr = pll_cfg_addr(pll); - - reg = __raw_readl(addr); - if (enable) - reg &= ~PLLxCFG_PD; - else - reg |= PLLxCFG_PD; - - __raw_writel(reg, addr); - return 0; -} - -static int xi_enable(int enable) -{ - u32 reg; - - reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS); - if (enable) - reg |= CLKCTRL_XE; - else - reg &= ~CLKCTRL_XE; - - __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS); - return 0; -} - -static int root_clk_enable(enum root_clks src) -{ - switch (src) { - case CLK_SRC_PLL0: return pll_enable(0, 1); - case CLK_SRC_PLL1: return pll_enable(1, 1); - case CLK_SRC_PLL2: return pll_enable(2, 1); - case CLK_SRC_XI: return xi_enable(1); - default: - BUG(); - } - return 0; -} - -static int root_clk_disable(enum root_clks root_src) -{ - switch (root_src) { - case CLK_SRC_PLL0: return pll_enable(0, 0); - case CLK_SRC_PLL1: return pll_enable(1, 0); - case CLK_SRC_PLL2: return pll_enable(2, 0); - case CLK_SRC_XI: return xi_enable(0); - default: - BUG(); - } - return 0; -} - -static int enable_clk(struct clk *clk) -{ - u32 reg; - - if (clk->root_id != CLK_SRC_NOROOT) - return root_clk_enable(clk->root_id); - - if (clk->aclkreg) { - reg = __raw_readl(clk->aclkreg); - reg |= ACLK_EN; - __raw_writel(reg, clk->aclkreg); - } - if (clk->bclkctr) { - reg = __raw_readl(clk->bclkctr); - reg |= 1 << clk->bclk_shift; - __raw_writel(reg, clk->bclkctr); - } - return 0; -} - -static void disable_clk(struct clk *clk) -{ - u32 reg; - - if (clk->root_id != CLK_SRC_NOROOT) { - root_clk_disable(clk->root_id); - return; - } - - if (clk->bclkctr) { - reg = __raw_readl(clk->bclkctr); - reg &= ~(1 << clk->bclk_shift); - __raw_writel(reg, clk->bclkctr); - } - if (clk->aclkreg) { - reg = __raw_readl(clk->aclkreg); - reg &= ~ACLK_EN; - __raw_writel(reg, clk->aclkreg); - } -} - -static unsigned long get_rate_pll(int pll) -{ - u32 reg; - unsigned long s, m, p; - void __iomem *addr = pll_cfg_addr(pll); - - reg = __raw_readl(addr); - s = (reg >> 16) & 0x07; - m = (reg >> 8) & 0xff; - p = reg & 0x3f; - - return (m * xi_rate) / (p * (1 << s)); -} - -static unsigned long get_rate_pll_div(int pll) -{ - u32 reg; - unsigned long div = 0; - void __iomem *addr; - - switch (pll) { - case 0: - addr = CKC_BASE + CLKDIVC0_OFFS; - reg = __raw_readl(addr); - if (reg & CLKDIVC0_P0E) - div = (reg >> 24) & 0x3f; - break; - case 1: - addr = CKC_BASE + CLKDIVC0_OFFS; - reg = __raw_readl(addr); - if (reg & CLKDIVC0_P1E) - div = (reg >> 16) & 0x3f; - break; - case 2: - addr = CKC_BASE + CLKDIVC1_OFFS; - reg = __raw_readl(addr); - if (reg & CLKDIVC1_P2E) - div = __raw_readl(addr) & 0x3f; - break; - } - return get_rate_pll(pll) / (div + 1); -} - -static unsigned long get_rate_xi_div(void) -{ - unsigned long div = 0; - u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS); - - if (reg & CLKDIVC0_XE) - div = (reg >> 8) & 0x3f; - - return xi_rate / (div + 1); -} - -static unsigned long get_rate_xti_div(void) -{ - unsigned long div = 0; - u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS); - - if (reg & CLKDIVC0_XTE) - div = reg & 0x3f; - - return xti_rate / (div + 1); -} - -static unsigned long root_clk_get_rate(enum root_clks src) -{ - switch (src) { - case CLK_SRC_PLL0: return get_rate_pll(0); - case CLK_SRC_PLL1: return get_rate_pll(1); - case CLK_SRC_PLL2: return get_rate_pll(2); - case CLK_SRC_PLL0DIV: return get_rate_pll_div(0); - case CLK_SRC_PLL1DIV: return get_rate_pll_div(1); - case CLK_SRC_PLL2DIV: return get_rate_pll_div(2); - case CLK_SRC_XI: return xi_rate; - case CLK_SRC_XTI: return xti_rate; - case CLK_SRC_XIDIV: return get_rate_xi_div(); - case CLK_SRC_XTIDIV: return get_rate_xti_div(); - default: return 0; - } -} - -static unsigned long aclk_get_rate(struct clk *clk) -{ - u32 reg; - unsigned long div; - unsigned int src; - - reg = __raw_readl(clk->aclkreg); - div = reg & 0x0fff; - src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK; - return root_clk_get_rate(src) / (div + 1); -} - -static unsigned long aclk_best_div(struct clk *clk, unsigned long rate) -{ - unsigned long div, src, freq, r1, r2; - - src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; - src &= CLK_SRC_MASK; - freq = root_clk_get_rate(src); - div = freq / rate + 1; - r1 = freq / div; - r2 = freq / (div + 1); - if (r2 >= rate) - return div + 1; - if ((rate - r2) < (r1 - rate)) - return div + 1; - - return div; -} - -static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned int src; - - src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; - src &= CLK_SRC_MASK; - - return root_clk_get_rate(src) / aclk_best_div(clk, rate); -} - -static int aclk_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg; - - reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK; - reg |= aclk_best_div(clk, rate); - return 0; -} - -static unsigned long get_rate_sys(struct clk *clk) -{ - unsigned int src; - - src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK; - return root_clk_get_rate(src); -} - -static unsigned long get_rate_bus(struct clk *clk) -{ - unsigned int div; - - div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff; - return get_rate_sys(clk) / (div + 1); -} - -static unsigned long get_rate_cpu(struct clk *clk) -{ - unsigned int reg, div, fsys, fbus; - - fbus = get_rate_bus(clk); - reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS); - if (reg & (1 << 29)) - return fbus; - fsys = get_rate_sys(clk); - div = (reg >> 16) & 0x0f; - return fbus + ((fsys - fbus) * (div + 1)) / 16; -} - -static unsigned long get_rate_root(struct clk *clk) -{ - return root_clk_get_rate(clk->root_id); -} - -static int aclk_set_parent(struct clk *clock, struct clk *parent) -{ - u32 reg; - - if (clock->parent == parent) - return 0; - - clock->parent = parent; - - if (!parent) - return 0; - - if (parent->root_id == CLK_SRC_NOROOT) - return 0; - reg = __raw_readl(clock->aclkreg); - reg &= ~ACLK_SEL_MASK; - reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK; - __raw_writel(reg, clock->aclkreg); - - return 0; -} - -#define DEFINE_ROOT_CLOCK(name, ri, p) \ - static struct clk name = { \ - .root_id = ri, \ - .get_rate = get_rate_root, \ - .enable = enable_clk, \ - .disable = disable_clk, \ - .parent = p, \ - }; - -#define DEFINE_SPECIAL_CLOCK(name, gr, p) \ - static struct clk name = { \ - .root_id = CLK_SRC_NOROOT, \ - .get_rate = gr, \ - .parent = p, \ - }; - -#define DEFINE_ACLOCK(name, bc, bs, ar) \ - static struct clk name = { \ - .root_id = CLK_SRC_NOROOT, \ - .bclkctr = bc, \ - .bclk_shift = bs, \ - .aclkreg = ar, \ - .get_rate = aclk_get_rate, \ - .set_rate = aclk_set_rate, \ - .round_rate = aclk_round_rate, \ - .enable = enable_clk, \ - .disable = disable_clk, \ - .set_parent = aclk_set_parent, \ - }; - -#define DEFINE_BCLOCK(name, bc, bs, gr, p) \ - static struct clk name = { \ - .root_id = CLK_SRC_NOROOT, \ - .bclkctr = bc, \ - .bclk_shift = bs, \ - .get_rate = gr, \ - .enable = enable_clk, \ - .disable = disable_clk, \ - .parent = p, \ - }; - -DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL) -DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL) -DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi) -DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti) -DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi) -DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi) -DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi) -DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0) -DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1) -DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2) - -/* The following 3 clocks are special and are initialized explicitly later */ -DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL) -DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys) -DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys) - -DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT) -DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX) -DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ) -DEFINE_ACLOCK(ref, NULL, 0, ACLKREF) -DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0) -DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1) -DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2) -DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3) -DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4) -DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C) -DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC) -DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH) -DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD) -DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0) -DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1) -DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0) -DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1) -DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF) -DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC) -DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0) -DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1) -DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0) -DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1) -DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2) -DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3) -DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH) - -DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL) -DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL) -DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL) -DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL) -DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL) -DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL) -DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL) -DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL) -DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL) -DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL) -DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL) -DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL) -DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL) -DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL) -DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL) -DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL) -DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL) -DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL) -DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL) -DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL) -DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL) -DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL) - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, - -static struct clk_lookup lookups[] = { - _REGISTER_CLOCK(NULL, "bus", bus) - _REGISTER_CLOCK(NULL, "cpu", cpu) - _REGISTER_CLOCK(NULL, "tct", tct) - _REGISTER_CLOCK(NULL, "tcx", tcx) - _REGISTER_CLOCK(NULL, "tcz", tcz) - _REGISTER_CLOCK(NULL, "ref", ref) - _REGISTER_CLOCK(NULL, "dai0", dai0) - _REGISTER_CLOCK(NULL, "pic", pic) - _REGISTER_CLOCK(NULL, "tc", tc) - _REGISTER_CLOCK(NULL, "gpio", gpio) - _REGISTER_CLOCK(NULL, "usbd", usbd) - _REGISTER_CLOCK("tcc-uart.0", NULL, uart0) - _REGISTER_CLOCK("tcc-uart.2", NULL, uart2) - _REGISTER_CLOCK("tcc-i2c", NULL, i2c) - _REGISTER_CLOCK("tcc-uart.3", NULL, uart3) - _REGISTER_CLOCK(NULL, "ecc", ecc) - _REGISTER_CLOCK(NULL, "adc", adc) - _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0) - _REGISTER_CLOCK(NULL, "gdma0", gdma0) - _REGISTER_CLOCK(NULL, "lcd", lcd) - _REGISTER_CLOCK(NULL, "rtc", rtc) - _REGISTER_CLOCK(NULL, "nfc", nfc) - _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0) - _REGISTER_CLOCK(NULL, "g2d", g2d) - _REGISTER_CLOCK(NULL, "gdma1", gdma1) - _REGISTER_CLOCK("tcc-uart.1", NULL, uart1) - _REGISTER_CLOCK("tcc-spi.0", NULL, spi0) - _REGISTER_CLOCK(NULL, "mscl", mscl) - _REGISTER_CLOCK("tcc-spi.1", NULL, spi1) - _REGISTER_CLOCK(NULL, "bdma", bdma) - _REGISTER_CLOCK(NULL, "adma0", adma0) - _REGISTER_CLOCK(NULL, "spdif", spdif) - _REGISTER_CLOCK(NULL, "scfg", scfg) - _REGISTER_CLOCK(NULL, "cid", cid) - _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1) - _REGISTER_CLOCK("tcc-uart.4", NULL, uart4) - _REGISTER_CLOCK(NULL, "dai1", dai1) - _REGISTER_CLOCK(NULL, "adma1", adma1) - _REGISTER_CLOCK(NULL, "c3dec", c3dec) - _REGISTER_CLOCK("tcc-can.0", NULL, can0) - _REGISTER_CLOCK("tcc-can.1", NULL, can1) - _REGISTER_CLOCK(NULL, "gps", gps) - _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0) - _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1) - _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2) - _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3) - _REGISTER_CLOCK(NULL, "gdma2", gdma2) - _REGISTER_CLOCK(NULL, "gdma3", gdma3) - _REGISTER_CLOCK(NULL, "ddrc", ddrc) - _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1) -}; - -static struct clk *root_clk_by_index(enum root_clks src) -{ - switch (src) { - case CLK_SRC_PLL0: return &pll0; - case CLK_SRC_PLL1: return &pll1; - case CLK_SRC_PLL2: return &pll2; - case CLK_SRC_PLL0DIV: return &pll0div; - case CLK_SRC_PLL1DIV: return &pll1div; - case CLK_SRC_PLL2DIV: return &pll2div; - case CLK_SRC_XI: return ξ - case CLK_SRC_XTI: return &xti; - case CLK_SRC_XIDIV: return &xidiv; - case CLK_SRC_XTIDIV: return &xtidiv; - default: return NULL; - } -} - -static void find_aclk_parent(struct clk *clk) -{ - unsigned int src; - struct clk *clock; - - if (!clk->aclkreg) - return; - - src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; - src &= CLK_SRC_MASK; - - clock = root_clk_by_index(src); - if (!clock) - return; - - clk->parent = clock; - clk->set_parent = aclk_set_parent; -} - -void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq) -{ - int i; - - xi_rate = xi_freq; - xti_rate = xti_freq; - - /* fixup parents and add the clock */ - for (i = 0; i < ARRAY_SIZE(lookups); i++) { - find_aclk_parent(lookups[i].clk); - clkdev_add(&lookups[i]); - } - tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32); -} diff --git a/trunk/arch/arm/mach-tcc8k/common.h b/trunk/arch/arm/mach-tcc8k/common.h deleted file mode 100644 index 705690add395..000000000000 --- a/trunk/arch/arm/mach-tcc8k/common.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef MACH_TCC8K_COMMON_H -#define MACH_TCC8K_COMMON_H - -#include - -extern struct platform_device tcc_nand_device; - -struct clk; - -extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq); -extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq); -extern void tcc8k_init_irq(void); -extern void tcc8k_map_common_io(void); - -#endif diff --git a/trunk/arch/arm/mach-tcc8k/devices.c b/trunk/arch/arm/mach-tcc8k/devices.c deleted file mode 100644 index 6722ad7c2836..000000000000 --- a/trunk/arch/arm/mach-tcc8k/devices.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * linux/arch/arm/mach-tcc8k/devices.c - * - * Copyright (C) Telechips, Inc. - * Copyright (C) 2009 Hans J. Koch - * - * Licensed under the terms of GPL v2. - * - */ - -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include "common.h" - -static u64 tcc8k_dmamask = DMA_BIT_MASK(32); - -#ifdef CONFIG_MTD_NAND_TCC -/* NAND controller */ -static struct resource tcc_nand_resources[] = { - { - .start = (resource_size_t)NFC_BASE, - .end = (resource_size_t)NFC_BASE + 0x7f, - .flags = IORESOURCE_MEM, - }, { - .start = INT_NFC, - .end = INT_NFC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device tcc_nand_device = { - .name = "tcc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(tcc_nand_resources), - .resource = tcc_nand_resources, -}; -#endif - -#ifdef CONFIG_MMC_TCC8K -/* MMC controller */ -static struct resource tcc8k_mmc0_resource[] = { - { - .start = INT_SD0, - .end = INT_SD0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource tcc8k_mmc1_resource[] = { - { - .start = INT_SD1, - .end = INT_SD1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device tcc8k_mmc0_device = { - .name = "tcc-mmc", - .id = 0, - .num_resources = ARRAY_SIZE(tcc8k_mmc0_resource), - .resource = tcc8k_mmc0_resource, - .dev = { - .dma_mask = &tcc8k_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; - -struct platform_device tcc8k_mmc1_device = { - .name = "tcc-mmc", - .id = 1, - .num_resources = ARRAY_SIZE(tcc8k_mmc1_resource), - .resource = tcc8k_mmc1_resource, - .dev = { - .dma_mask = &tcc8k_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; - -static inline void tcc8k_init_mmc(void) -{ - u32 reg = __raw_readl(GPIOPS_BASE + GPIOPS_FS1_OFFS); - - reg |= GPIOPS_FS1_SDH0_BITS | GPIOPS_FS1_SDH1_BITS; - __raw_writel(reg, GPIOPS_BASE + GPIOPS_FS1_OFFS); - - platform_device_register(&tcc8k_mmc0_device); - platform_device_register(&tcc8k_mmc1_device); -} -#else -static inline void tcc8k_init_mmc(void) { } -#endif - -#ifdef CONFIG_USB_OHCI_HCD -static int tcc8k_ohci_init(struct device *dev) -{ - u32 reg; - - /* Use GPIO PK19 as VBUS control output */ - reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS0_OFFS); - reg &= ~(1 << 19); - __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS0_OFFS); - reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS1_OFFS); - reg &= ~(1 << 19); - __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS1_OFFS); - - reg = __raw_readl(GPIOPK_BASE + GPIOPK_DOE_OFFS); - reg |= (1 << 19); - __raw_writel(reg, GPIOPK_BASE + GPIOPK_DOE_OFFS); - /* Turn on VBUS */ - reg = __raw_readl(GPIOPK_BASE + GPIOPK_DAT_OFFS); - reg |= (1 << 19); - __raw_writel(reg, GPIOPK_BASE + GPIOPK_DAT_OFFS); - - return 0; -} - -static struct resource tcc8k_ohci0_resources[] = { - [0] = { - .start = (resource_size_t)USBH0_BASE, - .end = (resource_size_t)USBH0_BASE + 0x5c, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_USBH0, - .end = INT_USBH0, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource tcc8k_ohci1_resources[] = { - [0] = { - .start = (resource_size_t)USBH1_BASE, - .end = (resource_size_t)USBH1_BASE + 0x5c, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_USBH1, - .end = INT_USBH1, - .flags = IORESOURCE_IRQ, - } -}; - -static struct tccohci_platform_data tcc8k_ohci0_platform_data = { - .controller = 0, - .port_mode = PMM_PERPORT_MODE, - .init = tcc8k_ohci_init, -}; - -static struct tccohci_platform_data tcc8k_ohci1_platform_data = { - .controller = 1, - .port_mode = PMM_PERPORT_MODE, - .init = tcc8k_ohci_init, -}; - -static struct platform_device ohci0_device = { - .name = "tcc-ohci", - .id = 0, - .dev = { - .dma_mask = &tcc8k_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &tcc8k_ohci0_platform_data, - }, - .num_resources = ARRAY_SIZE(tcc8k_ohci0_resources), - .resource = tcc8k_ohci0_resources, -}; - -static struct platform_device ohci1_device = { - .name = "tcc-ohci", - .id = 1, - .dev = { - .dma_mask = &tcc8k_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &tcc8k_ohci1_platform_data, - }, - .num_resources = ARRAY_SIZE(tcc8k_ohci1_resources), - .resource = tcc8k_ohci1_resources, -}; - -static void __init tcc8k_init_usbhost(void) -{ - platform_device_register(&ohci0_device); - platform_device_register(&ohci1_device); -} -#else -static void __init tcc8k_init_usbhost(void) { } -#endif - -/* USB device controller*/ -#ifdef CONFIG_USB_GADGET_TCC8K -static struct resource udc_resources[] = { - [0] = { - .start = INT_USBD, - .end = INT_USBD, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = INT_UDMA, - .end = INT_UDMA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tcc8k_udc_device = { - .name = "tcc-udc", - .id = 0, - .resource = udc_resources, - .num_resources = ARRAY_SIZE(udc_resources), - .dev = { - .dma_mask = &tcc8k_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static void __init tcc8k_init_usb_gadget(void) -{ - platform_device_register(&tcc8k_udc_device); -} -#else -static void __init tcc8k_init_usb_gadget(void) { } -#endif /* CONFIG_USB_GADGET_TCC83X */ - -static int __init tcc8k_init_devices(void) -{ - tcc8k_init_mmc(); - tcc8k_init_usbhost(); - tcc8k_init_usb_gadget(); - return 0; -} - -arch_initcall(tcc8k_init_devices); diff --git a/trunk/arch/arm/mach-tcc8k/io.c b/trunk/arch/arm/mach-tcc8k/io.c deleted file mode 100644 index 9b39d7fa658f..000000000000 --- a/trunk/arch/arm/mach-tcc8k/io.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * linux/arch/arm/mach-tcc8k/io.c - * - * (C) 2009 Hans J. Koch - * - * derived from TCC83xx io.c - * Copyright (C) Telechips, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include - -#include - -/* - * The machine specific code may provide the extra mapping besides the - * default mapping provided here. - */ -static struct map_desc tcc8k_io_desc[] __initdata = { - { - .virtual = (unsigned long)CS1_BASE_VIRT, - .pfn = __phys_to_pfn(CS1_BASE), - .length = CS1_SIZE, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)AHB_PERI_BASE_VIRT, - .pfn = __phys_to_pfn(AHB_PERI_BASE), - .length = AHB_PERI_SIZE, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)APB0_PERI_BASE_VIRT, - .pfn = __phys_to_pfn(APB0_PERI_BASE), - .length = APB0_PERI_SIZE, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)APB1_PERI_BASE_VIRT, - .pfn = __phys_to_pfn(APB1_PERI_BASE), - .length = APB1_PERI_SIZE, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)EXT_MEM_CTRL_BASE_VIRT, - .pfn = __phys_to_pfn(EXT_MEM_CTRL_BASE), - .length = EXT_MEM_CTRL_SIZE, - .type = MT_DEVICE, - }, -}; - -/* - * Maps common IO regions for tcc8k. - * - */ -void __init tcc8k_map_common_io(void) -{ - iotable_init(tcc8k_io_desc, ARRAY_SIZE(tcc8k_io_desc)); -} diff --git a/trunk/arch/arm/mach-tcc8k/irq.c b/trunk/arch/arm/mach-tcc8k/irq.c deleted file mode 100644 index 34575c4963f0..000000000000 --- a/trunk/arch/arm/mach-tcc8k/irq.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (C) Telechips, Inc. - * Copyright (C) 2009-2010 Hans J. Koch - * - * Licensed under the terms of the GNU GPL version 2. - */ - -#include -#include -#include - -#include -#include - -#include -#include - -#include "common.h" - -/* Disable IRQ */ -static void tcc8000_mask_ack_irq0(unsigned int irq) -{ - PIC0_IEN &= ~(1 << irq); - PIC0_CREQ |= (1 << irq); -} - -static void tcc8000_mask_ack_irq1(unsigned int irq) -{ - PIC1_IEN &= ~(1 << (irq - 32)); - PIC1_CREQ |= (1 << (irq - 32)); -} - -static void tcc8000_mask_irq0(unsigned int irq) -{ - PIC0_IEN &= ~(1 << irq); -} - -static void tcc8000_mask_irq1(unsigned int irq) -{ - PIC1_IEN &= ~(1 << (irq - 32)); -} - -static void tcc8000_ack_irq0(unsigned int irq) -{ - PIC0_CREQ |= (1 << irq); -} - -static void tcc8000_ack_irq1(unsigned int irq) -{ - PIC1_CREQ |= (1 << (irq - 32)); -} - -/* Enable IRQ */ -static void tcc8000_unmask_irq0(unsigned int irq) -{ - PIC0_IEN |= (1 << irq); - PIC0_INTOEN |= (1 << irq); -} - -static void tcc8000_unmask_irq1(unsigned int irq) -{ - PIC1_IEN |= (1 << (irq - 32)); - PIC1_INTOEN |= (1 << (irq - 32)); -} - -static struct irq_chip tcc8000_irq_chip0 = { - .name = "tcc_irq0", - .mask = tcc8000_mask_irq0, - .ack = tcc8000_ack_irq0, - .mask_ack = tcc8000_mask_ack_irq0, - .unmask = tcc8000_unmask_irq0, -}; - -static struct irq_chip tcc8000_irq_chip1 = { - .name = "tcc_irq1", - .mask = tcc8000_mask_irq1, - .ack = tcc8000_ack_irq1, - .mask_ack = tcc8000_mask_ack_irq1, - .unmask = tcc8000_unmask_irq1, -}; - -void __init tcc8k_init_irq(void) -{ - int irqno; - - /* Mask and clear all interrupts */ - PIC0_IEN = 0x00000000; - PIC0_CREQ = 0xffffffff; - PIC1_IEN = 0x00000000; - PIC1_CREQ = 0xffffffff; - - PIC0_MEN0 = 0x00000003; - PIC1_MEN1 = 0x00000003; - PIC1_MEN = 0x00000003; - - /* let all IRQs be level triggered */ - PIC0_TMODE = 0xffffffff; - PIC1_TMODE = 0xffffffff; - /* all IRQs are IRQs (not FIQs) */ - PIC0_IRQSEL = 0xffffffff; - PIC1_IRQSEL = 0xffffffff; - - for (irqno = 0; irqno < NR_IRQS; irqno++) { - if (irqno < 32) - set_irq_chip(irqno, &tcc8000_irq_chip0); - else - set_irq_chip(irqno, &tcc8000_irq_chip1); - set_irq_handler(irqno, handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } -} diff --git a/trunk/arch/arm/mach-tcc8k/time.c b/trunk/arch/arm/mach-tcc8k/time.c deleted file mode 100644 index 78d06008841d..000000000000 --- a/trunk/arch/arm/mach-tcc8k/time.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * TCC8000 system timer setup - * - * (C) 2009 Hans J. Koch - * - * Licensed under the terms of the GPL version 2. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include "common.h" - -static void __iomem *timer_base; - -static cycle_t tcc_get_cycles(struct clocksource *cs) -{ - return __raw_readl(timer_base + TC32MCNT_OFFS); -} - -static struct clocksource clocksource_tcc = { - .name = "tcc_tc32", - .rating = 200, - .read = tcc_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .shift = 28, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int tcc_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS); - - __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS); - return 0; -} - -static void tcc_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - unsigned long tc32irq; - - switch (mode) { - case CLOCK_EVT_MODE_ONESHOT: - tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS); - tc32irq |= TC32IRQ_IRQEN0; - __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS); - tc32irq &= ~TC32IRQ_IRQEN0; - __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS); - break; - case CLOCK_EVT_MODE_PERIODIC: - case CLOCK_EVT_MODE_RESUME: - break; - } -} - -static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - - /* Acknowledge TC32 interrupt by reading TC32IRQ */ - __raw_readl(timer_base + TC32IRQ_OFFS); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct clock_event_device clockevent_tcc = { - .name = "tcc_timer1", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .set_mode = tcc_set_mode, - .set_next_event = tcc_set_next_event, - .rating = 200, -}; - -static struct irqaction tcc8k_timer_irq = { - .name = "TC32_timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = tcc8k_timer_interrupt, - .dev_id = &clockevent_tcc, -}; - -static int __init tcc_clockevent_init(struct clk *clock) -{ - unsigned int c = clk_get_rate(clock); - - clocksource_tcc.mult = clocksource_hz2mult(c, - clocksource_tcc.shift); - clocksource_register(&clocksource_tcc); - - clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC, - clockevent_tcc.shift); - clockevent_tcc.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_tcc); - clockevent_tcc.min_delta_ns = - clockevent_delta2ns(0xff, &clockevent_tcc); - - clockevent_tcc.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_tcc); - - return 0; -} - -void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq) -{ - u32 reg; - - timer_base = base; - tcc8k_timer_irq.irq = irq; - - /* Enable clocks */ - clk_enable(clock); - - /* Initialize 32-bit timer */ - reg = __raw_readl(timer_base + TC32EN_OFFS); - reg &= ~TC32EN_ENABLE; /* Disable timer */ - __raw_writel(reg, timer_base + TC32EN_OFFS); - /* Free running timer, counting from 0 to 0xffffffff */ - __raw_writel(0, timer_base + TC32EN_OFFS); - __raw_writel(0, timer_base + TC32LDV_OFFS); - reg = __raw_readl(timer_base + TC32IRQ_OFFS); - reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */ - __raw_writel(reg, timer_base + TC32IRQ_OFFS); - - __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS); - - tcc_clockevent_init(clock); - setup_irq(irq, &tcc8k_timer_irq); -} diff --git a/trunk/arch/arm/mach-versatile/include/mach/vmalloc.h b/trunk/arch/arm/mach-versatile/include/mach/vmalloc.h index ebd8a2543d3b..427e3612db5d 100644 --- a/trunk/arch/arm/mach-versatile/include/mach/vmalloc.h +++ b/trunk/arch/arm/mach-versatile/include/mach/vmalloc.h @@ -18,4 +18,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END 0xd8000000 +#define VMALLOC_END (PAGE_OFFSET + 0x18000000) diff --git a/trunk/arch/arm/mm/mmap.c b/trunk/arch/arm/mm/mmap.c index b0a98305055c..4f5b39687df5 100644 --- a/trunk/arch/arm/mm/mmap.c +++ b/trunk/arch/arm/mm/mmap.c @@ -144,25 +144,3 @@ int valid_mmap_phys_addr_range(unsigned long pfn, size_t size) { return !(pfn + (size >> PAGE_SHIFT) > 0x00100000); } - -#ifdef CONFIG_STRICT_DEVMEM - -#include - -/* - * devmem_is_allowed() checks to see if /dev/mem access to a certain - * address is valid. The argument is a physical page number. - * We mimic x86 here by disallowing access to system RAM as well as - * device-exclusive MMIO regions. This effectively disable read()/write() - * on /dev/mem. - */ -int devmem_is_allowed(unsigned long pfn) -{ - if (iomem_is_exclusive(pfn << PAGE_SHIFT)) - return 0; - if (!page_is_ram(pfn)) - return 1; - return 0; -} - -#endif diff --git a/trunk/arch/arm/plat-mxc/Kconfig b/trunk/arch/arm/plat-mxc/Kconfig index 95f8d614d4fc..6785db4179b8 100644 --- a/trunk/arch/arm/plat-mxc/Kconfig +++ b/trunk/arch/arm/plat-mxc/Kconfig @@ -92,18 +92,6 @@ config MXC_DEBUG_BOARD data/address de-multiplexing and decode, signal level shift, interrupt control and various board functions. -config HAVE_EPIT - bool - -config MXC_USE_EPIT - bool "Use EPIT instead of GPT" - depends on HAVE_EPIT - help - Use EPIT as the system timer on systems that have it. Normally you - don't have a reason to do so as the EPIT has the same features and - uses the same clocks as the GPT. Anyway, on some systems the GPT - may be in use for other purposes. - config MXC_ULPI bool diff --git a/trunk/arch/arm/plat-mxc/Makefile b/trunk/arch/arm/plat-mxc/Makefile index bb3443f9751a..78d405ed8616 100644 --- a/trunk/arch/arm/plat-mxc/Makefile +++ b/trunk/arch/arm/plat-mxc/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o -obj-$(CONFIG_MXC_USE_EPIT) += epit.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o diff --git a/trunk/arch/arm/plat-mxc/audmux-v2.c b/trunk/arch/arm/plat-mxc/audmux-v2.c index 62920490c0d6..f9e7cdbd0005 100644 --- a/trunk/arch/arm/plat-mxc/audmux-v2.c +++ b/trunk/arch/arm/plat-mxc/audmux-v2.c @@ -186,13 +186,7 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port); static int mxc_audmux_v2_init(void) { int ret; -#if defined(CONFIG_ARCH_MX5) - if (cpu_is_mx51()) { - audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR); - ret = 0; - return ret; - } -#endif + #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); diff --git a/trunk/arch/arm/plat-mxc/devices/Kconfig b/trunk/arch/arm/plat-mxc/devices/Kconfig index 404799487f17..9ab784b776f9 100644 --- a/trunk/arch/arm/plat-mxc/devices/Kconfig +++ b/trunk/arch/arm/plat-mxc/devices/Kconfig @@ -1,10 +1,3 @@ -config IMX_HAVE_PLATFORM_ESDHC - bool - -config IMX_HAVE_PLATFORM_FEC - bool - default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 - config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN bool @@ -12,9 +5,6 @@ config IMX_HAVE_PLATFORM_FLEXCAN config IMX_HAVE_PLATFORM_IMX_I2C bool -config IMX_HAVE_PLATFORM_IMX_SSI - bool - config IMX_HAVE_PLATFORM_IMX_UART bool diff --git a/trunk/arch/arm/plat-mxc/devices/Makefile b/trunk/arch/arm/plat-mxc/devices/Makefile index 0a3c1f089413..347da5161f7e 100644 --- a/trunk/arch/arm/plat-mxc/devices/Makefile +++ b/trunk/arch/arm/plat-mxc/devices/Makefile @@ -1,9 +1,8 @@ -obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o -obj-y += platform-imx-dma.o +ifdef CONFIG_CAN_FLEXCAN +# the ifdef can be removed once the flexcan driver has been merged +obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +endif obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/trunk/arch/arm/plat-mxc/devices/platform-esdhc.c b/trunk/arch/arm/plat-mxc/devices/platform-esdhc.c deleted file mode 100644 index 68db2a22d2cd..000000000000 --- a/trunk/arch/arm/plat-mxc/devices/platform-esdhc.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix, Wolfram Sang - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include -#include - -struct platform_device *__init imx_add_esdhc(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, - const struct esdhc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("sdhci-esdhc-imx", id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/trunk/arch/arm/plat-mxc/devices/platform-fec.c b/trunk/arch/arm/plat-mxc/devices/platform-fec.c deleted file mode 100644 index 11d087f4e219..000000000000 --- a/trunk/arch/arm/plat-mxc/devices/platform-fec.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include - -#define imx_fec_data_entry_single(soc) \ - { \ - .iobase = soc ## _FEC_BASE_ADDR, \ - .irq = soc ## _INT_FEC, \ - } - -#ifdef CONFIG_ARCH_MX25 -const struct imx_fec_data imx25_fec_data __initconst = - imx_fec_data_entry_single(MX25); -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_fec_data imx27_fec_data __initconst = - imx_fec_data_entry_single(MX27); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_ARCH_MX35 -const struct imx_fec_data imx35_fec_data __initconst = - imx_fec_data_entry_single(MX35); -#endif - -#ifdef CONFIG_ARCH_MX51 -const struct imx_fec_data imx51_fec_data __initconst = - imx_fec_data_entry_single(MX51); -#endif - -struct platform_device *__init imx_add_fec( - const struct imx_fec_data *data, - const struct fec_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_4K, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("fec", 0 /* -1? */, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); -} diff --git a/trunk/arch/arm/plat-mxc/devices/platform-imx-dma.c b/trunk/arch/arm/plat-mxc/devices/platform-imx-dma.c deleted file mode 100644 index 02d989018059..000000000000 --- a/trunk/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include -#include - -#include -#include -#ifdef SDMA_IS_MERGED -#include -#else -struct sdma_platform_data { - int sdma_version; - char *cpu_name; - int to_version; -}; -#endif - -struct imx_imx_sdma_data { - resource_size_t iobase; - resource_size_t irq; - struct sdma_platform_data pdata; -}; - -#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\ - { \ - .iobase = soc ## _SDMA ## _BASE_ADDR, \ - .irq = soc ## _INT_SDMA, \ - .pdata = { \ - .sdma_version = _sdma_version, \ - .cpu_name = _cpu_name, \ - .to_version = _to_version, \ - }, \ - } - -#ifdef CONFIG_ARCH_MX25 -const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = - imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_ARCH_MX31 -struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = - imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); -#endif /* ifdef CONFIG_ARCH_MX31 */ - -#ifdef CONFIG_ARCH_MX35 -struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = - imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); -#endif /* ifdef CONFIG_ARCH_MX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = - imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); -#endif /* ifdef CONFIG_ARCH_MX51 */ - -static struct platform_device __init __maybe_unused *imx_add_imx_sdma( - const struct imx_imx_sdma_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("imx-sdma", -1, - res, ARRAY_SIZE(res), - &data->pdata, sizeof(data->pdata)); -} - -static struct platform_device __init __maybe_unused *imx_add_imx_dma(void) -{ - return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); -} - -static int __init imxXX_add_imx_dma(void) -{ - struct platform_device *ret; - -#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27) - if (cpu_is_mx21() || cpu_is_mx27()) - ret = imx_add_imx_dma(); - else -#endif - -#if defined(CONFIG_ARCH_MX25) - if (cpu_is_mx25()) - ret = imx_add_imx_sdma(&imx25_imx_sdma_data); - else -#endif - -#if defined(CONFIG_ARCH_MX31) - if (cpu_is_mx31()) { - imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; - ret = imx_add_imx_sdma(&imx31_imx_sdma_data); - } else -#endif - -#if defined(CONFIG_ARCH_MX35) - if (cpu_is_mx35()) { - imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; - ret = imx_add_imx_sdma(&imx35_imx_sdma_data); - } else -#endif - -#if defined(CONFIG_ARCH_MX51) - if (cpu_is_mx51()) - ret = imx_add_imx_sdma(&imx51_imx_sdma_data); - else -#endif - ret = ERR_PTR(-ENODEV); - - if (IS_ERR(ret)) - return PTR_ERR(ret); - - return 0; -} -arch_initcall(imxXX_add_imx_dma); diff --git a/trunk/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/trunk/arch/arm/plat-mxc/devices/platform-imx-i2c.c index ca988d40a3d7..d0af9f7d8aed 100644 --- a/trunk/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/trunk/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -6,94 +6,24 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ -#include #include -#define imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_I2C ## _hwid, \ - } - -#define imx_imx_i2c_data_entry(soc, _id, _hwid, _size) \ - [_id] = imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX1 -const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst = - imx_imx_i2c_data_entry_single(MX1, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX1 */ - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = - imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_ARCH_MX25 -const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { -#define imx25_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) - imx25_imx_i2c_data_entry(0, 1), - imx25_imx_i2c_data_entry(1, 2), - imx25_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { -#define imx27_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX27, _id, _hwid, SZ_4K) - imx27_imx_i2c_data_entry(0, 1), - imx27_imx_i2c_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_ARCH_MX31 -const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { -#define imx31_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) - imx31_imx_i2c_data_entry(0, 1), - imx31_imx_i2c_data_entry(1, 2), - imx31_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX31 */ - -#ifdef CONFIG_ARCH_MX35 -const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { -#define imx35_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) - imx35_imx_i2c_data_entry(0, 1), - imx35_imx_i2c_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { -#define imx51_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) - imx51_imx_i2c_data_entry(0, 1), - imx51_imx_i2c_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX51 */ - -struct platform_device *__init imx_add_imx_i2c( - const struct imx_imx_i2c_data *data, +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, const struct imxi2c_platform_data *pdata) { struct resource res[] = { { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, + .start = iobase, + .end = iobase + iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = data->irq, - .end = data->irq, + .start = irq, + .end = irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("imx-i2c", data->id, - res, ARRAY_SIZE(res), + return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/trunk/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/trunk/arch/arm/plat-mxc/devices/platform-imx-ssi.c deleted file mode 100644 index 38a7a0b8f2f1..000000000000 --- a/trunk/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include -#include - -#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_SSI ## _hwid, \ - .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0, \ - .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0, \ - .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1, \ - .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { -#define imx21_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K) - imx21_imx_ssi_data_entry(0, 1), - imx21_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_ARCH_MX25 -const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { -#define imx25_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) - imx25_imx_ssi_data_entry(0, 1), - imx25_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { -#define imx27_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K) - imx27_imx_ssi_data_entry(0, 1), - imx27_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_ARCH_MX31 -const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { -#define imx31_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) - imx31_imx_ssi_data_entry(0, 1), - imx31_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX31 */ - -#ifdef CONFIG_ARCH_MX35 -const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { -#define imx35_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) - imx35_imx_ssi_data_entry(0, 1), - imx35_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { -#define imx51_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) - imx51_imx_ssi_data_entry(0, 1), - imx51_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX51 */ - -struct platform_device *__init imx_add_imx_ssi( - const struct imx_imx_ssi_data *data, - const struct imx_ssi_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, -#define DMARES(_name) { \ - .name = #_name, \ - .start = data->dma ## _name, \ - .end = data->dma ## _name, \ - .flags = IORESOURCE_DMA, \ -} - DMARES(tx0), - DMARES(rx0), - DMARES(tx1), - DMARES(rx1), - }; - - return imx_add_platform_device("imx-ssi", data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); -} diff --git a/trunk/arch/arm/plat-mxc/devices/platform-imx-uart.c b/trunk/arch/arm/plat-mxc/devices/platform-imx-uart.c index 2039640adf27..fa3dff1433e8 100644 --- a/trunk/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/trunk/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -6,148 +6,55 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ -#include #include -#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irqrx = soc ## _INT_UART ## _hwid ## RX, \ - .irqtx = soc ## _INT_UART ## _hwid ## TX, \ - .irqrts = soc ## _INT_UART ## _hwid ## RTS, \ - } - -#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_UART ## _hwid, \ - } - -#ifdef CONFIG_SOC_IMX1 -const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = { -#define imx1_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0) - imx1_imx_uart_data_entry(0, 1), - imx1_imx_uart_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX1 */ - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { -#define imx21_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K) - imx21_imx_uart_data_entry(0, 1), - imx21_imx_uart_data_entry(1, 2), - imx21_imx_uart_data_entry(2, 3), - imx21_imx_uart_data_entry(3, 4), -}; -#endif - -#ifdef CONFIG_ARCH_MX25 -const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { -#define imx25_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) - imx25_imx_uart_data_entry(0, 1), - imx25_imx_uart_data_entry(1, 2), - imx25_imx_uart_data_entry(2, 3), - imx25_imx_uart_data_entry(3, 4), - imx25_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { -#define imx27_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K) - imx27_imx_uart_data_entry(0, 1), - imx27_imx_uart_data_entry(1, 2), - imx27_imx_uart_data_entry(2, 3), - imx27_imx_uart_data_entry(3, 4), - imx27_imx_uart_data_entry(4, 5), - imx27_imx_uart_data_entry(5, 6), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_ARCH_MX31 -const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { -#define imx31_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) - imx31_imx_uart_data_entry(0, 1), - imx31_imx_uart_data_entry(1, 2), - imx31_imx_uart_data_entry(2, 3), - imx31_imx_uart_data_entry(3, 4), - imx31_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_ARCH_MX31 */ - -#ifdef CONFIG_ARCH_MX35 -const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { -#define imx35_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) - imx35_imx_uart_data_entry(0, 1), - imx35_imx_uart_data_entry(1, 2), - imx35_imx_uart_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { -#define imx51_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) - imx51_imx_uart_data_entry(0, 1), - imx51_imx_uart_data_entry(1, 2), - imx51_imx_uart_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX51 */ - -struct platform_device *__init imx_add_imx_uart_3irq( - const struct imx_imx_uart_3irq_data *data, +struct platform_device *__init imx_add_imx_uart_3irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irqrx, resource_size_t irqtx, + resource_size_t irqrts, const struct imxuart_platform_data *pdata) { struct resource res[] = { { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, + .start = iobase, + .end = iobase + iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = data->irqrx, - .end = data->irqrx, + .start = irqrx, + .end = irqrx, .flags = IORESOURCE_IRQ, }, { - .start = data->irqtx, - .end = data->irqtx, + .start = irqtx, + .end = irqtx, .flags = IORESOURCE_IRQ, }, { - .start = data->irqrts, - .end = data->irqrx, + .start = irqrts, + .end = irqrx, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("imx-uart", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); + return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); } -struct platform_device *__init imx_add_imx_uart_1irq( - const struct imx_imx_uart_1irq_data *data, +struct platform_device *__init imx_add_imx_uart_1irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, const struct imxuart_platform_data *pdata) { struct resource res[] = { { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, + .start = iobase, + .end = iobase + iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = data->irq, - .end = data->irq, + .start = irq, + .end = irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res), + return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/trunk/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/trunk/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 3fdcc32e3d67..1c286418d123 100644 --- a/trunk/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/trunk/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -7,77 +7,38 @@ * Free Software Foundation. */ #include -#include #include -#define imx_mxc_nand_data_entry_single(soc, _size) \ - { \ - .iobase = soc ## _NFC_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_NFC \ - } - -#define imx_mxc_nandv3_data_entry_single(soc, _size) \ - { \ - .id = -1, \ - .iobase = soc ## _NFC_BASE_ADDR, \ - .iosize = _size, \ - .axibase = soc ## _NFC_AXI_BASE_ADDR, \ - .irq = soc ## _INT_NFC \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX21, SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_ARCH_MX25 -const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX25, SZ_8K); -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX27, SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_ARCH_MX31 -const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX31, SZ_4K); -#endif - -#ifdef CONFIG_ARCH_MX35 -const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX35, SZ_8K); -#endif - -#ifdef CONFIG_ARCH_MX51 -const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = - imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); -#endif - -struct platform_device *__init imx_add_mxc_nand( - const struct imx_mxc_nand_data *data, - const struct mxc_nand_platform_data *pdata) +static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata, + resource_size_t iosize) { - /* AXI has to come first, that's how the mxc_nand driver expect it */ + static int id = 0; + struct resource res[] = { { - .start = data->axibase, - .end = data->axibase + SZ_16K - 1, + .start = iobase, + .end = iobase + iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, + .start = irq, + .end = irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("mxc_nand", data->id, - res + !data->axibase, - ARRAY_SIZE(res) - !data->axibase, + + return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } + +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K); +} + +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K); +} diff --git a/trunk/arch/arm/plat-mxc/devices/platform-spi_imx.c b/trunk/arch/arm/plat-mxc/devices/platform-spi_imx.c index e48340ec331e..2831a6d3eb4b 100644 --- a/trunk/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/trunk/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -6,96 +6,25 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ -#include +#include #include -#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_ ## type ## hwid, \ - } - -#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ - [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { -#define imx21_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K) - imx21_cspi_data_entry(0, 1), - imx21_cspi_data_entry(1, 2), -#endif - -#ifdef CONFIG_ARCH_MX25 -const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { -#define imx25_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) - imx25_cspi_data_entry(0, 1), - imx25_cspi_data_entry(1, 2), - imx25_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { -#define imx27_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K) - imx27_cspi_data_entry(0, 1), - imx27_cspi_data_entry(1, 2), - imx27_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_ARCH_MX31 -const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { -#define imx31_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) - imx31_cspi_data_entry(0, 1), - imx31_cspi_data_entry(1, 2), - imx31_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX31 */ - -#ifdef CONFIG_ARCH_MX35 -const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { -#define imx35_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) - imx35_cspi_data_entry(0, 1), - imx35_cspi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_spi_imx_data imx51_cspi_data __initconst = - imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); - -const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { -#define imx51_ecspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K) - imx51_ecspi_data_entry(0, 1), - imx51_ecspi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX51 */ - -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, const struct spi_imx_master *pdata) { struct resource res[] = { { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, + .start = iobase, + .end = iobase + iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = data->irq, - .end = data->irq, + .start = irq, + .end = irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); + return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); } diff --git a/trunk/arch/arm/plat-mxc/ehci.c b/trunk/arch/arm/plat-mxc/ehci.c index 9915607683de..35a064ff02ba 100644 --- a/trunk/arch/arm/plat-mxc/ehci.c +++ b/trunk/arch/arm/plat-mxc/ehci.c @@ -249,8 +249,8 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) #ifdef CONFIG_ARCH_MX51 if (cpu_is_mx51()) { void __iomem *usb_base; - void __iomem *usbotg_base; - void __iomem *usbother_base; + u32 usbotg_base; + u32 usbother_base; int ret = 0; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); diff --git a/trunk/arch/arm/plat-mxc/epit.c b/trunk/arch/arm/plat-mxc/epit.c deleted file mode 100644 index ee9582f4972e..000000000000 --- a/trunk/arch/arm/plat-mxc/epit.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * linux/arch/arm/plat-mxc/epit.c - * - * Copyright (C) 2010 Sascha Hauer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#define EPITCR 0x00 -#define EPITSR 0x04 -#define EPITLR 0x08 -#define EPITCMPR 0x0c -#define EPITCNR 0x10 - -#define EPITCR_EN (1 << 0) -#define EPITCR_ENMOD (1 << 1) -#define EPITCR_OCIEN (1 << 2) -#define EPITCR_RLD (1 << 3) -#define EPITCR_PRESC(x) (((x) & 0xfff) << 4) -#define EPITCR_SWR (1 << 16) -#define EPITCR_IOVW (1 << 17) -#define EPITCR_DBGEN (1 << 18) -#define EPITCR_WAITEN (1 << 19) -#define EPITCR_RES (1 << 20) -#define EPITCR_STOPEN (1 << 21) -#define EPITCR_OM_DISCON (0 << 22) -#define EPITCR_OM_TOGGLE (1 << 22) -#define EPITCR_OM_CLEAR (2 << 22) -#define EPITCR_OM_SET (3 << 22) -#define EPITCR_CLKSRC_OFF (0 << 24) -#define EPITCR_CLKSRC_PERIPHERAL (1 << 24) -#define EPITCR_CLKSRC_REF_HIGH (1 << 24) -#define EPITCR_CLKSRC_REF_LOW (3 << 24) - -#define EPITSR_OCIF (1 << 0) - -#include -#include -#include -#include - -#include -#include -#include - -static struct clock_event_device clockevent_epit; -static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; - -static void __iomem *timer_base; - -static inline void epit_irq_disable(void) -{ - u32 val; - - val = __raw_readl(timer_base + EPITCR); - val &= ~EPITCR_OCIEN; - __raw_writel(val, timer_base + EPITCR); -} - -static inline void epit_irq_enable(void) -{ - u32 val; - - val = __raw_readl(timer_base + EPITCR); - val |= EPITCR_OCIEN; - __raw_writel(val, timer_base + EPITCR); -} - -static void epit_irq_acknowledge(void) -{ - __raw_writel(EPITSR_OCIF, timer_base + EPITSR); -} - -static cycle_t epit_read(struct clocksource *cs) -{ - return 0 - __raw_readl(timer_base + EPITCNR); -} - -static struct clocksource clocksource_epit = { - .name = "epit", - .rating = 200, - .read = epit_read, - .mask = CLOCKSOURCE_MASK(32), - .shift = 20, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int __init epit_clocksource_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - - clocksource_epit.mult = clocksource_hz2mult(c, - clocksource_epit.shift); - clocksource_register(&clocksource_epit); - - return 0; -} - -/* clock event */ - -static int epit_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long tcmp; - - tcmp = __raw_readl(timer_base + EPITCNR); - - __raw_writel(tcmp - evt, timer_base + EPITCMPR); - - return 0; -} - -static void epit_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call epit_set_next_event() - */ - local_irq_save(flags); - - /* Disable interrupt in GPT module */ - epit_irq_disable(); - - if (mode != clockevent_mode) { - /* Set event time into far-far future */ - - /* Clear pending interrupt */ - epit_irq_acknowledge(); - } - - /* Remember timer mode */ - clockevent_mode = mode; - local_irq_restore(flags); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - printk(KERN_ERR "epit_set_mode: Periodic mode is not " - "supported for i.MX EPIT\n"); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* - * Do not put overhead of interrupt enable/disable into - * epit_set_next_event(), the core has about 4 minutes - * to call epit_set_next_event() or shutdown clock after - * mode switching - */ - local_irq_save(flags); - epit_irq_enable(); - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appear */ - break; - } -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_epit; - - epit_irq_acknowledge(); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction epit_timer_irq = { - .name = "i.MX EPIT Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = epit_timer_interrupt, -}; - -static struct clock_event_device clockevent_epit = { - .name = "epit", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .set_mode = epit_set_mode, - .set_next_event = epit_set_next_event, - .rating = 200, -}; - -static int __init epit_clockevent_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - - clockevent_epit.mult = div_sc(c, NSEC_PER_SEC, - clockevent_epit.shift); - clockevent_epit.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_epit); - clockevent_epit.min_delta_ns = - clockevent_delta2ns(0x800, &clockevent_epit); - - clockevent_epit.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_epit); - - return 0; -} - -void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) -{ - clk_enable(timer_clk); - - timer_base = base; - - /* - * Initialise to a known state (all timers off, and timing reset) - */ - __raw_writel(0x0, timer_base + EPITCR); - - __raw_writel(0xffffffff, timer_base + EPITLR); - __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, - timer_base + EPITCR); - - /* init and register the timer to the framework */ - epit_clocksource_init(timer_clk); - epit_clockevent_init(timer_clk); - - /* Make irqs happen */ - setup_irq(irq, &epit_timer_irq); -} diff --git a/trunk/arch/arm/plat-mxc/gpio.c b/trunk/arch/arm/plat-mxc/gpio.c index 9d38da077edb..57ec4a896a5d 100644 --- a/trunk/arch/arm/plat-mxc/gpio.c +++ b/trunk/arch/arm/plat-mxc/gpio.c @@ -235,7 +235,7 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) unsigned long flags; spin_lock_irqsave(&port->lock, flags); - l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset); + l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset); __raw_writel(l, reg); spin_unlock_irqrestore(&port->lock, flags); } diff --git a/trunk/arch/arm/plat-mxc/include/mach/common.h b/trunk/arch/arm/plat-mxc/include/mach/common.h index 7a1e1f89ff09..2941472582d2 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/common.h +++ b/trunk/arch/arm/plat-mxc/include/mach/common.h @@ -32,7 +32,6 @@ extern void mx31_init_irq(void); extern void mx35_init_irq(void); extern void mx51_init_irq(void); extern void mxc91231_init_irq(void); -extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); diff --git a/trunk/arch/arm/plat-mxc/include/mach/devices-common.h b/trunk/arch/arm/plat-mxc/include/mach/devices-common.h index 049897880403..c5f68c587309 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/trunk/arch/arm/plat-mxc/include/mach/devices-common.h @@ -14,101 +14,47 @@ struct platform_device *imx_add_platform_device(const char *name, int id, const struct resource *res, unsigned int num_resources, const void *data, size_t size_data); -#include -struct imx_fec_data { - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_fec( - const struct imx_fec_data *data, - const struct fec_platform_data *pdata); - +#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE) #include struct platform_device *__init imx_add_flexcan(int id, resource_size_t iobase, resource_size_t iosize, resource_size_t irq, const struct flexcan_platform_data *pdata); +#else +/* the ifdef can be removed once the flexcan driver has been merged */ +struct flexcan_platform_data; +static inline struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata) +{ + return NULL; +} +#endif #include -struct imx_imx_i2c_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_i2c( - const struct imx_imx_i2c_data *data, +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, const struct imxi2c_platform_data *pdata); -#include -struct imx_imx_ssi_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; - resource_size_t dmatx0; - resource_size_t dmarx0; - resource_size_t dmatx1; - resource_size_t dmarx1; -}; -struct platform_device *__init imx_add_imx_ssi( - const struct imx_imx_ssi_data *data, - const struct imx_ssi_platform_data *pdata); - #include -struct imx_imx_uart_3irq_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irqrx; - resource_size_t irqtx; - resource_size_t irqrts; -}; -struct platform_device *__init imx_add_imx_uart_3irq( - const struct imx_imx_uart_3irq_data *data, +struct platform_device *__init imx_add_imx_uart_3irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irqrx, resource_size_t irqtx, + resource_size_t irqrts, const struct imxuart_platform_data *pdata); - -struct imx_imx_uart_1irq_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_uart_1irq( - const struct imx_imx_uart_1irq_data *data, +struct platform_device *__init imx_add_imx_uart_1irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, const struct imxuart_platform_data *pdata); #include -struct imx_mxc_nand_data { - /* - * id is traditionally 0, but -1 is more appropriate. We use -1 for new - * machines but don't change existing devices as the nand device usually - * appears in the kernel command line to pass its partitioning. - */ - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t axibase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_nand( - const struct imx_mxc_nand_data *data, - const struct mxc_nand_platform_data *pdata); +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); #include -struct imx_spi_imx_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t iosize; - int irq; -}; -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, const struct spi_imx_master *pdata); - -#include -struct platform_device *__init imx_add_esdhc(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, - const struct esdhc_platform_data *pdata); diff --git a/trunk/arch/arm/plat-mxc/include/mach/esdhc.h b/trunk/arch/arm/plat-mxc/include/mach/esdhc.h deleted file mode 100644 index a48a9aaa56b1..000000000000 --- a/trunk/arch/arm/plat-mxc/include/mach/esdhc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright 2010 Wolfram Sang - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; version 2 - * of the License. - */ - -#ifndef __ASM_ARCH_IMX_ESDHC_H -#define __ASM_ARCH_IMX_ESDHC_H - -struct esdhc_platform_data { - unsigned int wp_gpio; /* write protect pin */ -}; -#endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/trunk/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/trunk/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 5160f1073ec9..21bfa46785bb 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/trunk/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -45,15 +45,6 @@ typedef enum iomux_config { PAD_CTL_PKE | PAD_CTL_HYS) #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ PAD_CTL_SRE_FAST) -#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) - -#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) -#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) -#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) /* * The naming convention for the pad modes is MX51_PAD___ @@ -115,20 +106,14 @@ typedef enum iomux_config { #define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) #define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) @@ -141,32 +126,18 @@ typedef enum iomux_config { #define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) #define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) @@ -214,25 +185,15 @@ typedef enum iomux_config { #define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) #define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) @@ -275,14 +236,14 @@ typedef enum iomux_config { #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) @@ -334,17 +295,11 @@ typedef enum iomux_config { #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) #define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) #define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL) #define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL) #define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL) #define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL) #define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx21.h b/trunk/arch/arm/plat-mxc/include/mach/mx21.h index 8bc59720b6e4..ed98b9c9f389 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mx21.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mx21.h @@ -120,7 +120,7 @@ #define MX21_INT_GPT1 26 #define MX21_INT_WDOG 27 #define MX21_INT_PCMCIA 28 -#define MX21_INT_NFC 29 +#define MX21_INT_NANDFC 29 #define MX21_INT_BMI 30 #define MX21_INT_CSI 31 #define MX21_INT_DMACH0 32 diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx25.h b/trunk/arch/arm/plat-mxc/include/mach/mx25.h index 153dd1b2a473..4a6f800990f8 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mx25.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mx25.h @@ -50,8 +50,6 @@ #define MX25_SSI1_BASE_ADDR 0x50034000 #define MX25_NFC_BASE_ADDR 0xbb000000 #define MX25_DRYICE_BASE_ADDR 0x53ffc000 -#define MX25_ESDHC1_BASE_ADDR 0x53fb4000 -#define MX25_ESDHC2_BASE_ADDR 0x53fb8000 #define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_KPP_BASE_ADDR 0x43fa8000 #define MX25_OTG_BASE_ADDR 0x53ff4000 @@ -61,8 +59,6 @@ #define MX25_INT_I2C1 3 #define MX25_INT_I2C2 4 #define MX25_INT_UART4 5 -#define MX25_INT_MMC_SDHC2 8 -#define MX25_INT_MMC_SDHC1 9 #define MX25_INT_I2C3 10 #define MX25_INT_SSI2 11 #define MX25_INT_SSI1 12 @@ -73,7 +69,7 @@ #define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 #define MX25_INT_UART2 32 -#define MX25_INT_NFC 33 +#define MX25_INT_NANDFC 33 #define MX25_INT_LCDC 39 #define MX25_INT_UART5 40 #define MX25_INT_CAN1 43 @@ -81,13 +77,4 @@ #define MX25_INT_UART1 45 #define MX25_INT_FEC 57 -#define MX25_DMA_REQ_SSI2_RX1 22 -#define MX25_DMA_REQ_SSI2_TX1 23 -#define MX25_DMA_REQ_SSI2_RX0 24 -#define MX25_DMA_REQ_SSI2_TX0 25 -#define MX25_DMA_REQ_SSI1_RX1 26 -#define MX25_DMA_REQ_SSI1_TX1 27 -#define MX25_DMA_REQ_SSI1_RX0 28 -#define MX25_DMA_REQ_SSI1_TX0 29 - #endif /* ifndef __MACH_MX25_H__ */ diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx27.h b/trunk/arch/arm/plat-mxc/include/mach/mx27.h index 2237ba2e5351..a8ab2e02a8ca 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mx27.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mx27.h @@ -167,7 +167,7 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_GPT1 26 #define MX27_INT_WDOG 27 #define MX27_INT_PCMCIA 28 -#define MX27_INT_NFC 29 +#define MX27_INT_NANDFC 29 #define MX27_INT_ATA 30 #define MX27_INT_CSI 31 #define MX27_INT_DMACH0 32 diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx31.h b/trunk/arch/arm/plat-mxc/include/mach/mx31.h index 03e2afabc9fc..afee3ab9d62e 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mx31.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mx31.h @@ -168,7 +168,7 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_POWER_FAIL 30 #define MX31_INT_CCM_DVFS 31 #define MX31_INT_UART2 32 -#define MX31_INT_NFC 33 +#define MX31_INT_NANDFC 33 #define MX31_INT_SDMA 34 #define MX31_INT_USB1 35 #define MX31_INT_USB2 36 @@ -197,15 +197,6 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 -#define MX31_DMA_REQ_SSI2_RX1 22 -#define MX31_DMA_REQ_SSI2_TX1 23 -#define MX31_DMA_REQ_SSI2_RX0 24 -#define MX31_DMA_REQ_SSI2_TX0 25 -#define MX31_DMA_REQ_SSI1_RX1 26 -#define MX31_DMA_REQ_SSI1_TX1 27 -#define MX31_DMA_REQ_SSI1_RX0 28 -#define MX31_DMA_REQ_SSI1_TX0 29 - #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ /* silicon revisions specific to i.MX31 */ diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx35.h b/trunk/arch/arm/plat-mxc/include/mach/mx35.h index cb071b7b17e5..af3038c12e39 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mx35.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mx35.h @@ -1,6 +1,5 @@ #ifndef __MACH_MX35_H__ #define __MACH_MX35_H__ - /* * IRAM */ @@ -53,9 +52,6 @@ #define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) #define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) #define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) -#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000) -#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000) -#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000) #define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) #define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) #define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) @@ -67,8 +63,6 @@ #define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) -#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) - #define MX35_OTG_BASE_ADDR 0x53ff4000 #define MX35_ROMP_BASE_ADDR 0x60000000 @@ -151,7 +145,7 @@ #define MX35_INT_GPT 29 #define MX35_INT_POWER_FAIL 30 #define MX35_INT_UART2 32 -#define MX35_INT_NFC 33 +#define MX35_INT_NANDFC 33 #define MX35_INT_SDMA 34 #define MX35_INT_USBHS 35 #define MX35_INT_USBOTG 37 @@ -179,18 +173,22 @@ #define MX35_INT_EXT_WDOG 62 #define MX35_INT_EXT_TV 63 -#define MX35_DMA_REQ_SSI2_RX1 22 -#define MX35_DMA_REQ_SSI2_TX1 23 -#define MX35_DMA_REQ_SSI2_RX0 24 -#define MX35_DMA_REQ_SSI2_TX0 25 -#define MX35_DMA_REQ_SSI1_RX1 26 -#define MX35_DMA_REQ_SSI1_TX1 27 -#define MX35_DMA_REQ_SSI1_RX0 28 -#define MX35_DMA_REQ_SSI1_TX0 29 - #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ -#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 +/* silicon revisions specific to i.MX31 */ +#define MX35_CHIP_REV_1_0 0x10 +#define MX35_CHIP_REV_1_1 0x11 +#define MX35_CHIP_REV_1_2 0x12 +#define MX35_CHIP_REV_1_3 0x13 +#define MX35_CHIP_REV_2_0 0x20 +#define MX35_CHIP_REV_2_1 0x21 +#define MX35_CHIP_REV_2_2 0x22 +#define MX35_CHIP_REV_2_3 0x23 +#define MX35_CHIP_REV_3_0 0x30 +#define MX35_CHIP_REV_3_1 0x31 +#define MX35_CHIP_REV_3_2 0x32 + +#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 #define MX35_SYSTEM_REV_NUM 3 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx3x.h b/trunk/arch/arm/plat-mxc/include/mach/mx3x.h index d1bd26d7b8a6..7a356de385f5 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mx3x.h @@ -240,7 +240,7 @@ #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ -/* silicon revisions specific to i.MX31 and i.MX35 */ +/* silicon revisions specific to i.MX31 */ #define MX3x_CHIP_REV_1_0 0x10 #define MX3x_CHIP_REV_1_1 0x11 #define MX3x_CHIP_REV_1_2 0x12 @@ -267,14 +267,6 @@ static inline int mx31_revision(void) { return mx31_cpu_rev; } - -extern unsigned int mx35_cpu_rev; -extern void mx35_read_cpu_rev(void); - -static inline int mx35_revision(void) -{ - return mx35_cpu_rev; -} #endif #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS @@ -397,6 +389,19 @@ static inline int mx35_revision(void) #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG #define MXC_INT_EXT_TV MX3x_INT_EXT_TV #define PROD_SIGNATURE MX3x_PROD_SIGNATURE +#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0 +#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1 +#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2 +#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3 +#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0 +#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1 +#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2 +#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3 +#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0 +#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1 +#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 +#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN +#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM #endif #endif /* ifndef __MACH_MX3x_H__ */ diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx51.h b/trunk/arch/arm/plat-mxc/include/mach/mx51.h index c54b5c32d82e..5aad344d5651 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mx51.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mx51.h @@ -1,5 +1,5 @@ -#ifndef __MACH_MX51_H__ -#define __MACH_MX51_H__ +#ifndef __ASM_ARCH_MXC_MX51_H__ +#define __ASM_ARCH_MXC_MX51_H__ /* * MX51 memory map: @@ -7,23 +7,24 @@ * * Virt Phys Size What * --------------------------------------------------------------------------- - * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM) + * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM) * 30000000 256M GPU * 40000000 512M IPU - * fa200000 60000000 1M DEBUG - * fb100000 70000000 1M SPBA 0 - * fb000000 73f00000 1M AIPS 1 - * fb200000 83f00000 1M AIPS 2 - * 8fffc000 16K TZIC (interrupt controller) + * FA200000 60000000 1M DEBUG + * FB100000 70000000 1M SPBA 0 + * FB000000 73F00000 1M AIPS 1 + * FB200000 83F00000 1M AIPS 2 + * 8FFFC000 16K TZIC (interrupt controller) * 90000000 256M CSD0 SDRAM/DDR - * a0000000 256M CSD1 SDRAM/DDR - * b0000000 128M CS0 Flash - * b8000000 128M CS1 Flash - * c0000000 128M CS2 Flash - * c8000000 64M CS3 Flash - * cc000000 32M CS4 SRAM - * ce000000 32M CS5 SRAM - * cfff0000 64K NFC (NAND Flash AXI) + * A0000000 256M CSD1 SDRAM/DDR + * B0000000 128M CS0 Flash + * B8000000 128M CS1 Flash + * C0000000 128M CS2 Flash + * C8000000 64M CS3 Flash + * CC000000 32M CS4 SRAM + * CE000000 32M CS5 SRAM + * CFFF0000 64K NFC (NAND Flash AXI) + * */ /* @@ -35,151 +36,65 @@ /* * IRAM */ -#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ -#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000 +#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ +#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000 #define MX51_IRAM_PARTITIONS 16 +#define MX51_IRAM_PARTITIONS_TO1 12 #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ -#define MX51_GPU_BASE_ADDR 0x20000000 -#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 -#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 - -#define MX51_DEBUG_BASE_ADDR 0x60000000 -#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000 -#define MX51_DEBUG_SIZE SZ_1M - -#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) -#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000) -#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000) -#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000) -#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000) -#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000) -#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000) -#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000) - /* - * SPBA global module enabled #0 - */ -#define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 -#define MX51_SPBA0_SIZE SZ_1M - -#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) -#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) -#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) -#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) -#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) -#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) -#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) -#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) -#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) -#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) -#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000) -#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000) - -/* - * AIPS 1 + * NFC */ -#define MX51_AIPS1_BASE_ADDR 0x73f00000 -#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 -#define MX51_AIPS1_SIZE SZ_1M - -#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) -#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) -#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) -#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) -#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) -#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) -#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) -#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) -#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) -#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) -#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000) -#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000) -#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000) -#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000) -#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000) -#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000) -#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000) -#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000) -#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000) -#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000) +#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ +#define MX51_NFC_AXI_SIZE SZ_64K /* - * AIPS 2 + * Graphics Memory of GPU */ -#define MX51_AIPS2_BASE_ADDR 0x83f00000 -#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000 -#define MX51_AIPS2_SIZE SZ_1M +#define MX51_GPU_BASE_ADDR 0x20000000 +#define MX51_GPU2D_BASE_ADDR 0xD0000000 -#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) -#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000) -#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000) -#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000) -#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000) -#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000) -#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) -#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) -#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) -#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) -#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) -#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) -#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) -#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) -#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) -#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) -#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) -#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) -#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000) -#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000) -#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000) -#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000) -#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000) -#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00) -#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) -#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) -#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) -#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) -#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) -#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) -#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) -#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000) +#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000 +#define MX51_TZIC_BASE_ADDR 0xE0000000 -#define MX51_CSD0_BASE_ADDR 0x90000000 -#define MX51_CSD1_BASE_ADDR 0xa0000000 -#define MX51_CS0_BASE_ADDR 0xb0000000 -#define MX51_CS1_BASE_ADDR 0xb8000000 -#define MX51_CS2_BASE_ADDR 0xc0000000 -#define MX51_CS3_BASE_ADDR 0xc8000000 -#define MX51_CS4_BASE_ADDR 0xcc000000 -#define MX51_CS5_BASE_ADDR 0xce000000 +#define MX51_DEBUG_BASE_ADDR 0x60000000 +#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 +#define MX51_DEBUG_SIZE SZ_1M +#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000) +#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000) +#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000) +#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000) +#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000) +#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000) +#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000) +#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000) /* - * NFC + * SPBA global module enabled #0 */ -#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */ -#define MX51_NFC_AXI_SIZE SZ_64K - -#define MX51_GPU2D_BASE_ADDR 0xd0000000 -#define MX51_TZIC_BASE_ADDR 0xe0000000 - -#define MX51_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ - IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \ - IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS2)) +#define MX51_SPBA0_BASE_ADDR 0x70000000 +#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000 +#define MX51_SPBA0_SIZE SZ_1M -/* This is currently used in , but should go away */ -#define MX51_AIPS1_IO_ADDRESS(x) \ - (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) +#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) +#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) +#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) +#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) +#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) +#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) +#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) +#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) +#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) +#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) +#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) +#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) /* * defines for SPBA modules */ #define MX51_SPBA_SDHC1 0x04 #define MX51_SPBA_SDHC2 0x08 -#define MX51_SPBA_UART3 0x0c +#define MX51_SPBA_UART3 0x0C #define MX51_SPBA_CSPI1 0x10 #define MX51_SPBA_SSI2 0x14 #define MX51_SPBA_SDHC3 0x20 @@ -188,7 +103,35 @@ #define MX51_SPBA_ATA 0x30 #define MX51_SPBA_SLIM 0x34 #define MX51_SPBA_HSI2C 0x38 -#define MX51_SPBA_CTRL 0x3c +#define MX51_SPBA_CTRL 0x3C + +/* + * AIPS 1 + */ +#define MX51_AIPS1_BASE_ADDR 0x73F00000 +#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000 +#define MX51_AIPS1_SIZE SZ_1M + +#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000) +#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000) +#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000) +#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000) +#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000) +#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000) +#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000) +#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000) +#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000) +#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000) +#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000) +#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000) +#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000) +#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000) +#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000) +#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000) +#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000) +#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000) +#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000) +#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000) /* * Defines for modules using static and dynamic DMA channels @@ -221,186 +164,282 @@ #define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL #define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL +/* + * AIPS 2 + */ +#define MX51_AIPS2_BASE_ADDR 0x83F00000 +#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000 +#define MX51_AIPS2_SIZE SZ_1M + +#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000) +#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000) +#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000) +#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000) +#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000) +#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000) +#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000) +#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000) +#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000) +#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000) +#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000) +#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000) +#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000) +#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000) +#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000) +#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000) +#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000) +#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000) +#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000) +#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000) +#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000) +#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000) +#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000) +#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00) +#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000) +#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000) +#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000) +#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000) +#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000) +#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000) +#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000) +#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000) + +/* + * Memory regions and CS + */ +#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 +#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 +#define MX51_CSD0_BASE_ADDR 0x90000000 +#define MX51_CSD1_BASE_ADDR 0xA0000000 +#define MX51_CS0_BASE_ADDR 0xB0000000 +#define MX51_CS1_BASE_ADDR 0xB8000000 +#define MX51_CS2_BASE_ADDR 0xC0000000 +#define MX51_CS3_BASE_ADDR 0xC8000000 +#define MX51_CS4_BASE_ADDR 0xCC000000 +#define MX51_CS5_BASE_ADDR 0xCE000000 + +/* Does given address belongs to the specified memory region? */ +#define ADDRESS_IN_REGION(addr, start, size) \ + (((addr) >= (start)) && ((addr) < (start)+(size))) + +/* Does given address belongs to the specified named `module'? */ +#define MX51_IS_MODULE(addr, module) \ + ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \ + MX51_ ## module ## _SIZE) +/* + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + */ + +#define MX51_IO_ADDRESS(x) \ + (void __iomem *) \ + (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ + 0xDEADBEEF) + +/* + * define the address mapping macros: in physical address order + */ +#define MX51_IRAM_IO_ADDRESS(x) \ + (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT) + +#define MX51_DEBUG_IO_ADDRESS(x) \ + (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT) + +#define MX51_SPBA0_IO_ADDRESS(x) \ + (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT) + +#define MX51_AIPS1_IO_ADDRESS(x) \ + (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) + +#define MX51_AIPS2_IO_ADDRESS(x) \ + (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) + #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 /* * DMA request assignments */ -#define MX51_DMA_REQ_VPU 0 -#define MX51_DMA_REQ_GPC 1 -#define MX51_DMA_REQ_ATA_RX 2 -#define MX51_DMA_REQ_ATA_TX 3 -#define MX51_DMA_REQ_ATA_TX_END 4 -#define MX51_DMA_REQ_SLIM_B 5 -#define MX51_DMA_REQ_CSPI1_RX 6 -#define MX51_DMA_REQ_CSPI1_TX 7 -#define MX51_DMA_REQ_CSPI2_RX 8 -#define MX51_DMA_REQ_CSPI2_TX 9 -#define MX51_DMA_REQ_HS_I2C_TX 10 -#define MX51_DMA_REQ_HS_I2C_RX 11 -#define MX51_DMA_REQ_FIRI_RX 12 -#define MX51_DMA_REQ_FIRI_TX 13 -#define MX51_DMA_REQ_EXTREQ1 14 -#define MX51_DMA_REQ_GPU 15 -#define MX51_DMA_REQ_UART2_RX 16 -#define MX51_DMA_REQ_UART2_TX 17 -#define MX51_DMA_REQ_UART1_RX 18 -#define MX51_DMA_REQ_UART1_TX 19 -#define MX51_DMA_REQ_SDHC1 20 -#define MX51_DMA_REQ_SDHC2 21 -#define MX51_DMA_REQ_SSI2_RX1 22 -#define MX51_DMA_REQ_SSI2_TX1 23 -#define MX51_DMA_REQ_SSI2_RX0 24 -#define MX51_DMA_REQ_SSI2_TX0 25 -#define MX51_DMA_REQ_SSI1_RX1 26 -#define MX51_DMA_REQ_SSI1_TX1 27 -#define MX51_DMA_REQ_SSI1_RX0 28 -#define MX51_DMA_REQ_SSI1_TX0 29 -#define MX51_DMA_REQ_EMI_RD 30 -#define MX51_DMA_REQ_CTI2_0 31 -#define MX51_DMA_REQ_EMI_WR 32 -#define MX51_DMA_REQ_CTI2_1 33 -#define MX51_DMA_REQ_EPIT2 34 -#define MX51_DMA_REQ_SSI3_RX2 35 -#define MX51_DMA_REQ_IPU 36 -#define MX51_DMA_REQ_SSI3_TX2 37 -#define MX51_DMA_REQ_CSPI_RX 38 -#define MX51_DMA_REQ_CSPI_TX 39 -#define MX51_DMA_REQ_SDHC3 40 -#define MX51_DMA_REQ_SDHC4 41 -#define MX51_DMA_REQ_SLIM_B_TX 42 -#define MX51_DMA_REQ_UART3_RX 43 -#define MX51_DMA_REQ_UART3_TX 44 -#define MX51_DMA_REQ_SPDIF 45 -#define MX51_DMA_REQ_SSI3_RX1 46 -#define MX51_DMA_REQ_SSI3_TX1 47 +#define MX51_DMA_REQ_SSI3_TX1 47 +#define MX51_DMA_REQ_SSI3_RX1 46 +#define MX51_DMA_REQ_SPDIF 45 +#define MX51_DMA_REQ_UART3_TX 44 +#define MX51_DMA_REQ_UART3_RX 43 +#define MX51_DMA_REQ_SLIM_B_TX 42 +#define MX51_DMA_REQ_SDHC4 41 +#define MX51_DMA_REQ_SDHC3 40 +#define MX51_DMA_REQ_CSPI_TX 39 +#define MX51_DMA_REQ_CSPI_RX 38 +#define MX51_DMA_REQ_SSI3_TX2 37 +#define MX51_DMA_REQ_IPU 36 +#define MX51_DMA_REQ_SSI3_RX2 35 +#define MX51_DMA_REQ_EPIT2 34 +#define MX51_DMA_REQ_CTI2_1 33 +#define MX51_DMA_REQ_EMI_WR 32 +#define MX51_DMA_REQ_CTI2_0 31 +#define MX51_DMA_REQ_EMI_RD 30 +#define MX51_DMA_REQ_SSI1_TX1 29 +#define MX51_DMA_REQ_SSI1_RX1 28 +#define MX51_DMA_REQ_SSI1_TX2 27 +#define MX51_DMA_REQ_SSI1_RX2 26 +#define MX51_DMA_REQ_SSI2_TX1 25 +#define MX51_DMA_REQ_SSI2_RX1 24 +#define MX51_DMA_REQ_SSI2_TX2 23 +#define MX51_DMA_REQ_SSI2_RX2 22 +#define MX51_DMA_REQ_SDHC2 21 +#define MX51_DMA_REQ_SDHC1 20 +#define MX51_DMA_REQ_UART1_TX 19 +#define MX51_DMA_REQ_UART1_RX 18 +#define MX51_DMA_REQ_UART2_TX 17 +#define MX51_DMA_REQ_UART2_RX 16 +#define MX51_DMA_REQ_GPU 15 +#define MX51_DMA_REQ_EXTREQ1 14 +#define MX51_DMA_REQ_FIRI_TX 13 +#define MX51_DMA_REQ_FIRI_RX 12 +#define MX51_DMA_REQ_HS_I2C_RX 11 +#define MX51_DMA_REQ_HS_I2C_TX 10 +#define MX51_DMA_REQ_CSPI2_TX 9 +#define MX51_DMA_REQ_CSPI2_RX 8 +#define MX51_DMA_REQ_CSPI1_TX 7 +#define MX51_DMA_REQ_CSPI1_RX 6 +#define MX51_DMA_REQ_SLIM_B 5 +#define MX51_DMA_REQ_ATA_TX_END 4 +#define MX51_DMA_REQ_ATA_TX 3 +#define MX51_DMA_REQ_ATA_RX 2 +#define MX51_DMA_REQ_GPC 1 +#define MX51_DMA_REQ_VPU 0 /* * Interrupt numbers */ -#define MX51_MXC_INT_BASE 0 -#define MX51_MXC_INT_RESV0 0 -#define MX51_MXC_INT_MMC_SDHC1 1 -#define MX51_MXC_INT_MMC_SDHC2 2 -#define MX51_MXC_INT_MMC_SDHC3 3 -#define MX51_MXC_INT_MMC_SDHC4 4 -#define MX51_MXC_INT_RESV5 5 -#define MX51_INT_SDMA 6 -#define MX51_MXC_INT_IOMUX 7 -#define MX51_INT_NFC 8 -#define MX51_MXC_INT_VPU 9 -#define MX51_MXC_INT_IPU_ERR 10 -#define MX51_MXC_INT_IPU_SYN 11 -#define MX51_MXC_INT_GPU 12 -#define MX51_MXC_INT_RESV13 13 -#define MX51_MXC_INT_USB_H1 14 -#define MX51_MXC_INT_EMI 15 -#define MX51_MXC_INT_USB_H2 16 -#define MX51_MXC_INT_USB_H3 17 -#define MX51_MXC_INT_USB_OTG 18 -#define MX51_MXC_INT_SAHARA_H0 19 -#define MX51_MXC_INT_SAHARA_H1 20 -#define MX51_MXC_INT_SCC_SMN 21 -#define MX51_MXC_INT_SCC_STZ 22 -#define MX51_MXC_INT_SCC_SCM 23 -#define MX51_MXC_INT_SRTC_NTZ 24 -#define MX51_MXC_INT_SRTC_TZ 25 -#define MX51_MXC_INT_RTIC 26 -#define MX51_MXC_INT_CSU 27 -#define MX51_MXC_INT_SLIM_B 28 -#define MX51_INT_SSI1 29 -#define MX51_INT_SSI2 30 -#define MX51_INT_UART1 31 -#define MX51_INT_UART2 32 -#define MX51_INT_UART3 33 -#define MX51_MXC_INT_RESV34 34 -#define MX51_MXC_INT_RESV35 35 -#define MX51_INT_ECSPI1 36 -#define MX51_INT_ECSPI2 37 -#define MX51_INT_CSPI 38 -#define MX51_MXC_INT_GPT 39 -#define MX51_MXC_INT_EPIT1 40 -#define MX51_MXC_INT_EPIT2 41 -#define MX51_MXC_INT_GPIO1_INT7 42 -#define MX51_MXC_INT_GPIO1_INT6 43 -#define MX51_MXC_INT_GPIO1_INT5 44 -#define MX51_MXC_INT_GPIO1_INT4 45 -#define MX51_MXC_INT_GPIO1_INT3 46 -#define MX51_MXC_INT_GPIO1_INT2 47 -#define MX51_MXC_INT_GPIO1_INT1 48 -#define MX51_MXC_INT_GPIO1_INT0 49 -#define MX51_MXC_INT_GPIO1_LOW 50 -#define MX51_MXC_INT_GPIO1_HIGH 51 -#define MX51_MXC_INT_GPIO2_LOW 52 -#define MX51_MXC_INT_GPIO2_HIGH 53 -#define MX51_MXC_INT_GPIO3_LOW 54 -#define MX51_MXC_INT_GPIO3_HIGH 55 -#define MX51_MXC_INT_GPIO4_LOW 56 -#define MX51_MXC_INT_GPIO4_HIGH 57 -#define MX51_MXC_INT_WDOG1 58 -#define MX51_MXC_INT_WDOG2 59 -#define MX51_MXC_INT_KPP 60 -#define MX51_MXC_INT_PWM1 61 -#define MX51_INT_I2C1 62 -#define MX51_INT_I2C2 63 -#define MX51_MXC_INT_HS_I2C 64 -#define MX51_MXC_INT_RESV65 65 -#define MX51_MXC_INT_RESV66 66 -#define MX51_MXC_INT_SIM_IPB 67 -#define MX51_MXC_INT_SIM_DAT 68 -#define MX51_MXC_INT_IIM 69 -#define MX51_MXC_INT_ATA 70 -#define MX51_MXC_INT_CCM1 71 -#define MX51_MXC_INT_CCM2 72 -#define MX51_MXC_INT_GPC1 73 -#define MX51_MXC_INT_GPC2 74 -#define MX51_MXC_INT_SRC 75 -#define MX51_MXC_INT_NM 76 -#define MX51_MXC_INT_PMU 77 -#define MX51_MXC_INT_CTI_IRQ 78 -#define MX51_MXC_INT_CTI1_TG0 79 -#define MX51_MXC_INT_CTI1_TG1 80 -#define MX51_MXC_INT_MCG_ERR 81 -#define MX51_MXC_INT_MCG_TMR 82 -#define MX51_MXC_INT_MCG_FUNC 83 -#define MX51_MXC_INT_GPU2_IRQ 84 -#define MX51_MXC_INT_GPU2_BUSY 85 -#define MX51_MXC_INT_RESV86 86 -#define MX51_INT_FEC 87 -#define MX51_MXC_INT_OWIRE 88 -#define MX51_MXC_INT_CTI1_TG2 89 -#define MX51_MXC_INT_SJC 90 -#define MX51_MXC_INT_SPDIF 91 -#define MX51_MXC_INT_TVE 92 -#define MX51_MXC_INT_FIRI 93 -#define MX51_MXC_INT_PWM2 94 -#define MX51_MXC_INT_SLIM_EXP 95 -#define MX51_MXC_INT_SSI3 96 -#define MX51_MXC_INT_EMI_BOOT 97 -#define MX51_MXC_INT_CTI1_TG3 98 -#define MX51_MXC_INT_SMC_RX 99 -#define MX51_MXC_INT_VPU_IDLE 100 -#define MX51_MXC_INT_EMI_NFC 101 -#define MX51_MXC_INT_GPU_IDLE 102 +#define MX51_MXC_INT_BASE 0 +#define MX51_MXC_INT_RESV0 0 +#define MX51_MXC_INT_MMC_SDHC1 1 +#define MX51_MXC_INT_MMC_SDHC2 2 +#define MX51_MXC_INT_MMC_SDHC3 3 +#define MX51_MXC_INT_MMC_SDHC4 4 +#define MX51_MXC_INT_RESV5 5 +#define MX51_MXC_INT_SDMA 6 +#define MX51_MXC_INT_IOMUX 7 +#define MX51_MXC_INT_NFC 8 +#define MX51_MXC_INT_VPU 9 +#define MX51_MXC_INT_IPU_ERR 10 +#define MX51_MXC_INT_IPU_SYN 11 +#define MX51_MXC_INT_GPU 12 +#define MX51_MXC_INT_RESV13 13 +#define MX51_MXC_INT_USB_H1 14 +#define MX51_MXC_INT_EMI 15 +#define MX51_MXC_INT_USB_H2 16 +#define MX51_MXC_INT_USB_H3 17 +#define MX51_MXC_INT_USB_OTG 18 +#define MX51_MXC_INT_SAHARA_H0 19 +#define MX51_MXC_INT_SAHARA_H1 20 +#define MX51_MXC_INT_SCC_SMN 21 +#define MX51_MXC_INT_SCC_STZ 22 +#define MX51_MXC_INT_SCC_SCM 23 +#define MX51_MXC_INT_SRTC_NTZ 24 +#define MX51_MXC_INT_SRTC_TZ 25 +#define MX51_MXC_INT_RTIC 26 +#define MX51_MXC_INT_CSU 27 +#define MX51_MXC_INT_SLIM_B 28 +#define MX51_MXC_INT_SSI1 29 +#define MX51_MXC_INT_SSI2 30 +#define MX51_MXC_INT_UART1 31 +#define MX51_MXC_INT_UART2 32 +#define MX51_MXC_INT_UART3 33 +#define MX51_MXC_INT_RESV34 34 +#define MX51_MXC_INT_RESV35 35 +#define MX51_MXC_INT_CSPI1 36 +#define MX51_MXC_INT_CSPI2 37 +#define MX51_MXC_INT_CSPI 38 +#define MX51_MXC_INT_GPT 39 +#define MX51_MXC_INT_EPIT1 40 +#define MX51_MXC_INT_EPIT2 41 +#define MX51_MXC_INT_GPIO1_INT7 42 +#define MX51_MXC_INT_GPIO1_INT6 43 +#define MX51_MXC_INT_GPIO1_INT5 44 +#define MX51_MXC_INT_GPIO1_INT4 45 +#define MX51_MXC_INT_GPIO1_INT3 46 +#define MX51_MXC_INT_GPIO1_INT2 47 +#define MX51_MXC_INT_GPIO1_INT1 48 +#define MX51_MXC_INT_GPIO1_INT0 49 +#define MX51_MXC_INT_GPIO1_LOW 50 +#define MX51_MXC_INT_GPIO1_HIGH 51 +#define MX51_MXC_INT_GPIO2_LOW 52 +#define MX51_MXC_INT_GPIO2_HIGH 53 +#define MX51_MXC_INT_GPIO3_LOW 54 +#define MX51_MXC_INT_GPIO3_HIGH 55 +#define MX51_MXC_INT_GPIO4_LOW 56 +#define MX51_MXC_INT_GPIO4_HIGH 57 +#define MX51_MXC_INT_WDOG1 58 +#define MX51_MXC_INT_WDOG2 59 +#define MX51_MXC_INT_KPP 60 +#define MX51_MXC_INT_PWM1 61 +#define MX51_MXC_INT_I2C1 62 +#define MX51_MXC_INT_I2C2 63 +#define MX51_MXC_INT_HS_I2C 64 +#define MX51_MXC_INT_RESV65 65 +#define MX51_MXC_INT_RESV66 66 +#define MX51_MXC_INT_SIM_IPB 67 +#define MX51_MXC_INT_SIM_DAT 68 +#define MX51_MXC_INT_IIM 69 +#define MX51_MXC_INT_ATA 70 +#define MX51_MXC_INT_CCM1 71 +#define MX51_MXC_INT_CCM2 72 +#define MX51_MXC_INT_GPC1 73 +#define MX51_MXC_INT_GPC2 74 +#define MX51_MXC_INT_SRC 75 +#define MX51_MXC_INT_NM 76 +#define MX51_MXC_INT_PMU 77 +#define MX51_MXC_INT_CTI_IRQ 78 +#define MX51_MXC_INT_CTI1_TG0 79 +#define MX51_MXC_INT_CTI1_TG1 80 +#define MX51_MXC_INT_MCG_ERR 81 +#define MX51_MXC_INT_MCG_TMR 82 +#define MX51_MXC_INT_MCG_FUNC 83 +#define MX51_MXC_INT_GPU2_IRQ 84 +#define MX51_MXC_INT_GPU2_BUSY 85 +#define MX51_MXC_INT_RESV86 86 +#define MX51_MXC_INT_FEC 87 +#define MX51_MXC_INT_OWIRE 88 +#define MX51_MXC_INT_CTI1_TG2 89 +#define MX51_MXC_INT_SJC 90 +#define MX51_MXC_INT_SPDIF 91 +#define MX51_MXC_INT_TVE 92 +#define MX51_MXC_INT_FIRI 93 +#define MX51_MXC_INT_PWM2 94 +#define MX51_MXC_INT_SLIM_EXP 95 +#define MX51_MXC_INT_SSI3 96 +#define MX51_MXC_INT_EMI_BOOT 97 +#define MX51_MXC_INT_CTI1_TG3 98 +#define MX51_MXC_INT_SMC_RX 99 +#define MX51_MXC_INT_VPU_IDLE 100 +#define MX51_MXC_INT_EMI_NFC 101 +#define MX51_MXC_INT_GPU_IDLE 102 /* silicon revisions specific to i.MX51 */ -#define MX51_CHIP_REV_1_0 0x10 -#define MX51_CHIP_REV_1_1 0x11 -#define MX51_CHIP_REV_1_2 0x12 -#define MX51_CHIP_REV_1_3 0x13 -#define MX51_CHIP_REV_2_0 0x20 -#define MX51_CHIP_REV_2_1 0x21 -#define MX51_CHIP_REV_2_2 0x22 -#define MX51_CHIP_REV_2_3 0x23 -#define MX51_CHIP_REV_3_0 0x30 -#define MX51_CHIP_REV_3_1 0x31 -#define MX51_CHIP_REV_3_2 0x32 +#define MX51_CHIP_REV_1_0 0x10 +#define MX51_CHIP_REV_1_1 0x11 +#define MX51_CHIP_REV_1_2 0x12 +#define MX51_CHIP_REV_1_3 0x13 +#define MX51_CHIP_REV_2_0 0x20 +#define MX51_CHIP_REV_2_1 0x21 +#define MX51_CHIP_REV_2_2 0x22 +#define MX51_CHIP_REV_2_3 0x23 +#define MX51_CHIP_REV_3_0 0x30 +#define MX51_CHIP_REV_3_1 0x31 +#define MX51_CHIP_REV_3_2 0x32 + +/* Mandatory defines used globally */ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) + extern int mx51_revision(void); #endif -/* tape-out 1 defines */ -#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000 - -#endif /* ifndef __MACH_MX51_H__ */ +#endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/trunk/arch/arm/plat-tcc/Kconfig b/trunk/arch/arm/plat-tcc/Kconfig deleted file mode 100644 index 1bf499570f42..000000000000 --- a/trunk/arch/arm/plat-tcc/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -if ARCH_TCC_926 - -menu "Telechips ARM926-based CPUs" - -choice - prompt "Telechips CPU type:" - default ARCH_TCC8K - -config ARCH_TCC8K - bool TCC8000 - select USB_ARCH_HAS_OHCI - help - Support for Telechips TCC8000 systems - -endchoice - -source "arch/arm/mach-tcc8k/Kconfig" - -endmenu -endif diff --git a/trunk/arch/arm/plat-tcc/Makefile b/trunk/arch/arm/plat-tcc/Makefile deleted file mode 100644 index eceabc869b8f..000000000000 --- a/trunk/arch/arm/plat-tcc/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# "Telechips Platform Common Modules" - -obj-y := clock.o system.o diff --git a/trunk/arch/arm/plat-tcc/clock.c b/trunk/arch/arm/plat-tcc/clock.c deleted file mode 100644 index f3ced10d5271..000000000000 --- a/trunk/arch/arm/plat-tcc/clock.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Clock framework for Telechips SoCs - * Based on arch/arm/plat-mxc/clock.c - * - * Copyright (C) 2004 - 2005 Nokia corporation - * Written by Tuukka Tikkanen - * Modified for omap shared clock framework by Tony Lindgren - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2010 Hans J. Koch, hjk@linutronix.de - * - * Licensed under the terms of the GPL v2. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -static DEFINE_MUTEX(clocks_mutex); - -/*------------------------------------------------------------------------- - * Standard clock functions defined in include/linux/clk.h - *-------------------------------------------------------------------------*/ - -static void __clk_disable(struct clk *clk) -{ - BUG_ON(clk->refcount == 0); - - if (!(--clk->refcount) && clk->disable) { - /* Unconditionally disable the clock in hardware */ - clk->disable(clk); - /* recursively disable parents */ - if (clk->parent) - __clk_disable(clk->parent); - } -} - -static int __clk_enable(struct clk *clk) -{ - int ret = 0; - - if (clk->refcount++ == 0 && clk->enable) { - if (clk->parent) - ret = __clk_enable(clk->parent); - if (ret) - return ret; - else - return clk->enable(clk); - } - - return 0; -} - -/* This function increments the reference count on the clock and enables the - * clock if not already enabled. The parent clock tree is recursively enabled - */ -int clk_enable(struct clk *clk) -{ - int ret = 0; - - if (!clk) - return -EINVAL; - - mutex_lock(&clocks_mutex); - ret = __clk_enable(clk); - mutex_unlock(&clocks_mutex); - - return ret; -} -EXPORT_SYMBOL_GPL(clk_enable); - -/* This function decrements the reference count on the clock and disables - * the clock when reference count is 0. The parent clock tree is - * recursively disabled - */ -void clk_disable(struct clk *clk) -{ - if (!clk) - return; - - mutex_lock(&clocks_mutex); - __clk_disable(clk); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL_GPL(clk_disable); - -/* Retrieve the *current* clock rate. If the clock itself - * does not provide a special calculation routine, ask - * its parent and so on, until one is able to return - * a valid clock rate - */ -unsigned long clk_get_rate(struct clk *clk) -{ - if (!clk) - return 0UL; - - if (clk->get_rate) - return clk->get_rate(clk); - - return clk_get_rate(clk->parent); -} -EXPORT_SYMBOL_GPL(clk_get_rate); - -/* Round the requested clock rate to the nearest supported - * rate that is less than or equal to the requested rate. - * This is dependent on the clock's current parent. - */ -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (!clk) - return 0; - if (!clk->round_rate) - return 0; - - return clk->round_rate(clk, rate); -} -EXPORT_SYMBOL_GPL(clk_round_rate); - -/* Set the clock to the requested clock rate. The rate must - * match a supported rate exactly based on what clk_round_rate returns - */ -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - if (!clk) - return ret; - if (!clk->set_rate || !rate) - return ret; - - mutex_lock(&clocks_mutex); - ret = clk->set_rate(clk, rate); - mutex_unlock(&clocks_mutex); - - return ret; -} -EXPORT_SYMBOL_GPL(clk_set_rate); - -/* Set the clock's parent to another clock source */ -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - struct clk *old; - int ret = -EINVAL; - - if (!clk) - return ret; - if (!clk->set_parent || !parent) - return ret; - - mutex_lock(&clocks_mutex); - old = clk->parent; - if (clk->refcount) - __clk_enable(parent); - ret = clk->set_parent(clk, parent); - if (ret) - old = parent; - if (clk->refcount) - __clk_disable(old); - mutex_unlock(&clocks_mutex); - - return ret; -} -EXPORT_SYMBOL_GPL(clk_set_parent); - -/* Retrieve the clock's parent clock source */ -struct clk *clk_get_parent(struct clk *clk) -{ - if (!clk) - return NULL; - - return clk->parent; -} -EXPORT_SYMBOL_GPL(clk_get_parent); diff --git a/trunk/arch/arm/plat-tcc/include/mach/clkdev.h b/trunk/arch/arm/plat-tcc/include/mach/clkdev.h deleted file mode 100644 index 04b37a89801c..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_MACH_CLKDEV_H -#define __ASM_MACH_CLKDEV_H - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/trunk/arch/arm/plat-tcc/include/mach/clock.h b/trunk/arch/arm/plat-tcc/include/mach/clock.h deleted file mode 100644 index a12f58ad71a8..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/clock.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Low level clock header file for Telechips TCC architecture - * (C) 2010 Hans J. Koch - * - * Licensed under the GPL v2. - */ - -#ifndef __ASM_ARCH_TCC_CLOCK_H__ -#define __ASM_ARCH_TCC_CLOCK_H__ - -#ifndef __ASSEMBLY__ - -struct clk { - struct clk *parent; - /* id number of a root clock, 0 for normal clocks */ - int root_id; - /* Reference count of clock enable/disable */ - int refcount; - /* Address of associated BCLKCTRx register. Must be set. */ - void __iomem *bclkctr; - /* Bit position for BCLKCTRx. Must be set. */ - int bclk_shift; - /* Address of ACLKxxx register, if any. */ - void __iomem *aclkreg; - /* get the current clock rate (always a fresh value) */ - unsigned long (*get_rate) (struct clk *); - /* Function ptr to set the clock to a new rate. The rate must match a - supported rate returned from round_rate. Leave blank if clock is not - programmable */ - int (*set_rate) (struct clk *, unsigned long); - /* Function ptr to round the requested clock rate to the nearest - supported rate that is less than or equal to the requested rate. */ - unsigned long (*round_rate) (struct clk *, unsigned long); - /* Function ptr to enable the clock. Leave blank if clock can not - be gated. */ - int (*enable) (struct clk *); - /* Function ptr to disable the clock. Leave blank if clock can not - be gated. */ - void (*disable) (struct clk *); - /* Function ptr to set the parent clock of the clock. */ - int (*set_parent) (struct clk *, struct clk *); -}; - -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_MXC_CLOCK_H__ */ diff --git a/trunk/arch/arm/plat-tcc/include/mach/debug-macro.S b/trunk/arch/arm/plat-tcc/include/mach/debug-macro.S deleted file mode 100644 index 97537845df64..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/debug-macro.S +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 1994-1999 Russell King - * Copyright (C) 2008-2009 Telechips - * Copyright (C) 2009 Hans J. Koch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - - .macro addruart,rx,tmp - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #0x90000000 @ physical base address - movne \rx, #0xF1000000 @ virtual base - orr \rx, \rx, #0x00007000 @ UART0 - .endm - - .macro senduart,rd,rx - strb \rd, [\rx, #0x44] - .endm - - .macro waituart,rd,rx - .endm - - .macro busyuart,rd,rx -1001: - ldr \rd, [\rx, #0x14] - tst \rd, #0x20 - - beq 1001b - .endm diff --git a/trunk/arch/arm/plat-tcc/include/mach/entry-macro.S b/trunk/arch/arm/plat-tcc/include/mach/entry-macro.S deleted file mode 100644 index 748f401e4b6d..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/entry-macro.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * include/asm-arm/arch-tcc83x/entry-macro.S - * - * Author : - * Created: June 10, 2008 - * Description: Low-level IRQ helper macros for Telechips-based platforms - * - * Copyright (C) 2008-2009 Telechips - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - ldr \base, =0xF2003000 @ base address of PIC registers - - @@ read MREQ register of PIC0 - - mov \irqnr, #0 - ldr \irqstat, [\base, #0x00000014 ] @ lower 32 interrupts - cmp \irqstat, #0 - bne 1001f - - @@ read MREQ register of PIC1 - - ldr \irqstat, [\base, #0x00000094] @ upper 32 interrupts - cmp \irqstat, #0 - beq 1002f - mov \irqnr, #0x20 - -1001: - movs \tmp, \irqstat, lsl #16 - movne \irqstat, \tmp - addeq \irqnr, \irqnr, #16 - - movs \tmp, \irqstat, lsl #8 - movne \irqstat, \tmp - addeq \irqnr, \irqnr, #8 - - movs \tmp, \irqstat, lsl #4 - movne \irqstat, \tmp - addeq \irqnr, \irqnr, #4 - - movs \tmp, \irqstat, lsl #2 - movne \irqstat, \tmp - addeq \irqnr, \irqnr, #2 - - movs \tmp, \irqstat, lsl #1 - addeq \irqnr, \irqnr, #1 - orrs \base, \base, #1 -1002: - @@ exit here, Z flag unset if IRQ - - .endm diff --git a/trunk/arch/arm/plat-tcc/include/mach/hardware.h b/trunk/arch/arm/plat-tcc/include/mach/hardware.h deleted file mode 100644 index e70d126ccaf3..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/hardware.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Author: RidgeRun, Inc. Greg Lonnon - * Reorganized for Linux-2.6 by Tony Lindgren - * and Dirk Behme - * Rewritten by: - * Description: Hardware definitions for TCC8300 processors and boards - * - * Copyright (C) 2001 RidgeRun, Inc. - * Copyright (C) 2008-2009 Telechips - * - * Modifications for mainline (C) 2009 Hans J. Koch - * - * Licensed under the terms of the GNU Pulic License version 2. - */ - -#ifndef __ASM_ARCH_TCC_HARDWARE_H -#define __ASM_ARCH_TCC_HARDWARE_H - -#include -#ifndef __ASSEMBLER__ -#include -#endif -#include - -/* - * ---------------------------------------------------------------------------- - * Clocks - * ---------------------------------------------------------------------------- - */ -#define CLKGEN_REG_BASE 0xfffece00 -#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) -#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) -#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) -#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) -#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) -#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) -#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) -#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) - -/* DPLL control registers */ -#define DPLL_CTL 0xfffecf00 - -#endif /* __ASM_ARCH_TCC_HARDWARE_H */ diff --git a/trunk/arch/arm/plat-tcc/include/mach/io.h b/trunk/arch/arm/plat-tcc/include/mach/io.h deleted file mode 100644 index 3e911d3ea0f1..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/io.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * IO definitions for TCC8000 processors and boards - * - * Copyright (C) 1997-1999 Russell King - * Copyright (C) 2008-2009 Telechips - * Copyright (C) 2010 Hans J. Koch - * - * Licensed under the terms of the GNU Public License version 2. - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... - */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#endif diff --git a/trunk/arch/arm/plat-tcc/include/mach/irqs.h b/trunk/arch/arm/plat-tcc/include/mach/irqs.h deleted file mode 100644 index da863894d498..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/irqs.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * IRQ definitions for TCC8xxx - * - * Copyright (C) 2008-2009 Telechips - * Copyright (C) 2009 Hans J. Koch - * - * Licensed under the terms of the GPL v2. - * - */ - -#ifndef __ASM_ARCH_TCC_IRQS_H -#define __ASM_ARCH_TCC_IRQS_H - -#define NR_IRQS 64 - -/* PIC0 interrupts */ -#define INT_ADMA1 0 -#define INT_BDMA 1 -#define INT_ADMA0 2 -#define INT_GDMA1 3 -#define INT_I2S0RX 4 -#define INT_I2S0TX 5 -#define INT_TC 6 -#define INT_UART0 7 -#define INT_USBD 8 -#define INT_SPI0TX 9 -#define INT_UDMA 10 -#define INT_LIRQ 11 -#define INT_GDMA2 12 -#define INT_GDMA0 13 -#define INT_TC32 14 -#define INT_LCD 15 -#define INT_ADC 16 -#define INT_I2C 17 -#define INT_RTCP 18 -#define INT_RTCA 19 -#define INT_NFC 20 -#define INT_SD0 21 -#define INT_GSB0 22 -#define INT_PK 23 -#define INT_USBH0 24 -#define INT_USBH1 25 -#define INT_G2D 26 -#define INT_ECC 27 -#define INT_SPI0RX 28 -#define INT_UART1 29 -#define INT_MSCL 30 -#define INT_GSB1 31 -/* PIC1 interrupts */ -#define INT_E0 32 -#define INT_E1 33 -#define INT_E2 34 -#define INT_E3 35 -#define INT_E4 36 -#define INT_E5 37 -#define INT_E6 38 -#define INT_E7 39 -#define INT_UART2 40 -#define INT_UART3 41 -#define INT_SPI1TX 42 -#define INT_SPI1RX 43 -#define INT_GSB2 44 -#define INT_SPDIF 45 -#define INT_CDIF 46 -#define INT_VBON 47 -#define INT_VBOFF 48 -#define INT_SD1 49 -#define INT_UART4 50 -#define INT_GDMA3 51 -#define INT_I2S1RX 52 -#define INT_I2S1TX 53 -#define INT_CAN0 54 -#define INT_CAN1 55 -#define INT_GSB3 56 -#define INT_KRST 57 -#define INT_UNUSED 58 -#define INT_SD0D3 59 -#define INT_SD1D3 60 -#define INT_GPS0 61 -#define INT_GPS1 62 -#define INT_GPS2 63 - -#endif /* ASM_ARCH_TCC_IRQS_H */ diff --git a/trunk/arch/arm/plat-tcc/include/mach/memory.h b/trunk/arch/arm/plat-tcc/include/mach/memory.h deleted file mode 100644 index cd91ba8a670b..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/memory.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2008-2009 Telechips - * Copyright (C) 2010 Hans J. Koch - * - * Licensed under the terms of the GPL v2. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PHYS_OFFSET UL(0x20000000) - -#endif diff --git a/trunk/arch/arm/plat-tcc/include/mach/system.h b/trunk/arch/arm/plat-tcc/include/mach/system.h deleted file mode 100644 index 909e6035d843..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/system.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Author: - * Created: June 10, 2008 - * Description: LINUX SYSTEM FUNCTIONS for TCC83x - * - * Copyright (C) 2008-2009 Telechips - * - * Licensed under the terms of the GPL v2. - * - */ - -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H -#include - -#include -#include - -extern void plat_tcc_reboot(void); - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - plat_tcc_reboot(); -} - -#endif diff --git a/trunk/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/trunk/arch/arm/plat-tcc/include/mach/tcc8k-regs.h deleted file mode 100644 index 1d9428295332..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/tcc8k-regs.h +++ /dev/null @@ -1,807 +0,0 @@ -/* - * Telechips TCC8000 register definitions - * - * (C) 2009 Hans J. Koch - * - * Licensed under the terms of the GPLv2. - */ - -#ifndef TCC8K_REGS_H -#define TCC8K_REGS_H - -#include - -#define EXT_SDRAM_BASE 0x20000000 -#define INT_SRAM_BASE 0x30000000 -#define INT_SRAM_SIZE SZ_32K -#define CS0_BASE 0x40000000 -#define CS1_BASE 0x50000000 -#define CS1_SIZE SZ_64K -#define CS2_BASE 0x60000000 -#define CS3_BASE 0x70000000 -#define AHB_PERI_BASE 0x80000000 -#define AHB_PERI_SIZE SZ_64K -#define APB0_PERI_BASE 0x90000000 -#define APB0_PERI_SIZE SZ_128K -#define APB1_PERI_BASE 0x98000000 -#define APB1_PERI_SIZE SZ_128K -#define DATA_TCM_BASE 0xa0000000 -#define DATA_TCM_SIZE SZ_8K -#define EXT_MEM_CTRL_BASE 0xf0000000 -#define EXT_MEM_CTRL_SIZE SZ_4K - -#define CS1_BASE_VIRT (void __iomem *)0xf7000000 -#define AHB_PERI_BASE_VIRT (void __iomem *)0xf4000000 -#define APB0_PERI_BASE_VIRT (void __iomem *)0xf1000000 -#define APB1_PERI_BASE_VIRT (void __iomem *)0xf2000000 -#define EXT_MEM_CTRL_BASE_VIRT (void __iomem *)0xf3000000 -#define INT_SRAM_BASE_VIRT (void __iomem *)0xf5000000 -#define DATA_TCM_BASE_VIRT (void __iomem *)0xf6000000 - -#define __REG(x) (*((volatile u32 *)(x))) - -/* USB Device Controller Registers */ -#define UDC_BASE (AHB_PERI_BASE_VIRT + 0x8000) -#define UDC_BASE_PHYS (AHB_PERI_BASE + 0x8000) - -#define UDC_IR_OFFS 0x00 -#define UDC_EIR_OFFS 0x04 -#define UDC_EIER_OFFS 0x08 -#define UDC_FAR_OFFS 0x0c -#define UDC_FNR_OFFS 0x10 -#define UDC_EDR_OFFS 0x14 -#define UDC_RT_OFFS 0x18 -#define UDC_SSR_OFFS 0x1c -#define UDC_SCR_OFFS 0x20 -#define UDC_EP0SR_OFFS 0x24 -#define UDC_EP0CR_OFFS 0x28 - -#define UDC_ESR_OFFS 0x2c -#define UDC_ECR_OFFS 0x30 -#define UDC_BRCR_OFFS 0x34 -#define UDC_BWCR_OFFS 0x38 -#define UDC_MPR_OFFS 0x3c -#define UDC_DCR_OFFS 0x40 -#define UDC_DTCR_OFFS 0x44 -#define UDC_DFCR_OFFS 0x48 -#define UDC_DTTCR1_OFFS 0x4c -#define UDC_DTTCR2_OFFS 0x50 -#define UDC_ESR2_OFFS 0x54 - -#define UDC_SCR2_OFFS 0x58 -#define UDC_EP0BUF_OFFS 0x60 -#define UDC_EP1BUF_OFFS 0x64 -#define UDC_EP2BUF_OFFS 0x68 -#define UDC_EP3BUF_OFFS 0x6c -#define UDC_PLICR_OFFS 0xa0 -#define UDC_PCR_OFFS 0xa4 - -#define UDC_UPCR0_OFFS 0xc8 -#define UDC_UPCR1_OFFS 0xcc -#define UDC_UPCR2_OFFS 0xd0 -#define UDC_UPCR3_OFFS 0xd4 - -/* Bits in UDC_EIR */ -#define UDC_EIR_EP0I (1 << 0) -#define UDC_EIR_EP1I (1 << 1) -#define UDC_EIR_EP2I (1 << 2) -#define UDC_EIR_EP3I (1 << 3) -#define UDC_EIR_EPI_MASK 0x0f - -/* Bits in UDC_EIER */ -#define UDC_EIER_EP0IE (1 << 0) -#define UDC_EIER_EP1IE (1 << 1) -#define UDC_EIER_EP2IE (1 << 2) -#define UDC_EIER_EP3IE (1 << 3) - -/* Bits in UDC_FNR */ -#define UDC_FNR_FN_MASK 0x7ff -#define UDC_FNR_SM (1 << 13) -#define UDC_FNR_FTL (1 << 14) - -/* Bits in UDC_SSR */ -#define UDC_SSR_HFRES (1 << 0) -#define UDC_SSR_HFSUSP (1 << 1) -#define UDC_SSR_HFRM (1 << 2) -#define UDC_SSR_SDE (1 << 3) -#define UDC_SSR_HSP (1 << 4) -#define UDC_SSR_DM (1 << 5) -#define UDC_SSR_DP (1 << 6) -#define UDC_SSR_TBM (1 << 7) -#define UDC_SSR_VBON (1 << 8) -#define UDC_SSR_VBOFF (1 << 9) -#define UDC_SSR_EOERR (1 << 10) -#define UDC_SSR_DCERR (1 << 11) -#define UDC_SSR_TCERR (1 << 12) -#define UDC_SSR_BSERR (1 << 13) -#define UDC_SSR_TMERR (1 << 14) -#define UDC_SSR_BAERR (1 << 15) - -/* Bits in UDC_SCR */ -#define UDC_SCR_HRESE (1 << 0) -#define UDC_SCR_HSSPE (1 << 1) -#define UDC_SCR_RRDE (1 << 5) -#define UDC_SCR_SPDEN (1 << 6) -#define UDC_SCR_DIEN (1 << 12) - -/* Bits in UDC_EP0SR */ -#define UDC_EP0SR_RSR (1 << 0) -#define UDC_EP0SR_TST (1 << 1) -#define UDC_EP0SR_SHT (1 << 4) -#define UDC_EP0SR_LWO (1 << 6) - -/* Bits in UDC_EP0CR */ -#define UDC_EP0CR_ESS (1 << 1) - -/* Bits in UDC_ESR */ -#define UDC_ESR_RPS (1 << 0) -#define UDC_ESR_TPS (1 << 1) -#define UDC_ESR_LWO (1 << 4) -#define UDC_ESR_FFS (1 << 6) - -/* Bits in UDC_ECR */ -#define UDC_ECR_ESS (1 << 1) -#define UDC_ECR_CDP (1 << 2) - -#define UDC_ECR_FLUSH (1 << 6) -#define UDC_ECR_DUEN (1 << 7) - -/* Bits in UDC_UPCR0 */ -#define UDC_UPCR0_VBD (1 << 1) -#define UDC_UPCR0_VBDS (1 << 6) -#define UDC_UPCR0_RCD_12 (0x0 << 9) -#define UDC_UPCR0_RCD_24 (0x1 << 9) -#define UDC_UPCR0_RCD_48 (0x2 << 9) -#define UDC_UPCR0_RCS_EXT (0x1 << 11) -#define UDC_UPCR0_RCS_XTAL (0x0 << 11) - -/* Bits in UDC_UPCR1 */ -#define UDC_UPCR1_CDT(x) ((x) << 0) -#define UDC_UPCR1_OTGT(x) ((x) << 3) -#define UDC_UPCR1_SQRXT(x) ((x) << 8) -#define UDC_UPCR1_TXFSLST(x) ((x) << 12) - -/* Bits in UDC_UPCR2 */ -#define UDC_UPCR2_TP (1 << 0) -#define UDC_UPCR2_TXRT(x) ((x) << 2) -#define UDC_UPCR2_TXVRT(x) ((x) << 5) -#define UDC_UPCR2_OPMODE(x) ((x) << 9) -#define UDC_UPCR2_XCVRSEL(x) ((x) << 12) -#define UDC_UPCR2_TM (1 << 14) - -/* USB Host Controller registers */ -#define USBH0_BASE (AHB_PERI_BASE_VIRT + 0xb000) -#define USBH1_BASE (AHB_PERI_BASE_VIRT + 0xb800) - -#define OHCI_INT_ENABLE_OFFS 0x10 - -#define RH_DESCRIPTOR_A_OFFS 0x48 -#define RH_DESCRIPTOR_B_OFFS 0x4c - -#define USBHTCFG0_OFFS 0x100 -#define USBHHCFG0_OFFS 0x104 -#define USBHHCFG1_OFFS 0x104 - -/* DMA controller registers */ -#define DMAC0_BASE (AHB_PERI_BASE + 0x4000) -#define DMAC1_BASE (AHB_PERI_BASE + 0xa000) -#define DMAC2_BASE (AHB_PERI_BASE + 0x4800) -#define DMAC3_BASE (AHB_PERI_BASE + 0xa800) - -#define DMAC_CH_OFFSET(ch) (ch * 0x30) - -#define ST_SADR_OFFS 0x00 -#define SPARAM_OFFS 0x04 -#define C_SADR_OFFS 0x0c -#define ST_DADR_OFFS 0x10 -#define DPARAM_OFFS 0x14 -#define C_DADR_OFFS 0x1c -#define HCOUNT_OFFS 0x20 -#define CHCTRL_OFFS 0x24 -#define RPTCTRL_OFFS 0x28 -#define EXTREQ_A_OFFS 0x2c - -/* Bits in CHCTRL register */ -#define CHCTRL_EN (1 << 0) - -#define CHCTRL_IEN (1 << 2) -#define CHCTRL_FLAG (1 << 3) -#define CHCTRL_WSIZE8 (0 << 4) -#define CHCTRL_WSIZE16 (1 << 4) -#define CHCTRL_WSIZE32 (2 << 4) - -#define CHCTRL_BSIZE1 (0 << 6) -#define CHCTRL_BSIZE2 (1 << 6) -#define CHCTRL_BSIZE4 (2 << 6) -#define CHCTRL_BSIZE8 (3 << 6) - -#define CHCTRL_TYPE_SINGLE_E (0 << 8) -#define CHCTRL_TYPE_HW (1 << 8) -#define CHCTRL_TYPE_SW (2 << 8) -#define CHCTRL_TYPE_SINGLE_L (3 << 8) - -#define CHCTRL_BST (1 << 10) - -/* Use DMA controller 0, channel 2 for USB */ -#define USB_DMA_BASE (DMAC0_BASE + DMAC_CH_OFFSET(2)) - -/* NAND flash controller registers */ -#define NFC_BASE (AHB_PERI_BASE_VIRT + 0xd000) -#define NFC_BASE_PHYS (AHB_PERI_BASE + 0xd000) - -#define NFC_CMD_OFFS 0x00 -#define NFC_LADDR_OFFS 0x04 -#define NFC_BADDR_OFFS 0x08 -#define NFC_SADDR_OFFS 0x0c -#define NFC_WDATA_OFFS 0x10 -#define NFC_LDATA_OFFS 0x20 -#define NFC_SDATA_OFFS 0x40 -#define NFC_CTRL_OFFS 0x50 -#define NFC_PSTART_OFFS 0x54 -#define NFC_RSTART_OFFS 0x58 -#define NFC_DSIZE_OFFS 0x5c -#define NFC_IREQ_OFFS 0x60 -#define NFC_RST_OFFS 0x64 -#define NFC_CTRL1_OFFS 0x68 -#define NFC_MDATA_OFFS 0x70 - -#define NFC_WDATA_PHYS_ADDR (NFC_BASE_PHYS + NFC_WDATA_OFFS) - -/* Bits in NFC_CTRL */ -#define NFC_CTRL_BHLD_MASK (0xf << 0) -#define NFC_CTRL_BPW_MASK (0xf << 4) -#define NFC_CTRL_BSTP_MASK (0xf << 8) -#define NFC_CTRL_CADDR_MASK (0x7 << 12) -#define NFC_CTRL_CADDR_1 (0x0 << 12) -#define NFC_CTRL_CADDR_2 (0x1 << 12) -#define NFC_CTRL_CADDR_3 (0x2 << 12) -#define NFC_CTRL_CADDR_4 (0x3 << 12) -#define NFC_CTRL_CADDR_5 (0x4 << 12) -#define NFC_CTRL_MSK (1 << 15) -#define NFC_CTRL_PSIZE256 (0 << 16) -#define NFC_CTRL_PSIZE512 (1 << 16) -#define NFC_CTRL_PSIZE1024 (2 << 16) -#define NFC_CTRL_PSIZE2048 (3 << 16) -#define NFC_CTRL_PSIZE4096 (4 << 16) -#define NFC_CTRL_PSIZE_MASK (7 << 16) -#define NFC_CTRL_BSIZE1 (0 << 19) -#define NFC_CTRL_BSIZE2 (1 << 19) -#define NFC_CTRL_BSIZE4 (2 << 19) -#define NFC_CTRL_BSIZE8 (3 << 19) -#define NFC_CTRL_BSIZE_MASK (3 << 19) -#define NFC_CTRL_RDY (1 << 21) -#define NFC_CTRL_CS0SEL (1 << 22) -#define NFC_CTRL_CS1SEL (1 << 23) -#define NFC_CTRL_CS2SEL (1 << 24) -#define NFC_CTRL_CS3SEL (1 << 25) -#define NFC_CTRL_CSMASK (0xf << 22) -#define NFC_CTRL_BW (1 << 26) -#define NFC_CTRL_FS (1 << 27) -#define NFC_CTRL_DEN (1 << 28) -#define NFC_CTRL_READ_IEN (1 << 29) -#define NFC_CTRL_PROG_IEN (1 << 30) -#define NFC_CTRL_RDY_IEN (1 << 31) - -/* Bits in NFC_IREQ */ -#define NFC_IREQ_IRQ0 (1 << 0) -#define NFC_IREQ_IRQ1 (1 << 1) -#define NFC_IREQ_IRQ2 (1 << 2) - -#define NFC_IREQ_FLAG0 (1 << 4) -#define NFC_IREQ_FLAG1 (1 << 5) -#define NFC_IREQ_FLAG2 (1 << 6) - -/* MMC controller registers */ -#define MMC0_BASE (AHB_PERI_BASE_VIRT + 0xe000) -#define MMC1_BASE (AHB_PERI_BASE_VIRT + 0xe800) - -/* UART base addresses */ - -#define UART0_BASE (APB0_PERI_BASE_VIRT + 0x07000) -#define UART0_BASE_PHYS (APB0_PERI_BASE + 0x07000) -#define UART1_BASE (APB0_PERI_BASE_VIRT + 0x08000) -#define UART1_BASE_PHYS (APB0_PERI_BASE + 0x08000) -#define UART2_BASE (APB0_PERI_BASE_VIRT + 0x09000) -#define UART2_BASE_PHYS (APB0_PERI_BASE + 0x09000) -#define UART3_BASE (APB0_PERI_BASE_VIRT + 0x0a000) -#define UART3_BASE_PHYS (APB0_PERI_BASE + 0x0a000) -#define UART4_BASE (APB0_PERI_BASE_VIRT + 0x15000) -#define UART4_BASE_PHYS (APB0_PERI_BASE + 0x15000) - -#define UART_BASE UART0_BASE -#define UART_BASE_PHYS UART0_BASE_PHYS - -/* ECC controller */ -#define ECC_CTR_BASE (APB0_PERI_BASE_VIRT + 0xd000) - -#define ECC_CTRL_OFFS 0x00 -#define ECC_BASE_OFFS 0x04 -#define ECC_MASK_OFFS 0x08 -#define ECC_CLEAR_OFFS 0x0c -#define ECC4_0_OFFS 0x10 -#define ECC4_1_OFFS 0x14 - -#define ECC_EADDR0_OFFS 0x50 - -#define ECC_ERRNUM_OFFS 0x90 -#define ECC_IREQ_OFFS 0x94 - -/* Bits in ECC_CTRL */ -#define ECC_CTRL_ECC4_DIEN (1 << 28) -#define ECC_CTRL_ECC8_DIEN (1 << 29) -#define ECC_CTRL_ECC12_DIEN (1 << 30) -#define ECC_CTRL_ECC_DISABLE 0x0 -#define ECC_CTRL_ECC_SLC_ENC 0x8 -#define ECC_CTRL_ECC_SLC_DEC 0x9 -#define ECC_CTRL_ECC4_ENC 0xa -#define ECC_CTRL_ECC4_DEC 0xb -#define ECC_CTRL_ECC8_ENC 0xc -#define ECC_CTRL_ECC8_DEC 0xd -#define ECC_CTRL_ECC12_ENC 0xe -#define ECC_CTRL_ECC12_DEC 0xf - -/* Bits in ECC_IREQ */ -#define ECC_IREQ_E4DI (1 << 4) - -#define ECC_IREQ_E4DF (1 << 20) -#define ECC_IREQ_E4EF (1 << 21) - -/* Interrupt controller */ - -#define PIC0_BASE (APB1_PERI_BASE_VIRT + 0x3000) -#define PIC0_BASE_PHYS (APB1_PERI_BASE + 0x3000) - -#define PIC0_IEN_OFFS 0x00 -#define PIC0_CREQ_OFFS 0x04 -#define PIC0_IREQ_OFFS 0x08 -#define PIC0_IRQSEL_OFFS 0x0c -#define PIC0_SRC_OFFS 0x10 -#define PIC0_MREQ_OFFS 0x14 -#define PIC0_TSTREQ_OFFS 0x18 -#define PIC0_POL_OFFS 0x1c -#define PIC0_IRQ_OFFS 0x20 -#define PIC0_FIQ_OFFS 0x24 -#define PIC0_MIRQ_OFFS 0x28 -#define PIC0_MFIQ_OFFS 0x2c -#define PIC0_TMODE_OFFS 0x30 -#define PIC0_SYNC_OFFS 0x34 -#define PIC0_WKUP_OFFS 0x38 -#define PIC0_TMODEA_OFFS 0x3c -#define PIC0_INTOEN_OFFS 0x40 -#define PIC0_MEN0_OFFS 0x44 -#define PIC0_MEN_OFFS 0x48 - -#define PIC0_IEN __REG(PIC0_BASE + PIC0_IEN_OFFS) -#define PIC0_IEN_PHYS __REG(PIC0_BASE_PHYS + PIC0_IEN_OFFS) -#define PIC0_CREQ __REG(PIC0_BASE + PIC0_CREQ_OFFS) -#define PIC0_CREQ_PHYS __REG(PIC0_BASE_PHYS + PIC0_CREQ_OFFS) -#define PIC0_IREQ __REG(PIC0_BASE + PIC0_IREQ_OFFS) -#define PIC0_IRQSEL __REG(PIC0_BASE + PIC0_IRQSEL_OFFS) -#define PIC0_IRQSEL_PHYS __REG(PIC0_BASE_PHYS + PIC0_IRQSEL_OFFS) -#define PIC0_SRC __REG(PIC0_BASE + PIC0_SRC_OFFS) -#define PIC0_MREQ __REG(PIC0_BASE + PIC0_MREQ_OFFS) -#define PIC0_TSTREQ __REG(PIC0_BASE + PIC0_TSTREQ_OFFS) -#define PIC0_POL __REG(PIC0_BASE + PIC0_POL_OFFS) -#define PIC0_IRQ __REG(PIC0_BASE + PIC0_IRQ_OFFS) -#define PIC0_FIQ __REG(PIC0_BASE + PIC0_FIQ_OFFS) -#define PIC0_MIRQ __REG(PIC0_BASE + PIC0_MIRQ_OFFS) -#define PIC0_MFIQ __REG(PIC0_BASE + PIC0_MFIQ_OFFS) -#define PIC0_TMODE __REG(PIC0_BASE + PIC0_TMODE_OFFS) -#define PIC0_TMODE_PHYS __REG(PIC0_BASE_PHYS + PIC0_TMODE_OFFS) -#define PIC0_SYNC __REG(PIC0_BASE + PIC0_SYNC_OFFS) -#define PIC0_WKUP __REG(PIC0_BASE + PIC0_WKUP_OFFS) -#define PIC0_TMODEA __REG(PIC0_BASE + PIC0_TMODEA_OFFS) -#define PIC0_INTOEN __REG(PIC0_BASE + PIC0_INTOEN_OFFS) -#define PIC0_MEN0 __REG(PIC0_BASE + PIC0_MEN0_OFFS) -#define PIC0_MEN __REG(PIC0_BASE + PIC0_MEN_OFFS) - -#define PIC1_BASE (APB1_PERI_BASE_VIRT + 0x3080) - -#define PIC1_IEN_OFFS 0x00 -#define PIC1_CREQ_OFFS 0x04 -#define PIC1_IREQ_OFFS 0x08 -#define PIC1_IRQSEL_OFFS 0x0c -#define PIC1_SRC_OFFS 0x10 -#define PIC1_MREQ_OFFS 0x14 -#define PIC1_TSTREQ_OFFS 0x18 -#define PIC1_POL_OFFS 0x1c -#define PIC1_IRQ_OFFS 0x20 -#define PIC1_FIQ_OFFS 0x24 -#define PIC1_MIRQ_OFFS 0x28 -#define PIC1_MFIQ_OFFS 0x2c -#define PIC1_TMODE_OFFS 0x30 -#define PIC1_SYNC_OFFS 0x34 -#define PIC1_WKUP_OFFS 0x38 -#define PIC1_TMODEA_OFFS 0x3c -#define PIC1_INTOEN_OFFS 0x40 -#define PIC1_MEN1_OFFS 0x44 -#define PIC1_MEN_OFFS 0x48 - -#define PIC1_IEN __REG(PIC1_BASE + PIC1_IEN_OFFS) -#define PIC1_CREQ __REG(PIC1_BASE + PIC1_CREQ_OFFS) -#define PIC1_IREQ __REG(PIC1_BASE + PIC1_IREQ_OFFS) -#define PIC1_IRQSEL __REG(PIC1_BASE + PIC1_IRQSEL_OFFS) -#define PIC1_SRC __REG(PIC1_BASE + PIC1_SRC_OFFS) -#define PIC1_MREQ __REG(PIC1_BASE + PIC1_MREQ_OFFS) -#define PIC1_TSTREQ __REG(PIC1_BASE + PIC1_TSTREQ_OFFS) -#define PIC1_POL __REG(PIC1_BASE + PIC1_POL_OFFS) -#define PIC1_IRQ __REG(PIC1_BASE + PIC1_IRQ_OFFS) -#define PIC1_FIQ __REG(PIC1_BASE + PIC1_FIQ_OFFS) -#define PIC1_MIRQ __REG(PIC1_BASE + PIC1_MIRQ_OFFS) -#define PIC1_MFIQ __REG(PIC1_BASE + PIC1_MFIQ_OFFS) -#define PIC1_TMODE __REG(PIC1_BASE + PIC1_TMODE_OFFS) -#define PIC1_SYNC __REG(PIC1_BASE + PIC1_SYNC_OFFS) -#define PIC1_WKUP __REG(PIC1_BASE + PIC1_WKUP_OFFS) -#define PIC1_TMODEA __REG(PIC1_BASE + PIC1_TMODEA_OFFS) -#define PIC1_INTOEN __REG(PIC1_BASE + PIC1_INTOEN_OFFS) -#define PIC1_MEN1 __REG(PIC1_BASE + PIC1_MEN1_OFFS) -#define PIC1_MEN __REG(PIC1_BASE + PIC1_MEN_OFFS) - -/* Timer registers */ -#define TIMER_BASE (APB1_PERI_BASE_VIRT + 0x4000) -#define TIMER_BASE_PHYS (APB1_PERI_BASE + 0x4000) - -#define TWDCFG_OFFS 0x70 - -#define TC32EN_OFFS 0x80 -#define TC32LDV_OFFS 0x84 -#define TC32CMP0_OFFS 0x88 -#define TC32CMP1_OFFS 0x8c -#define TC32PCNT_OFFS 0x90 -#define TC32MCNT_OFFS 0x94 -#define TC32IRQ_OFFS 0x98 - -/* Bits in TC32EN */ -#define TC32EN_PRESCALE_MASK 0x00ffffff -#define TC32EN_ENABLE (1 << 24) -#define TC32EN_LOADZERO (1 << 25) -#define TC32EN_STOPMODE (1 << 26) -#define TC32EN_LDM0 (1 << 28) -#define TC32EN_LDM1 (1 << 29) - -/* Bits in TC32IRQ */ -#define TC32IRQ_MSTAT_MASK 0x0000001f -#define TC32IRQ_RSTAT_MASK (0x1f << 8) -#define TC32IRQ_IRQEN0 (1 << 16) -#define TC32IRQ_IRQEN1 (1 << 17) -#define TC32IRQ_IRQEN2 (1 << 18) -#define TC32IRQ_IRQEN3 (1 << 19) -#define TC32IRQ_IRQEN4 (1 << 20) -#define TC32IRQ_RSYNC (1 << 30) -#define TC32IRQ_IRQCLR (1 << 31) - -/* GPIO registers */ -#define GPIOPD_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOPD_DAT_OFFS 0x00 -#define GPIOPD_DOE_OFFS 0x04 -#define GPIOPD_FS0_OFFS 0x08 -#define GPIOPD_FS1_OFFS 0x0c -#define GPIOPD_FS2_OFFS 0x10 -#define GPIOPD_RPU_OFFS 0x30 -#define GPIOPD_RPD_OFFS 0x34 -#define GPIOPD_DV0_OFFS 0x38 -#define GPIOPD_DV1_OFFS 0x3c - -#define GPIOPS_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOPS_DAT_OFFS 0x40 -#define GPIOPS_DOE_OFFS 0x44 -#define GPIOPS_FS0_OFFS 0x48 -#define GPIOPS_FS1_OFFS 0x4c -#define GPIOPS_FS2_OFFS 0x50 -#define GPIOPS_FS3_OFFS 0x54 -#define GPIOPS_RPU_OFFS 0x70 -#define GPIOPS_RPD_OFFS 0x74 -#define GPIOPS_DV0_OFFS 0x78 -#define GPIOPS_DV1_OFFS 0x7c - -#define GPIOPS_FS1_SDH0_BITS 0x000000ff -#define GPIOPS_FS1_SDH1_BITS 0x0000ff00 - -#define GPIOPU_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOPU_DAT_OFFS 0x80 -#define GPIOPU_DOE_OFFS 0x84 -#define GPIOPU_FS0_OFFS 0x88 -#define GPIOPU_FS1_OFFS 0x8c -#define GPIOPU_FS2_OFFS 0x90 -#define GPIOPU_RPU_OFFS 0xb0 -#define GPIOPU_RPD_OFFS 0xb4 -#define GPIOPU_DV0_OFFS 0xb8 -#define GPIOPU_DV1_OFFS 0xbc - -#define GPIOPU_FS0_TXD0 (1 << 0) -#define GPIOPU_FS0_RXD0 (1 << 1) -#define GPIOPU_FS0_CTS0 (1 << 2) -#define GPIOPU_FS0_RTS0 (1 << 3) -#define GPIOPU_FS0_TXD1 (1 << 4) -#define GPIOPU_FS0_RXD1 (1 << 5) -#define GPIOPU_FS0_CTS1 (1 << 6) -#define GPIOPU_FS0_RTS1 (1 << 7) -#define GPIOPU_FS0_TXD2 (1 << 8) -#define GPIOPU_FS0_RXD2 (1 << 9) -#define GPIOPU_FS0_CTS2 (1 << 10) -#define GPIOPU_FS0_RTS2 (1 << 11) -#define GPIOPU_FS0_TXD3 (1 << 12) -#define GPIOPU_FS0_RXD3 (1 << 13) -#define GPIOPU_FS0_CTS3 (1 << 14) -#define GPIOPU_FS0_RTS3 (1 << 15) -#define GPIOPU_FS0_TXD4 (1 << 16) -#define GPIOPU_FS0_RXD4 (1 << 17) -#define GPIOPU_FS0_CTS4 (1 << 18) -#define GPIOPU_FS0_RTS4 (1 << 19) - -#define GPIOFC_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOFC_DAT_OFFS 0xc0 -#define GPIOFC_DOE_OFFS 0xc4 -#define GPIOFC_FS0_OFFS 0xc8 -#define GPIOFC_FS1_OFFS 0xcc -#define GPIOFC_FS2_OFFS 0xd0 -#define GPIOFC_FS3_OFFS 0xd4 -#define GPIOFC_RPU_OFFS 0xf0 -#define GPIOFC_RPD_OFFS 0xf4 -#define GPIOFC_DV0_OFFS 0xf8 -#define GPIOFC_DV1_OFFS 0xfc - -#define GPIOFD_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOFD_DAT_OFFS 0x100 -#define GPIOFD_DOE_OFFS 0x104 -#define GPIOFD_FS0_OFFS 0x108 -#define GPIOFD_FS1_OFFS 0x10c -#define GPIOFD_FS2_OFFS 0x110 -#define GPIOFD_RPU_OFFS 0x130 -#define GPIOFD_RPD_OFFS 0x134 -#define GPIOFD_DV0_OFFS 0x138 -#define GPIOFD_DV1_OFFS 0x13c - -#define GPIOLC_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOLC_DAT_OFFS 0x140 -#define GPIOLC_DOE_OFFS 0x144 -#define GPIOLC_FS0_OFFS 0x148 -#define GPIOLC_FS1_OFFS 0x14c -#define GPIOLC_RPU_OFFS 0x170 -#define GPIOLC_RPD_OFFS 0x174 -#define GPIOLC_DV0_OFFS 0x178 -#define GPIOLC_DV1_OFFS 0x17c - -#define GPIOLD_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOLD_DAT_OFFS 0x180 -#define GPIOLD_DOE_OFFS 0x184 -#define GPIOLD_FS0_OFFS 0x188 -#define GPIOLD_FS1_OFFS 0x18c -#define GPIOLD_FS2_OFFS 0x190 -#define GPIOLD_RPU_OFFS 0x1b0 -#define GPIOLD_RPD_OFFS 0x1b4 -#define GPIOLD_DV0_OFFS 0x1b8 -#define GPIOLD_DV1_OFFS 0x1bc - -#define GPIOAD_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOAD_DAT_OFFS 0x1c0 -#define GPIOAD_DOE_OFFS 0x1c4 -#define GPIOAD_FS0_OFFS 0x1c8 -#define GPIOAD_RPU_OFFS 0x1f0 -#define GPIOAD_RPD_OFFS 0x1f4 -#define GPIOAD_DV0_OFFS 0x1f8 -#define GPIOAD_DV1_OFFS 0x1fc - -#define GPIOXC_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOXC_DAT_OFFS 0x200 -#define GPIOXC_DOE_OFFS 0x204 -#define GPIOXC_FS0_OFFS 0x208 -#define GPIOXC_RPU_OFFS 0x230 -#define GPIOXC_RPD_OFFS 0x234 -#define GPIOXC_DV0_OFFS 0x238 -#define GPIOXC_DV1_OFFS 0x23c - -#define GPIOXC_FS0 __REG(GPIOXC_BASE + GPIOXC_FS0_OFFS) - -#define GPIOXC_FS0_CS0 (1 << 26) -#define GPIOXC_FS0_CS1 (1 << 27) - -#define GPIOXD_BASE (APB1_PERI_BASE_VIRT + 0x5000) - -#define GPIOXD_DAT_OFFS 0x240 -#define GPIOXD_FS0_OFFS 0x248 -#define GPIOXD_RPU_OFFS 0x270 -#define GPIOXD_RPD_OFFS 0x274 -#define GPIOXD_DV0_OFFS 0x278 -#define GPIOXD_DV1_OFFS 0x27c - -#define GPIOPK_BASE (APB1_PERI_BASE_VIRT + 0x1c000) - -#define GPIOPK_RST_OFFS 0x008 -#define GPIOPK_DAT_OFFS 0x100 -#define GPIOPK_DOE_OFFS 0x104 -#define GPIOPK_FS0_OFFS 0x108 -#define GPIOPK_FS1_OFFS 0x10c -#define GPIOPK_FS2_OFFS 0x110 -#define GPIOPK_IRQST_OFFS 0x210 -#define GPIOPK_IRQEN_OFFS 0x214 -#define GPIOPK_IRQPOL_OFFS 0x218 -#define GPIOPK_IRQTM0_OFFS 0x21c -#define GPIOPK_IRQTM1_OFFS 0x220 -#define GPIOPK_CTL_OFFS 0x22c - -#define PMGPIO_BASE (APB1_PERI_BASE_VIRT + 0x10000) -#define BACKUP_RAM_BASE PMGPIO_BASE - -#define PMGPIO_DAT_OFFS 0x800 -#define PMGPIO_DOE_OFFS 0x804 -#define PMGPIO_FS0_OFFS 0x808 -#define PMGPIO_RPU_OFFS 0x810 -#define PMGPIO_RPD_OFFS 0x814 -#define PMGPIO_DV0_OFFS 0x818 -#define PMGPIO_DV1_OFFS 0x81c -#define PMGPIO_EE0_OFFS 0x820 -#define PMGPIO_EE1_OFFS 0x824 -#define PMGPIO_CTL_OFFS 0x828 -#define PMGPIO_DI_OFFS 0x82c -#define PMGPIO_STR_OFFS 0x830 -#define PMGPIO_STF_OFFS 0x834 -#define PMGPIO_POL_OFFS 0x838 -#define PMGPIO_APB_OFFS 0x800 - -/* Clock controller registers */ -#define CKC_BASE ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000)) - -#define CLKCTRL_OFFS 0x00 -#define PLL0CFG_OFFS 0x04 -#define PLL1CFG_OFFS 0x08 -#define CLKDIVC0_OFFS 0x0c - -#define BCLKCTR0_OFFS 0x14 -#define SWRESET0_OFFS 0x18 - -#define BCLKCTR1_OFFS 0x60 -#define SWRESET1_OFFS 0x64 -#define PWDCTL_OFFS 0x68 -#define PLL2CFG_OFFS 0x6c -#define CLKDIVC1_OFFS 0x70 - -#define ACLKREF_OFFS 0x80 -#define ACLKI2C_OFFS 0x84 -#define ACLKSPI0_OFFS 0x88 -#define ACLKSPI1_OFFS 0x8c -#define ACLKUART0_OFFS 0x90 -#define ACLKUART1_OFFS 0x94 -#define ACLKUART2_OFFS 0x98 -#define ACLKUART3_OFFS 0x9c -#define ACLKUART4_OFFS 0xa0 -#define ACLKTCT_OFFS 0xa4 -#define ACLKTCX_OFFS 0xa8 -#define ACLKTCZ_OFFS 0xac -#define ACLKADC_OFFS 0xb0 -#define ACLKDAI0_OFFS 0xb4 -#define ACLKDAI1_OFFS 0xb8 -#define ACLKLCD_OFFS 0xbc -#define ACLKSPDIF_OFFS 0xc0 -#define ACLKUSBH_OFFS 0xc4 -#define ACLKSDH0_OFFS 0xc8 -#define ACLKSDH1_OFFS 0xcc -#define ACLKC3DEC_OFFS 0xd0 -#define ACLKEXT_OFFS 0xd4 -#define ACLKCAN0_OFFS 0xd8 -#define ACLKCAN1_OFFS 0xdc -#define ACLKGSB0_OFFS 0xe0 -#define ACLKGSB1_OFFS 0xe4 -#define ACLKGSB2_OFFS 0xe8 -#define ACLKGSB3_OFFS 0xec - -#define PLLxCFG_PD (1 << 31) - -/* CLKCTRL bits */ -#define CLKCTRL_XE (1 << 31) - -/* CLKDIVCx bits */ -#define CLKDIVC0_XTE (1 << 7) -#define CLKDIVC0_XE (1 << 15) -#define CLKDIVC0_P1E (1 << 23) -#define CLKDIVC0_P0E (1 << 31) - -#define CLKDIVC1_P2E (1 << 7) - -/* BCLKCTR0 clock bits */ -#define BCLKCTR0_USBD (1 << 4) -#define BCLKCTR0_ECC (1 << 9) -#define BCLKCTR0_USBH0 (1 << 11) -#define BCLKCTR0_NFC (1 << 16) - -/* BCLKCTR1 clock bits */ -#define BCLKCTR1_USBH1 (1 << 20) - -/* SWRESET0 bits */ -#define SWRESET0_USBD (1 << 4) -#define SWRESET0_USBH0 (1 << 11) - -/* SWRESET1 bits */ -#define SWRESET1_USBH1 (1 << 20) - -/* System clock sources. - * Note: These are the clock sources that serve as parents for - * all other clocks. They have no parents themselves. - * - * These values are used for struct clk->root_id. All clocks - * that are not system clock sources have this value set to - * CLK_SRC_NOROOT. - * The values for system clocks start with CLK_SRC_PLL0 == 0 - * because this gives us exactly the values needed for the lower - * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is - * defined as -1 to not disturb the order. - */ -enum root_clks { - CLK_SRC_NOROOT = -1, - CLK_SRC_PLL0 = 0, - CLK_SRC_PLL1, - CLK_SRC_PLL0DIV, - CLK_SRC_PLL1DIV, - CLK_SRC_XI, - CLK_SRC_XIDIV, - CLK_SRC_XTI, - CLK_SRC_XTIDIV, - CLK_SRC_PLL2, - CLK_SRC_PLL2DIV, - CLK_SRC_PK0, - CLK_SRC_PK1, - CLK_SRC_PK2, - CLK_SRC_PK3, - CLK_SRC_PK4, - CLK_SRC_48MHZ -}; - -#define CLK_SRC_MASK 0xf - -/* Bits in ACLK* registers */ -#define ACLK_EN (1 << 28) -#define ACLK_SEL_SHIFT 24 -#define ACLK_SEL_MASK 0x0f000000 -#define ACLK_DIV_MASK 0x00000fff - -/* System configuration registers */ - -#define SCFG_BASE (APB1_PERI_BASE_VIRT + 0x13000) - -#define BMI_OFFS 0x00 -#define AHBCON0_OFFS 0x04 -#define APBPWE_OFFS 0x08 -#define DTCMWAIT_OFFS 0x0c -#define ECCSEL_OFFS 0x10 -#define AHBCON1_OFFS 0x14 -#define SDHCFG_OFFS 0x18 -#define REMAP_OFFS 0x20 -#define LCDSIAE_OFFS 0x24 -#define XMCCFG_OFFS 0xe0 -#define IMCCFG_OFFS 0xe4 - -/* Values for ECCSEL */ -#define ECCSEL_EXTMEM 0x0 -#define ECCSEL_DTCM 0x1 -#define ECCSEL_INT_SRAM 0x2 -#define ECCSEL_AHB 0x3 - -/* Bits in XMCCFG */ -#define XMCCFG_NFCE (1 << 1) -#define XMCCFG_FDXD (1 << 2) - -/* External memory controller registers */ - -#define EMC_BASE EXT_MEM_CTRL_BASE - -#define SDCFG_OFFS 0x00 -#define SDFSM_OFFS 0x04 -#define MCFG_OFFS 0x08 - -#define CSCFG0_OFFS 0x10 -#define CSCFG1_OFFS 0x14 -#define CSCFG2_OFFS 0x18 -#define CSCFG3_OFFS 0x1c - -#define MCFG_SDEN (1 << 4) - -#endif /* TCC8K_REGS_H */ diff --git a/trunk/arch/arm/plat-tcc/include/mach/timex.h b/trunk/arch/arm/plat-tcc/include/mach/timex.h deleted file mode 100644 index 057acbe651d9..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/timex.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * A definition needed by arch core code. - * - */ -#define CLOCK_TICK_RATE (HZ * 100000UL) diff --git a/trunk/arch/arm/plat-tcc/include/mach/uncompress.h b/trunk/arch/arm/plat-tcc/include/mach/uncompress.h deleted file mode 100644 index 7a3e33a27a30..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/uncompress.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2009 Hans J. Koch - * - * This file is licensed under the terms of the GPL version 2. - */ - -#include -#include - -#include - -unsigned int system_rev; - -#define ID_MASK 0x7fff - -static void putc(int c) -{ - u32 *uart_lsr = (u32 *)(UART_BASE_PHYS + (UART_LSR << 2)); - u32 *uart_tx = (u32 *)(UART_BASE_PHYS + (UART_TX << 2)); - - while (!(*uart_lsr & UART_LSR_THRE)) - barrier(); - *uart_tx = c; -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/trunk/arch/arm/plat-tcc/include/mach/vmalloc.h b/trunk/arch/arm/plat-tcc/include/mach/vmalloc.h deleted file mode 100644 index 99414d9c2b94..000000000000 --- a/trunk/arch/arm/plat-tcc/include/mach/vmalloc.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Author: - * Created: June 10, 2008 - * - * Copyright (C) 2000 Russell King. - * Copyright (C) 2008-2009 Telechips - * - * Licensed under the terms of the GPL v2. - */ -#define VMALLOC_END 0xf0000000UL diff --git a/trunk/arch/arm/plat-tcc/system.c b/trunk/arch/arm/plat-tcc/system.c deleted file mode 100644 index cc208fae3e7a..000000000000 --- a/trunk/arch/arm/plat-tcc/system.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * System functions for Telechips TCCxxxx SoCs - * - * Copyright (C) Hans J. Koch - * - * Licensed under the terms of the GPL v2. - * - */ - -#include - -#include - -/* System reboot */ -void plat_tcc_reboot(void) -{ - /* Make sure clocks are on */ - __raw_writel(0xffffffff, CKC_BASE + BCLKCTR0_OFFS); - - /* Enable watchdog reset */ - __raw_writel(0x49, TIMER_BASE + TWDCFG_OFFS); - /* Wait for reset */ - while(1) - ; -} diff --git a/trunk/arch/avr32/Kconfig b/trunk/arch/avr32/Kconfig index 9ac87255a03a..f51572772e21 100644 --- a/trunk/arch/avr32/Kconfig +++ b/trunk/arch/avr32/Kconfig @@ -90,7 +90,6 @@ config PLATFORM_AT32AP select ARCH_REQUIRE_GPIOLIB select GENERIC_ALLOCATOR select HAVE_FB_ATMEL - select HAVE_NET_MACB # # CPU types diff --git a/trunk/drivers/leds/Kconfig b/trunk/drivers/leds/Kconfig index cc2a88d5192f..e4112622e5a2 100644 --- a/trunk/drivers/leds/Kconfig +++ b/trunk/drivers/leds/Kconfig @@ -304,22 +304,13 @@ config LEDS_MC13783 config LEDS_NS2 tristate "LED support for Network Space v2 GPIO LEDs" - depends on MACH_NETSPACE_V2 || MACH_INETSPACE_V2 || MACH_NETSPACE_MAX_V2 || D2NET_V2 + depends on MACH_NETSPACE_V2 || MACH_INETSPACE_V2 || MACH_NETSPACE_MAX_V2 default y help This option enable support for the dual-GPIO LED found on the Network Space v2 board (and parents). This include Internet Space v2, Network Space (Max) v2 and d2 Network v2 boards. -config LEDS_NETXBIG - tristate "LED support for Big Network series LEDs" - depends on MACH_NET2BIG_V2 || MACH_NET5BIG_V2 - default y - help - This option enable support for LEDs found on the LaCie 2Big - and 5Big Network v2 boards. The LEDs are wired to a CPLD and are - controlled through a GPIO extension bus. - config LEDS_TRIGGERS bool "LED Trigger support" help diff --git a/trunk/drivers/leds/Makefile b/trunk/drivers/leds/Makefile index 9c96db40ef6d..7d6b95831f8e 100644 --- a/trunk/drivers/leds/Makefile +++ b/trunk/drivers/leds/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o obj-$(CONFIG_LEDS_NS2) += leds-ns2.o -obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o # LED SPI Drivers obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o diff --git a/trunk/drivers/leds/leds-netxbig.c b/trunk/drivers/leds/leds-netxbig.c deleted file mode 100644 index f2e51c134399..000000000000 --- a/trunk/drivers/leds/leds-netxbig.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * leds-netxbig.c - Driver for the 2Big and 5Big Network series LEDs - * - * Copyright (C) 2010 LaCie - * - * Author: Simon Guinot - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * GPIO extension bus. - */ - -static DEFINE_SPINLOCK(gpio_ext_lock); - -static void gpio_ext_set_addr(struct netxbig_gpio_ext *gpio_ext, int addr) -{ - int pin; - - for (pin = 0; pin < gpio_ext->num_addr; pin++) - gpio_set_value(gpio_ext->addr[pin], (addr >> pin) & 1); -} - -static void gpio_ext_set_data(struct netxbig_gpio_ext *gpio_ext, int data) -{ - int pin; - - for (pin = 0; pin < gpio_ext->num_data; pin++) - gpio_set_value(gpio_ext->data[pin], (data >> pin) & 1); -} - -static void gpio_ext_enable_select(struct netxbig_gpio_ext *gpio_ext) -{ - /* Enable select is done on the raising edge. */ - gpio_set_value(gpio_ext->enable, 0); - gpio_set_value(gpio_ext->enable, 1); -} - -static void gpio_ext_set_value(struct netxbig_gpio_ext *gpio_ext, - int addr, int value) -{ - unsigned long flags; - - spin_lock_irqsave(&gpio_ext_lock, flags); - gpio_ext_set_addr(gpio_ext, addr); - gpio_ext_set_data(gpio_ext, value); - gpio_ext_enable_select(gpio_ext); - spin_unlock_irqrestore(&gpio_ext_lock, flags); -} - -static int __devinit gpio_ext_init(struct netxbig_gpio_ext *gpio_ext) -{ - int err; - int i; - - if (unlikely(!gpio_ext)) - return -EINVAL; - - /* Configure address GPIOs. */ - for (i = 0; i < gpio_ext->num_addr; i++) { - err = gpio_request(gpio_ext->addr[i], "GPIO extension addr"); - if (err) - goto err_free_addr; - err = gpio_direction_output(gpio_ext->addr[i], 0); - if (err) { - gpio_free(gpio_ext->addr[i]); - goto err_free_addr; - } - } - /* Configure data GPIOs. */ - for (i = 0; i < gpio_ext->num_data; i++) { - err = gpio_request(gpio_ext->data[i], "GPIO extension data"); - if (err) - goto err_free_data; - err = gpio_direction_output(gpio_ext->data[i], 0); - if (err) { - gpio_free(gpio_ext->data[i]); - goto err_free_data; - } - } - /* Configure "enable select" GPIO. */ - err = gpio_request(gpio_ext->enable, "GPIO extension enable"); - if (err) - goto err_free_data; - err = gpio_direction_output(gpio_ext->enable, 0); - if (err) { - gpio_free(gpio_ext->enable); - goto err_free_data; - } - - return 0; - -err_free_data: - for (i = i - 1; i >= 0; i--) - gpio_free(gpio_ext->data[i]); - i = gpio_ext->num_addr; -err_free_addr: - for (i = i - 1; i >= 0; i--) - gpio_free(gpio_ext->addr[i]); - - return err; -} - -static void __devexit gpio_ext_free(struct netxbig_gpio_ext *gpio_ext) -{ - int i; - - gpio_free(gpio_ext->enable); - for (i = gpio_ext->num_addr - 1; i >= 0; i--) - gpio_free(gpio_ext->addr[i]); - for (i = gpio_ext->num_data - 1; i >= 0; i--) - gpio_free(gpio_ext->data[i]); -} - -/* - * Class LED driver. - */ - -struct netxbig_led_data { - struct netxbig_gpio_ext *gpio_ext; - struct led_classdev cdev; - int mode_addr; - int *mode_val; - int bright_addr; - int bright_max; - struct netxbig_led_timer *timer; - int num_timer; - enum netxbig_led_mode mode; - int sata; - spinlock_t lock; -}; - -static int netxbig_led_get_timer_mode(enum netxbig_led_mode *mode, - unsigned long delay_on, - unsigned long delay_off, - struct netxbig_led_timer *timer, - int num_timer) -{ - int i; - - for (i = 0; i < num_timer; i++) { - if (timer[i].delay_on == delay_on && - timer[i].delay_off == delay_off) { - *mode = timer[i].mode; - return 0; - } - } - return -EINVAL; -} - -static int netxbig_led_blink_set(struct led_classdev *led_cdev, - unsigned long *delay_on, - unsigned long *delay_off) -{ - struct netxbig_led_data *led_dat = - container_of(led_cdev, struct netxbig_led_data, cdev); - enum netxbig_led_mode mode; - int mode_val; - int ret; - - /* Look for a LED mode with the requested timer frequency. */ - ret = netxbig_led_get_timer_mode(&mode, *delay_on, *delay_off, - led_dat->timer, led_dat->num_timer); - if (ret < 0) - return ret; - - mode_val = led_dat->mode_val[mode]; - if (mode_val == NETXBIG_LED_INVALID_MODE) - return -EINVAL; - - spin_lock_irq(&led_dat->lock); - - gpio_ext_set_value(led_dat->gpio_ext, led_dat->mode_addr, mode_val); - led_dat->mode = mode; - - spin_unlock_irq(&led_dat->lock); - - return 0; -} - -static void netxbig_led_set(struct led_classdev *led_cdev, - enum led_brightness value) -{ - struct netxbig_led_data *led_dat = - container_of(led_cdev, struct netxbig_led_data, cdev); - enum netxbig_led_mode mode; - int mode_val, bright_val; - int set_brightness = 1; - unsigned long flags; - - spin_lock_irqsave(&led_dat->lock, flags); - - if (value == LED_OFF) { - mode = NETXBIG_LED_OFF; - set_brightness = 0; - } else { - if (led_dat->sata) - mode = NETXBIG_LED_SATA; - else if (led_dat->mode == NETXBIG_LED_OFF) - mode = NETXBIG_LED_ON; - else /* Keep 'timer' mode. */ - mode = led_dat->mode; - } - mode_val = led_dat->mode_val[mode]; - - gpio_ext_set_value(led_dat->gpio_ext, led_dat->mode_addr, mode_val); - led_dat->mode = mode; - /* - * Note that the brightness register is shared between all the - * SATA LEDs. So, change the brightness setting for a single - * SATA LED will affect all the others. - */ - if (set_brightness) { - bright_val = DIV_ROUND_UP(value * led_dat->bright_max, - LED_FULL); - gpio_ext_set_value(led_dat->gpio_ext, - led_dat->bright_addr, bright_val); - } - - spin_unlock_irqrestore(&led_dat->lock, flags); -} - -static ssize_t netxbig_led_sata_store(struct device *dev, - struct device_attribute *attr, - const char *buff, size_t count) -{ - struct led_classdev *led_cdev = dev_get_drvdata(dev); - struct netxbig_led_data *led_dat = - container_of(led_cdev, struct netxbig_led_data, cdev); - unsigned long enable; - enum netxbig_led_mode mode; - int mode_val; - int ret; - - ret = strict_strtoul(buff, 10, &enable); - if (ret < 0) - return ret; - - enable = !!enable; - - spin_lock_irq(&led_dat->lock); - - if (led_dat->sata == enable) { - ret = count; - goto exit_unlock; - } - - if (led_dat->mode != NETXBIG_LED_ON && - led_dat->mode != NETXBIG_LED_SATA) - mode = led_dat->mode; /* Keep modes 'off' and 'timer'. */ - else if (enable) - mode = NETXBIG_LED_SATA; - else - mode = NETXBIG_LED_ON; - - mode_val = led_dat->mode_val[mode]; - if (mode_val == NETXBIG_LED_INVALID_MODE) { - ret = -EINVAL; - goto exit_unlock; - } - - gpio_ext_set_value(led_dat->gpio_ext, led_dat->mode_addr, mode_val); - led_dat->mode = mode; - led_dat->sata = enable; - - ret = count; - -exit_unlock: - spin_unlock_irq(&led_dat->lock); - - return ret; -} - -static ssize_t netxbig_led_sata_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct led_classdev *led_cdev = dev_get_drvdata(dev); - struct netxbig_led_data *led_dat = - container_of(led_cdev, struct netxbig_led_data, cdev); - - return sprintf(buf, "%d\n", led_dat->sata); -} - -static DEVICE_ATTR(sata, 0644, netxbig_led_sata_show, netxbig_led_sata_store); - -static void __devexit delete_netxbig_led(struct netxbig_led_data *led_dat) -{ - if (led_dat->mode_val[NETXBIG_LED_SATA] != NETXBIG_LED_INVALID_MODE) - device_remove_file(led_dat->cdev.dev, &dev_attr_sata); - led_classdev_unregister(&led_dat->cdev); -} - -static int __devinit -create_netxbig_led(struct platform_device *pdev, - struct netxbig_led_data *led_dat, - const struct netxbig_led *template) -{ - struct netxbig_led_platform_data *pdata = pdev->dev.platform_data; - int ret; - - spin_lock_init(&led_dat->lock); - led_dat->gpio_ext = pdata->gpio_ext; - led_dat->cdev.name = template->name; - led_dat->cdev.default_trigger = template->default_trigger; - led_dat->cdev.blink_set = netxbig_led_blink_set; - led_dat->cdev.brightness_set = netxbig_led_set; - /* - * Because the GPIO extension bus don't allow to read registers - * value, there is no way to probe the LED initial state. - * So, the initial sysfs LED value for the "brightness" and "sata" - * attributes are inconsistent. - * - * Note that the initial LED state can't be reconfigured. - * The reason is that the LED behaviour must stay uniform during - * the whole boot process (bootloader+linux). - */ - led_dat->sata = 0; - led_dat->cdev.brightness = LED_OFF; - led_dat->cdev.flags |= LED_CORE_SUSPENDRESUME; - led_dat->mode_addr = template->mode_addr; - led_dat->mode_val = template->mode_val; - led_dat->bright_addr = template->bright_addr; - led_dat->bright_max = (1 << pdata->gpio_ext->num_data) - 1; - led_dat->timer = pdata->timer; - led_dat->num_timer = pdata->num_timer; - - ret = led_classdev_register(&pdev->dev, &led_dat->cdev); - if (ret < 0) - return ret; - - /* - * If available, expose the SATA activity blink capability through - * a "sata" sysfs attribute. - */ - if (led_dat->mode_val[NETXBIG_LED_SATA] != NETXBIG_LED_INVALID_MODE) { - ret = device_create_file(led_dat->cdev.dev, &dev_attr_sata); - if (ret) - led_classdev_unregister(&led_dat->cdev); - } - - return ret; -} - -static int __devinit netxbig_led_probe(struct platform_device *pdev) -{ - struct netxbig_led_platform_data *pdata = pdev->dev.platform_data; - struct netxbig_led_data *leds_data; - int i; - int ret; - - if (!pdata) - return -EINVAL; - - leds_data = kzalloc(sizeof(struct netxbig_led_data) * pdata->num_leds, - GFP_KERNEL); - if (!leds_data) - return -ENOMEM; - - ret = gpio_ext_init(pdata->gpio_ext); - if (ret < 0) - goto err_free_data; - - for (i = 0; i < pdata->num_leds; i++) { - ret = create_netxbig_led(pdev, &leds_data[i], &pdata->leds[i]); - if (ret < 0) - goto err_free_leds; - } - - platform_set_drvdata(pdev, leds_data); - - return 0; - -err_free_leds: - for (i = i - 1; i >= 0; i--) - delete_netxbig_led(&leds_data[i]); - - gpio_ext_free(pdata->gpio_ext); -err_free_data: - kfree(leds_data); - - return ret; -} - -static int __devexit netxbig_led_remove(struct platform_device *pdev) -{ - struct netxbig_led_platform_data *pdata = pdev->dev.platform_data; - struct netxbig_led_data *leds_data; - int i; - - leds_data = platform_get_drvdata(pdev); - - for (i = 0; i < pdata->num_leds; i++) - delete_netxbig_led(&leds_data[i]); - - gpio_ext_free(pdata->gpio_ext); - kfree(leds_data); - - return 0; -} - -static struct platform_driver netxbig_led_driver = { - .probe = netxbig_led_probe, - .remove = __devexit_p(netxbig_led_remove), - .driver = { - .name = "leds-netxbig", - .owner = THIS_MODULE, - }, -}; -MODULE_ALIAS("platform:leds-netxbig"); - -static int __init netxbig_led_init(void) -{ - return platform_driver_register(&netxbig_led_driver); -} - -static void __exit netxbig_led_exit(void) -{ - platform_driver_unregister(&netxbig_led_driver); -} - -module_init(netxbig_led_init); -module_exit(netxbig_led_exit); - -MODULE_AUTHOR("Simon Guinot "); -MODULE_DESCRIPTION("LED driver for LaCie xBig Network boards"); -MODULE_LICENSE("GPL"); diff --git a/trunk/drivers/leds/leds-ns2.c b/trunk/drivers/leds/leds-ns2.c index f77d48d0b3e4..350eb34f049c 100644 --- a/trunk/drivers/leds/leds-ns2.c +++ b/trunk/drivers/leds/leds-ns2.c @@ -141,12 +141,10 @@ static ssize_t ns2_led_sata_store(struct device *dev, struct device_attribute *attr, const char *buff, size_t count) { - struct led_classdev *led_cdev = dev_get_drvdata(dev); - struct ns2_led_data *led_dat = - container_of(led_cdev, struct ns2_led_data, cdev); int ret; unsigned long enable; enum ns2_led_modes mode; + struct ns2_led_data *led_dat = dev_get_drvdata(dev); ret = strict_strtoul(buff, 10, &enable); if (ret < 0) @@ -174,9 +172,7 @@ static ssize_t ns2_led_sata_store(struct device *dev, static ssize_t ns2_led_sata_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct led_classdev *led_cdev = dev_get_drvdata(dev); - struct ns2_led_data *led_dat = - container_of(led_cdev, struct ns2_led_data, cdev); + struct ns2_led_data *led_dat = dev_get_drvdata(dev); return sprintf(buf, "%d\n", led_dat->sata); } @@ -238,6 +234,7 @@ create_ns2_led(struct platform_device *pdev, struct ns2_led_data *led_dat, if (ret < 0) goto err_free_slow; + dev_set_drvdata(led_dat->cdev.dev, led_dat); ret = device_create_file(led_dat->cdev.dev, &dev_attr_sata); if (ret < 0) goto err_free_cdev; diff --git a/trunk/drivers/net/Kconfig b/trunk/drivers/net/Kconfig index 1c767ade7ef8..2cc81a54cbf3 100644 --- a/trunk/drivers/net/Kconfig +++ b/trunk/drivers/net/Kconfig @@ -2,9 +2,6 @@ # Network device configuration # -config HAVE_NET_MACB - bool - menuconfig NETDEVICES default y if UML depends on NET @@ -224,7 +221,7 @@ config MII config MACB tristate "Atmel MACB support" - depends on HAVE_NET_MACB + depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45 || ARCH_AT91CAP9 select PHYLIB help The Atmel MACB ethernet interface is found on many AT32 and AT91 diff --git a/trunk/drivers/spi/Kconfig b/trunk/drivers/spi/Kconfig index 7e631fa51098..91c2f4f3af10 100644 --- a/trunk/drivers/spi/Kconfig +++ b/trunk/drivers/spi/Kconfig @@ -143,26 +143,10 @@ config SPI_GPIO GPIO operations, you should be able to leverage that for better speed with a custom version of this driver; see the source code. -config SPI_IMX_VER_IMX1 - def_bool y if SOC_IMX1 - -config SPI_IMX_VER_0_0 - def_bool y if SOC_IMX21 || SOC_IMX27 - -config SPI_IMX_VER_0_4 - def_bool y if ARCH_MX31 - -config SPI_IMX_VER_0_7 - def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51 - -config SPI_IMX_VER_2_3 - def_bool y if ARCH_MX51 - config SPI_IMX tristate "Freescale i.MX SPI controllers" depends on ARCH_MXC select SPI_BITBANG - default m if IMX_HAVE_PLATFORM_SPI_IMX help This enables using the Freescale i.MX SPI controllers in master mode. diff --git a/trunk/drivers/spi/spi_imx.c b/trunk/drivers/spi/spi_imx.c index 55a38e2c6c13..7972e9077473 100644 --- a/trunk/drivers/spi/spi_imx.c +++ b/trunk/drivers/spi/spi_imx.c @@ -56,28 +56,7 @@ struct spi_imx_config { unsigned int speed_hz; unsigned int bpw; unsigned int mode; - u8 cs; -}; - -enum spi_imx_devtype { - SPI_IMX_VER_IMX1, - SPI_IMX_VER_0_0, - SPI_IMX_VER_0_4, - SPI_IMX_VER_0_5, - SPI_IMX_VER_0_7, - SPI_IMX_VER_2_3, - SPI_IMX_VER_AUTODETECT, -}; - -struct spi_imx_data; - -struct spi_imx_devtype_data { - void (*intctrl)(struct spi_imx_data *, int); - int (*config)(struct spi_imx_data *, struct spi_imx_config *); - void (*trigger)(struct spi_imx_data *); - int (*rx_available)(struct spi_imx_data *); - void (*reset)(struct spi_imx_data *); - unsigned int fifosize; + int cs; }; struct spi_imx_data { @@ -97,7 +76,11 @@ struct spi_imx_data { const void *tx_buf; unsigned int txfifo; /* number of words pushed in tx FIFO */ - struct spi_imx_devtype_data devtype_data; + /* SoC specific functions */ + void (*intctrl)(struct spi_imx_data *, int); + int (*config)(struct spi_imx_data *, struct spi_imx_config *); + void (*trigger)(struct spi_imx_data *); + int (*rx_available)(struct spi_imx_data *); }; #define MXC_SPI_BUF_RX(type) \ @@ -157,7 +140,7 @@ static unsigned int spi_imx_clkdiv_1(unsigned int fin, return max; } -/* MX1, MX31, MX35, MX51 CSPI */ +/* MX1, MX31, MX35 */ static unsigned int spi_imx_clkdiv_2(unsigned int fin, unsigned int fspi) { @@ -172,128 +155,6 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin, return 7; } -#define SPI_IMX2_3_CTRL 0x08 -#define SPI_IMX2_3_CTRL_ENABLE (1 << 0) -#define SPI_IMX2_3_CTRL_XCH (1 << 2) -#define SPI_IMX2_3_CTRL_MODE(cs) (1 << ((cs) + 4)) -#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8 -#define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12 -#define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18) -#define SPI_IMX2_3_CTRL_BL_OFFSET 20 - -#define SPI_IMX2_3_CONFIG 0x0c -#define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) -#define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) -#define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) -#define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) - -#define SPI_IMX2_3_INT 0x10 -#define SPI_IMX2_3_INT_TEEN (1 << 0) -#define SPI_IMX2_3_INT_RREN (1 << 3) - -#define SPI_IMX2_3_STAT 0x18 -#define SPI_IMX2_3_STAT_RR (1 << 3) - -/* MX51 eCSPI */ -static unsigned int spi_imx2_3_clkdiv(unsigned int fin, unsigned int fspi) -{ - /* - * there are two 4-bit dividers, the pre-divider divides by - * $pre, the post-divider by 2^$post - */ - unsigned int pre, post; - - if (unlikely(fspi > fin)) - return 0; - - post = fls(fin) - fls(fspi); - if (fin > fspi << post) - post++; - - /* now we have: (fin <= fspi << post) with post being minimal */ - - post = max(4U, post) - 4; - if (unlikely(post > 0xf)) { - pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", - __func__, fspi, fin); - return 0xff; - } - - pre = DIV_ROUND_UP(fin, fspi << post) - 1; - - pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", - __func__, fin, fspi, post, pre); - return (pre << SPI_IMX2_3_CTRL_PREDIV_OFFSET) | - (post << SPI_IMX2_3_CTRL_POSTDIV_OFFSET); -} - -static void __maybe_unused spi_imx2_3_intctrl(struct spi_imx_data *spi_imx, int enable) -{ - unsigned val = 0; - - if (enable & MXC_INT_TE) - val |= SPI_IMX2_3_INT_TEEN; - - if (enable & MXC_INT_RR) - val |= SPI_IMX2_3_INT_RREN; - - writel(val, spi_imx->base + SPI_IMX2_3_INT); -} - -static void __maybe_unused spi_imx2_3_trigger(struct spi_imx_data *spi_imx) -{ - u32 reg; - - reg = readl(spi_imx->base + SPI_IMX2_3_CTRL); - reg |= SPI_IMX2_3_CTRL_XCH; - writel(reg, spi_imx->base + SPI_IMX2_3_CTRL); -} - -static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx, - struct spi_imx_config *config) -{ - u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0; - - /* set master mode */ - ctrl |= SPI_IMX2_3_CTRL_MODE(config->cs); - - /* set clock speed */ - ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz); - - /* set chip select to use */ - ctrl |= SPI_IMX2_3_CTRL_CS(config->cs); - - ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET; - - cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs); - - if (config->mode & SPI_CPHA) - cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs); - - if (config->mode & SPI_CPOL) - cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs); - - if (config->mode & SPI_CS_HIGH) - cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs); - - writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL); - writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG); - - return 0; -} - -static int __maybe_unused spi_imx2_3_rx_available(struct spi_imx_data *spi_imx) -{ - return readl(spi_imx->base + SPI_IMX2_3_STAT) & SPI_IMX2_3_STAT_RR; -} - -static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx) -{ - /* drain receive buffer */ - while (spi_imx2_3_rx_available(spi_imx)) - readl(spi_imx->base + MXC_CSPIRXDATA); -} - #define MX31_INTREG_TEEN (1 << 0) #define MX31_INTREG_RREN (1 << 3) @@ -317,7 +178,7 @@ static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx) * the i.MX35 has a slightly different register layout for bits * we do not use here. */ -static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) +static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; @@ -329,7 +190,7 @@ static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable writel(val, spi_imx->base + MXC_CSPIINT); } -static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) +static void mx31_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; @@ -338,42 +199,20 @@ static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } -static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx, - struct spi_imx_config *config) -{ - unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; - int cs = spi_imx->chipselect[config->cs]; - - reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << - MX31_CSPICTRL_DR_SHIFT; - - reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; - - if (config->mode & SPI_CPHA) - reg |= MX31_CSPICTRL_PHA; - if (config->mode & SPI_CPOL) - reg |= MX31_CSPICTRL_POL; - if (config->mode & SPI_CS_HIGH) - reg |= MX31_CSPICTRL_SSPOL; - if (cs < 0) - reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT; - - writel(reg, spi_imx->base + MXC_CSPICTRL); - - return 0; -} - -static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx, +static int mx31_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) { unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; - int cs = spi_imx->chipselect[config->cs]; reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << MX31_CSPICTRL_DR_SHIFT; - reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; - reg |= MX31_CSPICTRL_SSCTL; + if (cpu_is_mx31()) + reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; + else if (cpu_is_mx25() || cpu_is_mx35()) { + reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; + reg |= MX31_CSPICTRL_SSCTL; + } if (config->mode & SPI_CPHA) reg |= MX31_CSPICTRL_PHA; @@ -381,26 +220,23 @@ static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx, reg |= MX31_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) reg |= MX31_CSPICTRL_SSPOL; - if (cs < 0) - reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT; + if (config->cs < 0) { + if (cpu_is_mx31()) + reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT; + else if (cpu_is_mx25() || cpu_is_mx35()) + reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; + } writel(reg, spi_imx->base + MXC_CSPICTRL); return 0; } -static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) +static int mx31_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; } -static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx) -{ - /* drain receive buffer */ - while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR) - readl(spi_imx->base + MXC_CSPIRXDATA); -} - #define MX27_INTREG_RR (1 << 4) #define MX27_INTREG_TEEN (1 << 9) #define MX27_INTREG_RREN (1 << 13) @@ -414,7 +250,7 @@ static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx) #define MX27_CSPICTRL_DR_SHIFT 14 #define MX27_CSPICTRL_CS_SHIFT 19 -static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable) +static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; @@ -426,7 +262,7 @@ static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable writel(val, spi_imx->base + MXC_CSPIINT); } -static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx) +static void mx27_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; @@ -435,11 +271,10 @@ static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } -static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx, +static int mx27_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) { unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; - int cs = spi_imx->chipselect[config->cs]; reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << MX27_CSPICTRL_DR_SHIFT; @@ -451,24 +286,19 @@ static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx, reg |= MX27_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) reg |= MX27_CSPICTRL_SSPOL; - if (cs < 0) - reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT; + if (config->cs < 0) + reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; writel(reg, spi_imx->base + MXC_CSPICTRL); return 0; } -static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx) +static int mx27_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; } -static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx) -{ - writel(1, spi_imx->base + MXC_RESET); -} - #define MX1_INTREG_RR (1 << 3) #define MX1_INTREG_TEEN (1 << 8) #define MX1_INTREG_RREN (1 << 11) @@ -480,7 +310,7 @@ static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx) #define MX1_CSPICTRL_MASTER (1 << 10) #define MX1_CSPICTRL_DR_SHIFT 13 -static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) +static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; @@ -492,7 +322,7 @@ static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) writel(val, spi_imx->base + MXC_CSPIINT); } -static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) +static void mx1_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; @@ -501,7 +331,7 @@ static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } -static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, +static int mx1_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) { unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; @@ -520,73 +350,11 @@ static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, return 0; } -static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) +static int mx1_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; } -static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) -{ - writel(1, spi_imx->base + MXC_RESET); -} - -/* - * These version numbers are taken from the Freescale driver. Unfortunately it - * doesn't support i.MX1, so this entry doesn't match the scheme. :-( - */ -static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = { -#ifdef CONFIG_SPI_IMX_VER_IMX1 - [SPI_IMX_VER_IMX1] = { - .intctrl = mx1_intctrl, - .config = mx1_config, - .trigger = mx1_trigger, - .rx_available = mx1_rx_available, - .reset = mx1_reset, - .fifosize = 8, - }, -#endif -#ifdef CONFIG_SPI_IMX_VER_0_0 - [SPI_IMX_VER_0_0] = { - .intctrl = mx27_intctrl, - .config = mx27_config, - .trigger = mx27_trigger, - .rx_available = mx27_rx_available, - .reset = spi_imx0_0_reset, - .fifosize = 8, - }, -#endif -#ifdef CONFIG_SPI_IMX_VER_0_4 - [SPI_IMX_VER_0_4] = { - .intctrl = mx31_intctrl, - .config = spi_imx0_4_config, - .trigger = mx31_trigger, - .rx_available = mx31_rx_available, - .reset = spi_imx0_4_reset, - .fifosize = 8, - }, -#endif -#ifdef CONFIG_SPI_IMX_VER_0_7 - [SPI_IMX_VER_0_7] = { - .intctrl = mx31_intctrl, - .config = spi_imx0_7_config, - .trigger = mx31_trigger, - .rx_available = mx31_rx_available, - .reset = spi_imx0_4_reset, - .fifosize = 8, - }, -#endif -#ifdef CONFIG_SPI_IMX_VER_2_3 - [SPI_IMX_VER_2_3] = { - .intctrl = spi_imx2_3_intctrl, - .config = spi_imx2_3_config, - .trigger = spi_imx2_3_trigger, - .rx_available = spi_imx2_3_rx_available, - .reset = spi_imx2_3_reset, - .fifosize = 64, - }, -#endif -}; - static void spi_imx_chipselect(struct spi_device *spi, int is_active) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); @@ -602,21 +370,21 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active) static void spi_imx_push(struct spi_imx_data *spi_imx) { - while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) { + while (spi_imx->txfifo < 8) { if (!spi_imx->count) break; spi_imx->tx(spi_imx); spi_imx->txfifo++; } - spi_imx->devtype_data.trigger(spi_imx); + spi_imx->trigger(spi_imx); } static irqreturn_t spi_imx_isr(int irq, void *dev_id) { struct spi_imx_data *spi_imx = dev_id; - while (spi_imx->devtype_data.rx_available(spi_imx)) { + while (spi_imx->rx_available(spi_imx)) { spi_imx->rx(spi_imx); spi_imx->txfifo--; } @@ -630,12 +398,11 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id) /* No data left to push, but still waiting for rx data, * enable receive data available interrupt. */ - spi_imx->devtype_data.intctrl( - spi_imx, MXC_INT_RR); + spi_imx->intctrl(spi_imx, MXC_INT_RR); return IRQ_HANDLED; } - spi_imx->devtype_data.intctrl(spi_imx, 0); + spi_imx->intctrl(spi_imx, 0); complete(&spi_imx->xfer_done); return IRQ_HANDLED; @@ -650,7 +417,7 @@ static int spi_imx_setupxfer(struct spi_device *spi, config.bpw = t ? t->bits_per_word : spi->bits_per_word; config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; config.mode = spi->mode; - config.cs = spi->chip_select; + config.cs = spi_imx->chipselect[spi->chip_select]; if (!config.speed_hz) config.speed_hz = spi->max_speed_hz; @@ -672,7 +439,7 @@ static int spi_imx_setupxfer(struct spi_device *spi, } else BUG(); - spi_imx->devtype_data.config(spi_imx, &config); + spi_imx->config(spi_imx, &config); return 0; } @@ -691,7 +458,7 @@ static int spi_imx_transfer(struct spi_device *spi, spi_imx_push(spi_imx); - spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE); + spi_imx->intctrl(spi_imx, MXC_INT_TE); wait_for_completion(&spi_imx->xfer_done); @@ -718,39 +485,6 @@ static void spi_imx_cleanup(struct spi_device *spi) { } -static struct platform_device_id spi_imx_devtype[] = { - { - .name = DRIVER_NAME, - .driver_data = SPI_IMX_VER_AUTODETECT, - }, { - .name = "imx1-cspi", - .driver_data = SPI_IMX_VER_IMX1, - }, { - .name = "imx21-cspi", - .driver_data = SPI_IMX_VER_0_0, - }, { - .name = "imx25-cspi", - .driver_data = SPI_IMX_VER_0_7, - }, { - .name = "imx27-cspi", - .driver_data = SPI_IMX_VER_0_0, - }, { - .name = "imx31-cspi", - .driver_data = SPI_IMX_VER_0_4, - }, { - .name = "imx35-cspi", - .driver_data = SPI_IMX_VER_0_7, - }, { - .name = "imx51-cspi", - .driver_data = SPI_IMX_VER_0_7, - }, { - .name = "imx51-ecspi", - .driver_data = SPI_IMX_VER_2_3, - }, { - /* sentinel */ - } -}; - static int __devinit spi_imx_probe(struct platform_device *pdev) { struct spi_imx_master *mxc_platform_info; @@ -802,31 +536,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) init_completion(&spi_imx->xfer_done); - if (pdev->id_entry->driver_data == SPI_IMX_VER_AUTODETECT) { - if (cpu_is_mx25() || cpu_is_mx35()) - spi_imx->devtype_data = - spi_imx_devtype_data[SPI_IMX_VER_0_7]; - else if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) - spi_imx->devtype_data = - spi_imx_devtype_data[SPI_IMX_VER_0_4]; - else if (cpu_is_mx27() || cpu_is_mx21()) - spi_imx->devtype_data = - spi_imx_devtype_data[SPI_IMX_VER_0_0]; - else if (cpu_is_mx1()) - spi_imx->devtype_data = - spi_imx_devtype_data[SPI_IMX_VER_IMX1]; - else - BUG(); - } else - spi_imx->devtype_data = - spi_imx_devtype_data[pdev->id_entry->driver_data]; - - if (!spi_imx->devtype_data.intctrl) { - dev_err(&pdev->dev, "no support for this device compiled in\n"); - ret = -ENODEV; - goto out_gpio_free; - } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "can't get platform resource\n"); @@ -858,6 +567,24 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) goto out_iounmap; } + if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) { + spi_imx->intctrl = mx31_intctrl; + spi_imx->config = mx31_config; + spi_imx->trigger = mx31_trigger; + spi_imx->rx_available = mx31_rx_available; + } else if (cpu_is_mx27() || cpu_is_mx21()) { + spi_imx->intctrl = mx27_intctrl; + spi_imx->config = mx27_config; + spi_imx->trigger = mx27_trigger; + spi_imx->rx_available = mx27_rx_available; + } else if (cpu_is_mx1()) { + spi_imx->intctrl = mx1_intctrl; + spi_imx->config = mx1_config; + spi_imx->trigger = mx1_trigger; + spi_imx->rx_available = mx1_rx_available; + } else + BUG(); + spi_imx->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(spi_imx->clk)) { dev_err(&pdev->dev, "unable to get clock\n"); @@ -868,9 +595,15 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) clk_enable(spi_imx->clk); spi_imx->spi_clk = clk_get_rate(spi_imx->clk); - spi_imx->devtype_data.reset(spi_imx); + if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) + writel(1, spi_imx->base + MXC_RESET); + + /* drain receive buffer */ + if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) + while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR) + readl(spi_imx->base + MXC_CSPIRXDATA); - spi_imx->devtype_data.intctrl(spi_imx, 0); + spi_imx->intctrl(spi_imx, 0); ret = spi_bitbang_start(&spi_imx->bitbang); if (ret) { @@ -935,7 +668,6 @@ static struct platform_driver spi_imx_driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, }, - .id_table = spi_imx_devtype, .probe = spi_imx_probe, .remove = __devexit_p(spi_imx_remove), };