From 9bc93312074f582f75def4b09cc1b4e57c764574 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Fri, 6 Jul 2012 21:56:01 +0200 Subject: [PATCH] --- yaml --- r: 312117 b: refs/heads/master c: 78d4803f75277f78ab4fc3be7ad462d78f726df9 h: refs/heads/master i: 312115: 791efedbb090501547c695d0943faa5e06901279 v: v3 --- [refs] | 2 +- trunk/arch/mips/include/asm/cpu.h | 2 +- trunk/arch/mips/kernel/cpu-probe.c | 4 ++++ trunk/arch/mips/kernel/traps.c | 1 + 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 10b7210213b1..17a6843e8e2d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 113c62d9844d9037508fa156e47db1b5407a27c3 +refs/heads/master: 78d4803f75277f78ab4fc3be7ad462d78f726df9 diff --git a/trunk/arch/mips/include/asm/cpu.h b/trunk/arch/mips/include/asm/cpu.h index c64910586b74..95e40c1e8ed1 100644 --- a/trunk/arch/mips/include/asm/cpu.h +++ b/trunk/arch/mips/include/asm/cpu.h @@ -266,7 +266,7 @@ enum cpu_type_enum { /* * MIPS64 class processors */ - CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, + CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_XLR, CPU_XLP, diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c index aaf39f3eaa51..f4630e1082ab 100644 --- a/trunk/arch/mips/kernel/cpu-probe.c +++ b/trunk/arch/mips/kernel/cpu-probe.c @@ -811,6 +811,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_5KC; __cpu_name[cpu] = "MIPS 5Kc"; break; + case PRID_IMP_5KE: + c->cputype = CPU_5KE; + __cpu_name[cpu] = "MIPS 5KE"; + break; case PRID_IMP_20KC: c->cputype = CPU_20KC; __cpu_name[cpu] = "MIPS 20Kc"; diff --git a/trunk/arch/mips/kernel/traps.c b/trunk/arch/mips/kernel/traps.c index f985b7292cd9..ce95f2c41f3f 100644 --- a/trunk/arch/mips/kernel/traps.c +++ b/trunk/arch/mips/kernel/traps.c @@ -1249,6 +1249,7 @@ static inline void parity_protection_init(void) break; case CPU_5KC: + case CPU_5KE: write_c0_ecc(0x80000000); back_to_back_c0_hazard(); /* Set the PE bit (bit 31) in the c0_errctl register. */