From 9d593fd611972a08c80c9ea2c7d274ca229cdfde Mon Sep 17 00:00:00 2001
From: Zhang Wei <wei.zhang@freescale.com>
Date: Tue, 26 Jun 2007 18:22:40 -0500
Subject: [PATCH] --- yaml --- r: 60623 b: refs/heads/master c:
 20243c72a8564ccd22437fd1bda16ca5bccd5701 h: refs/heads/master i:   60621:
 dddbd4a0b6cbd76189073475450ca043745a6404   60619:
 5572b0406900132a965183fe81d0acc499ad2cc6   60615:
 2edbd5c0654fabd2279f5e481a84a01de2af977d   60607:
 7cde81336138f1664efcd3274fa8ed5c2ee7e410 v: v3

---
 [refs]                                  |  2 +-
 trunk/arch/powerpc/platforms/86xx/pci.c | 37 +++++++++++++++++++++++++
 2 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 5c1d11715326..03fc3d52d9da 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6d8ff10c3ab1e3d4a40788442f1369e868103e43
+refs/heads/master: 20243c72a8564ccd22437fd1bda16ca5bccd5701
diff --git a/trunk/arch/powerpc/platforms/86xx/pci.c b/trunk/arch/powerpc/platforms/86xx/pci.c
index 6f3c0f674bbf..2d7254c91ad9 100644
--- a/trunk/arch/powerpc/platforms/86xx/pci.c
+++ b/trunk/arch/powerpc/platforms/86xx/pci.c
@@ -134,6 +134,43 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
 	early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 }
 
+static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
+{
+	struct resource *res;
+	int i, res_idx = PCI_BRIDGE_RESOURCES;
+	struct pci_controller *hose;
+
+	/*
+	 * Make the bridge be transparent.
+	 */
+	dev->transparent = 1;
+
+	hose = pci_bus_to_hose(dev->bus->number);
+	if (!hose) {
+		printk(KERN_ERR "Can't find hose for bus %d\n",
+		       dev->bus->number);
+		return;
+	}
+
+	if (hose->io_resource.flags) {
+		res = &dev->resource[res_idx++];
+		res->start = hose->io_resource.start;
+		res->end = hose->io_resource.end;
+		res->flags = hose->io_resource.flags;
+	}
+
+	for (i = 0; i < 3; i++) {
+		res = &dev->resource[res_idx + i];
+		res->start = hose->mem_resources[i].start;
+		res->end = hose->mem_resources[i].end;
+		res->flags = hose->mem_resources[i].flags;
+	}
+}
+
+
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
+
 #define PCIE_LTSSM	0x404	/* PCIe Link Training and Status */
 #define PCIE_LTSSM_L0	0x16	/* L0 state */