From 9f091760655ed1082e290959a8ce805b7365909e Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 11 Jan 2012 15:37:16 +0100
Subject: [PATCH] --- yaml --- r: 284683 b: refs/heads/master c:
 d7a887a73dec6c387b02a966a71aac767bbd9ce6 h: refs/heads/master i:   284681:
 209e28fe78aa264d8fc8b7524a7ea6177b355818   284679:
 5b25328f62b0543f5881f2889a55913da5437923 v: v3

---
 [refs]                                   |  2 +-
 trunk/arch/mips/include/asm/pgtable-32.h | 11 ------
 trunk/arch/mips/mm/tlb-r4k.c             | 47 ------------------------
 3 files changed, 1 insertion(+), 59 deletions(-)

diff --git a/[refs] b/[refs]
index 738e42be8e51..40948b9f638b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c539ef7d355219c7b0e16cc302bf179fcad936b3
+refs/heads/master: d7a887a73dec6c387b02a966a71aac767bbd9ce6
diff --git a/trunk/arch/mips/include/asm/pgtable-32.h b/trunk/arch/mips/include/asm/pgtable-32.h
index 8a153d2fa62a..d169c07c38ee 100644
--- a/trunk/arch/mips/include/asm/pgtable-32.h
+++ b/trunk/arch/mips/include/asm/pgtable-32.h
@@ -24,17 +24,6 @@
 extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 			       unsigned long entryhi, unsigned long pagemask);
 
-/*
- * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
- *	starting at the top and working down. This is for populating the
- *	TLB before trap_init() puts the TLB miss handler in place. It
- *	should be used only for entries matching the actual page tables,
- *	to prevent inconsistencies.
- */
-extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
-			       unsigned long entryhi, unsigned long pagemask);
-
-
 /* Basically we have the same two-level (which is the logical three level
  * Linux page table layout folded) page tables as the i386.  Some day
  * when we have proper page coloring support we can have a 1% quicker
diff --git a/trunk/arch/mips/mm/tlb-r4k.c b/trunk/arch/mips/mm/tlb-r4k.c
index 88dc49cfa163..74d67c885743 100644
--- a/trunk/arch/mips/mm/tlb-r4k.c
+++ b/trunk/arch/mips/mm/tlb-r4k.c
@@ -376,51 +376,6 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 	EXIT_CRITICAL(flags);
 }
 
-/*
- * Used for loading TLB entries before trap_init() has started, when we
- * don't actually want to add a wired entry which remains throughout the
- * lifetime of the system
- */
-
-static int temp_tlb_entry __cpuinitdata;
-
-__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
-			       unsigned long entryhi, unsigned long pagemask)
-{
-	int ret = 0;
-	unsigned long flags;
-	unsigned long wired;
-	unsigned long old_pagemask;
-	unsigned long old_ctx;
-
-	ENTER_CRITICAL(flags);
-	/* Save old context and create impossible VPN2 value */
-	old_ctx = read_c0_entryhi();
-	old_pagemask = read_c0_pagemask();
-	wired = read_c0_wired();
-	if (--temp_tlb_entry < wired) {
-		printk(KERN_WARNING
-		       "No TLB space left for add_temporary_entry\n");
-		ret = -ENOSPC;
-		goto out;
-	}
-
-	write_c0_index(temp_tlb_entry);
-	write_c0_pagemask(pagemask);
-	write_c0_entryhi(entryhi);
-	write_c0_entrylo0(entrylo0);
-	write_c0_entrylo1(entrylo1);
-	mtc0_tlbw_hazard();
-	tlb_write_indexed();
-	tlbw_use_hazard();
-
-	write_c0_entryhi(old_ctx);
-	write_c0_pagemask(old_pagemask);
-out:
-	EXIT_CRITICAL(flags);
-	return ret;
-}
-
 static int __cpuinitdata ntlb;
 static int __init set_ntlb(char *str)
 {
@@ -458,8 +413,6 @@ void __cpuinit tlb_init(void)
 		write_c0_pagegrain(pg);
 	}
 
-	temp_tlb_entry = current_cpu_data.tlbsize - 1;
-
         /* From this point on the ARC firmware is dead.  */
 	local_flush_tlb_all();