From 9fab9a2d91dcaa8ee7ce79508bd0c4d2a740cf1a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 27 Aug 2011 06:14:23 -0500 Subject: [PATCH] --- yaml --- r: 274219 b: refs/heads/master c: 37caf9f2a1b99d11ba71e17168d221da9ca13f24 h: refs/heads/master i: 274217: d3c6df498388bd7586011521780ab450830050c7 274215: f103e5bb97d10c66844ec68d94f7aab53b4b0d17 v: v3 --- [refs] | 2 +- trunk/arch/powerpc/include/asm/reg_booke.h | 3 +++ trunk/arch/powerpc/kernel/traps.c | 9 ++++++++- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index be78a7f12e72..4f2b04bd3b32 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 09af52f78e58d9aee0980276833bf3adee3ed07b +refs/heads/master: 37caf9f2a1b99d11ba71e17168d221da9ca13f24 diff --git a/trunk/arch/powerpc/include/asm/reg_booke.h b/trunk/arch/powerpc/include/asm/reg_booke.h index 9ec0b39f9ddc..28cdbd9f399c 100644 --- a/trunk/arch/powerpc/include/asm/reg_booke.h +++ b/trunk/arch/powerpc/include/asm/reg_booke.h @@ -548,6 +548,9 @@ #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ +/* Bit definitions for L1CSR2. */ +#define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */ + /* Bit definitions for L2CSR0. */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ diff --git a/trunk/arch/powerpc/kernel/traps.c b/trunk/arch/powerpc/kernel/traps.c index f19d9777d3c1..4e5908264d1a 100644 --- a/trunk/arch/powerpc/kernel/traps.c +++ b/trunk/arch/powerpc/kernel/traps.c @@ -457,7 +457,14 @@ int machine_check_e500mc(struct pt_regs *regs) if (reason & MCSR_DCPERR_MC) { printk("Data Cache Parity Error\n"); - recoverable = 0; + + /* + * In write shadow mode we auto-recover from the error, but it + * may still get logged and cause a machine check. We should + * only treat the non-write shadow case as non-recoverable. + */ + if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) + recoverable = 0; } if (reason & MCSR_L2MMU_MHIT) {